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? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80c7d5a5 mt28c256564w18t.fm - rev. c pub 2/04 en 1 ?2004 micron technology, inc. all rights reserved. 256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary ? flash and cellularram ? combo memory mt28c256532w18t mt28c256564w18t low voltage, wireless temperature features stacked die combo package ? includes two 128mb flash devices choice of either one 32mb or one 64mb cellularram ? device basic configuration flash flexible multibank architecture 8 meg x 16 async/page/burst interface support for true concurrent operations with no latency cellularram low power, high-density design 2 meg x 16 or 4 meg x 16 configurations burst f_v cc , v cc q, f_v pp , c_v cc voltages 1.70v (min)/1.95v (max) f_v cc , c_v cc 1.70v (min)/2.24v (max) v cc q 1.80v (typ) f_v pp (in-system program/erase) 12v 5% (hv) f_v pp tolerant (factory program- ming compatibility) fast programming algorithm (fpa) enhanced suspend options erase-suspend-to-read within same bank program-suspend-to-read within same bank erase-suspend-to-program within same bank each flash contains two 64-bit chip protection registers for security purposes 100,000 erase cycles per block cross-compatible command set support extended command set common flash interface (cfi) compliant options flash timing 60ns 1 70ns flash burst frequency 66 mhz 1 54 mhz flash boot block configuration top/top top/bottom bottom/top bottom/bottom cellularram timing 70ns 85ns cellularram burst frequency 66 mhz i/o voltage range v cc q 1.70v?2.24v operating temperature range wireless temperature (-25c to +85c) package 88-ball fbga (standard) 8 x 10 grid with eight support balls 88-ball fbga (lead-free) 8 x 10 grid with eight support balls 2 note: 1. contact factory for availability. 2. contact fa ctory for details. a b c d e f g h j k l m 1 2 3 4 5 6 7 8 top view (ball down) c_v ss c_v ss f_v pp f_wp# f_rst# dq10 dq3 dq11 nc f_vcc a19 a23 rfu rfu c_ub# dq2 dq1 dq9 nc vccq nc a4 a5 a3 a2 a1 a0 c_oe# nc f_ce# c_v ss nc f_v cc clk c_ce# a20 a8 dq13 dq14 dq6 f_v cc v ss q nc a11 a12 a13 a15 a16 nc nc v cc q c_cre c_v ss nc f_v cc nc c_we# adv# f_we# dq5 dq12 dq4 c_v cc c_v ss nc a18 c_lb# a17 a7 a6 dq8 dq0 f_oe# nc v ss q nc nc a21 a22 a9 a10 a14 wait# dq7 dq15 v cc q f_v ss nc figure 1: 88-ball fbga
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 2 ?2004 micron technology. inc. all rights reserved. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 flash configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 multichip packaging consideratio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 unique ids, state machines, and registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 flash reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 flash electrical specific ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 3 ?2004 micron technology. inc. all rights reserved. list of figures figure 1: 88-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: flash memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 5: 88-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 4 ?2004 micron technology. inc. all rights reserved. list of tables table 1: cross-reference for abbreviated devi ce marks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 2: valid part number combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 3: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 4: truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 5: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 6: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 7: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 8: ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 9: cfi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 5 ?2004 micron technology. inc. all rights reserved. device general description the mt28c256532w18t/mt28c256564w18t com- bination flash and cellularram is a high-perfor- mance, high-density, memory solution that can significantly improve system performance. this mem- ory solution is comprised of two 128mb flash devices and one 32mb or one 64mb cellularram device. it is important to note that the specifications con- tained in this document supersede the specifications listed in the referenced in dividual flash and cellular- ram data sheets. flash general description the flash architecture features a multipartition configuration that supports read-while-program/ erase operations with no latency. an 8mb partition size enables optimal design flexibility. two flash devices are stacked to achieve the 256mb density. both flash die share a dedicated ce# and oe# control. the stacked flash device enables soft protection for blocks, as read only, by configuring soft protection reg- isters with dedicated comma nd sequences. for secu- rity purposes, two user-p rogrammable 64-bit chip protection registers are provided for each flash device. the embedded word program and block erase functions are fully automated by an on-chip write state machine (wsm). an on-chip device status register can be used to monitor the wsm status and determine the progress of the program/erase tasks. each flash device has a read configuration register (rcr) that defines how the flash interacts with the memory bus. for device specifications and additional documentation concerning flash, please refer to the mt28f1284w18 data sheet at www.micron.com/flash . flash configurations each flash memory implements a multibank archi- tecture (16 banks of 8mb each) to allow concurrent operations. any address with in a block address range selects that block for the required read, program, or erase operation. each flash memory features eight 8k-word sectors (8 x 65,536 bits), designated as parameter blocks, and the remaining part is organized in main blocks of 64k words each (524,288 bits). the parameter blocks are addressed either by the low order addresses (bottom boot) or by the higher order addresses (top boot). the two flash devices can be supplied with any combination of top or bottom boot (e.g., top/top, bot- tom/bottom, top/bottom, or bottom/top). please see figures 1 and 2 for more information. cellularram general description the cellularram architecture features high-speed cmos, dynamic random-access memories developed for low-power portable applications the cellularram device is available in either 32mb or 64mb densities. to operate seamlessly on a burst flash bus, cellularram products have incorporated a transparent self-refresh mechanism. the hidden refresh requires no addition al support from the system memory controller and has no significant impact on device read/write performance. the refresh configuration register (rcr) is used to control how refresh is performed on the cellularram array. these registers are automatically loaded with default settings during power-up and can be updated any time during normal operation. special attention has been focused on standby current consumption during self-refresh. cellularram products include three system-acces- sible mechanisms used to minimize standby current. partial array refresh (par) limits refresh to the portion of the memory array being used. temperature com- pensated refresh (tcr) is us ed to adjust the refresh rate according to the ambient temperature. the refresh rate can be decreased at lower temperatures to minimize current consumpt ion during standby. deep sleep mode halts the refresh operation altogether and is used when no vital information is stored in the device. these three refresh mechanisms are adjusted through the refresh configuration register (rcr). for device specificat ions and additional documentation concerning cellularram memory, p lease refer to the mt45w2mw16bfb and mt45w4mw16bfb cellularram data sheets at www.micron.com/cellularram .
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 6 ?2004 micron technology. inc. all rights reserved. figure 1: flash memory map note: figure 1 shows a tb (top/bottom) dual flash configuration. parameter blocks ? top boot (128mb to 256mb) main main main parameter blocks ? bottom boot (0mb to 128mb) main main main
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 7 ?2004 micron technology. inc. all rights reserved. figure 2: block diagram c_oe# c_cre c_ce# c_we# dq0 ? dq15 a0 ? a23 f_we# f_ wp# wait # flash #2 cellularram f_rst# c_ub# c_lb# 8,192k x 16 2,048k x 16 4,096k x 16 bank 31 bank 16 c_v cc adv# c_v ss flash #1 8,192k x 16 bank 15 bank 0 v cc q v ss q f_v cc f_v ss f_v pp clk f_oe# f_ce#
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 8 ?2004 micron technology. inc. all rights reserved. part numbering information micron?s combination memory devices are available with several different comb inations of features (see figure 3). figure 3: par t number chart note: 1. the first character in this field refers to flash die #2. the second character in this field refers to flash die #1. 2. contact factory for availability. valid part number combinations after building the part number from the part num- ber chart above, please go to micron?s part marking decoder web site at www.micron.com/decoder to ver- ify that the part number is offered and valid. if the device required is not on th is list, please contact the factory. device marking due to the size of the package, the micron standard part number is not printed on the top of each device. instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. the abbreviated device marks are cross-referenced to the micron part numbers at www.micron.com/decoder. to vi ew th e location of the abbreviated mark on the device, please refer to customer service note csn-11, ?product mark/ label,? at www.micron.com/csn . mt 28c 2565 64 w18 t ft-f70 5 p85 6 bb wt es micron technology flash family 28c = dual-supply flash/cellularram combo density/organization/banks 256 = 256mb (8,192k x 16) bank x = 5 multibank 32 banks (all banks have the same dimensions) flash access time f60 = 60ns 2 f70 = 70ns cellularram density 32 = 32mb cellularram (2 meg x 16) 64 = 64mb cellularram (4 meg x 16) flash read operation w = flash async/page/burst read package code ft = 88-ball fbga (standard) 8 x 10 grid with eight support balls bt = 88-ball fbga (lead-free) 8 x 10 grid with eight support balls 2 operating temperature range wt = wireless (-25oc to +85oc) flash burst frequency 5 = 54 mhz 6 = 66 mhz 2 cellularram access time p70 = 70ns p85 = 85ns operating voltage range 18 v cc = 1.70v?1.95v v cc q = 1.70v?2.24v ce select/special mark t = single ce flash with burst cellularram production status blank = production es = engineering samples qs = qualification samples flash boot block starting address 1 bb = bottom boot/bottom boot bt = bottom boot/top boot tt = top boot/top boot tb = top boot/bottom boot cellularram burst frequency 6 = 66 mhz
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 9 ?2004 micron technology. inc. all rights reserved. table 1: ball descriptions 88-ball fbga numbers symbol type descriptions g1, f1, e1, d1, b1, c1, f2, e2, f6, d7, e7, b8, c8, d8, f7, e8, f8, d2, b2, b3, e6, b7, c7, c3 a0?a23 input addresses: flash: a0?a23. cellularram: a0?a20 (32mb). cellularram: a0?a21 (64mb). k1 f_ce# input flash chip enable. j2 f_oe# input flash output enable. f5 f_we# input flash write enable. e4 f_wp# input flash write protect. e5 adv# input address valid (burst operation only). c6 clk input clock (burst operation only). f4 f_rst# input flash reset. c2 c_lb# input cellularram lower byte control. f3 c_ub# input cellularram upper byte control. d5 c_we# input cellularram write enable. h1 c_oe# input cellularram output enable. d6 c_ce# input cellularram chip enable. k8 c_cre input cellularram deep sleep mode and configuration mode. h2, h3, g3, h4, j5, g5, j6, h7, g2, j3, g4, j4, h5, g6, h6, j7 dq0?dq15 i/o flash/cellularram da ta input/output. g7 wait# output wait#. see ?wait ball operation? on page 10. l7 f_v ss supply flash core ground. d4 f_v pp supply flash v pp . b5, b6, k6, l4 f_v cc supply flash core power supply. b4, c4, l5, l1, l8 c_v ss supply cellularram core ground. k5 c_v cc supply cellularram core power supply. j8, k7, l3 v cc q supply flash/cellularram i/o supply. l2, l6 v ss q supply flash/cellularram i/o ground. a1, a2, a7, a8, c5, g8, h8, j1, k2, k3, k4, m1, m2, m7, m8 nc ? no connect. not internally connected to the die. d3, e3 rfu ? reserved for future use (a24, a25).
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 10 ?2004 micron technology. inc. all rights reserved. boot configurations the possible configurations for flash die are shown in table 2 below. this table shows the possible config- urations of the two flash de vices for either top boot or bottom boot. multichip packaging considerations multichip packaging presents unique challenges when controlling complex memory devices. the mt28c256532w18 and mtc256564w18 devices combine two micron flash devices with a sin- gle cellularram device. unique ids, state machines, and registers each flash device has a separate command state machine (csm) and status register (sr) and read con- figuration register (rcr). the read configuration regis- ter (rcr) settings are separate and can be different for the upper and lower device. each flash device has its own otp, cfi, and device code. depending on the boot configuration of each flash device, the otp, cfi, and device code information may differ. the cellularram memory has a refresh configura- tion register (rcr) that defines how the device per- forms self refresh, and a bus configuration register (bcr) to define the interface configuration. command codes all flash command codes are independent within each device. care must be taken when crossing the array boundary between the upper and lower flash device and the cellularram device to ensure that only one device is enabled at one time. in a two-cycle command sequence such as word program (0x40/data), it is required that both com- mands be issued to the same device. it is not recommended that simultaneous read, simultaneous write, or simultaneous erase operations occur on both flash devices. read operation all read operations are limited to the address boundaries of each device. the flash device boundary is encountered when a23 changes logic states. addresses with a23 = 0 access flash #1. addresses with a23 = 1 access flash #2. a new read operation must be started when cross- ing the device boundary. write operation the write operation is limited to the address boundaries of each device. the flash device boundary is encountered when a23 changes logic states. addresses with a23 = 0 access flash #1. addresses with a23 = 1 access flash #2. a new write operation must be started when crossing the device boundary. flash reset the reset control is shared by both flash die. bring- ing f_rst# conrol low will reset both the upper and lower device. wait ball operation it is important to note that the flash and cellular- ram devices share the wait ball functionality and must be configured correctly for proper burst mode operation. the flash and ce llularram devices use dif- ferent registers to configure the wait polarity and have opposite default values. the wait ball polarity for the flash device is config- ured by programming bit 10 in the read configuration register (rcr). the default is active low. the wait ball polarity for the cellularram device is configured by programming bit 10 in the bus configu- ration register (bcr). the default is active high. both the flash and cellularram wait ball polarities must be set to the same active level for proper opera- tion. power consumption multiple chip packaging requires that power calcu- lations consider the active operation of the upper and lower flash device as well as that of the cellularram device. total power consumed will be the sum of the currents associated with the state of each device. table 2: possible boot configurations for flash die configuration f_ce# order code top/top top tt top/bottom bottom tb bottom/top top bt bottom/bottom bottom bb
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 11 ?2004 micron technology, inc. all rights reserved. note: 1. wait status is only valid for burst mode operation. wait should be ignored for all other operating modes. 2. if a23 = 0, then flash #1 is selected; an d if a23 = 1, then fl ash #2 is selected. table 3: truth table modes flash signals 2 shared signals cellularram signals memory output f_ce# f_oe# f_we# f_rst# adv# wait# c_ce# c_cre c_oe# c_ub/lb# c_we# memory bus control dq0? dq15 flash #1 read llhh l active 1 cellularram memory must be in high-z flash d out write l h l h x asserted flash d in standby hxxh xhigh-z cellularram memory any mode allowable other high-z output disable lhhh x active 1 other high-z reset x x x l x high-z none high-z flash #2 read llhh l active 1 cellularram memory must be in high-z flash d out write l h l h x asserted flash d in standby hxxh xhigh-z cellularram memory any mode allowable other high-z output disable lhhh x active 1 other high-z reset x x x l x high-z none high-z cellularram memory read flash must be in high-z l active 1 lh l l h cellular ram d out write l active 1 lh h l l cellular ram d in standby flash any mode allowable xxhhxxxotherhigh-z output disable xxlhhxhotherhigh-z deep sleep mode xxhlxxxotherhigh-z
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 12 ?2004 micron technology. inc. all rights reserved. electrical specifications note: 1. stresses greater than those listed in table 4 may cause perma nent damage to the device. th is is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec- tions of this specification is not impl ied. exposure to absolute maximum rati ng conditions for ex tended periods may affect reliability. 2. see technical note tn-00-15, ?recommended soldering techniques,? for more information. table 4: absolute maximum ratings note 1 parameters/conditions min max units notes operating temperature range -25 +85 c storage temperature range -55 +125 c soldering cycle +260 c 2 table 5: recommended operating conditions parameter symbol min typ max units v cc supply voltage (f_v cc and c_v cc ) v cc 1.70 ? 1.95 v i/o supply voltage v cc q 1.70 ? 2.24 v table 6: capacitance t a = +25 c; f = 1 mhz parameter/condition symbol typ max units input capacitance c in 13 17 pf output capacitance c out 18 20 pf clock capacitance c clk 20 22 pf
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 13 ?2004 micron technology. inc. all rights reserved. note: 1. c_cre ball high, cr4 bit in the cellularram refresh conf iguration register set to zero. measured at 25c, this standby current is the sum of the flash standby curren t and the cellularram deep-power down mode current. 2. i cces and i ccws values are valid when the device is deselect ed. any read operation pe rformed while in suspend mode will have an additional cu rrent draw of suspend current. 3. automatic power save (aps) mode reduces i cc to approximately i ccs levels. 4. currents are measured using cellularram full array self-r efresh. currents may be furth er reduced by using the tcr or par features. table 7: dc characteristics it is important to note that the specifications contained in this document supersede the specifications listed in the referenced individual flash and cellularram data sh eets. all currents are in rms unless otherwise noted. parameter symbol typ max units notes v cc standby current with 32mb cellularram with 64mb cellularram i ccs 210 220 a 4 v cc standby current with cellularram device in deep power-down mode with 32mb cellularram with 64mb cellularram i sbzz 110 110 a 1, 4 v cc program suspend current with 32mb cellularram with 64mb cellularram i ccws 210 220 a 2, 4 v cc erase suspend current with 32mb cellularram with 64mb cellularram i cces 210 220 a 2, 4 v cc automatic power save current with 32mb cellularram with 64mb cellularram i ccaps 210 220 a 3, 4 table 8: cfi it is important to note that the specifications contained in this document supersede the specifications listed in the referenced individual flash and cellularram data sheets. offset data description 78 32mb: 0020 cellularram density 64mb: 0040
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice.. mt28c256564w18t.fm - rev. c pub 2/04 en 14 ?2004 micron technology, inc all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. cellularram is a trademark of micron technology, inc., inside the u.s. and a trademark of infineon technologies outside the u.s . all other trademarks are the property of their respective owners. figure 4: 88-ball fbga note: 1. all dimensions in millimeters. data sheet designation preliminary: this data sheet contains initial characterization limits that are subject to change upon full of characterization of production devices. for additional documentation concerning flash and cell ularram features, functional descriptions, program- ming, and timing, pl ease refer to the table below. ball a1 id ball a1 id ball a1 ball a8 mold compound: epoxy novolac substrate: plastic laminate 1.40 max 0.25 0.05 solder ball material: 62% sn, 36% pb, 2% ag solder ball pad: ? 0.30mm solder mask defined 5.60 9.00 0.10 2.80 0.05 4.50 0.05 8.80 4.40 0.05 6.00 0.05 12.00 0.10 88x 0.35 ? solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.35 c l c l seating plane 1.025 0.075 0.10 c c 0.80 typ 0.80 typ 0.10 (4x) device part number link flash mt28f1284w18 www.micron.com/flash cellularram mt45w2mw16bfb, mt45w4mw16bfb www.micron.com/cellularram
256mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80c7d5a5 micron technology, inc., reserves the right to change products or specifications without notice. mt28c256564w18t.fm - rev. c pub 2/04 en 15 ?2004 micron technology. inc. all rights reserved. revision history rev c, preliminary............................................................................................................. ..............................................2/04 updated standby current specifications in the dc characteristics table rev b, preliminary ............................................................................................................. ............................................11/03 original document, rev. a ...................................................................................................... ........................................7/03

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