View AS8530-ASOP_7424880.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.ams.com high performance needs great design . d atasheet: as8530 lin transceiver with i ntegrated voltage regulator and m cu interface for automotive applications please be patient while we update our brand image as austriamicrosystems and taos are now ams.
as8530 lin transceiver with integrated voltage regulator and mcu interface for automotive applications www.ams.com/lin_companionic/as8530 revision 1.1 1 - 32 1 general description the as8530 is a general purpose companion ic for sensor and actuator lin slaves offering lin transceiver and low drop voltage regulator. it also provides a 2-wire microcontroller interface through shared en and tx pins to access a window watchdog with rc oscillator, control registers, backup registers and monitoring information. the ic is fabricated in a high voltage cmos technology which is able to withstand voltages up to 42v. the product is available in ep-soic8 package. 2 key features ?? operating voltage 6v to 18v ?? linear, low-drop voltage regulator: vcc = 5v 5% or 3.3v 5% as a factory programming option ?? 50ma load current ?? operating modes: normal and standby or normal and sleep as a factory option ?? typically 45a quiescent current in standby mode, typically 35a quiescent current in sleep mode ?? under voltage reset with factory options ?? lin bus transceiver l conforming to lin 2.1, tx time out fail safe feature, over temperature warning and shut down ?? window watchdog if factory enabled ?? micro controller 2-wire interface through shared pins for watchdog trigger, monitoring, register read /write ?? chip id for traceability and module id ?? 8 backup registers to store data during vcc shut down ?? ep-soic8 package ?? -40oc to +125oc ambient operating temperature 3 applications the as8530 is a system basis chip for automotive lin networked sensor or actuator slaves. vsup en vcc temperature limiter tshd reset lin 30k rx receiver vsup vcc tx transmitter gnd por-vsup reset_vsup_n 15k 2-wire interface window watchdog (wwd) lin wakeup control signals lin transceiver reset_vsup_n reset_vcc_n wwd output ldo mode control por-vcc reset block slew control as8530 figure 1. as8530 lin transceiver block diagram
www.ams.com/lin_companionic/as8530 revision 1.1 2 - 32 as8530 datasheet - contents contents 1 general description ............................................................................................................ ...................................................... 1 2 key features................................................................................................................... .......................................................... 1 3 applications................................................................................................................... ............................................................ 1 4 pin assignments ................................................................................................................ ....................................................... 4 4.1 pin descriptions.......................................................................................................... .......................................................................... 4 5 absolute maximum ratings ....................................................................................................... ............................................... 5 6 electrical characteristics..................................................................................................... ...................................................... 6 6.1 operating conditions...................................................................................................... ...................................................................... 6 6.2 digital inputs and outputs ................................................................................................ .................................................................... 6 6.3 detailed system and block specifications .................................................................................. ......................................................... 7 6.3.1 electrical system specific ations ........................................................................................ .......................................................... 7 6.4 low dropout regulator..................................................................................................... .................................................................... 7 6.5 lin transceiver ........................................................................................................... ......................................................................... 8 6.5.1 dc electrical characteristics ........................................................................................... ............................................................ 8 6.5.2 ac electrical characteristics ........................................................................................... ............................................................ 9 6.5.3 temperature limiter ..................................................................................................... ............................................................. 10 6.5.4 tx timeout watchdog ..................................................................................................... .......................................................... 10 6.6 v cc undervoltage reset and window watchdog........................................................................................ ...................................... 11 6.7 two port serial interface ................................................................................................. ................................................................... 12 7 detailed description........................................................................................................... ..................................................... 13 7.1 voltage regulator (ldo) ................................................................................................... ................................................................. 13 7.2 temperature limiter....................................................................................................... ..................................................................... 13 7.3 v sup undervoltage reset ............................................................................................................ ..................................................... 13 7.3.1 v sup undervoltage in normal mode................................................................................................... ...................................... 13 7.3.2 v sup undervoltage in standby mode / sleep mode..................................................................................... ............................ 13 7.3.3 v sup undervoltage in low slew mode................................................................................................. .................................... 13 7.4 reset..................................................................................................................... ........................................................................... 14 7.5 v cc undervoltage reset ............................................................................................................ ....................................................... 14 7.6 window watchdog (wwd) ..................................................................................................... ............................................................ 14 7.7 lin transceiver ........................................................................................................... ....................................................................... 15 7.8 operating modes and states................................................................................................ .............................................................. 15 7.8.1 normal mode ............................................................................................................. ................................................................ 15 7.8.2 standby mode............................................................................................................ ................................................................ 15 7.8.3 sleep mode.............................................................................................................. .................................................................. 15 7.8.4 temporary shutdown mode ................................................................................................. ..................................................... 16 7.8.5 thermal shutdown state .................................................................................................. ......................................................... 16 7.9 state diagram............................................................................................................. ........................................................................ 17 8 application information ........................................................................................................ ................................................... 18 8.1 initialization............................................................................................................ ............................................................................. 18 8.2 wake-up................................................................................................................... .......................................................................... 19 8.3 over-temperature shutdown ................................................................................................. ............................................................ 19
www.ams.com/lin_companionic/as8530 revision 1.1 3 - 32 as8530 datasheet - contents 8.4 lin bus transceiver ....................................................................................................... ................................................................... 19 8.4.1 transmit mode........................................................................................................... ................................................................ 19 8.4.2 receive mode............................................................................................................ ................................................................ 20 8.5 rx and tx interface ....................................................................................................... .................................................................... 20 8.6 mode input en............................................................................................................. ..................................................................... 21 8.7 serial port interface..................................................................................................... ....................................................................... 23 8.7.1 device configuration using 2-wire serial port ........................................................................... ............................................... 23 8.8 control and diagnosis registers ........................................................................................... ............................................................. 26 8.8.1 definition of control and status registers.............................................................................. ................................................... 26 9 package drawings and markings .................................................................................................. ......................................... 28 10 ordering information........................................................................................................... .................................................. 31
www.ams.com/lin_companionic/as8530 revision 1.1 4 - 32 as8530 datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin number pin name pin type special requirements description 1en digital input with pull-down 2kv esd enable high-voltage compatible pin with pull down to vss and ? vcc trigger level, active high. 2v sup supply pad load dump (42v max), 4kv hbm esd, jump start (27v max) battery supply 3 lin analog i/o conforms to lin 2.1, 6kv hbm esd lin bus 4 vss supply pad 5rx digital output with pull-up 2kv esd lin transceiver receive signal, data out in test mode 6tx digital input with pull-up lin transceiver transmit signal, clock in test mode 7 reset digital output digital output referenced to vcc, active low 8 vcc supply pad regulated 5v / 3.3v supply for loads up to 50ma. otp selectable en vsup lin vss vcc reset tx rx as8530 1 2 3 4 8 7 6 5
www.ams.com/lin_companionic/as8530 revision 1.1 5 - 32 as8530 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 6 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments electrical parameters dc supply voltage v sup -0.3 42 v transient up to 500ms duration en -0.3 v sup + 0.3 v v cc -0.3 7 v lin -27 +40 v reset, rx, tx -0.3 v cc + 0.3 v input current (latchup immunity) i scr -100 100 ma norm: jedec 78 electrostatic discharge electrostatic discharge (esd) norm: aec-q-100-002 2 kv for on board signals v cc , tx, rx, reset 4 for v sup 6 lin to v ss , hbm model continuous power dissipation total operating power dissipation (all supplies and outputs) p t 0.25 w epsoic8 in still air, soldered on jedec standard board @125o ambient, static operation = no time limit temperature ranges and storage conditions storage temperature (t strg ) -55 +150 oc package body temperature (t body ) +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 % moisture sensitive level 3 represents a maximum floor life time of 168h
www.ams.com/lin_companionic/as8530 revision 1.1 6 - 32 as8530 datasheet - electrical characteristics 6 electrical characteristics 6.1 operating conditions 6.2 digital inputs and outputs all pull-up, pull-downs hav e been implemented with active devices. reset and rx have b een measured with 100pf load. symbol parameter conditions min typ max units v sup positive supply voltage normal operating condition 6 18 v vss negative supply voltage 0 v t amb ambient temperature maximum junction temperature (t j ) 150oc -40 +125 oc i supp supply current 65 ma symbol parameter conditions min typ max units en input v ih high level input voltage high voltage pin which can also be connected to vsup 0.8v cc v v il low level input voltage 0.2v cc v i leak input leakage current en = l -1 +1 a i pd_en pull down current en = v cc 20 40 a tx v ih high level input voltage 0.8v cc v v il low level input voltage 0.2v cc v i leak input leakage current tx = v cc -1 +1 a i pu pull up current tx pulled to vss -30 -10 a reset v oh high level output voltage i out = 1 ma, v sup 6v v cc - 0.5 v v ol low level output voltage v sup 6v vss + 0.4 v rx v oh high level output voltage v cc - 0.5 v v ol low level output voltage i out = 1 ma, v sup 6v vss + 0.4 v
www.ams.com/lin_companionic/as8530 revision 1.1 7 - 32 as8530 datasheet - electrical characteristics 6.3 detailed system and block specifications 6.3.1 electrical system specifications 6.4 low dropout regulator the ldo block is a linear voltage regulator, which provides a regulated (band-gap stabilized) output voltage (v cc ) from the battery supply voltage (v sup ). (6v < v sup < 18v for option 1, 6v 500a) 10 mv/ma loreg_nm load regulation (normal mode) v cc / iccn (for i load > 500a) 1 mv/ma cl1 output capacitor (electrolytic) 2.2 10 f esr1 110 cl2 output capacitor (ceramic) 100 220 nf esr2 0.02 1 csup1e input capacitor (electrolytic) for emc suppression 10 100 f esr1_csup 110 csup2c input capacitor (ceramic) 100 220 nf esr2_csup 0.02 1
www.ams.com/lin_companionic/as8530 revision 1.1 8 - 32 as8530 datasheet - electrical characteristics 6.5 lin transceiver 6.5.1 dc electrical characteristics (4.5v < v cc < 5.5v; 6v < v sup < 18v; -40c < t j < 150c, vbus is the voltage on the lin node. all voltages ar e with respect to ground (vss); positive current flows into the pin. symbol parameter conditions min typ max units driver i bus_lim current limitation in dominant state 1 lin = v sup _max 1. this failure condition triggers thermal shut down when shut down temperature threshold is exceeded. 40 120 200 ma lin_v ol output voltage bus (dominant state), i lin = 40ma (short-circuit condition tested at v ol = 2.5v) 2v pull-up resistor normal mode (recessive bus level on tx pin) 20 40 60 k i bus_leak_rec driver off; v sup = 7.0v, 8v < vbus < 18 20 a receiver i bus_leak_dom input leakage current at receiver input leakage current at receiver driver off; vbus = 0v; v sup = 12v; v cc = 5v -1 ma i bus_no_gnd vss = v sup ; v sup = 12v; 0v < vbus < 18v, v cc = 5v 2 -1 1 ma i bus_no_bat v sup = vss; 0v < vbus < 18v, v cc = vss 2 2. not production tested. 100 a v bus_dom 0.4 v sup v bus_rec 0.6 v sup v bus_cnt v bus_cnt = (v th_dom + v th_rec )/2 3 3. vth_dom: receiver threshold of the recessive to dominant lin bus edge vth_rec : receiver threshold of the dominant to recessive lin bus edge 0.475 0.525 v sup v hys v hys = (v th_dom ? v th_rec ) 3 0.05 0.175 v sup
www.ams.com/lin_companionic/as8530 revision 1.1 9 - 32 as8530 datasheet - electrical characteristics 6.5.2 ac electrical characteristics lin driver, bus load conditions (c bus ; r bus ): 1nf; 1k / 6,8nf; 660 / 10nf; 500 note: sleep-mode to normal mode transition is identical to the power-on sequence after the remote wakeup event on lin bus. the transition time will include the t res (reset time) and start-up time for the ldo. symbol conditions min typ max units d1 (worst case 20kbps transmission) v th_rec (max) = 0.744 x vsup; v th_dom (max) = 0.581 x vsup; vsup = 6.0v to 18v; tbit = 50 s; d1 = tbus_rec(min) / (2 x tbit) 0.369 d2 (worst case 20kbps transmission) v th_rec (min) = 0.422 x vsup; v th_dom (min) = 0.284 x vsup; vsup = 6v to 18v; tbit = 50 s; d2 = tbus_rec(max) / (2 x tbit) 0.581 d3 (worst case 10.4kbps transmission) v th_rec (max) = 0.778 x vsup; v th_dom (max) = 0.616 x vsup; vsup = 6.0v to 18v; tbit = 96 s; d3 = tbus_rec(min) / (2 x tbit) 0.417 d4 (worst case 10.4kbps transmission) v th_rec (min) = 0.389 x vsup; v th_dom (min) = 0.251 x vsup; vsup = 6v to18v; tbit = 96 s; d4 = tbus_rec(max) / (2 x tbit) 0.59 t dlr v cc = 5v; propagation delay bus dominant to rx low 6s t dhr v cc = 5v; propagation delay bus dominant to rx high 6s t rs receiver delay symmetry -2 2 s t wake wake-up delay time 30 150 s t sln transition from standby mode to normal mode (clock frequency is 128khz 25%) 4 clock cycles t nsl transition from normal mode to standby mode (clock frequency is 128khz 25%) 6 clock cycles t rec_deb receiver de-bounce time 1 3 s c int guaranteed by design 220 250 pf
www.ams.com/lin_companionic/as8530 revision 1.1 10 - 32 as8530 datasheet - electrical characteristics figure 3. lin timing 6.5.3 temperature limiter 6.5.4 tx timeout watchdog symbol parameter conditions min typ max units t sd shut down temperature junction temperature 139 171 oc t ret return temperature during shut down, the sensor must be powered by vsup. thermal shut down disables ldo and sets all drivers to high impedance, the ic returns from shut down with por. 121 149 oc t otset over-temp warning flag set the temperature beyond which the warning flag is set. 121 149 oc t otclear over-temp warning flag clear the return temperature when the warning flag is cleared 103 127 oc symbol parameter conditions min typ max units t lin_wdog time out duration (dominant state) 0.5 1 2 s vth_rec(max) vth_dom(max) vth_rec(min) vth_dom(min) t bus_dom(max) t bus_rec(min) t bus_dom(min) t bus_rec(max) txd t bit t bit lin
www.ams.com/lin_companionic/as8530 revision 1.1 11 - 32 as8530 datasheet - electrical characteristics 6.6 v cc undervoltage reset and window watchdog the values in this table are valid for normal and standby modes. all parameters are tested, unless mentioned otherwise. symbol parameter conditions min typ max units vuvr_off v cc under-voltage threshold off (default) rising edge of v cc 2.55 2.95 v vuvr_on v cc under voltage threshold on (default) falling edge of v cc 2.3 2.7 v vuvr1_off v cc under voltage threshold off (factory option) rising edge of v cc 1 1. these are factory options which could be made available on specific request. 3.0 3.4 v vuvr1_on v cc under voltage threshold on (factory option) falling edge of v cc 1 2.75 3.15 v vuvr2_off v cc under voltage threshold off (factory option) rising edge of v cc 1 3.5 3.9 v vuvr2_on v cc under voltage threshold on (factory option) falling edge of v cc 1 3.25 3.65 v vuvr3_off v cc under-voltage threshold off (factory option) rising edge of v cc 1 4.0 4.4 v vuvr3_on v cc under voltage threshold on (factory option) falling edge of v cc 1 3.75 4.15 v vhyst_vcc hysteresis of under-voltage threshold on/off v cc default and all other factory options 0.1 0.25 0.4 v t rr spike filter on v cc to remove disturbance 4 s vsuvr_off v sup under-voltage threshold off 3.85 v vsuvr_on v sup under-voltage threshold on bor level (considered to be the master reset for as8530) 3.25 v wd_tcl wwd non-service time (if factory enabled) reset will be generated 1 2 2. -40%, -20%, +20%, +60%, and +100% timings are available as factory options. 0-75 0 -100 0-125 ms wd_tsv wwd service ? time (if factory enabled) reset will not be generated 1 75-150 100-200 125-250 ms t res reset delay time 4ms, 16ms, 32ms (typ) are factory options (min = -25% and max = +50% of typical) 6812ms t shd temporary shutdown reset active time 0.1 1 s
www.ams.com/lin_companionic/as8530 revision 1.1 12 - 32 as8530 datasheet - electrical characteristics 6.7 two port serial interface symbol parameter conditions min typ max units general br 2wire_spi bit rate 250 kbps t ensclk_h clock high time 2 s t ensclk_l clock low time 2 s write timing t di_su data in setup time 20 ns t di_hd data in hold time 10 ns read timing t do_s data out setup time 130 ns t do_hd data out hold time 135 ns t do_d data out delay 80 ns t di_hz data in to high impedance delay time for the microcontroller to release the tx bus 80 ns timing parameters when entering 2-wire sp mode t tx_su tx setup time before en goes low 20 ns t tx_hd tx hold time after en goes high 20 ns t tx_sp_trigger en falling edge to tx falling edge to enter into 2-wire sp mode 2 10 s t stndy_trigger tx high time from en falling edge to enter into sleep/standby mode 5 cycles t en_ensclk en falling edge to start of 2-wire serial port clock 5 cycles
www.ams.com/lin_companionic/as8530 revision 1.1 13 - 32 as8530 datasheet - detailed description 7 detailed description the as8530 chip consists of a low drop-out regulator and a lin bus transceiver, which is a bi-directional bus interface for dat a transfer between lin bus and the lin protocol controller. additionally integrated is a reset unit with a power-on-reset delay and a programmable window watchdog. it also includes a watchdog time-out on lin tx node to indicate if the microcontroller is stuck in a loop and to rele ase unintentional lin bus dominant state. 7.1 voltage regulator (ldo) the voltage regulator has three operating modes. the features of the operating modes are given below: ?? normal mode: stability to be better 0.25v over input range and temperature for load current up to 50ma. the ldo output provides a voltage of 5v or 3.3v as otp option. ?? standby mode: the standby mode is a low quiescent current mode used in car applications that are always switched on. the load current in standby mode is 5ma. quiescent current (no load) is less than 45ma typically at room temperature. ?? sleep mode: power down or temporary shutdown of the regulator can be set by a register bit. this bit can be written through 2-wire mcu interface. the ldo takes the input from bandgap and scales it up to the required voltage. the ldo starts charging only after the por-v sup event occurs (reset_vsup_n switched from low to high). the ldo can be powered- down by a control signal (temporary shutdown register) for the temporary shutdown mode. 7.2 temperature limiter temperature limiter produces a power down when temperature exceed s 155oc 10%. it powers up and generates a reset when it retur ns to 135oc 10% junction temperature. during thermal shut down, temperature sensor is supplied by v sup . during the temperature ramp-up phase, as soon as the temperature exceeds 135oc 10%, a warning signal is issued and is written into the diagnostic register, which ca n be read through the sp interface. 7.3 v sup undervoltage reset v sup undervoltage reset generates a reset reset_vsup_n, switched from low to high when v sup ramps up above vsuvr_off. this is used to enable proper initialization of mode control and diagnostic registers. if v sup < vsuvr_on, then reset_ vsup_n switches from high level to low level (active). this is considered to be the master reset and will have the highest priority over all other signal s. as soon as v sup < vsuvr_on, the ldo, lin transceiver is completely shut off and system comes to a complete stop. as8530 enters into the normal op erating mode only after v sup > vsuvr_off. 7.3.1 v sup undervoltage in normal mode supply voltages below vsuvr_off and above vsuvr_on do not influence the voltage regulator. the output voltage v cc follows v sup . 7.3.2 v sup undervoltage in standby mode / sleep mode no exit from the sleep mode or standby mode take place if the v sup voltage drops down to vsuvr_off. if v sup goes below vsuvr_on, reset_vsup_n is active and resets the mode control and diagnosti c register. the voltage regulator, lin transceiver modules are turned off. if v sup rises again above vsuvr_off, reset_vsup_n is switched from low to hi gh. the system enters norma l mode where lin transceiver and ldo are switched on. 7.3.3 v sup undervoltage in low slew mode the behavior of as8530 at low v sup voltages is equal to the sleep mode. the low slew mode (set by control register through serial interface as an option) will be cancelled, if v sup drops below vsuvr_on in this mode. the as8530 enters the normal mode, if v sup rises again above vsuvr_off.
www.ams.com/lin_companionic/as8530 revision 1.1 14 - 32 as8530 datasheet - detailed description 7.4 reset reset generates an external reset signal to reset the microcontroller a nd all other exter nal circuits. the reset functionality is illustrated in figure 4 . reset consists of a digi tal buffer at the output. reset sign al can be affected by reset_vcc_n (which is the u nder-voltage res et on v cc ) and window watchdog output. all those conditions which cause a drop in the v cc voltage will be detected from the low voltage reset unit, which in-turn generates a reset signal. states like temporary shut-down, over-temperature monitor will influence the reset outp ut through reset_vcc_n signal only. figure 4. reset functionality 7.5 v cc undervoltage reset the por-vcc generates reset_vcc_n signal as output which determines under-voltage reset of the output of the ldo. the rising ed ge of the v cc gives an under-voltage reset ?off? and the falling edge of the v cc gives an under-voltage reset ?on?. this under-voltage signal is used to control the reset output. when v cc rises up vuvr_off for a period greater than reset duration (tres) then reset_vcc_n switches from low level to high level and pin r eset is inactive (high). if v cc falls below vuvr_on for a period grea ter than a predetermined delay (trr) then reset_vcc_n switches from high level to low level an d pin reset is active (low). the rese t_vcc_n signal is us ed to initializes window watchdog timer, tx time-out, test control circuits, 2-wire sp, and logic associated with sp (everything other than the sp contr ol registers). v cc under-voltage reset threshold voltage level adjustment can be made by 2 bit otp as explained in otp interface. 7.6 window watchdog (wwd) to keep the external microcontroller always in proper function state, a window watchdog circuit is implemented. the wwd trigger is generated by external mcu through sp interface. if the window is missed, a reset on the reset pin with certain reset time (t res ) is generated. the wwd function can be e nabled or disabled by fact ory setting. the watchdog is started after the assp exits reset. under normal workin g conditions, microcontroller gives a wwd trigger every time in the window peri od of wd_tsv (service time). if the trigger does not occur dur ing wd_tsv or occurs too early during wd_tcl (n on-service time), then reset ou tput is pulled low (active), wh ich will reset the micro-control ler. wwd circuit is turned on after the reset pin goe s back to high (inactive). if v cc < vuvr_on, wwd circuit is switched off. when the wwd function is enabled, there is a 3-bit factory programming available to set the trigger window. vcc vsup vuvr_off t res t rr t>tj t www.ams.com/lin_companionic/as8530 revision 1.1 15 - 32 as8530 datasheet - detailed description figure 5. window watchdog trigger 7.7 lin transceiver the transceiver provides short circuit limitation, hardware watchdog and over temperature shut down features. the tx watchdog t imer is active when tx is pulled low (active). as soon as the tx watchdog timeout occurs, the lin bus is released from dominant state to reces sive state. the lin transceiver has a pull-up resistor (for the slave node; extra resistor externally for the master node) to the v sup . a diode protection is available to protect it from back supply from bus line. the lin transmitter has the basic functionality of relaying the data from the micro-controller on to the lin. the data on the l in needs to have controlled slew to have reduced emi. the receiver relays the data from the lin to the micro-controller. this transmitter has op timized emc performance across different loading conditions conforming to the lin 2.1 standards. the wake-up detects a wake up event on the lin. 7.8 operating modes and states the as8530 provides four main operating modes ?normal?, ?sleep /stand-by? (programmed by otp), ?temporary shutdown? and ?thermal shutdown?. the lin transceiver can be programmed to operate with lower slew in the normal mode. refer to table 3 for a detailed description on transition for each mode. 7.8.1 normal mode this is the mode after the power-up. in normal mode, ldo, lin transceiver, window watchdog, resistive divider and the line driv ers are all turned on. all the blocks are completely functional. ldo is now capable of delivering maximum load current possible as per the device specifications. the lin transceiver is capable of sending the tx data from microcontroller to the lin bus at a maximum rate of 20kbps. en signal is set to high and lin, tx, rx pins can be driven into dominant (low) or recessive (high) states. if the junction temper ature increases more than t otset , a warning flag is set in the diagnostic register, which can be read through the 2-wire interface. 7.8.2 standby mode standby mode is a functional low-power mode where lin transceiver is disabled. the lin wake-up circuit and over-temperature mon itor circuit is enabled. window watchdog, tx timeout watchdog, resistive divider, relay driver circuits are disabled. en pin held low in thi s mode. tx pin is in recessive state (high). cs is pulled to v cc while sdi and sclk ou tputs are pulled to vss. 7.8.3 sleep mode as a factory programming option on request the as8530 offers as a replacement to the standby mode with sleep mode. sleep mode i s the most current saving mode. if en is held low, the ldo, lin transceiver and the reset and window watchdog unit will be switched off. v cc is pulled down to zero. the lin wake-up circuit, oscillator and over-temperature monitor circuit is active. lin bus is in recessive state (high). only wake- up possible is through remote wake-up, through lin pin, pulling it to dominant state for 100s typical (low), can change the st ate of the system. period non-service time (wd_tcl) service time (wd_tsv) trigger restart period trigger via spi last trigger point earliest possible trigger point (system will not reset) latest possible trigger point (system will not be reset) 50 % 100 % valid trigger point (system will not be reset) unwanted trigger point (system will be reset)
www.ams.com/lin_companionic/as8530 revision 1.1 16 - 32 as8530 datasheet - detailed description 7.8.4 temporary shutdown mode in this mode, the v cc is pulled down and the ldo is powered down. this mode is introduced to interface with other components which do not have a pin for the reset functionality. this provides an alternative way to reset those components interfacing with as8530. thi s mode is default disabled but can be enabled by an otp option. in this mode, all internal modules supplied by the ldo are disabled. only the osc illator, control registers are enabled. the v cc output can be temporarily switched off and pulled to vss. en signal, rx, tx is pulled low and lin transceiver along with the lin wake-up circuit is powered down. no remote wake-up functionality is possible. lin bus enters into recessive state. the system goes out of this mode to normal mode after the time-out of an internal counter delay (t shd ). normal mode to temporary shutdown transition will be controller by register bit in configuration register. 7.8.5 thermal shutdown state if the junction temperature t j is higher than t sd , the as8530 will be switched into the thermal shutdown mode. the transceiver is completely disabled. no wake-up functionality is available. window watchdog, tx timeout watchdog, and ldo are completely turned off. only the over- temperature monitor would be working. as soon as the temperature returns back to t ret , the system enters normal mode. for more information on transition, see table 3 . note: l = low state, h = high state, ot = over-temperature reset, uvcc = undervoltage v cc , uvbat = undervoltage vbat, rwake =remote wake, x = do not care. table 3. transition table transition interface reg. 0x05 d0 flags comments from mode to mode lin rx tx en rwake uvbat ot uvcc normal mode stand-by x-rs x-h 2 h 3 h-l 3 l x x inactive inactive tx is high for t stndy_triggerr sleep 1 1. chosen by factory programming option x-rs x-h 2 h 3 h-l 3 l x x inactive set tx is high for t stndy_triggerr 1 temporary shutdown x-rs x-h 2 x h 3 h x x inactive set the control bit is set through the 2-wire sp interface over- temperature x-rs x-h 2 xxlxx set set stand-by mode normal (lw) x h-x 2 x l-h 3 l x x inactive inactive normal (rw) x h-x 2 h x l set x inactive inactive remote wake up event occurred on lin temporary shutdown rs h 2 hl h 3 xxinactiveset the control bit is set through the 2-wire sp interface over- temperature rs h 2 hllxx set set temporary shutdown mode normal rs-x h-x 2 x x l x x inactive clear internal 128ms timer expired sleep mode 3 normal rs-x h-x 2 x x l set x inactive clear remote wake up event occurred on lin over- temperature rs h 2 2. effect of transition x x l x x set hold temperature monitor output asserted (covered by scan) all statespower offxxxxxx l-h 3 3. cause for transition xx
www.ams.com/lin_companionic/as8530 revision 1.1 17 - 32 as8530 datasheet - detailed description 7.9 state diagram the complete functional state machine for as8530 is illustrated in figure 6 . some soft-states in the fsm like ?txwd wait?, ?standby wait? and other ?wait? states have been included for the sake of completeness. figure 6. finite state machine model for the as8530 system reset timeout otp load init0 normal wait_test wait_otp ovtemp temporary shutdown sleep vsup > vsuvr_off otp_load rx=0 test_en t e m p o r ar y shu t d o w n o t p _ e n temperature > tsd temperature > tsd temperature > tsd temperature < tret s t a n d b y standby & sleep r w ak e _ w a i t 128msec rwake vcc < vuvr_on reset time > t res t e m p o r a r y s h u t d o w n vcc < vuvr_on || wwdtimeout standby wait txwd_timeout temperature > tsd ! s t a n d b y t e m p o r a r y s h u t d o w n txwd wait tx=1 t e m p o r a r y s h u t d o w n temperature > tsd temperature > tsd vcc < vuvr_on r x = 0 rwake temperature > tsd vcc < vuvr_on || wwdtimeout standby
www.ams.com/lin_companionic/as8530 revision 1.1 18 - 32 as8530 datasheet - application information 8 application information 8.1 initialization when the power supply is switched on, if v sup > vsuvr_off, reset_vsup_n becomes inactive (high). after this, the voltage regulator starts with a default ldo output setting of 3.3v and vuvr_off setting of 2.75v. if v cc > vuvr_off (2.75v), active-low porn_2_otp is generated. the rising edge of porn_2_otp loads contents of fuse onto the otp latch after load access time t load . load_otp_in_prereg signal loads contents of otp latch onto the pre-regulator domain register. th is register gives actual settings of ldo, vuvr_off and reset ti meout period t res . this is done because the otp block is powered by the v cc . if v cc > vuvr_off (phase 2), reset timeout is restarted. reset signal is de- asserted after reset timeout period t res (phase 2) and then device enters into normal mode. the circuit initializes correctly also for very slow ramp on v sup (of the order of 0.5v/min). figure 7. initialization sequence for as8530 ldo off ldo on vuvr_off = 2.75v, ldo setting = 3.3v t res = 4msec ldo on vuvr_off = from otp block, ldo setting = from otp block t res = from otp block vcc vsup device settings reset_vcc_n reset_vsup_n porn_2_otp load_otp_in_prereg reset vuvr_off vsuvr_off 6 cycles of rc-oscillator phase 1 phase 2 if phase 1 por threshold == phase 2 por threshold tres = reset timeout from otp block if phase 1 por threshold != phase 2 por threshold tres = reset timeout from otp block vuvr_off
www.ams.com/lin_companionic/as8530 revision 1.1 19 - 32 as8530 datasheet - application information 8.2 wake-up if the regulator is put into sleep/standby mode, it can be woken up with the bus interface. a transition on the bus (high to lo w) with a minimum predefined low time (t wake ) puts the regulator into normal mode. 8.3 over-temperature shutdown if the junction temperature increases beyond t sd the over-temperature recognition will be activated and the regulator voltage will be switched off. the v cc voltage drops down, the reset state is entered and the bus transceiver is switched off (recessive state). after t j falls below t ret , the as8530 will be initialized again. this initialization starts independently from the voltage levels on en and bus. within the th ermal shutdown mode, the transceiver cannot switch to the normal mode either with local or with remote wake-up. the operation of the as8530 is possible between t j (125oc) and the switch off temperature t sd , but small parameter differences can appear. after over-temperature switch-off, the ic initializes as explained in initialization on page 18 . the low slew mode for lin transceiver has to be selected again on re-initialization, if necessary. 8.4 lin bus transceiver the as8530 has an integrated bi-directional bus interface device for data transfer between lin bus and the lin protocol control ler. the transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage c omparator followed by a de-bouncing unit. 8.4.1 transmit mode during transmission the data at the pin tx will be transferred to the bus driver to generate a bus signal. to minimize the elec tromagnetic emission of the bus line, the bus driver has an integrated slew rate control and wave shaping unit. transmitting will be interrupted in the following cases: ?? sleep mode ?? thermal shutdown active ?? master reset (v sup < vsuvr_on) the recessive bus level is generated from the integrated 30k pull up resistor in serial with an active diode this diode prevent s the reverse current of vbus during differential voltage between v sup and bus (vbus>v sup ). no additional termination resistor is necessary to use the as8530 in lin slave nodes. if this ic is used for lin master nodes it is necessary that the bus pin is terminated via an extern al 1k resistor in series with a diode to vbat. table 4. v sup >vsuvr_on and v cc www.ams.com/lin_companionic/as8530 revision 1.1 20 - 32 as8530 datasheet - application information 8.4.2 receive mode the data signals from the bus pin will be transferred continuously to the pin rx. short spikes on the bus signal are suppressed by the implemented de-bouncing circuit. including all tolerances the lin specific receive threshold values of 0.4*v sup and 0.6*v sup will be securely observed. figure 8. receive mode impulse diagram 8.5 rx and tx interface input tx. the 5v input tx controls directly the bus level. lin transmitter acts like a slew-controlled level shifter. a dominant state (l ow) on tx leads to the lin bus being pulled low (dominant state) too. the tx pin has an internal active pull up connected to v cc . this guarantees that an open tx pin generates a recessive bus level. figure 9. tx input circuitry t < t deb_bus t < t deb_bus rx bus 40% 50% 60% v thr_max v thr_min v thr_hys v thr_cnt as8530 vcc mcu rc-filter (10ns) vcc i pu_txd tx
www.ams.com/lin_companionic/as8530 revision 1.1 21 - 32 as8530 datasheet - application information output rx. the received bus signal will be output to the rx pin: bus < vthr_cnt ? 0.5 * vthr_hys rx = low bus > vthr_cnt + 0.5 * vthr_hys rx = high this output is a push-pull driver between v cc and gnd with an output current of 1ma. figure 10. rx output circuitry 8.6 mode input en the as8530 is switched from normal mode to the standby/sleep mode with a falling edge on en and keeping tx high for t stndy_trigger time. device is switched from standby mode to normal mode with a rising edge at the en pin. the mode change for as8530 with a falling edge at en can be done independently from the state of the bus transceiver. device enters into serial port mode by forcing en low and driv ing tx high to low within t tx_sp_trigger time after en forced to low. this ensures the direct control of device to enter into standby/sleep mode by microcontroller using en pin. figure 11. en pin functionality the en input has an internal active pull down to secure that if this pin is not connected, a low level will be generated. mcu as8530 vcc rx en tx rd wr len 1 len 0 a4 d3 d2 d1 d0 normal mode normal mode serial port mode normal mode standby/sleep mode entry into serial port mode t tx_su t tx_hd t tx_su t tx_sp_trigger t stndy_trigger t en_ensclk
www.ams.com/lin_companionic/as8530 revision 1.1 22 - 32 as8530 datasheet - application information figure 12. enable controlled via. mcu if the application doesn?t need the wake up capability of the as8530, a direct connection en to v cc is possible. in this case the as8530 operates in permanent normal mode. also possible is the external (outside of the module) control of the en line via. v sup signal as shown below. figure 13. permanent normal mode en vsup vss vcc reset rx tx as8530 mcu c load v bat lin + + 5v en vsup vss vcc reset rx tx as8530 mcu c load v bat lin + + 5v
www.ams.com/lin_companionic/as8530 revision 1.1 23 - 32 as8530 datasheet - application information 8.7 serial port interface the interface is essentially used to trigger the window watchdog, to access test mode and read out diagnostic information for t he as8530. the description of this interface and the protocol is explained below. information on block status and errors can be displayed by d iagnosis registers. 8.7.1 device configuration using 2-wire serial port the as8530 device configuration register is programmed via a 2-wire serial programming interface. en/scl is used as serial cloc k and tx/ sda_io is used as serial data. en is used as clock input to access serial port registers in serial port mode. also en is used t o control transition from normal mode to standby/sleep mode. the tx input of the device will be multiplexed as following: ?? lin tx for transmitting data from microcontroller on lin bus ?? sda_io for serial data input/output, this will be used for serially accessing data from configuration and status register sp frame. a frame is formed by first byte for command and address/configuration and following bit stream that can be formed by an integer number of bytes. command is coded rd/wr on the first bits, length of the transfer is indicated by len1, len2 bits while address is given on lsb 5 bits. write command. for write command rd/wr = 0 after the command code, length of the transfer is send in next two bits, the address of register to be written has to be provid ed from the msb to the lsb. then one, two, four, or eight data bytes can be transferred from the msb to the lsb. for each data byte following the first one, used address is the incremented value of the previously written address. each bit of the frame has to be driven by the 2-wire sp mas ter on the sp clock (en pin) positive edge and the 2-wire sp slave (device) samples this bit on the next sp clock (en pin) negative edge. in the following figures two examples of write command (without and with address self-increment). figure 14. protocol for serial data write with length = 1 table 6. command bits command bits register address or transmission configuration rd/wr len1 len2 a4 a3 a2 a1 a0 rd/wr command description 0 write address writes data byte on the given starting address. 1 read address read data byte from the given starting address. table 7. transfer length len1 len2 length description 001 transfer consists of single data phase. after completion of single data phase device comes out of serial port interface. 012 transfer consist of two data phase. 104 transfer consist of four data phase. 118 transfer consist of eight data phase. en tx 0 len1 len0 a4 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d7 d6 transfer edge sampling edge data d7 ? d0 is moved to address a4..a0 here len1 = 0 len0 = 0 command & address phase data phase length of transaction = 1
www.ams.com/lin_companionic/as8530 revision 1.1 24 - 32 as8530 datasheet - application information figure 15. protocol for serial data write with length = 4 read command. for read command rd/wr=1. after the command code, length of the transfer is send in next two bits, the address of register to be read has to be provided from the msb to the lsb. then one, two, four or eight data bytes can be transferred from the spi slave to the master, always from the msb to the ls b. each bit of the command and address sections of the frame have to be driven by the 2-wire sp master on the sp clock (en pin) po sitive edge and the 2-wire sp slave (device) samples this bit on the next sp clock (en pin) negative edge. each bit of the data phase of th e frame has to be driven by the 2-wire sp slave (device) on the sp clock (en pin) positive edge and the 2-wire sp master samples this bit on the next sp clock (en pin) negative edge. the following figures illustrate two examples of read command (without and with address self-increment. ) figure 16. protocol for serial data read with length = 1 en tx 1 len1 len0 a 4 a 0 a 1 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 data d7-d0 is moved to address a4-a0 here 10 command & address phase data1 phase data2 phase data3 phase data4 phase len1 = 1 len0 = 0 length = 4 data d7-d0 is moved to address a4-a0 + 1 here data d7-d0 is moved to address a4-a0 + 2 here data d7-d0 is moved to address a4-a0 + 3 here en tx 0 len1 len0 a4 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d7 d6 transfer edge sampling edge data d7 ? d0 at address a4 ..a0 is read here len1 = 0 len0 = 0 command & address phase data phase length of transaction = 1 transfer edge sampling edge
www.ams.com/lin_companionic/as8530 revision 1.1 25 - 32 as8530 datasheet - application information figure 17. protocol for serial data read with length = 4 timing. the following figures illustrate timing waveforms and parameters. figure 18. timing for writing figure 19. timing for reading en tx 1 len1 len0 a 4 a 0 a 1 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 data d7-d0 at address a4-a0 is read here data d7-d0 at address a4-a0 +1 is read here data d7-d0 at address a4-a0 +2 is read here data d7-d0 at address a4-a0 +3 is read here data d7-d0 at address a4-a0 +4 is read here 10 command & address phase data1 phase data2 phase data3 phase data4 phase len1 = 1 len0 = 0 length = 4 tx en t ensclk_l t ensclk_h t di_hd t di_su datai datai tx en t ensclk_l t ensclk_h t di_hd t di_su datai datao datao t d0_d t di_hz t d0_d
www.ams.com/lin_companionic/as8530 revision 1.1 26 - 32 as8530 datasheet - application information 8.8 control and diagnosis registers the serial interface can be used as interface between the assp as 8530 and an external micro-controller. the interface is a slav e and only the micro-controller can start the communication. this interface will be used for device configuration, entering into test mode and carrying out diagnostic options. refer to table 8 for details on the configuration registers. 8.8.1 definition of cont rol and status registers a total of 32 control, diagnosis and test registers, each of 8-bit can be accessed using the 2-wire serial interface. table 8 provides a description of all control and status registers. table 8. configuration registers address register name por value rd / wr description control and configuration register 0 x 03 device configuration register on por_vcc 0000_1111 rd / wr d0 reserved d1 reserved d2 reserved d3 enable / disable lin transceiver 0 disabled 1 enabled d7?d4 reserved 0 x 04 device control register on por_vsup 0000_0001 rd / wr d7... d1 reserved 0 x 05 temporary shutdown register on por_vcc 0000_0000 rd / wr d0 temporary shutdown control bit 0 no temporary shutdown 1 enter into temporary shutdown d7?d1 reserved 0 x 06 window watch dog trigger register on por_vcc 0000_0000 wr d0 window watch dog trigger this bit will be set by mcu to indicate trigger event. if this trigger occurs outside t he window of watch dog coun ter, then reset signal is asserted. also on this trigger wwd counter is restarted and this bit will be cleared internally within 2 cycles of 128khz clock. d7 ? d1 reserved 0 x 07 low side driver data register on por_vcc 0000_0000 rd / wr d7 ? d0 reserved
www.ams.com/lin_companionic/as8530 revision 1.1 27 - 32 as8530 datasheet - application information note: when the device is powered on @ ambient temperature of 125oc, the status of the ovtemp140 can be high indicating an over temperature warning. this is because 125oc is within the limits for the ovtemp140. diagnosis register 0 x 08 diagnostic register 1 on por_vsup 0000_0011 rd d7..d0 = dr[7:0] 8 lsb bits of the 24 bit diagnostic register d0 porvsup (set when vsup < vsuvr_on, cleared after c read) d1 uvvcc under voltage vcc (set when vcc < vuvr_on, cleared after c read) d2 otemp160 over-temperature reset. (set when temp > t sd , cleared after c read) d3 otemp140 over-temperature warning (set when temp > t otset , cleared after c read) d4 ovvbat overvoltage vbat. (set when vsup > vovthh, cleared after c read) d5 reserved d6 rwake remote wakeup (set on remote wakeup event on lin bus, cleared after c read) d7 wwdt window watchdog timeout. (set on failure of window watchdog timeout, cleared after c read) 0 x 09 diagnostic register 2 on por_vsup 0000_0000 rd d7..d0 = dr[15:8] next 8 lsb bits of the 24 bit diagnostic register. d0 txtimeout tx timeout of 1sec. (set on tx low > 1sec, cleared after c read) d1 tempshut this bit is set on entering into temporary shutdown state and cleared after c read. d7 d2 reserved table 8. configuration registers address register name por value rd / wr description
www.ams.com/lin_companionic/as8530 revision 1.1 28 - 32 as8530 datasheet - package drawings and markings 9 package drawings and markings the device is available in a ep-soic8 package. figure 20. drawings and dimensions as8530 * yywwizz * the device marking for the vcc=5v option will change to as8530a .
www.ams.com/lin_companionic/as8530 revision 1.1 29 - 32 as8530 datasheet - package drawings and markings notes: 1. dimensions and tolerancing conform to asme y14.5m -1994 . 2. all dimensions are in miilimeters. angles are in degrees. 3. datums a and b to be determined at datum h. 4. extrusion of exposed area in bottom side is 0.20mm typical. marking: yywwizz. yy ww i zz last two digits of the manufacturing year manufacturing week plant identifier traceability code symbol min nom max a- -1.70 a1 0.00 - 0.15 a2 1.25 - - b0.31 - 0.51 c0.17 - 0.25 d - 4.90 bsc - d1 2.24 3.10 3.20 e - 6.00 bsc - e1 - 3.90 bsc - e2 1.55 2.41 2.51 e - 1.27 bsc - l 0.41 0.64 0.89 symbol min nom max l1 - 1.04 ref - l2 - 0.25 bsc - h0.25 - 0.50 0o - 8o aaa - 0.10 - bbb - 0.20 - ccc - 0.10 - ddd - 0.25 - eee - 0.10 - fff - 0.15 - n8
www.ams.com/lin_companionic/as8530 revision 1.1 30 - 32 as8530 datasheet - revision history revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 1.0 26 nov, 2010 mbl initial release 29 nov, 2010 kpt marking details updated under ordering information. 1.1 03 jun, 2011 mbl updated package drawings and markings, ordering information. dec 31, 2012 sju updated ordering table.
www.ams.com/lin_companionic/as8530 revision 1.1 31 - 32 as8530 datasheet - ordering information 10 ordering information the devices are available as the standard products shown in table 9 . note: all products are rohs compliant and ams green. buy our products or get free samples online at www.ams.com/icdirect technical support is available at www.ams.com/technical-support for further information and requests, email us at sales@ams.com (or) find your local distributor at www.ams.com/distributor table 9. ordering information 1 1. for both product versions , the reset delay time t res as well as undervoltage threshold are set to default value and window watchdog is disabled. on special request, optional factory settings can be made available on specific vendor addendum. ordering code description delivery form package AS8530-ASOP lin transceiver with integrated voltage regulator and mcu interface (3.3v version) 2 2. also available as 5v version. tape and reel (2500 pcs) soic-8 as8530-asom tape and reel (500 pcs) soic-8
www.ams.com/lin_companionic/as8530 revision 1.1 32 - 32 as8530 datasheet - copyrights copyrights copyright ? 1997-2013, ams ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all right s reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written con sent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by ams ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by description rega rding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without addi tional processing by ams ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the stan dard production flow, such as test flow or test location. the information furnished here by ams ag is believed to be correct and accurate. however, ams ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruptio n of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, perfo rmance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of ams ag rendering of technical or other services. contact information headquarters ams ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel : +43 (0) 3136 500 0 fax : +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.ams.com/contact

▲Up To Search▲

Price & Availability of AS8530-ASOP

	To Download AS8530-ASOP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .