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dual hdmi fast switching receiver with 12-bit, 170 mhz video and graphics digitizer a nd 3d comb filter decoder adv7842 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010-2011 analog devices, inc. all rights reserved. features dual hdmi? 1.4a fast switching receiver hdmi support 3d tv support content type bits cec 1.4-compatible extended colorimetry 256-ball, 17 mm 17 mm bga package hdmi 225 mhz receiver xpressview fast switching of hdmi ports 3d video format support including frame packing 1080p 24 hz, 720p 50 hz, 720p 60 hz full colorimetry support including sycc601, adobe rgb, adobe ycc 601 36-/30-bit deep color and 24-bit color support hdcp 1.4 support with internal hdcp keys adaptive hdmi equalizer integrated cec controller hdmi repeater support 5 v detect and hot plug assert for each hdmi port hdmi audio support including hbr and dsd advanced audio mute feature flexible digital audio output interfaces supports up to 5 s/pdif outputs supports up to 4 i 2 s outputs video and graphics digitizer four 170 mhz, 12-bit adcs 12-channel analog input mux 525i-/625i-component analog input 525p-/625p-component progressive scan support 720p-/1080i-/1080p-component hdtv support low refresh rates (24 hz/25 hz/30 hz) support for 720p/1080p digitizes rgb graphics up to 1600 1200 at 60 hz (uxga) scart fast blank support 3d video decoder ntsc/pal/secam color standards support ntsc/pal 2d/3d motion detecting comb filter advanced time-base correction (tbc) with frame synchronization interlaced-to-progressive conversion for 525i and 625i if compensation filters vertical peaking and horizontal peaking filters robust synchronization extraction for poor video source advanced vbi data slicer general highly flexible 36-bit pixel output interface internal edid ram for hdmi and graphics dual stdi (standard identification) function support any-to-any, 3 3 color space conversion (csc) matrix 2 programmable interrupt request output pins simultaneous analog processing and hdmi monitoring applications advanced tvs pdp hdtvs, lcd tvs (hdtv ready) lcd/dlp? rear projection hdtvs crt hdtvs, lcos? hdtvs avr video receivers lcd/dlp front projectors hdtv stbs with pvr projectors functional block diagram adc adc adc adc input mux output mux output mux cvbs scart g scart cvbs scart rgb + cvbs graphics rgb cvbs yc hdmi 1 hdmi 2 hd ypbpr sd/ps ypbpr scart b scart r y/g pb/b pr/r i 2 s s/pdif dsd hbr mclk sclk cvbs hs/vs field/de clk hs/vs field/de clk 36-bit ycbcr/rgb audio output mclk sclk to audio processor data hs/vs field/de clk data 48 36 4 5 sdram tmds ddc tmds ddc deep color hdmi rx fast switch hdcp keys adv7842 08849-001 sdp cvbs 3d yc s-video scart cp ypbpr 525p/625p 720p/1080i 1080p/ uxga rgb figure 1.
adv7842 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? general description ......................................................................... 3 ? detailed functional block diagram .............................................. 4 ? specifications ..................................................................................... 5 ? electrical characteristics ............................................................. 5 ? power specifications .................................................................... 6 ? analog specifications ................................................................... 8 ? video specifications ..................................................................... 8 ? timing characteristics ................................................................ 9 ? timing diagrams ........................................................................ 10 ? absolute maximum ratings .......................................................... 11 ? package thermal performance ................................................. 11 ? esd caution ................................................................................ 11 ? power supply sequencing .............................................................. 12 ? power-up sequence ................................................................... 12 ? power-down sequence .............................................................. 12 ? pin configuration and function descriptions ........................... 13 ? functional overview ...................................................................... 20 ? hdmi receiver ........................................................................... 20 ? analog front end ....................................................................... 20 ? standard definition processor ................................................. 21 ? component processor ............................................................... 21 ? other features ............................................................................ 22 ? external memory requirements .................................................. 23 ? single data rate (sdr) .............................................................. 23 ? double data rate (ddr) .......................................................... 23 ? pixel input/output formatting .................................................... 24 ? pixel data output modes features .......................................... 24 ? register map architecture ............................................................ 25 ? outline dimensions ....................................................................... 26 ? ordering guide .......................................................................... 26 ? revision history 1/11rev. spa to rev. b updated revision number ................................................ universal updated publication code ............................................................ 28 10/10rev. sp0 to rev. spa changes to product title and features section ............................ 1 changes to note 1, table 1 ....................................................................... 5 added note 1, table 5 ............................................................................... 9 changes to pin no. c11 description, table 7 .................................... 14 changes to pin no. n11 description, table 7 and pin no. p11 description, table 7 ................................................................................. 18 6/10revision sp0: initial version
adv7842 rev. b | page 3 of 28 general description the ad v7842 is a high quality, single - chip, 2:1 multiplexed hdmi? receiver and graphics digitizer with an integrated multiformat video decoder. the adv7842 incorporates a dual input hdmi 1.4 - compatible receiver that supports all hdtv formats up to 1080p and display resolutions up to uxga (160 0 1200 at 60 hz). the adv7842 incorporates xpressview? fast switching on both input hdmi ports. using the analog devices , inc., hardware - based hdcp engine that minimizes software overhead, xpressview technology allows fast switching between any hdmi inp ut ports in less than 1 second. the adv7842 supports all mandatory hdmi 1.4 3d tv formats in addition to all hdtv formats up to 1080p , 36 - bit deep color. the adv7842 also integrates an hdmi v1.4 cec controller that supports the capability discovery and c ontrol (cdc) feature. the adv7842 offers a flexible audio output port for the audio data decoded from the hdmi stream. hdmi audio formats, including super audio cd (sacd) via dsd and hbr are supported. each hdmi port has dedicated 5 v d etect and h ot p lug a ssert pins. the hdmi receiver also includes an integrated equalizer that ensures robust operation of the interface with cable lengths up to 30 meters. the hdmi receiver has advanced audio functionality, such as a mute controller, that prevents audible ext raneous noise in the audio output. the multiformat 3d comb filter decoder supports the conversion of pal, ntsc, and secam standards in the form of a composite or an s - video input signal into a digital itu - r bt.656 format. scart and overlay functionality ar e enabled by the ability of the adv7842 to process cvbs and standard definition rgb signals simultaneously. the adv7842 contains one main component processor (cp) that processes ypbpr and rgb component formats, including rgb graphics. the cp also processes the video signals from the hdmi receiver. the adv7842 can operate in dual hdmi and analog input mode, thus allowing for fast switching between the adcs and hdmi. the adv7842 supports the decoding of a component rgb/ ypbpr video signal into a digital ycbcr or rgb pixel output stream. the support for component video includes 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well as many other smpte and hd standards. the adv7842 supports graphics digitization. the adv7842 is capable of digi tizing rgb graphics signals from vga to uxga rates and converting them into a digital rgb or ycbcr pixel output stream. internal edid is available for one graphic port. fabricated in an advanced cmos process, the adv7842 is provided in a 17 mm 17 mm, 256 - ball, bga, surface - mount, rohs - compliant package and is specified over the ? 10c to +70 c tempera ture range.
adv7842 rev. b | page 4 of 28 detailed functional block diagram adc0 clam p 12 adc1 clam p 12 adc2 clam p 12 adc3 clam p 12 (a) (b) (c) (d) (a) (b) (c) 12 12 12 cec controller 5v detect and h pa controller edid/ repeater controller hdc p eeprom pll equal- izer equal- izer hdc p block sampler sampler f ast switching block + hdmi decode + mux dee p color conversion hs/cs, vs/field contro l contro l and d at a fi lter p acket processor 4:2:2 t o 4:4:4 conversion p acket/ infoframe memory vsi decoder i 2 c readback ancilla ry dat a form a tter f ast i 2 c inter f ace video d at a processor interrupt controller audio processor audio output form a tter video output form a tter ttx_sda/ttx_sc l sync_out field/de vs/field hs/cs llc p0 t o p 11 p12 t o p23 p24 t o p35 int1 int2 ap0 ap1 ap2 ap3 ap4 ap5 sclk mclk active peak and hsync depth noise and calibr a tion offset adder gain contro l digi tal fine clam p program- mable del ay macrovision and cgms detection cp csc and decim a tion fi l ters a v code insertion st andard identific a tion sync extract (esdp) sync source and polarit y detect component processor digi tal processing block st andard definition processor (sdp) 2d comb 3d comb ddr/sdr-sdram inter f ace tbc vertica l peaking horizon tal peaking cti and l ti st andard au t odection macrovision detection interlace t o progressive conversion decim a tion fi l ters color s p ace conversion f astblank overlay contro l aout cvbs yc scart rgb yprpb rgb sync1 sync2 hs_in1/tri5 vs_in1/tri6 hs_in2/tri7 vs_in2/tri8 tri1 t o tri4 scl sda a vlink cec rxa_5v/h p a_ a rxb_5v/h p a_b ddca_sda/ddca_sc l ddcb_sda/ddcb_sc l rxa_c rxb_c rxa_0 rxa_1 rxa_2 rxb_0 rxb_1 rxb_2 12-channe l input ma trix analog front end llc gener a tion sync processing and clock gener a tion tri-level slicer i 2 c contro l inter f ace a vlink controller 08849-002 mux figure 2 . detailed functional block diagram
adv7842 rev. b | page 5 of 28 specifications avdd = 1.8 v 5%, cvdd = 1.8 v 5%, dvdd = 1.8 v 5%, pvdd = 1.8 v 5%, dvddio = 3.3 v 5%, tvdd = 3.3 v 5%, vdd_sdram = 3.2 v to 3.4 v (sdr) , vdd_sdram = 2.35 v to 2.65 v (ddr). t min to t max = ? 10c to +70c, unless otherwise noted. electrical character istics table 1. parameter symbol test conditions /comments min typ max unit static performance resolution (each adc) n 12 bits integral nonlinearity inl 27 mhz (at a 12 - bit level) ? 3.0 to +8.0 lsb 54 mhz (at a 12 - bit level) ?3.0 to +8.0 lsb 74.25 mhz (at a 12 - bit level) ?4.0 to +7.0 lsb 108 mhz (at a 11 - bit level) ?3.5 to +8.0 lsb 170 mhz (at a 9 - bit level) ?0.7 to +1.5 lsb differential nonlinearity dnl 27 mhz (at a 12 - bit level) ?0.7 to +0.8 lsb 54 mhz (at a 1 2- bit level) ?0.7 to +0.8 lsb 75 mhz (at a 12 - bit level) ?0.7 to +0.8 lsb 108 mhz (at a 11 - bit level) ?0.7 to +0.8 lsb 170 mhz (at a 9 - bit level) ?0.6 to +0.5 lsb digital inputs input high voltage v ih xtaln and xtalp pins 1.2 v input low voltage v il xtaln and xtalp pins 0.4 v v ih other digital inputs 2 v v il other digital inputs 0.8 v input current i in reset pin 60 a ep_miso pin 60 a spdif_in pin 60 a test4 pin 60 a test6 p in 60 a other digital inputs 10 a input capacitance c in 10 pf digital inputs (5 v tolerant) 1 input high voltage v ih 2.6 v input low voltage v il 0.8 v input current i in ?82 +82 a digital outputs output high voltage v oh 2.4 v output low voltage v ol 0.4 v high impedance leakage current i leak 10 a output capacitance c out 20 pf 1 the following pins are 5 v tolerant: hs_in1/tri5, hs_in2/tri7, vs_in1/tri6, vs_in2/tri8, rxa_5v, rxb_5 v, ddca_scl, ddca_sda, ddcb_scl, and ddcb_sda.
adv7842 rev. b | page 6 of 28 power specifications table 2. parameter symbol min typ max unit test conditions /comments power requirements digital core power supply vdd 1.75 1.8 1.85 v digital i/o power supply dvddio 3.14 3.3 3.46 v sdram power supply vdd_sdram 3.2 3.3 3.4 v sdr memory vdd_sdram 2.35 2.5 2.65 v ddr memory pll power supply pvdd 1.71 1.8 1.89 v analog power supply avdd 1.71 1.8 1.89 v terminator power supply tvdd 3.14 3.3 3.46 v comparator power supply cvdd 1.71 1.8 1.89 v current consumption 1 , 2 , 3 digital core supply current i v dd 155 220 ma analog 1080p sampling at 148 mhz 148 196 ma rgb g raphics sampling at 162 mhz 285 343 ma rgb g raphics sampling at 162 mhz in simultaneous mode with both background ports enabled 163 176 ma hdmi 1080p: 12 - bit deep color 216 273 ma hdmi 1080p: 12 - bit deep color in simultaneous mode with both background ports enabled 194 230 ma cvbs processing 332 378 ma cvbs processing in simultaneous mode with both background ports enabled 57 72 ma sd 576i component processing 197 224 ma sd 576i component processing in simultaneous mode with both background ports enabled 270 289 ma scart p rocessing 404 435 ma scart p rocessing in simultaneous mode with both background ports enabled digital i/o supply current i dvddio 51 109 ma analog 1080p sampling at 148 mhz 41 129 ma rgb g raphics sampling at 162 mhz 45 117 ma rgb g raphics sampling at 162 mhz in simultaneous mode with both background ports enabled 27 32 ma hdmi 1080p: 12 - bit deep color 22 150 ma hdmi 108 0p: 12 - bit deep color in simultaneous mode with both background ports enabled 9 11 ma cvbs processing 10 11 ma cvbs processing in simultaneous mode with both background ports enabled 8 11 ma sd 576i component processing 8 11 ma sd 576i comp onent processing in simultaneous mode with both background ports enabled 10 11 ma scart p rocessing 10 12 ma scart p rocessing in simultaneous mode with both background ports enabled
adv7842 rev. b | page 7 of 28 parameter symbol min typ max unit test conditions /comments pll supply current i pvdd 28 30 ma analog 1080p sampling at 148 mh z 25 27 ma rgb graphics sampling at 162 mhz 25 28 ma rgb g raphics sampling at 162 mhz in simultaneous mode with both background ports enabled 35 36 ma hdmi 1080p: 12 - bit deep color 35 38 ma hdmi 1080p: 12 - bit deep color in simultaneous mode with both background ports enabled 34 37 ma cvbs processing 35 37 ma cvbs processing in simultaneous mode with both background ports enabled 22 24 ma sd 576i component processing 22 24 ma sd 576i component processing in simultaneous mode with both background ports enabled 34 37 ma scart p rocessing 35 37 ma scart p rocessing in simultaneous mode with both background ports enabled analog supply current i avdd 279 295 ma analog 1080p sampling at 148 mhz 281 297 ma rgb graphics sam pling at 162 mhz 285 301 ma rgb g raphics sampling at 162 mhz in simultaneous mode with both background ports enabled 0.1 0.3 ma hdmi 1080p: 12 - bit deep color 0.1 0.3 ma hdmi 1080p: 12 - bit deep color in simultaneous mode with both background por ts enabled 85 89 ma cvbs processing 86 91 ma cvbs processing in simultaneous mode with both background ports enabled 267 281 ma sd 576i component processing 270 285 ma sd 576i component processing in simultaneous mode with both background p orts enabled 283 294 ma scart p rocessing 286 301 scart p rocessing in simultaneous mode with both background ports enabled terminator supply current 4 i tvdd 85 95 ma one p ort c onnected 120 135 ma two p orts c onnected comparator supply current i cvdd 120 130 ma hdmi 1080p: 12 - bit deep color 220 250 ma hdmi 1080p: 12 - bit deep color in simultaneous mode with both background ports enabled memory interface supply current i vdd_sdram 28 35 ma cvbs input sampling at 54 mhz power - down curren ts 5 i dvddio 0.1 ma i vdd_sdram 2.6 ma i vdd 10 ma i avdd 0.1 ma i cvdd 0.5 ma i tvdd 1.1 ma i pvdd 1.7 ma power - up time t pwrup 25 ms 1 all maximum current values are guaranteed by characterization to assist in power supply design. 2 typical current consumption values are recorded with nomina l voltage supply levels, smpte b ar video pattern , and at room temperature. 3 maximum current consumption values are recorded with maximum rated voltage supply levels, moirex video pattern , and at maximum rated temperature. 4 termination power supply includes tvdd current consumed off chip. 5 power - down m ode entered by setting bit power_down high.
adv7842 rev. b | page 8 of 28 analog specification s table 3. parameter test conditions /comm ents min typ max unit clamp circuitry 1 input impedance clamps switched off 10 m analog (ain1 ? ain12) adc midscale (cml) 0.91 v adc full - scale level cml + 0.55 v adc zero - scale level cml ? 0.55 v adc dynamic range 1.1 v cl amp level (when locked) component input, y signal cml ? 0.12 v component input, pr signal cml v component input, pb signal cml v pc rgb input (r, g, b signals) cml ? 0.12 v cvbs input cml ? 0.205 v scart rgb input (r, g, b signals) cm l ? 0.205 v s- video input (y signal) cml ? 0.205 v s- video input (c signal) cml v large clamp source current sdp only 0.3 ma large clamp sink current sdp only 0.4 ma fine clamp source current sdp only 9 a fine clamp sink current sdp onl y 8 a 1 specified for e xternal c lamp c apacitor of 100 nf . video specifications table 4. parameter symbol test conditions /comments min typ max unit nonlinear specifications differential phase dp cvbs input (modulated five - step) 0.6 degrees differential gain dg cvbs i nput (modulated five - step) 0.8 % luma nonlinearity lnl cvbs input (modulated five - step) 0.9 % noise specifications measured at 27 mhz llc snr unweighted luma ramp 63 db snr unweighted luma flat field 64 db analog front - end crosstalk 60 db lock time specifications (sdp) horizontal lock range 5 % vertical lock range 40 70 hz subcarrier lock range f sc 0.8 khz color lock - in time 60 lines sync depth range 1 20 200 % color burst range 1 200 % vertical l ock time 300 ms horizontal lock time 100 lines chroma specifications (sdp) chroma amplitude error 0.9 % chroma phase error 0.3 degrees chroma luma intermodulation 0.3 % 1 nominal synchronization depth is 300 mv at 100% of the synchronization depth range.
adv7842 rev. b | page 9 of 28 timing characteristi cs data and i 2 c timing characteri stic table 5. parameter 1 symbol test conditions/comments min typ max unit clock and crystal crystal frequency, xtal 28.63636 mhz crystal frequency stability 50 ppm horizontal sync input frequency 10 110 khz llc frequency range 12.825 170 mhz i 2 c ports scl frequency 400 khz scl minimum pulse width high t 1 600 ns scl minimum pulse width low t 2 1.3 s start condition hold time t 3 600 ns start condition setup time t 4 600 ns sda setup time t 5 100 ns scl and sda rise time t 6 1000 ns scl and sda fall time t 7 300 ns stop condition setup time t 8 0.6 s ttx i 2 c ports scl frequency 3.4 mhz scl minimum pulse width high t 1 60 ns scl minimum pulse width lo w t 2 160 ns start condition hold time t 3 160 ns start condition setup time t 4 160 ns sda setup time t 5 10 ns scl and sda rise time t 6 10 80 ns scl and sda fall time t 7 10 80 ns stop condition setup time t 8 160 ns reset feature reset pulse width 5 ms clock outputs llc mark - space ratio t 9 :t 10 45:55 55:45 % duty cycle data and control outputs 2 data output transition time sdr (sdp) t 11 end of valid data to negative clock edge 2.9 4.6 ns data output tra nsition time sdr (sdp) t 12 negative clock edge to start of valid data 0.2 0.6 ns data output transition time sdr (cp) t 13 end of valid data to negative clock edge 1.5 2.2 ns data output transition time sdr (cp) t 14 negative clock edge to start of valid data 0.1 0.3 ns i 2 s port, master mode sclk mark - space ratio t 15 :t 16 45:55 55:45 % duty cycle lrclk data transition time t 17 end of valid data to negative sclk edge 10 ns lrclk data transition time t 18 negative sclk edge to start of valid da ta 10 ns i2sx data transition time t 19 end of valid data to negative sclk edge 5 ns i2sx data transition time t 20 negative sclk edge to start of valid data 5 ns 1 guaranteed by characterization. 2 with the dll block on output clock byp assed.
adv7842 rev. b | page 10 of 28 timing diagrams 08849-003 sda scl t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 figure 3 . i 2 c timing 08849-004 t 9 llc p0 to p35, hs/cs, vs/field, field/de t 11 t 12 t 10 figure 4 . pixel port and control sdr output timing (sdp) 08849-005 t 9 llc p0 to p35, vs/field, hs/cs, field/de t 13 t 14 t 10 figure 5 . pixel port and control sdr output timing (cp) sclk lrclk i2sx left-justified mode i2sx right-justified mode i2sx i 2 s mode msb msb ? 1 t 15 t 16 t 17 t 19 t 20 t 18 msb msb ? 1 lsb msb t 19 t 20 t 19 t 20 notes 1. the suffix x refers to 0, 1, 2, and 3 ending pin names. 2. lrclk is a signal accessible via ap5 pin. 3. i2sx are signals accessible via ap1 to ap4 pins. 08849-006 figure 6. i 2 s timing
adv7842 rev. b | page 11 of 28 absolute maximum rat ings table 6. parameter rating avdd to gnd 2.2 v vdd to gnd 2.2 v pvdd to gnd 2.2 v dvddio to gnd 4.0 v vdd_sdram to gnd 4.0 v cvdd to gnd 2.2 v tvdd to gnd 4.0 v avdd to pvdd ?0.3 v to +0.3 v avdd to vdd ?0.3 v to +0.3 v tvdd to cvdd ?0.3 v to +2.2 v d vd dio to vdd_sdram ?0.3 v to +3.3 v vdd_sdram to avdd ?0.3 v to +2 v vdd_sdram to vdd ?0.3 v to +2 v digital inputs voltage to gnd ?0.3 v to dvddio + 0.3 v digital outputs voltage to gnd ?0.3 v to dvddio + 0.3 v 5 v tolerant digital inputs to gnd 1 5.5 v analog inputs to gnd ?0.3 v to avdd + 0.3 v xtaln and xtalp to gnd ?0.3 v to pvdd + 0.3 v maximum junction temperature (t j max ) 125c storage temperature range ?65c to +150c infrared reflow soldering (20 sec) 260c 1 the following inputs are 3. 3 v inputs but are 5 v tolerant: hs_in1/tri5, hs_in2/tri7, vs_in1/tri6, vs_in2/tri8, ddca_scl, ddca_sda, ddcb_scl and ddcb_sda. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . package thermal perf ormance to reduce power consumption when using the adv7842, the user is advised to turn off unused sections of the part. due to pcb metal variation, and therefore variation in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with the ja value. the maximum junction temperature (t j max ) of 125c must not be exceeded. the following equation calculates the junction tempera - ture using the measured package surface temperature and applies only when no heat sink is used on the device under test (dut): ( ) total jt s j wtt += where: t s is the package sur face temperature (c). jt = 0.5c/w for the 256 - ball bga. w total = ( pvdd i pvdd ) + (0.4 tvdd i tvdd ) + ( cvdd i cvdd ) + ( avdd i avdd ) + ( vdd i vdd ) + ( a dvddio i dvddio ) + ( vdd_sdram i vdd_sdram ) where: 0.4 reflects the 40% of tvdd power that is dissipated on the par t itself. a = 0.5 w hen the output pixel clock is > 74 mhz. a = 0.75 when the output pixel clock is 74 mhz. esd caution
adv7842 rev. b | page 12 of 28 power supply sequenc ing power - up sequence the recommended power - up sequence of the adv7842 is as follows: 1. 3.3 v s upplies 2. 2.5 v s upply ( a pplies only if using ddr memory) 3. 1.8 v s upplies 08849-009 3.3v supplies power-up power supply (v) 3.3v supplies 1.8v supplies 2.5v supplies (if any) 2.5v supplies power-up 1.8v supplies power-up 3.3v 2.5v 1.8v figure 7 . recommended power - up sequence notes reset should be held low while the supplies are being powered up. ? 3.3 v supplies should be powered up first. ? 2.5 v supply s hould be powered after the 3.3 v supplies are established but before the 1.8 v supplies. ? 1.8 v supplies should be powered up last. the adv7842 can alternatively be powered up by simulta - neously asserting a ll supplies . in this case, care must be taken to e nsure that a lower rated supply does not go above a higher rated supply level, because the supplies are being established. power - down sequence the adv7842 supplies can be deasserted simultaneously as long as a higher rated supply does not go below a lowe r rated supply.
adv7842 rev. b | page 13 of 28 pin configuration and function descripti ons a b c d e f g h j k l m n p r t a b c d e f g h j k l m n p r t 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 gnd tvdd rxa_c? rxa_0? rxa_1? rxa_2? gnd rxb_c? rxb_0? rxb_1? rxb_2? tvdd p0 p1 p3 gnd xt al p tvdd rxa_c+ rxa_0+ rxa_1+ rxa_2+ gnd rxb_c+ rxb_0+ rxb_1+ rxb_2+ tvdd sync_out p2 p4 p5 xt aln gnd cvdd cvdd cvdd pwrdn1 rxa_5v rxb_5v hp a_ a hp a_b gnd hs/cs vs/field p6 p7 pvdd pvdd vga_sd a vga_sc l cvdd rterm ddca_sc l ddca_sd a ddcb_sc l ddcb_sd a cec gnd field/de ep_miso p8 p9 refn ref p vs_in2/tri8 hs_in2/tri7 cvdd cvdd gnd gnd gnd gnd gnd gnd ep_mosi ep_cs p10 gnd tri3 tri4 ain 11 ain12 a vdd gnd gnd gnd gnd gnd gnd dvddio ttx_scl ep_sck p11 p12 ain8 ain9 sync4 ain10 a vdd gnd gnd gnd gnd gnd gnd dvddio mclk ttx_sda p13 p14 sync3 ain7 tri2 tri1 a vdd gnd gnd gnd gnd gnd gnd dvddio ap5 ap0 p15 p16 gnd sync2 ain4 ain6 a vdd gnd gnd gnd gnd vdd gnd dvddio ap4 sclk p17 p18 ain3 ain2 vs_in1/tri6 ain5 a vdd gnd gnd vdd vdd vdd vdd dvddio ap1 ap3 p19 p20 sync1 ain1 hs_in1/tri5 aout a vdd gnd gnd vdd vdd vdd vdd dvddio ap2 scl p21 p22 gnd gnd gnd gnd gnd gnd vdd_sdram vdd_sdram vdd_sdram vdd_sdram vdd_sdram dvddio int1 sda p23 gnd sdram_cke sdram_ck sdram_dq 11 sdram_dq15 sdram_dq4 sdram_ldqs sdram_cs sdram_a0 sdram_a4 sdram_a8 test6 reset test4 int2 p24 llc sdram_ck sdram_udqs sdram_dq12 sdram_vref sdram_dq3 sdram_dq7 sdram_ras sdram_a10 sdram_a3 sdram_a7 sdram_a 11 test7 a vlink test5 p26 p25 sdram_dq8 sdram_dq9 sdram_dq13 sdram_dq0 sdram_dq2 sdram_dq6 sdram_cas sdram_ba1 sdram_a2 sdram_a6 sdram_a9 p34 p32 p30 p28 p27 gnd sdram_dq10 sdram_dq14 sdram_dq1 gnd sdram_dq5 sdram_we sdram_ba0 sdram_a1 sdram_a5 gnd p35 p33 p31 p29 gnd 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 08849-007 test8 figure 8 . pin configuration (top view)
adv7842 rev. b | page 14 of 28 table 7 . pin function descriptions pin no. mnemonic type description a1 gnd ground ground. a2 p3 d igital video output video pixel output port. a3 p1 digital video output video pixel output port. a4 p0 digital video output video pixel output port. a5 tvdd power terminator supply voltage (3.3 v). a6 rxb_2 ? hdmi input digital input channel 2 complement of port b in the hdmi interface. a7 rxb_1 ? hdmi input digital input channel 1 complement of port b in the hdmi interface. a8 rxb_0 ? hdmi input digital input channel 0 complement of port b in the hdmi interface. a9 rxb_c ? hdmi input digital input clock complement of port b in the hdmi interface. a10 gnd ground ground. a11 rxa_2 ? hdmi input digital input channel 2 complement of port a in the hdmi interface. a12 rxa_1 ? hdmi input digital input channel 1 complement of port a in the hdmi interface. a13 rxa_0 ? hdmi input digital input channel 0 complement of port a in the hdmi interface. a14 rxa_c ? hdmi input digital input clock complement of port a in the hdmi interface. a15 tvdd power terminator supply voltage (3.3 v). a16 gnd ground ground. b1 p5 d igital video output video pixel output port. b2 p4 digital video output video pixel output port. b3 p2 digital video output video pixel output port. b4 sync_out miscellaneous digital sliced synchronization output b5 tvdd power terminator supply voltage (3.3 v). b6 rxb_2+ hdmi input digital input channel 2 true of port b in the hdmi interface. b7 rxb_1+ hdmi input digital input channel 1 true of port b in the hdmi interface. b8 rxb_0+ hdmi input digital input channel 0 true of port b in the hdmi inter face. b9 rxb_c+ hdmi input digital input clock true of port b in the hdmi interface. b10 gnd ground ground. b11 rxa_2+ hdmi input digital input channel 2 true of port a in the hdmi interface. b12 rxa_1+ hdmi input digital input channel 1 true of port a in the hdmi interface. b13 rxa_0+ hdmi input digital input channel 0 true of port a in the hdmi interface. b14 rxa_c+ hdmi input digital input clock true of port a in the hdmi interface. b15 tvdd power terminator supply voltage (3.3 v). b16 xtalp misc ellaneous analog input pin for 28.63636 mhz crystal or external 1.8v, 28.63636 mhz clock oscillator source to clock the adv7842. c1 p7 digital video output video pixel output port. c2 p6 digital video output video pixel output port. c3 vs/field digital video output vertical synchronization/field synchronization. vs is a vertical synchronization output signal in the cp and hdmi processor. field is a field synchronization output signal in all interlaced video modes. vs or field can be configured for this p in. c4 hs/cs digital video output horizontal synchronization/composite synchronization. hs is a horizontal synchronization output signal in the cp and hdmi processor. cs (composite synchronization) signal is a single signal containing both horizontal and vertical synchronization pulses. hs or cs can be configured for this pin. c5 gnd ground ground. c6 hpa_b miscellaneous digital hot plug assert signal output for hdmi port b. c7 hpa_a miscellaneous digital hot plug assert signal output for hdmi port a. c8 rxb_5v hdmi input 5 v detect pin for port b in the hdmi interface. c9 rxa_5v hdmi input 5 v detect pin for port a in the hdmi interface. c10 pwrdn1 miscellaneous digital controls the power - up of the adv7842. should be connected to a digital 3.3 v i/o supply to power up the adv7842. c11 test8 test pin t ie this pin to ground via 4.7 k r esistor . c12 cvdd power comparator supply voltage (1.8 v). c13 cvdd power comparator supply voltage (1.8 v). c14 cvdd power comparator supply voltage (1.8 v).
adv7842 rev. b | page 15 of 28 pin no. mnemonic type description c15 gnd ground ground. c16 xtaln miscellaneous analog input pin for 28.63636 mhz crystal. d1 p9 digital video output video pixel output port. d2 p8 digital video output video pixel output port. d3 ep_miso digital input spi master in/slave out for external edid interface. d4 field/de miscellaneous digital data enable ( de) . de is a signal th at indicates active pixel data. field sync hronization output sig nal in all interlaced video modes (field) . de or field can be configured for this pin. d5 gnd ground ground. d6 cec digital input/output consumer electronic control channel. d7 ddcb_sda d igital input/output hdcp slave serial data port b. ddcb_sda is a 3.3 v input/output that is 5 v tolerant. d8 ddcb_scl digital input hdcp slave serial clock port b. ddcb_scl is a 3.3 v input that is 5 v tolerant. d9 ddca_sda digital input/output hdcp slav e serial data port a. ddca_sda is a 3.3 v input/output that is 5 v tolerant. d10 ddca_scl digital input hdcp slave serial clock port a. ddca_scl is a 3.3 v input that is 5 v tolerant. d11 rterm miscellaneous analog s ets internal termination resistance. a 500 r esistor between this pin and gnd should be used. d12 cvdd power comparator supply voltage (1.8 v). d13 vga_scl miscellaneous digital ddc port serial clock input for vga d14 vga_sda miscellaneous digital ddc port serial data input/output for vga d15 pvdd power pll supply voltage (1.8 v). d16 pvdd power pll supply voltage (1.8 v). e1 gnd ground ground. e2 p10 digital video output video pixel output port. e3 ep_cs digital output spi chip select for external edid interface. e4 ep_mosi digital output spi master out/slave in for external edid interface. e5 gnd ground ground. e6 gnd ground ground. e7 gnd ground ground. e8 gnd ground ground. e9 gnd ground ground. e10 gnd ground ground. e11 cvdd power comparator supply voltag e (1.8 v). e12 cvdd power comparator supply voltage (1.8 v). e13 hs_in2/tri7 miscellaneous analog hs on graphics port 2 (hs_ in 2) . the hs input signal is used for 5 - wire timing mode. trilevel / bilevel input on the scart or d - terminal connector (tri7) . (sel ection available via the i 2 c.) e14 vs_in2/tri8 miscellaneous analog vs on graphics port 2 (vs_in2) . the vs input signal is used for 5 - wire timing mode. trilevel / bilevel input on the scart or d - terminal connector (tri8) . (selection available via the i 2 c.) e15 refp miscellaneous analog internal voltage reference output. e16 refn miscellaneous analog internal voltage reference output. f1 p12 digital video output video pixel output port. f2 p11 digital video output video pixel output port. f3 ep_sck digi tal output spi clock for external edid interface. f4 ttx_scl miscellaneous digital fast i 2 c interface for teletext data extraction. ttx_scl is used as the i 2 c port serial clock input. f5 dvddio power digital i/o supply voltage (3.3 v). f6 gnd ground gro und. f7 gnd ground ground. f8 gnd ground ground. f9 gnd ground ground. f10 gnd ground ground. f11 gnd ground ground. f12 avdd power analog supply voltage (1.8 v).
adv7842 rev. b | page 16 of 28 pin no. mnemonic type description f13 ain12 analog video input analog video input channel. f14 ain11 analog video input analog video input channel. f15 tri4 miscellaneous analog trilevel or bilevel input on the scart or d - type connector. (selection available via the i 2 c.) f16 tri3 miscellaneous analog trilevel or bilevel input on the scart or d - type connector. (selection available via the i 2 c.) g1 p14 digital video output video pixel output port. g2 p13 digital video output video pixel output port. g3 ttx_sda miscellaneous digital fast i 2 c interface for teletext data extraction. ttx_sda is used as the i 2 c port serial d ata input/output pins. g4 mclk miscellaneous audio master clock output. g5 dvddio power digital i/o supply voltage (3.3 v). g6 gnd ground ground. g7 gnd ground ground. g8 gnd ground ground. g9 gnd ground ground. g10 gnd ground ground. g11 gnd groun d ground. g12 avdd power analog supply voltage (1.8 v). g13 ain10 analog video input analog video input channel. g14 sync4 miscellaneous analog this is a synchronization on green or luma input (sog/soy) used in embedded synchronization mode. user config urable. g15 ain9 analog video input analog video input channel. g16 ain8 analog video input analog video input channel. h1 p16 digital video output video pixel output port. h2 p15 digital video output video pixel output port. h3 ap0 miscellaneous audi o output pin. h4 ap5 miscellaneous audio output pin. h5 dvddio power digital i/o supply voltage (3.3 v). h6 gnd ground ground. h7 gnd ground ground. h8 gnd ground ground. h9 gnd ground ground. h10 gnd ground ground. h11 gnd ground ground. h12 av dd power analog supply voltage (1.8 v). h13 tri1 miscellaneous analog trilevel or bilevel input on the scart or d - type connector. (selection available via i 2 c.) h14 tri2 miscellaneous analog trilevel or bilevel input on the scart or d - type connector. (se lection available via i 2 c.) h15 ain7 analog video input analog video input channel. h16 sync3 miscellaneous analog this is a synchronization on green or luma input (sog/soy) used in embedded synchronization mode. user configurable. j1 p18 digital video output video pixel output port. j2 p17 digital video output video pixel output port. j3 sclk miscellaneous digital audio serial clock output. j4 ap4 miscellaneous audio output pin. j5 dvddio power digital i/o supply voltage (3.3 v). j6 gnd ground grou nd. j7 vdd power digital core supply voltage (1.8 v). j8 gnd ground ground. j9 gnd ground ground. j10 gnd ground ground. j11 gnd ground ground. j12 avdd power analog supply voltage (1.8 v). j13 ain6 analog video input analog video input channel .
adv7842 rev. b | page 17 of 28 pin no. mnemonic type description j1 4 ain4 analog video input analog video input channel. j15 sync2 miscellaneous analog this is a synchronization on green or luma input (sog/soy) used in embedded synchronization mode. user configurable. j16 gnd ground ground. k1 p20 digital video output video pixel output port. k2 p19 digital video output video pixel output port. k3 ap3 miscellaneous audio output pin. k4 ap1 miscellaneous audio output pin. k5 dvddio power digital i/o supply voltage (3.3 v). k6 vdd power digital core supply voltage (1.8 v). k7 vdd power digital core supply voltage (1.8 v). k8 vdd power digital core supply voltage (1.8 v). k9 vdd power digital core supply voltage (1.8 v). k10 gnd ground ground. k11 gnd ground ground. k12 avdd power analog supply voltage (1.8 v). k13 ain5 analog video input analog video input channel. k14 vs_in1/tri6 miscellaneous analog vs on graphics port 1 (vs_in1) . the vs input signal is used for 5 - wire timing mode. trilevel / bilevel input on the scart or d - terminal connector (tri6) . (selecti on available via the i 2 c.) k15 ain2 analog video input analog video input channel. k16 ain3 analog video input analog video input channel. l1 p22 digital video output video pixel output port. l2 p21 digital video output video pixel output port. l3 scl miscellaneous digital i 2 c port serial clock input. scl is the clock line for the control port. l4 ap2 miscellaneous audio output pin. l5 dvddio power digital i/o supply voltage (3.3 v). l6 vdd power digital core supply voltage (1.8 v). l7 vdd power d igital core supply voltage (1.8 v). l8 vdd power digital core supply voltage (1.8 v). l9 vdd power digital core supply voltage (1.8 v). l10 gnd ground ground. l11 gnd ground ground. l12 avdd power analog supply voltage (1.8 v). l13 aout analog monito r output analog monitor output. l14 hs_in1/tri5 miscellaneous analog hs on graphics port 1 (hs_in1) . the hs input signal is used for 5 - wire timing mode. trilevel / bilevel input on the scart or d - terminal connector (tri5) . (selection available via the i 2 c.) l15 ain1 analog video input analog video input channel. l16 sync1 miscellaneous analog this is a synchronization on green or luma input (sog/soy) used in embedded synchronization mode. user configurable. m1 gnd ground ground. m2 p23 digital video outp ut video pixel output port. m3 sda miscellaneous digital i 2 c port serial data input/output pin. sda is the data line for the control port. m4 int1 miscellaneous digital interrupt. this pin can be active low or active high. when status bits change, this p in is triggered. the events that trigger an interrupt are under user control. m5 dvddio power digital i/o supply voltage (3.3 v). m6 vdd_sdram power external memory interface digital input/output supply (ddr 2.5 v or sdr 3.3 v). m7 vdd_sdram power exter nal memory interface digital input/output supply (ddr 2.5 v or sdr 3.3 v). m8 vdd_sdram power external memory interface digital input/output supply (ddr 2.5 v or sdr 3.3 v). m9 vdd_sdram power external memory interface digital input/output supply (ddr 2. 5 v or sdr 3.3 v). m10 vdd_sdram power external memory interface digital input/output supply (ddr 2.5 v or sdr 3.3 v). m11 gnd ground ground.
adv7842 rev. b | page 18 of 28 pin no. mnemonic type description m12 gnd ground ground. m13 gnd ground ground. m14 gnd ground ground. m15 gnd ground ground. m16 gnd ground ground. n1 llc digital video output line - locked output clock for the pixel data. n2 p24 digital video output video pixel output port. n3 int2 miscellaneous digital interrupt. this pin can be active low or active high. when status bits change, this pin i s triggered. the events that trigger an interrupt are under user control. n4 test4 test connect this pin to ground. n5 reset miscellaneous digital system reset input. active low. a minimum low reset pulse width of 5 ms is required to re set the adv7842 circuitry. n6 test6 test float this pin. n7 sdram_a8 sdram interface address output. interface to external ram address lines. n8 sdram_a4 sdram interface address output. interface to external ram address lines. n9 sdram_a0 sdram interfa ce address output. interface to external ram address lines. n10 sdram_cs sdram interface chip select. sdram_cs enables and disables the command decoder on the ram. one of four command signals to the external sdram. n11 sdram_ldqs sdram interface lower data strobe pin. data strobe pins are used for the ram interface. this is an input when reading data from external memory and an output when writing data to external memory. it is edge aligned with data when reading from external memory and centered with data when writing to external memory . sdram_ ldqs corresponds to the data on sdram_dq7 to sdram_dq 0. n12 sdram_dq4 sdram interface data bus. interface to external ram 16 - bit data bus. n13 sdram_dq15 sdram interface data bus. interface to external ram 16 - bit data bus. n14 sdram_dq11 sdram interface data bus. interface to external ram 16 - bit data bus. n15 sdram_ck sdram interface differential clock output. all address and control output signals to the ram should be sampled on the positive edge of sdram_ck and on the negative edge of sdram_ck . n16 sdram_cke sdram interface clock enable. this pin acts as an enable to the clock signals of the external ram. p1 p25 digital video output video pixel output port. p2 p26 digital v ideo output video pixel output port. p3 test5 test connect this pin to ground. p4 avlink digital input/output digital scart control channel. p5 test7 test float this pin. p6 sdram_a11 sdram interface address output. interface to external ram address li nes. p7 sdram_a7 sdram interface address output. interface to external ram address lines. p8 sdram_a3 sdram interface address output. interface to external ram address lines. p9 sdram_a10 sdram interface address output. interface to external ram address lines. p10 sdram_ras sdram interface row address select command signal. one of four command signals to the external sdram. p11 sdram_dq7 sdram interface data bus. interface to external ram 16 - bit data bus. p12 sdram_dq3 sdram interfac e data bus. interface to external ram 16 - bit data bus. p13 sdram_vref sdram interface 1.25 v reference for ddr sdram interface or 1.65 v for sdr sdram interface. p14 sdram_dq12 sdram interface data bus. interface to external ram 16 - bit data bus. p15 sdram_udqs sdram interface upper data strobe pin. data strobe pins are used for the ram interface. this is an input when reading data from external memory and an output when writing data to external memory . it is edge aligned with data when reading from exter nal memory and centered with data when writing to external memory . sdram_udqs corr esponds to the data on sdram_dq15 to sdram_dq8 . p16 sdram_ck sdram interface differential clock output. all address and control output signals to the ram should be sampled on the positive edge of sdram_ck and on the negative edge of sdram_ck . r1 p27 digital video output video pixel output port. r2 p28 digital video output video pixel output port. r3 p30 digital video output video pixel o utput port. r4 p32 digital video output video pixel output port.
adv7842 rev. b | page 19 of 28 pin no. mnemonic type description r5 p34 digital video output video pixel output port. r6 sdram_a9 sdram interface address output. interface to external ram address lines. r7 sdram_a6 sdram interface address output. inter face to external ram address lines. r8 sdram_a2 sdram interface address output. interface to external ram address lines. r9 sdram_ba1 sdram interface bank address output. interface to external ram bank address lines. r10 sdram_cas sdra m interface column address select command signal. one of four command signals to the external sdram. r11 sdram_dq6 sdram interface data bus. interface to external ram 16 - bit data bus. r12 sdram_dq2 sdram interface data bus. interface to external ram 16 -b it data bus. r13 sdram_dq0 sdram interface data bus. interface to external ram 16 - bit data bus. r14 sdram_dq13 sdram interface data bus. interface to external ram 16 - bit data bus. r15 sdram_dq9 sdram interface data bus. interface to external ram 16 - bit data bus. r16 sdram_dq8 sdram interface data bus. interface to external ram 16 - bit data bus. t1 gnd ground ground. t2 p29 digital video output video pixel output port. t3 p31 digital video output video pixel output port. t4 p33 digital video output vi deo pixel output port. t5 p35 digital video output video pixel output port. t6 gnd ground ground. t7 sdram_a5 sdram interface address output. interface to external ram address lines. t8 sdram_a1 sdram interface address output. interface to external ram address lines. t9 sdram_ba0 sdram interface bank address output. interface to external ram bank address lines. t10 sdram_we sdram interface write enable output command signal. one of four command signals to the external sdram. t11 sdr am_dq5 sdram interface data bus. interface to external ram 16 - bit data bus. t12 gnd ground ground. t13 sdram_dq1 sdram interface data bus. interface to external ram 16 - bit data bus. t14 sdram_dq14 sdram interface data bus. interface to external ram 16 -b it data bus. t15 sdram_dq10 sdram interface data bus. interface to external ram 16 - bit data bus. t16 gnd ground ground.
adv7842 rev. b | page 20 of 28 functional overview hdmi receiver the adv7842 front end incorporates a 2:1 multiplexed hdmi 1.4 receiver with xpressview fast switc hing technology and support for hdmi 1.4 features such as 3d tv . building on the feature set of analog device existing hdmi devices, the adv7842 also offers support for all hd tv formats up to 12 - bit, 1080p deep color and all display resolutions up to uxga (1600 1200 at 60 hz). xpressview fast switching technology, using analog devices hardware - based hdcp engine that minimizes software overhead, allows switching between the two input ports in less than 1 second. with the inclusion of hdcp 1.4, the adv784 2 can receive encrypted video content. the hdmi interface of the adv7842 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewal of that authentication during transmission, as specified by the hdcp 1.4 protoco l. repeater support is also offered by the adv7842. the hdmi receiver incorporates active equalization of the hdmi data signals. this equalization compensates for the high frequency losses inherent in hdmi and dvi cabling, especially at longer lengths and higher frequencies. it is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance at even the highest hdmi data rates. the hdmi receiver offers advanced audio functionality. it supports multichannel i 2 s audio for up t o eight channels. it also supports a 6 - dsd channel interface with each channel carrying an over - sampled 1 - bit representation of the audio signal as delivered on sacd. the adv7842 can also receive hbr audio packet streams and outputs them through the hbr in terface in an spdif format conforming to the iec60958 standard. the receiver contains an audio mute controller that can detect a variety of conditions that may result in audible extraneous noise in the audio output. on detection of these conditions, the a udio signal can be ramped to mute to prevent audio clicks or pops. hdmi receiver features include: ? 2:1 multiplexed hdmi receiver ? hdmi 1.4, 3d f ormat support, dvi 1.0 ? 225 mhz hdmi receiver ? integrated equalizer ? high - bandwidth digital content protection (hd cp 1.4) also on background ports ? internal hdcp keys ? 36- /30 - bit deep color support ? pcm, hbr, dsd audio packet support ? repeater support ? internal e - edid ram ? hot p lug a ssert output pin for each hdmi port ? cec c ontroller analog front end the adv7842 analog front end comprises four 170 mhz, 12 - bit adcs that digitize the analog video signal before applying it to the standard definition processor (sdp) or component processor (cp). the analog front end uses differential channels to each adc to ensure high performance in a mixed - signal application. the front end also includes a 12 - channel input mux that enables multiple video signals to be applied to the adv7842 without the requirement of an external mux. current and voltage clamp control loops ensure that any dc offs ets are removed from the video signal. the clamps are positioned in front of each adc to ensure that the video signal remains within the range of the converter. the adcs are configured to run up to 8 oversampling mode when decoding composite or s - video i nputs. for component 525i, 625i, 525p, and 625p sources , 4 oversampling is performed. all other video standards are 1 oversampled. oversampling the video signals reduces the cost and complexity of external antialiasing filters with the benefit of an incr eased signal - to - noise ratio (snr). optional internal antialiasing filters with programmable bandwidth are positioned in front of each adc. these filters can be used to band limit video signals, removing spurious, out - of - band noise. the adv7842 can support the simultaneous processing of cvbs and rgb standard definition signals to enable scart compatibility and overlay functionality. a combination of cvbs and rgb inputs can be mixed with the output under the control of i 2 c registers. analog front - end featur es include: ? four 170 mhz, nsv, 12 - bit adcs that enable true 12 - bit video decoding ? 12- channel analog input mux that enables multiple source connections without the requirement of an external mux ? four current and voltage clamp control loops that ensure any d c offsets are removed from the video signal ? scart functionality and sd rgb overlay on cvbs controlled by fast blank input ? scart source switching detection through tri1 - tri8 input ? four programmable antialiasing filters
adv7842 rev. b | page 21 of 28 standard definition processor the sdp is capable of decoding a large selection of baseband video signals in composite and s-video formats. the video standards supported by the sdp include pal, pal 60, pal m, pal n, pal nc, ntsc m/j, ntsc 4.43, and secam. the adv7842 can automatically dete ct the video standard and process it accordingly. the sdp has a 3d temporal comb filter and a five-line adaptive 2d comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. this highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality with no user intervention required. the sdp has an if filter block that compensates for attenuation in the high frequency chroma spectrum due to a tuner saw filter. the sdp has specific luminance and chrominance parameter controls for brightness, contrast, saturation, and hue. the adv7842 implements a patented adaptive digital line length tracking (adllt?) algorithm to track varying video line lengths from sources such as a vcr. adllt enables the adv7842 to track and decode poor quality video sources (such as vcrs) and noisy sources (such as tuner outputs, vcr players, and camcorders). frame tbc ensures stable clock synchronization between the decoder and the downstream devices. the sdp also contains both a luma transient improvement (lti) block and a chroma transient improvement (cti) block. these increase the edge rate on the luma and chroma transitions, resulting in a sharper video image. the sdp has a macrovision? detection circuit that allows type i, type ii, and type iii macrovision protection levels. the decoder is also fully robust to all macrovision signal inputs. sdp features include: ? advanced adaptive 3d comb (using either external ddr or sdr sdram memory) ? adaptive 2d five-line comb filters for ntsc and pal that give superior chrominance and luminance separation for composite video ? full automatic detection and autoswitching of all worldwide standards (pal, ntsc, and secam) ? automatic gain control with white peak mode that ensures the video is always processed without loss of the video processing range ? proprietary architecture for locking to weak, noisy, and unstable sources from vcrs and tuners ? if filter block that compensates for high frequency luma attenuation due to tuner saw filter ? lti and cti ? vertical and horizontal programmable luma peaking filters ? 8 oversampling (108 mhz) for cvbs, and s-video modes ? line-locked clock (llc) output ? free run output mode that provides stable timing when no video input is present or video lock is lost ? internal color bar test pattern ? advanced tbc with frame synchronization, which ensures nominal clock and data for nonstandard input ? interlace-to-progressive conversion for 525i and 625i formats, enabling direct drive of hdmi tx devices ? color controls that include hue, brightness, saturation, and contrast component processor the cp section of the adv7842 is capable of decoding and digitizing a wide range of component video formats in any color space. component video standards supported by the cp are 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, vga up to uxga at 60 hz, and other standards. the any-to-any, 3 3 csc matrix is placed between the analog front end and the cp section. this enables ypbpr to rgb and rgb to ycbcr conversions. many other standards of color space can be implemented using the color space converter. the cp section contains circuitry to enable the detection of macrovision encoded ypbpr signals for 525i, 625i, 525p, and 625p. it is designed to be fully robust when decoding these types of signals. vbi extraction of cgms data is performed by the cp section of the adv7842 for interlaced, progressive, and high definition scanning rates. the data extracted can be read back over the i 2 c interface. cp features include: ? 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other hdtv formats are supported ? supports 720p 24 hz/25 hz formats ? manual adjustments, including gain (contrast), offset (brightness), hue, and saturation ? support for analog component ypbpr and rgb video formats with embedded synchronization, composite synchronization or separate hs and vs ? any-to-any, 3 3 csc matrix that supports ycbcr-to- rgb and rgb-to-ycbcr, fully programmable or preprogrammable configurations ? synchronization source polarity detector (sspd) that determines the source and polarity of the synchronization signals that accompany the input video ? macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p) ? free-run output mode that provides stable timing when no video input is present or video lock is lost ? arbitrary pixel sampling support for nonstandard video sources ? 170 mhz conversion rate, which supports rgb input resolutions up to 1600 1200 at 60 hz ? standard identification enabled by stdi block ? rgb that can be color space converted to ycbcr and decimated to a 4:2:2 format for video-centric back-end ic interfacing
adv7842 rev. b | page 22 of 28 ? data enable (de) output signal supplied for direct connection to hdmi/dvi tx ic ? 32-phase dll that allows optimum pixel clock sampling ? automatic detection of synchronization source and polarity by sspd block ? contrast, brightness, hue, and saturation controls ? automatic or manual clamp-and-gain controls for graphics modes other features the adv7842 has hs, vs, field, and de output signals with programmable position, polarity, and width, and two i 2 c host port interfaces (control and vbi). the adv7842 has two programmable interrupt request output pins, int1 and int2. it also features a number of low power modes and a full power- down mode. the adv7842 is provided in a 17 mm 17 mm, rohs-compliant bga package, and is specified over the ?10c to +70c temperature range. for more detailed product information about the adv7842, contact your local analog devices sales office.
adv7842 rev. b | page 23 of 28 external memory requ irements the adv7842 uses external sdram for 3d comb and frame synchronizer. the adv7842 supports either sdr or ddr sd ram. single data rate (sd r) the adv7842 can use sdr external memory to provide 3d comb or frame synchronizer operation nonconcurrently. there is a 64 mb sdr sdram minimum memory require - ment. the required memory architecture is four banks of 1 mb 16 (4m16) with a speed grade of 133 mhz at cas latency (cl) 3. using 22 ? series termination resistors is recom - mended for this configuration. recommended sdr memory that is compatible with the adv7842 includes winbond w9864g6ph - 7. double data rate (dd r) the adv7842 can use ddr external memory to simultaneously provide 3d comb and frame synchronizer operation. there is a 128 mb ddr sdram minimum memory require ment. the required memory architecture is four banks of 2 mb 16 (8m16) with a speed grade of 133 mhz at cl 2.5. using 22 ? series termination resistors is recommend ed for this configuration recommended ddr memory that is compatible with the adv7842 includes the k4h561638j - lcb3 from samsung, the mt46v16m16p - 6t from micron technology, inc. and the h5du1262gtr - e3c from hynix inc.
adv7842 rev. b | page 24 of 28 pixel input/output f ormatting the ou tput section of the adv7842 is highly flexible. the pixel output bus can support up to 36 - bit 4:4:4. the pixel data supports both single and double data rates modes. in sdr mode, a 16 - /20 - /24 - bit 4:2:2 or 24 - /30 - /36 - bit 4:4:4 output is possible. in ddr mod e, the pixel output port can be configured in 8- /10 - /12 - bit 4:2:2 modes or 24- /30 - /36 - bit 4:4:4 modes. bus rotation and bus inversion are also supported. all output modes are controlled via i 2 c controls. pixel data output mo des features the output pixel port features include the following: ? 8- /10 - /12 - bit itu - r bt.656 4:2:2 with embedded time codes and/or hs, vs, and field output signals ? sdr 16 - /20 - /24 - /30 - /36 bit with embedded time codes and/or hs /cs and vs/field pin timing ? ddr 8 - /10 - /12 - bit 4:2:2 with em bedded time codes and/or hs, vs, and field output signals ? ddr 24 - /30 - /36 bit 4:4:4 with embedded time codes and/or hs, vs, and field output signals note that ddr modes are supported up to 54 mhz by characterization.
adv7842 rev. b | page 25 of 28 register map archite cture the reg isters of the adv7842 are controlled via a 2 - wire serial (i 2 c- compatible) interface. the adv7842 has 12 maps. the io map has a static i 2 c address. all other map addresses must be programmed ; this ensures no addressing clashes on the system. figure 9 shows the register map architecture. table 8. register map name default address programmable address location at which address can be programmed io map 0x40 not programmable not applicable cp map 0x00 programmable io map, register 0xfd sdp map 0x00 programmable io map, register 0xf1 sdp_io map 0x00 programmable io map, register 0xf2 vdp map 0x00 programmable io map, register 0xfe avlink map 0x00 programmable io map, register 0xf3 cec ma p 0x00 programmable io map, register 0xf4 hdmi map 0x00 programmable io map, register 0xfb edid map 0x00 programmable io map, register 0xfa repeater map 0x00 programmable io map, register 0xf9 afe, dpll map 0x00 programmable io map, register 0xf8 info frame map 0x00 programmable io map, register 0xf5 cec map slave address: programmable a vlink map slave address: programmable vdp map slave address: programmable sdp_io map slave address: programmable sdp map slave address: programmable cp map slave address: programmable io map slave address: 0x40 infoframe map slave address: programmable afe, dpl l map slave address: programmable repeater map slave address: programmable edid map slave address: programmable hdmi map slave address: programmable scl sda 08849-008 figure 9 . register map architecture
adv7842 rev. b | page 26 of 28 outline dimensions compliant to jedec standards mo-192-aaf-1 022007-a 1.00 bsc a b c d e f g h j k l m n p r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view 15.00 bsc sq a 1 ball corner 16 t 1.10 max 0.25 min coplanarity 0.20 0.70 0.60 0.50 ball diameter 0.30 min detail a top view detail a 1.70 max 17.20 17.00 sq 16.80 ball a1 corner seating plane figure 10. 256-ball chip scale package ball grid array [csp_bga] (bc-256-3) dimensions shown in millimeters ordering guide model 1 notes temperature range packag e description package option adv7842kbcz-5 2, 3 ?10c to +70c 256-ball chip scale package ball grid array [csp_bga] bc-256-3 adv7842kbcz-5p 2, 4, 5 ?10c to +70c 256-ball chip scale package ball grid array [csp_bga] bc-256-3 EVAL-ADV7842EB1Z 3, 6, 7 front-end evaluation board eval-adv7842eb2z 5, 6, 8 front-end evaluation board 1 z = rohs compliant part. 2 speed grade: 5 = 170 mhz. 3 this part is programmed with internal hdcp keys. customers must have hdcp adopter status (consult digital content protection, llc, for licensing requirements) to purchase any components with internal hdcp keys. 4 hdcp functionality: p = no hdcp functionality (professional version). 5 professional version for non-hdcp encrypted applications. purchaser is not required to be an hdcp adopter. 6 an atv motherboard is also required to process the adv7842 digital outputs and achi eve video output. an at v video output board is optional to evaluate performance through an hdmi transmitter and video encoder. 7 front-end board for the atv video evaluation platform, fitted with adv7842kbcz-5 decoder. 8 front-end board for the atv video evaluation platform, fitted with adv7842kbcz-5p decoder.
adv7842 rev. b | page 27 of 28 notes
adv7842 rev. b | page 28 of 28 notes i 2 c refers to a communications protocol originally developed by phillips semiconductors (now nxp semiconductors). hdmi, the hdmi logo, and high-definition mult imedia interface are trademarks or register ed trademarks of hdmi licensing llc in the united states and other countries. ?2010-2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08849-0-1/11(b)

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