? semiconductor components industries, llc, 2013 january, 2013 ? rev. 2 1 publication order number: ndd01n60/d ndd01n60, ndt01n60 n-channel power mosfet 600 v, 8.5 features ? 100% avalanche tested ? these devices are pb-free, halogen free/bfr free and are rohs compliant absolute maximum ratings (t j = 25 c unless otherwise noted) parameter symbol ndd ndt unit drain ? to ? source voltage v dss 600 v continuous drain current r jc steady state, t c = 25 c (note 1) i d 1.5 0.4 a continuous drain current r jc steady state, t c = 100 c (note 1) i d 1.0 0.25 a pulsed drain current, t p = 10 s i dm 6.0 1.5 a power dissipation ? r jc steady state, t c = 25 c p d 46 2.5 w gate ? to ? source voltage v gs 30 v single pulse drain ? to ? source avalanche energy (i pk = 1.0 a) eas 13 mj peak diode recovery (note 2) dv/dt 4.5 v/ns source current (body diode) i s 1.5 0.4 a lead temperature for soldering leads t l 260 c operating junction and storage temperature t j , t stg ? 55 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. limited by maximum junction temperature 2. i s = 1.5 a, di/dt 100 a/ s, v dd bv dss thermal resistance parameter symbol value unit junction ? to ? case (drain) ndd01n60 r jc 2.7 c/w junction ? to ? ambient (note 4) ndd01n60 (note 3) ndd01n60 ? 1 (note 4) ndt01n60 (note 5) ndt01n60 r ja 38 96 58 141 c/w 3. insertion mounted. 4. surface ? mounted on fr4 board using 1? sq. pad size (cu area = 1.127? sq. [2 oz] including traces). 5. surface ? mounted on fr4 board using minimum recommended pad size (cu area = 0.026? sq. [2 oz]). http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information v (br)dss r ds(on) max 600 v 8.5 @ 10 v dpak case 369c style 2 ipak case 369d style 2 1 2 3 4 1 2 3 4 n ? channel mosfet d (2) s (3) g (1) marking diagrams y = year ww = work week g = pb ? free package 4 drain 2 drain 1 gate 3 source yww 01 n60g 1 gate 2 drain 3 source 4 drain yww 01 n60g a = assembly location y = year w = work week 01n60 = specific device code = pb ? free package ayw 01n60 (note: microdot may be in either location) sot ? 223 case 318e style 3 1 2 3 4 2 drain 1 gate 3 source 4 drain
ndd01n60, ndt01n60 http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol test conditions min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs =0v, i d =1ma 600 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j reference to 25 c, i d = 1 ma 660 mv/ c drain ? to ? source leakage current i dss v ds = 600 v, v gs =0v t j =25 c 1 a t j = 125 c 50 gate ? to ? source leakage current i gss v gs = 20 v 100 na on characteristics (note 6) gate threshold voltage v gs(th) v ds =v gs , i d =50 a 2.2 3.3 3.7 v negative threshold temperature coef- ficient v gs(th) /t j 7.0 mv/ c static drain-to-source on resistance r ds(on) v gs =10v, i d = 0.2 a 8.0 8.5 forward transconductance g fs v ds =15v, i d = 0.2 a 0.9 s charges, capacitances & gate resistances input capacitance (note 7) c iss v ds =25v, v gs = 0 v, f = 1 mhz 160 pf output capacitance (note 7) c oss 22 reverse transfer capacitance (note 7) c rss 4.0 total gate charge (note 7) q g v ds = 300 v, i d = 0.4 a, v gs =10v 7.2 nc gate-to-source charge (note 7) q gs 1.2 gate-to-drain charge (note 7) q gd 3.1 plateau voltage v gp 4.5 v gate resistance r g 6.7 switching characteristics (note 8) turn-on delay time t d(on) v dd = 300 v, i d = 0.4 a, v gs =10v, r g = 0 8.0 ns rise time t r 5.1 turn-off delay time t d(off) 16.5 fall time t f 21.3 drain ? source diode characteristics diode forward voltage v sd i s = 0.4 a, v gs =0v t j =25 c 0.78 1.6 v t j = 125 c 0.63 reverse recovery time t rr v gs =0v, v dd =30v i s = 1.0 a, d i /d t = 100 a/ s 179 ns charge time t a 37 discharge time t b 141 reverse recovery charge q rr 288 nc 6. pulse width 300 s, duty cycle 2%. 7. guaranteed by design. 8. switching characteristics are independent of operating junction temperatures. ordering information device package shipping ? ndd01n60 ? 1g ipak (pb-free, halogen-free) 75 units / rail ndd01n60t4g dpak (pb-free, halogen-free) 2500 / tape & reel ndt01n60t1g sot ? 223 (pb-free, halogen-free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ndd01n60, ndt01n60 http://onsemi.com 3 typical characteristics figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 9 8 7 6 5 4 3 2 0 0.4 0.8 1.2 1.6 2.0 figure 3. on ? resistance vs. gate voltage figure 4. on ? resistance vs. drain current and gate voltage v gs , gate ? to ? source voltage (v) i d , drain current (a) 10 9 8 7 6 5 4 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10 3.0 2.5 2.0 1.5 1.0 0.5 0 6 8 10 12 14 16 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 125 100 75 50 25 0 ? 25 ? 50 0.4 0.8 1.2 1.6 2.0 2.4 600 500 400 300 200 100 0 10 100 1000 10,000 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) v gs = 10 v t j = 25 c 5.5 v 4.8 v 4.6 v 4.4 v 4.2 v 4.0 v v ds 25 v t j = 25 c 10 t j = 125 c t j = ? 55 c i d = 200 ma t j = 25 c r ds(on) , drain ? to ? source resistance ( ) v gs = 10 v t j = 25 c 150 i d = 200 ma v gs = 10 v t j = 125 c t j = 150 c v gs = 0 v
ndd01n60, ndt01n60 http://onsemi.com 4 typical characteristics q gs figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 100 10 1 1 10 7 6 5 4 3 2 1 0 0 2 4 6 8 10 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 0.1 1 10 100 1000 1.0 0.8 0.6 0.4 0.2 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 figure 11. maximum rated forward biased safe operating area ndd01n60 figure 12. maximum rated forward biased safe operating area ndt01n60 v ds , drain ? to ? source voltage (v) v ds , drain ? to ? source voltage (v) 1000 100 10 1 0.1 0.01 0.1 1 10 1000 100 10 1 0.1 0.01 0.1 1 10 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i d , drain current (a) i d , drain current (a) v gs = 0 v t j = 25 c f = 1 mhz c iss c oss c rss v ds = 300 v t j = 25 c i d = 400 ma 8 q t q gd v ds = 300 v i d = 400 ma v gs = 10 v t f t r t d(off) t d(on) v gs = 0 v t j = 25 c v gs = 10 v single pulse t c = 25 c t j = 150 c r ds(on) limit thermal limit package limit v gs = 10 v single pulse t c = 25 c t j = 150 c r ds(on) limit thermal limit package limit 10 s 100 s 1 ms 10 ms dc 100 s 1 ms 10 ms dc 0 100 200 250 300 350 150 50 v ds v ds , drain ? to ? source voltage (v)
ndd01n60, ndt01n60 http://onsemi.com 5 typical characteristics figure 13. thermal impedance (junction ? to ? case) for ndd01n60 pulse time (sec) 0.01 0.001 10 100 0.0001 0.00001 1000 0.000001 0.01 0.1 1 10 figure 14. thermal impedance (junction ? to ? ambient) for ndt01n60 pulse time (sec) 0.01 0.1 1 10 100 r(t) ( c/w) r(t) ( c/w) 0.1 1 0.01 0.001 10 100 0.0001 0.00001 1000 0.000001 0.1 1 single pulse 50% duty cycle 20% 10% 5% 2% 1% single pulse 50% duty cycle 20% 10% 5% 2% 1%
ndd01n60, ndt01n60 http://onsemi.com 6 package dimensions sot ? 223 (to ? 261) case 318e ? 04 issue n a1 b1 d e b e e1 4 123 0.08 (0003) a l1 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inch. 1.5 0.059 mm inches scale 6:1 3.8 0.15 2.0 0.079 6.3 0.248 2.3 0.091 2.3 0.091 2.0 0.079 soldering footprint h e dim a min nom max min millimeters 1.50 1.63 1.75 0.060 inches a1 0.02 0.06 0.10 0.001 b 0.60 0.75 0.89 0.024 b1 2.90 3.06 3.20 0.115 c 0.24 0.29 0.35 0.009 d 6.30 6.50 6.70 0.249 e 3.30 3.50 3.70 0.130 e 2.20 2.30 2.40 0.087 0.85 0.94 1.05 0.033 0.064 0.068 0.002 0.004 0.030 0.035 0.121 0.126 0.012 0.014 0.256 0.263 0.138 0.145 0.091 0.094 0.037 0.041 nom max l1 1.50 1.75 2.00 0.060 6.70 7.00 7.30 0.264 0.069 0.078 0.276 0.287 h e ? ? e1 0 1 0 0 1 0 l l 0.20 ??? ??? 0.008 ??? ??? style 3: pin 1. gate 2. drain 3. source 4. drain
ndd01n60, ndt01n60 http://onsemi.com 7 package dimensions 123 4 v s a k ? t ? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? ipak case 369d issue c style 2: pin 1. gate 2. drain 3. source 4. drain
ndd01n60, ndt01n60 http://onsemi.com 8 package dimensions dpak (single gauge) case 369c ? 01 issue d b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 2: pin 1. gate 2. drain 3. source 4. drain on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ndd01n60/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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