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deco sm5865cm nippon precision circuits? nippon precision circuits inc. d/a converter for digital audio overview the sm5865cm is a 24-bit input d/a converter lsi for high-quality digital audio equipment. it com- prises newly developed dem (dynamic element matching) circuits, 3rd-order ? noise shaper and 31-level quantizer to realize super low total har- monic distortion and wide dynamic range. also, the device is widely reduced residual quantization noise up to high-frequency bandwidth in the audio band so the order of the required ?al-stage analog lowpass ?ter can be reduced, making it ideal for application with high-frequency sampling format. the output stage employs differential current outputs for high- accuracy analog signals, with appropriate lowpass ?tering of the output signal. this device can be used in combination with an 8-times oversampling digital ?ter of sm5847af and others like that for the com- patibility with 192k h z sampling format. features mono-channel d/a converter lsi high performance 0.00030 % (?10.5db) typ. thd + n 117 db typ. dynamic range 120 db typ. s/n input interface 20 or 24-bit word length msb ?st, right-justi?d format 8 or 4 times oversampling at fs = 16/32/44.1/48/ 88.2/96/176.4/192 khz system clock frequency 192/256/384/512/768/1024 fs single 5 v operating supply voltage 24-pin ssop package molybdenum-gate cmos process ordering information pinout (top view) package dimensions (unit: mm) weight: 0.23g 24-pin ssop device package sm5865cm 24-pin ssop 1 13 24 12 dvss di bcki wcki iwsl rstn tstn avssa ra iouta vba n.c. avdda avddb to rb dvdd cki ckdvn cvss ioutb vbb n.c. avssb c sm5 865 m 0.36 0.10 10.20 0.30 10.05 0.20 0.10 0.10 1.80 7.80 0.30 5.40 0.20 010 0.50 0.20 0.8 0.12 m 0.10 1.90 ? 0.10 +0.20 0.15 + 0.10 ? 0.05
sm5865cm nippon precision circuits? block diagram noise shaper input interface timing control rstn dvss cki avssa 31 level dem dac 31 level dem dac dvdd ckdvn cvss interpolation to tstn divider iwsl wcki bcki di noise shaper 31 level dem dac 31 level dem dac vbb ioutb rb avddb avdda vba iouta ra avssb 1 2 3 4 5 6 7 8 9 11 10 12 13 15 16 17 18 19 21 22 23 24
sm5865cm nippon precision circuits? pin description i p : pull-up input number name i/o description 1 dvss digital ground 2 di i data input 3 bcki i bit clock input 4 wcki i word clock input 5 iwsl ip input data word length select. 24-bit when high, and 20-bit when low. 6 rstn ip system reset. reset when low. 7 tstn ip test pin. tie high or leave open for normal operation. 8 to o test output 9 dvdd digital supply 10 cki i system clock input 11 ckdvn ip system clock frequency divider ratio select. 1 when high (no division), and 2 when low (half of the input frequency). 12 cvss system clock ground 13 avssb analog ground b 14 n. c. leave open for no connection or connect with ground 15 vbb o 1/2 supply output b 16 ioutb o inverse-phase analog output b 17 rb i built-in resistor connection b 18 avddb analog supply b 19 avdda analog supply a 20 n. c. leave open for no connection or connect with ground 21 vba o 1/2 supply output a 22 iouta o in-phase analog output a 23 ra i built-in resistor connection a 24 avssa analog ground a
sm5865cm nippon precision circuits? specifications absolute maximum ratings dvss = avssa = avssb = cvss = 0 v, dvdd = avdda = avddb recommended operating conditions dvss = avssa = avssb = cvss = 0 v, dvdd = avdda = avddb parameter symbol rating unit supply voltage range dvdd, avdda, avddb ? 0.3 to 7.0 v input voltage range 1 1. pins di, bcki, wcki, ckdvn, iwsl, rstn, tstn. also applicable during supply switching. v in dvss ? 0.3 to dvdd + 0.3 v storage temperature range t stg ? 55 to 125 c power dissipation p d 250 mw parameter symbol rating unit supply voltage range dvdd, avdda, avddb 4.5 to 5.5 v supply voltage variation dvdd ? avdda, dvdd ? avddb, avdda ? avddb, dvss ? avssa, dvss ? avssb, avssa ? avssb, dvss ? cvss, avssa ? cvss, avssb ? cvss ?.1 v operating temperature range t opr ? 40 to 85 c
sm5865cm nippon precision circuits? dc electrical characteristics recommended operating conditions, unless otherwise speci ed. parameter symbol condition rating unit min typ max dvdd, avdda, avddb supply current 1 1. no output load, npc-standard input data pattern. i dd f cki = 11.2896 mhz 7 11 ma f cki = 16.9344 mhz 10 14 ma f cki = 24.576 mhz 15 19 ma f cki = 36.864 mhz 21 26 ma cki high-level input voltage v ihc 0.7 dvdd v cki low-level input voltage v ilc 0.3 dvdd v cki input voltage v inac ac coupling 1.0 vp-p high-level input voltage 2 2. pins di, bcki, wcki, ckdvn, iwsl, rstn, tstn. v ih 2.4 v low-level input voltage 2 v il 0.5 v high-level output voltage 3 3. pin to. v oh i oh = ? 1 ma dvdd ? 0.4 v low-level output voltage 3 v ol i ol = 1 ma 0.4 v cki high-level input current i ihc v in = dvdd 30 60 120 ? cki low-level input current i ilc v in = 0 v 30 60 120 ? low-level input current 4 4. pins ckdvn, iwsl, rstn, tstn. i il2 v in = 0 v 5 15 a high-level input leakage current 5 5. pins di, bcki, wcki. i ih1 v in = dvdd 1.0 ? low-level input leakage current 5 i il1 v in = 0 v 1.0 ? high-level input leakage current 4 i ih2 v in = dvdd 1.0 ?
sm5865cm nippon precision circuits? ac electrical characteristics system clock input (cki) internal system clock internal system clock frequency is the same as the cki clock frequency when ckdvn = high. internal system clock frequency is half the cki clock frequency when ckdvn = low. reset input (rstn) parameter symbol rating unit min typ max cki clock frequency f cki 5 60 mhz high-level clock pulsewidth t cwh 5ns low-level clock pulsewidth t cwl 5ns parameter symbol condition rating unit min typ max internal system clock frequency f sys 5 46 mhz parameter symbol condition rating unit min typ max rstn low-level pulsewidth t rstn at power on 1 ? after power on 100 ns 0.5 ? dvdd cki cwl t cwh t cki 1/f v ihc v ilc
sm5865cm nippon precision circuits? serial input (bcki, di, wcki) group delay parameter symbol rating unit min typ max bcki high-level pulsewidth t bcwh 10 ns bcki low-level pulsewidth t bcwl 10 ns bcki pulse cycle t bcy 22 ns di setup time t ds 5ns di hold time t dh 5ns wcki edge to ?st bcki rising edge t wb 10 ns last bcki rising edge to wcki edge t bw 10 ns parameter symbol condition rating unit min typ max group delay 1 1. fsi is the input sampling rate of sm5865cm. for example, fsi is 384khz when this lsi is used in combination with an 8-times oversampling digital ?ter of which input sampl ing rate is 48khz. t gd 2/fsi s bcki di wcki bcwh t bcwl t bcy t ds t dh t 1.5v wb t 1.5v 1.5v bw t
sm5865cm nippon precision circuits? ac analog characteristics measurement conditions analog characteristics external 8fs digital lter : npc sm5847af external operational ampli er : jrc njm5534d supply voltage sm5865cm : dvdd = avdda = avddb = 5v, dvss = avssa = avssb = cvss = 0v sm5847af : + 3.3v njm5534d : 15v ambient temperature : 25 c input data of sm5847af : 48khz sampling (fs), 24-bit data system clock : 24.576mhz (= 512fs), (64fs noise shaper operation) audio analyzer : audio precision system two (rms mode) measurement lter condition : thd + n 22hzhpf, 20khzlpf (flp-a20k) : d.r 22hzhpf, 22khzlpf, a-weight (fil-awt) : s/n 22hzhpf, 22khzlpf, a-weight (fil-awt) measurement circuits diagram : see next page. parameter symbol condition rating unit min typ max output level 1 1. v out is the output level of the ?st i? conversion stage. v out 1 khz, 0 db 1.28 1.33 1.38 vrms total harmonic distortion thd + n 1 khz, 0 db 0.00030 ( ? 110.5db) 0.00060 ( ? 104.4db) % dynamic range d.r 1 khz, ? 60 db 111 117 db signal-to-noise ratio s/n 1 khz, 0/ ? db 117 120 db gain drift g.d 10 ppm/ c
sm5865cm nippon precision circuits? measurement circuit dvss di bcki wcki iwsl rstn tstn to dvdd cki ckdvn cvss avssa ra iouta vba n.c. avdda avddb rb ioutb vbb n.c. avssb 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v dd u1 njm5534d v cc v ee gnd gnd 2 3 6 7 r1 820 r3 620 c3 220p r2 820 gnd r4 620 c4 220p c5 4.7 r5 470 out 2vrms j1 gnd ic1 sm5865cm gnd 4 c6 0.1 + c7 470 c1 330p 18 5 v cc v ee 2 3 6 7 4 18 5 c2 330p r6 4.7k r7 4.7k gnd v dd u2 njm5534d v cc v ee 2 3 6 7 4 18 5 u3 njm5534d gnd v dd gnd c8 0.1 + c9 100 gnd wcki bcki di cki
sm5865cm nippon precision circuits?0 dynamics characteristics (under measurement conditions in page 8) figure 1. 0db input fft (1) (1khz notch lter 32768point 8average) +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 d b r a 2k 4k 6k 8k 10k hz 12k 14k 16k 18k 20k figure 2. 0db input fft (2) (1khz notch lter 32768point 8average) 10k 20k 30k 40k 50k hz 60k 70k 80k 90k 100k +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 d b r a figure 3. 60db input fft (32768point 8average) +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 d b r a 2k 4k 6k 8k 10k hz 12k 14k 16k 18k 20k figure 4. thd + n vs. frequency -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 d b 500 200 100 50 20 10 1k 2k 5k 10k 20k hz figure 5. thd + n(%) vs. amplitude -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0 dbfs 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0005 0.0002 0.0001 % figure 6. thd + n (db) vs. amplitude -70 -72.5 -75 -77.5 -80 -82.5 -85 -87.5 -90 -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 d b r a -60 -50 -40 -30 -20 -10 +0 -70 -80 -90 -100 -110 -120 dbfs figure 7. linearity +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 d b r a -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dbfs figure 8. evaluation board frequency response 10 20 50 100 200 500 1k 2k 5k 10k 20k hz -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 +0 +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 +0.7 +0.8 +0.9 +1 d b r a
sm5865cm nippon precision circuits?1 functional description analog outputs iouta, ioutb the sm5865cm input data in-phase signal is processed by noise shaper a and 31-level dem-dac with cur- rent output on differential output a, and input data reverse-phase signal is processed by noise shaper b and 31- level dem-dac with current output on differential output b. differential outputs a and b also have separate in-phase and reverse-phase outputs: a in-phase output and b reverse-phase output are connected internally and output on iouta, and b in-phase output and a reverse-phase output are connected internally and output on ioutb. the iouta and ioutb current outputs are i/v converted by external circuit and then input to a differential input op-amp to obtain the nal analog signal. ra, rb internal resistors are connected between iouta and ra pins and between ioutb and rb pins, which serve as the op-amp feedback resistors. the feedback resistors have a resistance of 4.7k ? . the i/v converter output gain can be adjusted by connecting external resistors in parallel or serial with the internal resistors. note, however, that the internal resistance can vary from device to device by 10%, and if external resistors are used, the output level changes depending on the difference between each resistor ratio. if the i/v converter gain is increased, a dynamic range higher even than that given in analog characteristics (page 8) can be obtained. figure 9. analog outputs 31 level dem dac noise shaper a ra iouta 31 level dem dac noise shaper b rb ioutb in-phase output a in-phase output b inverse-phase output a inverse-phase output b data input
sm5865cm nippon precision circuits?2 vba, vbb a 0.5vdd signal is output from vba, vbb using a resistor divider network. using these pins allows the use of the sm5865cm to replace the pin-compatible sm5865bm product. audio data input (di, bcki, wcki, iwsl) input data format the audio data is input in msb- rst, 2s-complement, 24-bit/20-bit serial format. the input word bit length is selected by iwsl, 24-bit when high, and 20-bit when low. jitter-free function the sm5865cm serial input data from di synchronize with the word clock (wcki) and are read into the rst register stage, and those also synchronize with the clock derived from divided system clock and are read into the next register stage. this word clock and the system clock are always phase compared. when a phase shift was detected, the comparison result is used to perform input timing adjustment in the system clock. therefore this process enable internal calculations not to be affected by generated large jitter on the word clock or chang- ing the sampling rate during inputting data. system clock divider (ckdvn) the sm5865cm has a built-in clock frequency divider. the divider enables the internal system clock to oper- ate at half the input frequency, for example when the external system clock input frequency is high. system reset (rstn) the device should be reset in the following cases. at power on when the system clock cki stops, or other abnormalities occur. the device is reset by applying a low-level pulse on rstn. figure 10. vba, vbb sm5865cm ra iouta rb ioutb 31 level dem dac 31 level dem dac 31 level dem dac 31 level dem dac vba vbb
sm5865cm nippon precision circuits?3 theoretical quantization noise reduction the sm5865cm employs a 3rd-order 31-level quantized noise shaper to widely reduce quantization noise in the audio band to the high frequency bandwidth. the theoretical quantization noise level at 16fs to 96fs opera- tion is shown in gure 11. figure 11. theoretical quantization noise level 0.5 1 1.5 2 2.5 3 3.5 4 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 frequency (fs) quantization noise (db) 16fs 24fs 32fs 48fs 64fs 96fs 0 db sine wave equivalent white noise level 16-bit, fs quantization noise level 20-bit, fs quantization noise level 24-bit, fs quantization noise level
sm5865cm nippon precision circuits?4 internal oversampling operation the sm5865cm accepts data output from an 8-times or 4-times oversampling digital lter, and oversampled internally again up to the noise shaper operating rate. the internal oversampling factor is determined automati- cally from the system clock input frequency and the input sampling frequency. this internal oversampling fac- tor (n) must be an integer satisfying the conditions shown in table 1. table 1. operating conditions parameter ckdvn = high ckdvn = low f wcki and f cki compulsory conditions 1 1. f wcki = word clock frequency, f cki = input system clock frequency, n = internal oversampling factor where n = 1, 2, 3, ... where n = 1, 2, 3, ... noise shaper operating frequency figure 12. clock-related inputs f cki f wcki 8 n = f cki f wcki 16 n = f ns f wcki n f cki 8 ---------- - = = f ns f wcki n f cki 16 ---------- - = = word clock input ckdvn wcki sm5865cm system clock divider select system clock input cki
sm5865cm nippon precision circuits?5 system clock frequencies table 2 shows some possible combinations for the circuit con guration shown in gure 13. figure 13. circuit con guration table 2. system clock frequencies (ckdvn = high) fs system clock frequency 1 f cki 1. when ckdvn = low, the system clock frequency f cki is halved, so the values shown are half the input frequency required for the same sampling rate and internal factors. noise shaper operating rate internal factor (8fs input) internal factor (4fs input) 16 khz 6.144 mhz (384fs) 48fs 6 12 16 khz 8.192 mhz (512fs) 64fs 8 16 16 khz 12.288 mhz (768fs) 96fs 12 24 32 khz 6.144 mhz (192fs) 24fs 3 6 32 khz 8.192 mhz (256fs) 32fs 4 8 32 khz 12.288 mhz (384fs) 48fs 6 12 32 khz 16.384 mhz (512fs) 64fs 8 16 32 khz 24.576 mhz (768fs) 96fs 12 24 44.1 khz 8.4672 mhz (192fs) 24fs 3 6 44.1 khz 11.2896 mhz (256fs) 32fs 4 8 44.1 khz 16.9344 mhz (384fs) 48fs 6 12 44.1 khz 22.5792 mhz (512fs) 64fs 8 16 44.1 khz 33.8688 mhz (768fs) 96fs 12 24 48 khz 9.216 mhz (192fs) 24fs 3 6 48 khz 12.288 mhz (256fs) 32fs 4 8 48 khz 18.432 mhz (384fs) 48fs 6 12 48 khz 24.576 mhz (512fs) 64fs 8 16 48 khz 36.864 mhz (768fs) 96fs 12 24 88.2 khz 16.9344 mhz (192fs) 24fs 3 6 88.2 khz 22.5792 mhz (256fs) 32fs 4 8 88.2 khz 33.8688 mhz (384fs) 48fs 6 12 88.2 khz 45.1584 mhz (512fs) 64fs 8 16 96 khz 18.432 mhz (192fs) 24fs 3 6 96 khz 24.576 mhz (256fs) 32fs 4 8 96 khz 36.864 mhz (384fs) 48fs 6 12 176.4 khz 33.8688 mhz (192fs) 24fs 3 6 176.4 khz 45.1584 mhz (256fs) 32fs 4 8 192 khz 36.864 mhz (192fs) 24fs 3 6 ckdvn fs sm5865cm interpolating ?ter (8-times/4-times) f cki f wcki
sm5865cm nippon precision circuits?6 timing diagrams 192fs system clock input timing 384fs system clock input timing *: data can be input at any period within the word clock cycle. cki 1 / 8fs bcki di 21 22 23 24 (1)20bit * msb lsb msb lsb 1 2 3 4 5 6 7 8 9 101112131415 16 17 18 19 20 123456789101112131415 16 17 18 19 20 msb lsb 123456789101112131415 16 17 18 19 20 bcki di (2)20bit bcki di (3)24bit wcki cki 1 / 8fs bcki di 21 22 23 24 (1)20bit * msb lsb msb lsb 1 2 3 4 5 6 7 8 9 101112131415 16 17 18 19 20 1 2 3 4 5 6 7 8 9 101112131415 16 17 18 19 20 msb lsb 1 2 3 4 5 6 7 8 9 101112131415 16 17 18 19 20 bcki di (2)20bit bcki di (3)24bit wcki
sm5865cm nippon precision circuits?7 256fs system clock input timing 512fs system clock input timing *: data can be input at any period within the word clock cycle. cki 1 / 8fs bcki di 21 22 23 24 (1)20bit * msb lsb msb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 123456789101112131415 16 17 18 19 20 msb lsb 123456789101112131415 16 17 18 19 20 bcki di (2)20bit bcki di (3)24bit * wcki 21 22 23 24 msb 1 2 3 4 5 6 7 8 9 101112131415 16 17 18 19 20 bcki di (4)24bit lsb lsb cki 1 / 8fs bcki di 21 22 23 24 (1)20bit * msb lsb msb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 123456789101112131415 16 17 18 19 20 msb lsb 123456789101112131415 16 17 18 19 20 bcki di (2)20bit bcki di (3)24bit * wcki 21 22 23 24 msb 1 2 3 4 5 6 7 8 9 101112131415 16 17 18 19 20 bcki di (4)24bit lsb lsb
sm5865cm nippon precision circuits?8 typical applications input interface circuit sm5847af dol dor wcko bcko sm5865cm di cki wcki bcki sm5865cm di cki wcki bcki xti
sm5865cm nippon precision circuits?9 analog output circuits analog output circuit 1 analog output circuit 2 note that the output analog characteristics and other speci?ations are not guaranteed for particular formats or application ci rcuits. note that npc has no responsibility for patents related to application circuits in these datasheets. sm5865cm ra iouta rb ioutb 31 level dem dac 31 level dem dac 31 level dem dac 31 level dem dac sm5865cm ra iouta rb ioutb 31 level dem dac 31 level dem dac 31 level dem dac 31 level dem dac
sm5865cm nippon precision circuits?0 nc0019ae 2000.12 nippon precision circuits inc. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. nippon precision circuits inc. assumes no responsib ility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. applications for any devices shown in this data sheet are for illustration only and nippon p recision circuits inc. makes no claim or warranty that such applications will be suitable for the use speci?d without further testing o r modi?ation. the products described in this data sheet are not intended to use for the apparatus which in?ence human lives due to the failu re or malfunction of the products. customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. customers shall not export, dir ectly or indirectly, any products without ?st obtaining required licenses and approvals from appropriate government agencies. nippon precision circuits inc. 4-3, fukuzumi 2-chome koto-ku, tokyo 135-8430, japan telephone: +81-3-3642-6661 facsimile: +81-3-3642-6698 http://www.npc.co.jp/ email: sales @ npc.co.jp nippon precision circuits inc.

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