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skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 1 data sheet SKY72300-21: spur-free, 2.1 ghz dual fractional-n frequency synthesizer applications x general purpose rf systems x 2.5g and 3g wireless infrastructure x broadband wireless access x low bit rate wireless telemetry x instrumentation x l-band receivers x satellite communications features x spur-free operation x 2.1 ghz maximum operating frequency x 500 mhz maximum auxiliary synthesizer x ultra-fine step size, 100 hz or less x high internal reference frequency enables large loop bandwidth implementations x very fast switching speed (e.g., below 100 p s) x phase noise to C91 dbc/hz inside the loop filter bandwidth @ 1800 mhz x software programmable power-down modes x high-speed serial interface up to 100 mbps x three-wire programming x programmable division ratios on reference frequency x phase detectors with programmable gain to provide a programmable loop bandwidth x frequency power steering further enhances rapid acquisition time x on-chip crystal oscillator x frequency adjust for temperature compensation skyworks offers lead (pb)-free rohs (restriction of hazardous substances) compliant packaging. innovation to go tm now available for purchase online. x direct digital modulation x 3 v operation x 5 v output to loop filter x ep-tssop (28-pin, 9.7 x 6.4 x 1.1 mm) package (msl3, 260 q c per jedec j-std-020) description skyworks SKY72300-21 direct digital modulation fractional-n frequency synthesizer provides ultra-fine frequency resolution, fast switching speed, and low phase-noise performance. this synthesizer is a key building block for high-performance radio system designs that require low power and fine step size. the ultra-fine step size of less than 100 hz allows this synthesizer to be used in very narrowband wireless applications. with proper temperature sensing or through control channels, the synthesizers fine step size can compensate for crystal oscillator or intermediate frequency (if) filter drift. as a result, crystal oscillators or crystals can replace temperature-compensated or ovenized crystal oscillators, reducing parts count and associated component cost. the devices fine step size can also be used for doppler shift corrections. the SKY72300-21 has a phase noise floor of C90 dbc/hz up to 2.1 ghz operation as measured inside the loop bandwidth. this is permitted by the on-chip low noise dividers and low divide ratios provided by the devices high fractionality. reference crystals or oscillators up to 50 mhz can be used with the SKY72300-21. the crystal frequency is divided down by independent programmable dividers (1 to 32) for the main and auxiliary synthesizers. the phase detectors can operate at a maximum speed of 25 mhz, which allows better phase noise due to the lower division value. with a high reference frequency, the loop bandwidths can also be increased. larger loop bandwidths improve the settling times and reduce in-band phase noise. therefore, typical switching times of less than 100 s can be achieved. the lower in-band phase noise also permits the use of lower cost voltage controlled oscillators (vcos) in customer applications.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 2 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n the SKY72300-21 has a frequency power steering circuit that helps the loop filter to steer the vco when the frequency is too fast or too slow, further enhancing acquisition time. the unit operates with a three-wire, high-speed serial interface. a combination of large bandwidth, fine resolution, and the three- wire, high-speed serial interface allows for a direct frequency modulation of the vco. this supports any continuous phase, constant envelope modulation scheme such as frequency modulation (fm), frequency shift keying (fsk), minimum shift keying (msk), or gaussian minimum shift keying (gmsk). this capability can eliminate the need for in-phase and quadrature (i/q) digital-to-analog converters (dacs), quadrature upconverters, and if filters from the transmitter portion of the radio system. figure 1 shows a functional block diagram for the SKY72300-21. the device package and pinout for the 28-pin exposed pad thin shrink small outline package (ep-tssop) are shown in figure 2. serial interface modulation unit main divider auxiliary divider fvco_aux fvco_aux fvco_main fpd_main fpd_aux fref_main fref_aux fref cpout_aux cpout_main ld/psmain ld/psaux fvco_main reference frequency oscillator reference frequency oscillator main phase/freq. detector and charge pump auxiliary phase/freq. detector and charge pump main divider auxiliary prescaler data mux mod_in mux_out clock cs fractional unit fractional unit ? 18-bit ? 10-bit registers modulation data main divider modulation control ref freq dividers pd/charge pump & pwr-dn/mux out control aux divider main msb/lsb dividend aux dividend lock detection or power steering lock detection or power steering c1447 figure 1. SKY72300-21 functional block diagram c1412 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 clock mod_in mux_out vsubdigital gndcml vcccml_main fvco_main fvco_main ld/psmain vcccp_main cpout_main gndcp_main xtalacgnd/osc xtalin/osc cs data vccdigital gnddigital vcccml_aux vccvco_aux fvco_aux gndcp_aux cpout_aux vcccp_aux ld/psaux gndxtal vccxtal xtalout/nc figure 2. SKY72300-21 pinout, 28-pin ep-tssop (top view)
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 3 technical description the SKY72300-21 is a fractional-n frequency synthesizer using a '6 modulation technique. the fractional-n implementation provides low in-band noise by having a low division ratio and fast frequency settling time. in addition, the SKY72300-21 provides arbitrarily fine frequency resolution with a digital word, so that the frequency synthesizer can be used to compensate for crystal frequency drift in the rf transceiver. serial interface the serial interface is a versatile three-wire interface consisting of three pins: clock (serial clock), data (serial input), and cs (chip select). it enables the SKY72300-21 to operate in a system where one or multiple masters and slaves are present. to perform a loopback test at startup and to check the integrity of the board and processor, the serial data is fed back to the master device (e.g., a microcontroller or microprocessor unit) through a programmable multiplexer. this facilitates hardware and software debugging. registers there are ten 16-bit registers in the SKY72300-21. for more information, see the register descriptions section of this document. main and auxiliary ' 6 modulators the fractionality of the SKY72300-21 is accomplished by the use of a proprietary, configurable 10-bit or 18-bit '6 modulator for the main synthesizer and 10-bit '6 modulator for the auxiliary synthesizer. main and auxiliary fractional units the SKY72300-21 provides fractionality through the use of main and auxiliary '6 modulators. the output from the modulators is combined with the main and auxiliary divider ratios through their respective fractional units. vco prescalers the vco prescalers provide low-noise signal conditioning of the vco signals. they translate from an off-chip, single-ended or differential signal to an on-chip differential current mode logic (cml) signal. the SKY72300-21 has independent main and auxiliary vco prescalers. main and auxiliary vco dividers the SKY72300-21 provides programmable dividers that control the cml prescalers and supply the required signals to the charge pump phase detectors. programmable divide ratios ranging from 38 to 537 are possible in fractional-n mode and from 32 to 543 in integer-n mode. reference frequency oscillator the SKY72300-21 has a self-contained, low-noise crystal oscillator. this crystal oscillator is followed by the clock generation circuitry that generates the required clock for the programmable reference frequency dividers. reference frequency dividers the crystal oscillator signal can be divided by a ratio of 1 to 32 to create the reference frequencies for the phase detectors. the SKY72300-21 has both a main and an auxiliary frequency synthesizer, and provides independently configurable dividers of the crystal oscillator frequency for both the main and auxiliary phase detectors. the divide ratios are programmed by the reference frequency dividers register. note: the divided crystal oscillator frequencies (which are the internal reference frequencies), fref_main and fref_aux, are referred to as reference frequencies throughout this document. phase detectors and charge pumps the SKY72300-21 uses a separate charge pump phase detector for each synthesizer which provides a programmable gain, kd, from 31.25 to 1000 p a/2 s radians in 32 steps programmed using the phase detector/charge pump control register. frequency steering when programmed for frequency power steering, the sky72300- 21 has a circuit that helps the loop filter steer the vco, through the ld/psmain signal (pin 9). in this configuration, the ld/psmain signal can provide for more rapid acquisition. when programmed for lock detection, internal frequency steering is implemented and provides frequency acquisition times comparable to conventional phase/frequency detectors. lock detection when programmed for lock detection, the SKY72300-21 provides an active low, pulsing open collector output using the ld/psmain signal (pin 9) to indicate the out-of-lock condition. when locked, the ld/psmain signal is tri-stated (high impedance). power down the SKY72300-21 supports a number of power-down modes through the serial interface. for more information, see the register descriptions section of this document.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 4 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n serial interface operation the serial interface consists of three pins: clock (pin 1), data (pin 27), and cs (pin 28). the clock signal controls data on the two serial data lines (data and cs). the data pin bits shift into a temporary register on the rising edge of clock. the cs line allows individual selection transfers that synchronize and sample the information of slave devices on the same bus. figure 3 functionally depicts how a serial transfer takes place. a serial transfer is initiated when a microcontroller or microprocessor forces the cs line to a low state. this is followed immediately by an address/data stream sent to the data pin that coincides with the rising edges of the clock presented on the clock line. each rising edge of the clock signal shifts in one bit of data on the data line into a shift register. at the same time, one bit of data is shifted out of the mux_out pin (if the serial bit stream is selected) at each falling edge of clock. to load any of the registers, 16 bits of address or data must be presented to the data line with the lsb last while the cs signal is low. if the cs signal is low for more than 16 clock cycles, only the last address or data bits are used to load the registers. if the cs signal is brought to a high state before the 13 th clock edge, the bit stream is assumed to be modulation data samples. in this case, it is assumed that no address bits are present and that all the bits in the stream should be loaded into the modulation data register. register programming register programming equations, described in this section, use the following variables and constants: n fractional desired vco division ratio in fractional-n applications. this is a real number and can be interpreted as the reference frequency ( f ref ) multiplying factor such that the resulting frequency is equal to the desired vco frequency. n integer desired vco division ratio in integer-n applications. this number is an integer and can be interpreted as the reference frequency ( f ref ) multiplying factor so that the resulting frequency is equal to the desired vco frequency. n reg nine-bit unsigned input value to the divider ranging from 0 to 511 (integer-n mode) and from 6 to 505 (fractional-n mode). divider this constant equals 262144 when the '6 modulator is in 18-bit mode, and 1024 when the '6 modulator is in 10-bit mode. dividend when in 18-bit mode, this is the 18-bit signed input value to the '6 modulator, ranging from C131072 to +131071 and providing 262144 steps, each step equal to f div_ref /218 hz. when in 10-bit mode, this is the 10-bit signed input value to the '6 modulator, ranging from C512 to +511 and providing 1024 steps, each step equal to f div_ref /210 hz. f vco desired vco frequency (either f vco_main or f vco_aux ). f div_ref divided reference frequency presented to the phase detector (either f ref_main or f ref_aux ). x a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xxx clock last data cs c1413 figure 3. serial transfer timing diagram
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 5 fractional-n applications . the desired division ratio for the main and auxiliary synthesizers is given by: ref _ div vco fractional f f n where n fractional must be between 37.5 and 537.5. the value to be programmed by the main or auxiliary divider register is given by: 32 ) n ( round n fractional reg note: the round function rounds the number to the nearest integer. when in fractional mode, allowed values for n reg are from 6 to 505 inclusive. the value to be programmed by either of the msb/lsb dividend registers or the auxiliary dividend register is given by: )] 32 n n ( divider [ round dividend reg fractional u where the divider is either 1024 in 10-bit mode or 262144 in 18-bit mode. therefore, the dividend is a signed binary value either 10 or 18 bits long. note: because of the high fractionality of the SKY72300-21, there is no practical need for any integer relationship between the reference frequency and the channel spacing or desired vco frequencies. sample calculations for two fractional-n applications are provided in figure 4. integer-n applications . the desired division ratio for the main or auxiliary synthesizer is given by: ref _ div main _ vco eger int f f n where n integer is an integer number from 32 to 543. the value to be programmed by the main or auxiliary divider register is given by: 32 n n eger int reg when in integer mode, allowed values for n reg are from 0 to 511 for both the main and auxiliary synthesizers. note: as with all integer-n synthesizers, the minimum step size is related to the crystal frequency and reference frequency division ratio. a sample calculation for an integer-n application is provided in figure 5. register loading order . in applications where the main synthesizer is in 18-bit mode, the main dividend msb register holds the 10 msbs of the dividend and the main dividend lsb register holds the 8 lsbs of the dividend. the registers that control the main synthesizers divide ratio are to be loaded in the following order: x main divider register x main dividend lsb register x main dividend msb register (at which point the new divide ratio takes effect) in applications where the main synthesizer is in 10-bit mode, the main dividend msb register holds the 10 bits of the dividend. the registers that control the main synthesizers divide ratio are to be loaded in the following order: x main divider register x main dividend msb register (at which point the new divide ratio takes effect) for the auxiliary synthesizer, the auxiliary dividend register holds the 10 bits of the dividend. the registers that control the auxiliary synthesizers divide ratio are to be loaded in the following order: x auxiliary divider register x auxiliary dividend register (at which point the new divide ratio takes effect) note: when in integer mode, the new divide ratios take effect as soon as the main or auxiliary divider register is loaded. direct digital modulation the high fractionality and small step size of the SKY72300-21 allow the user to tune to practically any frequency in the vcos operating range. this allows direct digital modulation by programming the different desired frequencies at precise instants. typically, the channel frequency is programmed by the main divider and msb/lsb dividend registers, and the instantaneous frequency offset from the carrier is programmed by the modulation data register. the modulation data register can be accessed in three ways as defined in the following subsections.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 6 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n case 1: to achieve a desired f vco_main frequency of 902.4530 mhz using a crystal frequency of 40 mhz with operation of the synthesizer in 18-bit mode. since the maximum internal reference frequency ( f div_ref ) is 25 mhz, the crystal frequency is divided by 2 to obtain a f div_ref of 20 mhz. therefore: n fractional = f vco_main f div_ref = 902.4530 20 = 45.12265 the value to be programmed in the main divider register is: n reg = round[ n fractional ] C 32 = round[45.12265] C 32 = 45 C 32 = 13 (decimal) = 000001101 (binary) with the modulator in 18-bit mode, the value to be programmed in the main dividend registers is: dividend = round[divider ( n fractional C n reg C 32)] = round[262144 (45.12265 C 13 C 32)] = round[262144 (0.12265)] = round[32151.9616] = 32152 (decimal) = 000111110110011000 (binary) where 00 0111 1101 is loaded in the msb of the main dividend register and 1001 1000 is loaded in the lsb of the main dividend register. summary: main divider register = 0 0000 1101 main dividend register, lsb = 1001 1000 main dividend register, msb = 00 0111 1101 the resulting main vco frequency is 902.453 mhz step size is 76.3 hz note: the frequency step size for this case is 20 mhz divided by 2 18 , giving 76.3 hz. c1414 figure 4. fractional-n applications: sample calculation (1 of 2)
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 7 case 2: to achieve a desired f vco_main frequency of 917.7786 mhz using a crystal frequency of 19.2 mhz with operation of the synthesizer in 10-bit mode. since the maximum internal reference frequency ( f div_ref ) is 25 mhz, the crystal frequency does not require the internal division to be greater than 1, which makes f div_ref = 19.2 mhz. therefore: n fractional = f vco_main f div_ref = 917.7786 19.2 = 47.80097 the value to be programmed in the main divider register is: n reg = round[ n fractional ] C 32 = round[47.80087] C 32 = 48 C 32 = 16 (decimal) = 000010000 (binary) with the modulator in 10-bit mode, the value to be programmed in the main dividend registers is: dividend = round[divider ( n fractional C n reg C 32)] = round[1024 (47.80087 C 16 C 32)] = round[1024 (C0.1990312)] = round[C203.808] = 204 (decimal) = 1100110100 (binary) where 11 0011 0100 is loaded in the msb of the main dividend register. summary: main divider register = 0 0001 0000 main dividend register, msb = 11 0011 0100 the resulting main vco frequency is 917.775 mhz step size is 18.75 khz note: the frequency step size for this case is 19.2 mhz divided by 2 10 , giving 18.75 khz. c1415 figure 4. fractional-n applications: sample calculation (2 of 2)
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 8 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n case 1: to achieve a desired f vco_aux frequency of 400 mhz using a crystal frequency of 16 mhz. since the minimum divide ratio is 32, the reference frequency ( f div_ref ) must be a maximum of 12.5 mhz. choosing a reference frequency divide ratio of 2 provides a reference frequency of 8 mhz. therefore: n integer = f vco_aux f div_ref = 400 8 = 50 the value to be programmed in the auxiliary divider register is: n reg = n integer C 32 = 50 C 32 = 18 (decimal) = 000010010 (binary) summary: auxiliary divide register = 0 0001 0010 c141 6 figure 5. integer-n applications: sample calculation normal register write . a normal 16-bit serial interface write occurs when the cs signal is 16 clock cycles wide. the corresponding 16-bit modulation data is simultaneously presented to the data pin. the content of the modulation data register is passed to the modulation unit at the next falling edge of the divided main vco frequency ( f pd_main ). short cs through data pin (no address bits required) . a shortened serial interface write occurs when the cs signal is from 2 to 12 clock cycles wide. the corresponding modulation data (2 to 12 bits) is simultaneously presented to the data pin. the data pin is the default pin used to enter modulation data directly in the modulation data register with shortened cs strobes. this method of data entry eliminates the register address overhead on the serial interface. all serial interface bits are re- synchronized internally at the reference oscillator frequency. the content of the modulation data register is passed to the modulation unit at the next falling edge of the divided main vco frequency ( f pd_main ). short cs through mod_in pin (no address bits required) . a shortened serial interface write occurs when the cs signal is from 2 to 12 clock cycles wide. the corresponding modulation data (2 to 12 bits) is simultaneously presented on the mod_in pin, an alternate pin used to enter modulation data directly into the modulation data register with shortened cs strobes. this mode is selected through the modulation control register. this method of data entry also eliminates the register address overhead on the serial interface and allows a different device than the one controlling the channel selection to enter the modulation data (e.g., a microcontroller for channel selection and a digital signal processor for modulation data). all serial interface bits are internally re-synchronized at the reference oscillator frequency and the content of the modulation data register is passed to the modulation unit at the next falling edge of the divided main vco frequency ( f pd_main ). modulation data samples in the modulation data register can be from 2 to 12 bits long, and enable the user to select how many distinct frequency steps are to be used for the desired modulation scheme. the user can also control the frequency deviation through the modulation data magnitude offset in the modulation control register. this allows shifting of the modulation data to accomplish a 2 m multiplication of frequency deviation. note: the programmable range of C0.5 to +0.5 of the main '6 modulator can be exceeded up to the condition where the sum of the dividend and the modulation data conform to: 5625 . 0 ) dividend n ( 5625 . 0 mod d d
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 9 table 1. SKY72300-21 register map address (hex) register (note 1) length (bits) address (bits) 0 main divider register 12 4 1 main dividend msb register 12 4 2 main dividend lsb register 12 4 3 auxiliary divider register 12 4 4 auxiliary dividend register 12 4 5 reference frequency dividers register 12 4 6 phase detector/charge pump control register 12 4 7 power down/multiplexer output se lect control register 12 4 8 modulation control register 12 4 9 modulation data register modulation data register (not e 2) direct input 12 2 length 12 bits 4 0 note 1 : all registers are write only. note 2 : no address bits are required for modulation data. any serial data between 2 and 12 bits long is considered modulation data. when the sum of the dividend and modulation data lie outside this range, the value of n integer must be changed. for a more detailed description of direct digital modulation functionality, refer to the skyworks application note, direct digital modulation using the SKY72300-21, sky72301, and sky72302 dual synthesizers/plls (document number 101349). register descriptions table 1 lists the 10 16-bit registers that are used to program the SKY72300-21. all register writes are programmed address first, followed directly with data. msbs are entered first. on power up, all registers are reset to 0x000 except registers at addresses 0x0 and 0x3, which are set to 0x006. main synthesizer registers the main divider register contains the integer portion closest to the desired fractional-n (or the integer-n) value minus 32 for the main synthesizer. this register, in conjunction with the main dividend msb and lsb registers (which control the fraction offset from C0.5 to +0.5), allows selection of a precise frequency. as shown in figure 6, the value to be loaded is: x main synthesizer divider index = nine-bit value for the integer portion of the main synthesizer dividers. valid values for this register are from 6 to 505 (fractional-n) or 0 to 511 (integer-n). the main dividend msb and lsb registers control the fraction part of the desired fractional-n value and allow an offset of C0.5 to +0.5 to the main integer selected through the main divider register. as shown in figures 7 and 8, values to be loaded are: x main synthesizer dividend (msbs) = ten-bit value for the msbs of the 18-bit dividend for the main synthesizer. x main synthesizer dividend (lsbs) = eight-bit value for the lsbs of the 18-bit dividend for the main synthesizer. the main dividend register msb and lsb values are 2's complement format. note: when in 10-bit mode, the main dividend lsb register is not required. auxiliary synthesizer registers the auxiliary divider register contains the integer portion closest to the desired fractional-n (or integer-n) value minus 32 for the auxiliary synthesizer. this register, in conjunction with the auxiliary dividend register (which controls the fraction offset from C0.5 to +0.5), allows selection of a precise frequency. as shown in figure 9, the value to be loaded is: x auxiliary synthesizer divider index = nine-bit value for the integer portion of the auxiliary synthesizer dividers. valid values for this register are from 6 to 505 (fractional-n) or from 0 to 511 (integer-n). the auxiliary dividend register controls the fraction part of the desired fractional-n value and allows an offset of C0.5 to +0.5 to the auxiliary integer selected through the auxiliary divider register. as shown figure 10, the value to be loaded is: x auxiliary synthesizer dividend = ten-bit value for the auxiliary synthesizer dividend.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 10 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 x x x msb lsb main synthesizer divider inde x c141 7 figure 6. main divider register (write only) c1418 a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 x x msb lsb main synthesizer dividend (msbs) figure 7. main dividend msb register (write only) a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 x x x x msb lsb main synthesizer dividend (lsbs) c1419 figure 8. main dividend lsb register (write only) general synthesizer registers the dual-programmable reference frequency dividers provide the reference frequencies to the phase detectors by dividing the crystal oscillator frequency. the lower five bits hold the reference frequency divide index for the main phase detector. the next five bits hold the reference frequency divide index for the auxiliary phase detector. divide ratios from 1 to 32 are possible for each reference frequency divider (see tables 2 and 3). the reference frequency dividers register configures the dual- programmable reference frequency dividers for the main and auxiliary synthesizers. as shown in figure 11, the values to be loaded are: x main reference frequency divider index = desired main oscillator frequency division ratio C1. default value on power up is 0, signifying that the reference frequency is not divided for the main phase detector. x auxiliary reference frequency divider index = desired auxiliary oscillator frequency division ratio C1. default value on power up is 0, signifying that the reference frequency is not divided for the auxiliary phase detector.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 11 a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 x x x msb lsb auxiliary synthesizer divider index c1420 figure 9. auxiliary divider register (write only) a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 x x msb lsb auxiliary synthesizer dividend c1421 figure 10. auxiliary dividend register (write only) table 2. programming the main reference frequency divider decimal bit 4 (msb) bit 3 bit 2 bit 1 bit 0 (lsb) reference divider ratio 0 0 0 0 0 0 1 1 0 0 0 0 1 2 2 0 0 0 1 0 3 31 1 1 1 1 1 32 table 3. programming the auxiliary reference frequency divider decimal bit 9 (msb) bit 8 bit 7 bit 6 bit 5 (lsb) reference divider ratio 0 0 0 0 0 0 1 1 0 0 0 0 1 2 2 0 0 0 1 0 3 31 1 1 1 1 1 32
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 12 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 0101xx main reference frequency divider index auxiliary reference frequency divider index c1422 figure 11. reference frequency dividers register (write only) a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 0110 main phase detector gain main power steering/lock detect enable auxiliary phase detector gain auxiliary power steering/lock detect enable c1423 figure 12. phase detector/charge pump control register (write only) the phase detector/charge pump control register allows control of the gain for both phase detectors and configuration of the ld/psmain and ld/psaux signals for frequency power steering or lock detection. as shown in figure 12, the values to be loaded are: x main phase detector gain = five-bit value for programmable main phase detector gain. range is from 0 to 31 decimal for 31.25 to 1000 p a/ 2 s radian, respectively. x main power steering enable = one-bit flag to enable the frequency power steering circuitry of the main phase detector. when this bit is cleared, the ld/psmain pin is configured to be a lock detect, active low, open collector pin. when this bit is set, the ld/psmain pin is configured to be a frequency power steering pin and can be used to bypass the external main loop filter to provide faster frequency acquisition. x auxiliary phase detector gain = five-bit value for programmable auxiliary phase detector gain. range is from 0 to 31 decimal for 31.25 to 1000 p a/2 s radians, respectively. x auxiliary power steering enable = one-bit flag to enable the frequency power steering circuitry of the auxiliary phase detector. when this bit is cleared, the ld/psaux pin is configured to be a lock detect, active low, open collector pin. when this bit is set, the ld/psaux pin is configured to be a frequency power steering pin and may be used to bypass the external auxiliary loop filter to provide faster frequency acquisition. the power down/multiplexer output select control register allows control of the power-down modes, internal multiplexer output, and main '6 synthesizer fractionality. as shown in figure 13, the values to be loaded are: x full power down = one-bit flag to power down the sky72300- 21 except for the reference oscillator and the serial interface. when this bit is cleared, the SKY72300-21 is powered up. when this bit is set, the SKY72300-21 is in full power-down mode excluding the mux_out signal (pin 3). x main synthesizer power down = one-bit flag to power down the main synthesizer. when this bit is cleared, the main synthesizer is powered up. when this bit is set, the main synthesizer is in power-down mode. x main synthesizer mode = one-bit flag to power down the main synthesizers '6 modulator and fractional unit to operate as an integer-n synthesizer. when this bit is cleared, the main synthesizer is in fractional-n mode. when this bit is set, the main synthesizer is in integer-n mode.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 13 a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 x x msb lsb full power down main synthesizer power down main synthesizer mode main synthesizer ? fractionality auxiliary synthesizer power down auxiliary synthesizer mode multiplexer output selection mux_out pin tri-state enable c1424 figure 13. power down and multiplexer output register (write only) table 4. multiplexer output multiplexer output select (bit 8) multiplexer output select (bit 7) multiplexer output select (bit 6) multiplexer output (mux_out) 0 0 0 reference oscillator 0 0 1 auxiliary reference frequency ( f ref_aux ) 0 1 0 main reference frequency ( f ref_main ) 0 1 1 auxiliary phase detector frequency ( f pd_aux ) 1 0 0 main phase detector frequency ( f pd_main ) 1 0 1 serial data out 1 1 0 serial interface test output 1 1 1 unused x main synthesizer '6 fractionality = one-bit flag to configure the size of the main '6 modulator. this has a direct effect on power consumption, and on the level of fractionality and step size. when this bit is cleared, the main '6 modulator is 18-bit with a fractionality of 218 and a step size of f ref_main /262144. when this bit is set, the main '6 modulator is 10-bit with a fractionality of 210 and a step size of f ref_main /1024. x auxiliary synthesizer power down = one-bit flag to power down the auxiliary synthesizer. when this bit is cleared, the auxiliary synthesizer is powered up. when this bit is set, the auxiliary synthesizer is in power-down mode. x auxiliary synthesizer mode = one-bit flag to power down the auxiliary synthesizers '6 modulator and fractional unit to operate as an integer-n synthesizer. when this bit is cleared, the auxiliary synthesizer is in fractional-n mode. when this bit is set, the auxiliary synthesizer is in integer-n mode. note: there are no special power-up sequences required for the SKY72300-21. x multiplexer output selection = three-bit value that selects which internal signal is output to the mux_out pin. the following internal signals are available on this pin: reference oscillator: f ref main or auxiliary divided reference (post-reference frequency main or auxiliary dividers): f ref_main or f ref_aux main or auxiliary phase detector frequency (post-main or auxiliary frequency dividers): f pd_main or f pd_aux serial data out for loop-back and test purposes refer to table 4 for more information. x mux_out pin tri-state enable = one-bit flag to tri-state the mux_out pin. when this bit is cleared, the mux_out pin is enabled. when this bit is set, the mux_out pin is tri-stated.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 14 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 000x x reserved bits modulation data magnitude offset modulation data input select modulation address disable c1425 figure 14. modulation control register (write only) a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 msb lsb modulation data bits c1426 figure 15. modulation data register (write only) the modulation control register is used to configure the modulation unit of the main synthesizer. the modulation unit adds or subtracts a frequency offset to the selected center frequency at which the main synthesizer operates. the size of the modulation data sample, controlled by the duration of the cs signal, can be from 2 to 12 bits wide to provide from 4 to 4096 selectable frequency offset steps. the modulation data magnitude offset selects the magnitude multiplier for the modulation data and can be from 0 to 8. as shown in figure 14, the values to be loaded are: x modulation data magnitude offset = four-bit value that indicates the magnitude multiplier (m) for the modulation data samples. valid values range from 0 to 13, effectively providing a 2m multiplication of the modulation data sample. x modulation data input select = one-bit flag to indicate the pin on which modulation data samples are serially input when the cs signal is between 2 and 12 bits long. when this bit is cleared, modulation data samples are to be presented on the data pin. when this bit is set, modulation data samples are to be presented on the mod_in pin. x modulation address disable = one-bit flag to indicate the presence of the address as modulation data samples are presented on either the mod_in or data pins. when this bit is cleared, the address is presented with the modulation data samples (i.e., all transfers are 16 bits long). when this bit is set, no address is presented with the modulation data samples (i.e., all transfers are 2 to 12 bits long). the modulation data register is used to load the modulation data samples to the modulation unit. these values are transferred to the modulation unit on the falling edge of f pd_main where they are passed to the main '6 modulator at the selected magnitude offset on the next falling edge of f pd_main . modulation data register values are 2's complement format. as shown in figure 15, the value to be loaded is: x modulation data bits = modulation data samples that represent the instantaneous frequency offset to the selected main synthesizer frequency (selected channel) before being affected by the modulation data magnitude offset. package and handling information since the device package is sensitive to moisture absorption, it is baked and vacuum packed before shipping. instructions on the shipping container label regarding exposure to moisture after the container seal is broken must be followed. otherwise, problems related to moisture absorption may occur when the part is subjected to high temperature during solder assembly. the SKY72300-21 is rated to moisture sensitivity level 3 (msl3) at 260 q c. it can be used for lead or lead-free soldering. care must be taken when attaching this product, whether it is done manually or in a production solder reflow environment.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 15 production quantities of this product are shipped in a standard tape and reel format. for packaging details, refer to the skyworks application note, tape and reel, document number 101568. electrical and mechanical specifications the SKY72300-21 is supplied as a 28-pin ep-tssop. the exposed pad is located on the bottom side of the package and must be connected to ground for proper operation. the exposed pad should be soldered directly to the circuit board. signal pin assignments and functional pin descriptions are described in table 5. the absolute maximum ratings of the SKY72300-21 are provided in table 6. the recommended operating conditions are specified in table 7 and electrical specifications are provided in table 8. figure 16 provides a schematic diagram for the SKY72300-21. figure 17 shows the package dimensions for the 28-pin ep-tssop and figure 18 provides the tape and reel dimensions. table 5. SKY72300-21 signal descriptions (1 of 2) pin # pin name type description 1 clock digital input clock signal pin. when cs is low, the register address and data are shifted in address bits first on the data pin on the rising edge of clock. 2 mod_in digital input alternate serial modulation data input pin. address bits are followed by data bits. 3 mux_out digital output internal multiplexer output. selects from oscillator frequency, main or auxiliary reference frequency, main or auxiliary divided vco frequency, serial data out, or testability signals. this pin can be tri-stated from the general synthesizer registers. 4 vsubdigital C substrate isolation. connect to ground. 5 gndecl/cml (note 1) power and ground emitte r coupled logic (ecl)/current mode logic (cml) ground. 6 vcccml_main (note 1) power and ground ecl/cml 3 v. removing power safely powers down the associated divider chain and charge pump. 7 fvco_main input main vco differential input. 8 fvco_main input main vco compliment ary differential input. 9 ld/psmain analog output progr ammable output pin. indicates main phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detect ed), or helps the loop filter steer the main vco. this pin is configured using the phase detecto r/charge pump control register. 10 vcccp_main (note 1) power and ground main charge pump supply, 3 to 5 v. removing power safely powers down the associated divider chain and charge pump. 11 cpout_main analog output main charge pump output. the gain of the main charge pump phase detector is controlled by the phase detector/charge pump control register. 12 gndcp_main (note 1) power and ground main charge pump ground. 13 xtalacgnd/osc ground/input reference crystal ac ground or external oscillator differential input. 14 xtalin/osc input reference crystal input or external oscillator differential input. 15 xtalout/nc input reference cr ystal output or no connect. 16 vccxtal power and ground crystal oscillator ecl/cml, 3 v. 17 gndxtal power and ground crystal oscillator ground. 18 ld/psaux analog output programmable output pin. indicates auxiliary phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the auxiliary vco. this pin is configured using the phase detec tor/charge pump control register.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 16 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n table 5. SKY72300-21 signal descriptions (2 of 2) pin # pin name type description 19 vcccp_aux (note 1) power and ground auxiliary charge pump supply, 3 to 5 v. removing power safely powers down the associated divider chain and charge pump. 20 cpout_aux analog output auxiliary charge pump output. the gain of the auxiliary charge pump phase detector is controlled by the phase detector/charge pump control register. 21 gndcp_aux (note 1) power and ground auxiliary charge pump ground. 22 fvco_aux input auxiliary vco complimentary differential input. 23 fvco_aux input auxiliary vco differential input. 24 vcccml_aux (note 1) power and ground ecl/cml, 3 v. removing power safely powers down the associated divider chain and charge pump. 25 gnddigital (note 1) power and ground digital ground. 26 vccdigital (note 1) power and ground digital 3 v. 27 data digital input serial address and data input pin. address bits are followed by data bits. 28 cs digital input active low enable pin. enables loading of address and data on the data pin on the rising edge of clock. when cs goes high, data is transferred to the register indicated by the address. subsequent clock edges are ignored. note 1 : associated pairs of power and ground pins must be decoupled using 0.1 p f capacitors. table 6. absolute maximum ratings parameter min max units maximum analog rf supply voltage 3.6 vdc maximum digital supply voltage 3.6 vdc maximum charge pump supply voltage 5.25 vdc storage temperature C65 +150 c operating temperature C40 +85 c note : exposure to maximum rating conditions for extended periods m ay reduce device reliability. there is no damage to device with o nly one parameter set at the limit and all other parameters set at or below their nominal values. exceeding any of the limits listed here may result in permanent damage to the device. caution : although this device is designed to be as robust as possible, electrostatic discharge (esd) can damage this device. this devi ce must be protected at all times from esd. static charges may easily produce potentials of several kilovolts on the human body or equipment, which can discharge without detection. industry-standard esd precautions should be used at all times. table 7. recommended operating conditions parameter min max units analog rf supplies 2.7 3.3 vdc digital supply 2.7 3.3 vdc charge pump supplies 2.7 5.0 (note 1) vdc operating temperature (t a ) C40 +85 c note 1 : when power steering is enabled, the charge pump must be 4.5 v maximum.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 17 table 8. electrical characteristics (note 1) (1 of 2) (vdd = 3 v, t a = 25 q c, unless otherwise noted) parameter symbol test conditions min typ max units power consumption charge pump currents of 200 p a. both synthesizers fractional, f ref _ main = 20 mhz, f ref _ aux = 1 mhz 37.5 mw total power consumption p total auxiliary synthesizer power down 27 mw power-down current i cc _ pwdn 10 (note 2) p a reference oscillator reference oscillator frequency f osc 50 mhz oscillator sensitivity (as a buffer) v osc ac coupled, single-ended 0.1 2.0 vpp frequency shift versus supply voltage f shift _ supply 2.7 v d v xtal d 3.3 v r 0.3 ppm vcos main synthesizer operating frequency f vco _ main sinusoidal, C40 q c to +85 q c 100 (note 3) 2100 mhz auxiliary synthesizer operating frequency f vco _ aux sinusoidal, C40 q c to +85 q c 100 (note 3) 500 mhz rf input sensitivity v vco ac coupled 50 250 mv peak rf input impedance z vco _ in 94 C j140 @ 1200 mhz : main fractional-n tuning step size ' f step _ main f ref _ main /218 or f ref _ main /210 hz auxiliary fractional-n tuning step size ' f step _ aux f ref _ aux /210 hz noise phase noise floor p nf measured inside the loop bandwidth using 25 mhz reference frequency, C40 q c to +85 q c C128 + 20 log (n) dbc/hz phase detectors and charge pumps main phase detector frequency f ref _ main C40 q c to +85 q c 25 mhz auxiliary phase detector frequency f ref _ aux C40 q c to +85 q c 25 mhz charge pump output source current i cp - source v cp = 0.5 vcc cp 125 1000 p a charge pump output sink current i cp - sink v cp = 0.5 vcc cp C125 C1000 p a charge pump accuracy i cp - accuracy 20 % charge pump output volt age linearity range i cp vs v cp 0.5 v d v cp d (vcc cp C 0.5 v) gnd + 400 vcc cp C 400 mv charge pump current ver sus temperature i cp vs t v cp = 0.5 vcc cp C40 q c < t < +85 q c 5 % charge pump current versus voltage i cp vs v cp 0.5 v d v cp d (vcc cp C 0.5 v) 8 %
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 18 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n table 8. electrical characteristics (note 1) (2 of 2) (vdd = 3 v, t a = 25 q c, unless otherwise noted) parameter symbol test conditions min typ max units digital pins high level input voltage v ih 0.7 v digital v low level input voltage v il 0.3 v digital v high level output voltage v oh i oh = C2 ma v digital C0.2 v low level output voltage v ol i ol = +2 ma gnd + 0.2 v timing C serial interface clock frequency f clock 100 mhz data and cs set up time to clock rising t su 3 ns data and cs hold time after clock rising t hold 0 ns note 1: performance is guaranteed only under the conditions listed in this table and is not guaranteed over the full operating or stor age temperature ranges. operation at elevated temperatures may reduce reliability of the device. note 2 : a 5 v charge pump power supply (on pin 10 and/or pin 19) results in higher power-down leakage current. note 3 : the minimum synthesizer frequency is 12 x f osc , where f osc is the frequency at the xtalin/osc pin.
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 19 clock mod_in mux_out vsubdigital gndecl/cml vcccml_main fvco_main cs data vccdigital gnddigital vcccml_aux fvco_aux fvco_aux fvco_main ld/psmain vcccp_main cpout_main gndcp_main xtalacgnd/osc xtalin/osc gndcp_aux cpout_aux vcccp_aux ld/psaux gndxtal vccxtal xtalout/nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd to microprocessor 3 v 3 v 3 v vc c 3 v 3 v 3 v 3 v 3 v c5 c7 1 543 2 4 3 1 2 rf out main j1 1 5 4 4 2 1 3 3 2 rf out auxiliary j1 main vco y1 main synthesizer loop filter auxiliary synthesizer loop filter auxiliary vco external pad connection to ground gnd vcc c14 r4 r6 100 k r5 c15 c8 gnd vt vcc rfout c12 c9 c4 c6 r3 r2 c19 c18 c17 c17 1 nf v cc rfout vt lock detect main output lock detect auxiliary output c10 1 nf a r1 100 k c3 1 nf c11 1 nf c2 1 nf c1 1 nf c16 100 pf c1427 < > figure 16. SKY72300-21 application schematic
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 20 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n 3.50 +0.10/C0.86 3.00 +0.10/C0.86 0.127 +0.037/C0.033 0.19/0.30 0.09/0.2 6.40 1.00 1.1 max 0.05/0.150 detail a with plating base metal seating plane parting line detail b 1.00 0.65 2.200 2x 14 tips 11 28 28 2 3 4.40 0.01 9.70 0.01 0.60 0.10 + + (1.00) 0.22 0.03 0.90 0.05 top view side view detail a end view detail b exposed pad view 0.25 0 o /8 o 14.00 o 14.00 o 0.325 b a d c h h d aCb c 0.20 c 0.076 d aCb c 0.10 c1428 all measurements are in millimeters ? 1.00 c 0.05 figure 17. SKY72300-21 28-pin ep-tssop package dimensions
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 101217n ? skyworks proprietary information ? products and product information are subject to change without notice ? sep tember 11, 2009 21 0.318 0.013 1.10 3.96 6.75 0.10 8 o max 7 o max 1.60 0.10 9.95 0.10 1.50 0.25 16.00 +0.30/C0.10 7.50 0.10 8.00 0.10 4.00 0.10 2.00 0.05 1.75 0.10 1.50 0.10 pin #1 notes: 1. carrier tape material: black conductive polystyrene 2. cover tape material: transparent conductive psa 3. cover tape size: 13.3 mm width 4. all measurements are in millimeters c1430 ab a b b a figure 18. SKY72300-21 tape and reel dimensions
data sheet ? SKY72300-21 frequency synthesizer skyworks solutions, inc. ? phone [781] 376-3000 ? fax [781] 376-3100 ? sales@skyworksinc.com ? www.skyworksinc.com 22 september 11, 2009 ? skyworks proprietary information ? products and product information are subject to change without not ice ? 101217n ordering information model name manufacturing part number evaluation kit part number SKY72300-21 2.1 ghz frequency synthesizer SKY72300-21 (pb-free package) tw16-d400-011 copyright ? 2001, 2002, 2004, 2005, 2006, 2007, 2009 skyworks solutions, inc. all rights reserved. information in this document is provided in connection with skyworks solutions, inc. (skyworks) products or services. these m aterials, including the information contained herein, are provided by skyworks as a service to its customers and may be used for informational purposes only by the customer. skyworks assumes no res ponsibility for errors or omissions in these materials or the information contained herein. skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other diff iculties arising from any future changes. no license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document . skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of skyworks products, information or mate rials, except as may be provided in skyworks terms and conditions of sale. the materials, products and information are provided as is without warranty of any kind, whether express, implied, statutory, or otherwise, including fitness for a particular purpose or use, mercha ntability, performance, quality or non-infringement of any intellectual property right; all su ch warranties are hereby expressly disclaimed. skyworks does not warrant the accuracy or completeness of the information, text, graphics or other items contained within these materials. skyworks shall not be liable for any damages, including but not limited to any special, indirect, incidental, statutory, or consequentia l damages, including without limitation, lost revenues or lost profits that may result from the use of the materials or information, whether or not the recipient of mat erials has been advised of the possibility of such damage. skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the skyworks products could lead to personal injury, death, physical or environmental damage. skyworks customers using or selling skyworks products for use in such applications do so at their own risk and agree to fully indemnify skyworks for any damages resulting from such improper use or sale. customers are responsible for their products and applications using skyworks products, which may deviate from published specifi cations as a result of design defects, errors, or operation of products outside of published parameters or design specifications. customers should include design and operating safeguards to minimize these and other risks. skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of skyworks products outsid e of stated published specifications or parameters. skyworks, the skyworks symbol, and breakthrough simplicity are trademarks or registered trademarks of skyworks solutions, inc ., in the united states and other countries. third-party brands and names are for identification purposes only, and are the property of their respective owners. additional information, includ ing relevant terms and conditions, posted at www.skyworksinc.com, are incorporated by reference.
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