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| 16 - bit, serial input, loop - powered, 4 ma to 20 ma dac da ta sheet ad5421 rev. f document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any inf ringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and regi stered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2011 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 16- b it r esolution and m onotonicity pin selectable namur - compliant r anges 4 m a to 2 0 m a 3. 8 m a to 2 1 m a 3. 2 m a to 2 4 m a namur - c ompliant alarm c urrents downscale alarm current = 3. 2 m a upscale alarm c urrent = 22. 8 m a/2 4 m a t otal u nadjusted e rror (tu e) : 0.05 % maximum inl error: 0.0035% fsr maximum o utput tc : 3 ppm/ c typ ical quiescent current: 300 a m ax imum flexible spi - c omp atible serial digital interface with schmitt t riggered i nputs on - c hip f ault a lerts via fault pin or alarm c urrent automatic r ea dback of f ault r egister on each write cycle slew r ate c ontrol f unction gain and o ffset a djust r egisters on - c hip r eference tc : 4 ppm/ c m ax imum selectable r egulated v oltage o utput loop voltage range: 5. 5 v to 5 2 v temperature range : ?4 0c to +105c tssop an d lfcsp p ackage s applications industrial p rocess c ontrol 4 ma to 2 0 m a l oop - p owered t ransmitter s smart t ransmitter s hart network connectivity general description the ad5421 is a complete, loop - powered, 4 ma to 2 0 ma digital - to - analog converter (dac) designed to meet the needs of smart transmitter manufacturers in t he i ndustrial c ontrol industr y. the dac provides a high precision, fully integrated, low cost solution in compact tssop and lfcsp package s. the ad542 1 includes a regulated voltage output that is used to power itself and other devices in the transmitter. this regulator provides a regulated 1.8 v to 12 v output voltage. the ad5421 also contains 1.22 v and 2.5 v references , thus eliminating the need for a discrete r egulator and voltage reference. the ad5421 can be used with standard hart? fsk protocol communication circuitry without any degradation in specified performance. the high speed serial interface is capable of opera - ting at 30 m hz and allows for s imple connection to commonly used microprocessors and microcontrollers via a spi - compatible , 3 - wire interface. the ad542 1 is guaranteed monotonic to 16 bits . it provides 0.0015% integral nonlinearity, 0.001 2 % offset error , and 0.0006% gain error under typi cal conditions . the ad5421 is available in a 28 - lead tssop and a 32 - lead lfcsp specified over the extended industrial temperature range of ? 40 c to +105c. c ompanion low power products hart modem: ad5700 , ad5700 - 1 microcontroller: aducm360 functional bl ock diagram r set 24k? sync sclk sdin sdo ldac range0 range1 alarm_current_direction fault r int /r ext input register control logic gain/offset adjustment registers temperature sensor refout2 refin c in r ext1 r ext2 refout1 vref 16 16-bit dac loop voltage monitor v loop dv dd iodv dd ad5421 voltage regulator reg_sel0 reg_sel1 reg_sel2 reg out reg in drive loop? 11.5k? 52? 09128-001 com figure 1.
ad5421 data sheet rev. f | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 companion low power products .................................................. 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 ac performance characteristics ................................................ 9 timing characteristics ................................................................ 9 absolute maximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 typical performance characteristics ........................................... 14 terminology .................................................................................... 20 theory of operation ...................................................................... 21 fault alerts .................................................................................. 21 external current setting resistor ............................................ 22 loop current range selection .................................................. 22 connection to loop power supply .......................................... 22 on - chip adc ............................................................................ 23 voltage regulator ....................................................................... 23 loop current slew rate control .............................................. 23 power - on default ...................................................................... 24 hart communications ........................................................... 24 serial interface ................................................................................ 26 input shift register .................................................................... 26 register readback ...................................................................... 26 dac register .............................................................................. 27 control register ......................................................................... 28 fault register .............................................................................. 29 offset adjust register ................................................................ 30 gain adjust register .................................................................. 30 applications information .............................................................. 32 determining the expected total error .................................... 32 thermal and supply considerations ....................................... 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 36 data sheet ad5421 rev. f | page 3 of 36 revision history 1 /1 3 rev. e to rev. f moved revision history section ..................................................... 3 change to table 7 ............................................................................ 11 changes to table 8 .......................................................................... 1 3 changes to on - chip adc section ............................................... 23 changes to table 19 and on - chip adc transfer function equations section ............................................................................ 29 7 /12 rev. d to rev. e changes to figure 1 and companion products section .............. 1 changes to pin loop ? description ............................................ 1 2 changes to applications informatio n section and figure 49 ... 31 added figure 50 .............................................................................. 32 5 /12 rev. c to rev. d changes to features section and applications section ; added companion products section .......................................................... 1 changes to line regulation parameter, table 1 ............................ 5 updated outline dimensions ........................................................ 33 12/11 rev. b to rev. c change to refout1 pin, capacitive load parameter, test conditions, table 1 ........................................................................... 4 change to reg out output, capacitive load parameter, test conditions, table 1 ........................................................................... 5 changes to esd parameter, table 6 .............................................. 10 12 /11 rev. a to rev. b added 32- lead lfcsp ...................................................... universal changes to the specifications section, table 1 ............................. 3 changes to table 7 .......................................................................... 10 added figure 5, renumbered sequentially ................................. 11 changes to table 8 .......................................................................... 11 changes to figure 33 ...................................................................... 17 changes to the on - chip adc section ........................................ 22 changes to figure 46 ...................................................................... 23 changes to figure 48 ...................................................................... 24 changes to the re g ister re adback section .................................. 25 updated outline dimensions ........................................................ 33 changes to ordering guide ........................................................... 34 5/11 rev. 0 to rev. a change s to reg in , refout1, and refout2 pin description s in table 8 .......................................................................................... 10 change to figure 45 ........................................................................ 22 changes to input shift register section, table 11, and r egister readback section ............................................................................ 24 change s to figure 48 ...................................................................... 30 2 /1 1 revision 0: initial version ad5421 data sheet rev. f | page 4 of 36 specifications loop v oltage = 24 v; refin = 2.5 v external ; r l = 250 ? ; external nmos connected; a ll loop current r anges; all specifications t min to t max , unless other wise noted . table 1 . parameter 1 min typ max unit test conditions/comments accuracy , internal r set resolution 16 bits total unadjusted error (tue) 2 ?0 .126 + 0.126 % fsr c grade ? 0. 041 0.0064 +0. 041 % fsr c grade, t a = 25c ?0 . 18 + 0 . 18 % fsr b grade ?0 . 06 0.0 11 +0. 06 % fsr b grade, t a = 25c ? 0.27 + 0.27 % fsr a grade ? 0.08 0.0 11 + 0.08 a grade, t a = 25c tue long - term stability 210 ppm fsr drift after 1000 hours at t a = 1 25c relative accuracy (inl) ?0.00 35 0.0015 +0.0035 % fsr c grade ?0.0 12 0.006 +0. 012 % fsr b grade ? 0.024 0.01 + 0.024 % fsr a grade differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic offset error ?0.056 +0.056 % fsr b grade and c grade ?0.008 0.0008 +0.008 % fsr b grade and c grade, t a = 25c ?0.11 0.0008 +0.11 % fsr a grade offset error tc 3 1 ppm fsr/c gain error ?0.107 +0.107 % fsr b grade and c grade ?0.035 0.0058 +0.035 % fsr b grade and c grade, t a = 25c ?0. 2 0. 0058 +0. 2 % fsr a grade gain error tc 3 4 ppm fsr/c full - scale error ?0.126 +0.126 % fsr b grade and c grade ?0.041 0.0065 +0.041 % fsr b grade and c grade, t a = 25c ?0. 25 0.0065 +0. 25 % fsr a grade full - scale error tc 3 5 ppm fsr/c downscale alarm current 3.19 3.21 ma upscale alarm current 22.77 22.83 ma 4 ma to 20 ma and 3.8 ma to 21 ma ranges 23.97 24.03 ma 3.2 ma to 24 ma r ange accuracy, external r set (24 k?) assumes ideal resistor, b grade an d c grade only; not specified for a grade resolution 16 bits total unadjusted error (tue) 2 ?0.048 +0.048 % fsr c grade ?0.027 0.002 +0.027 % fsr c grade, t a = 25c ?0 .08 + 0 .08 % fsr b grade ?0 .04 0.00 3 +0.04 % fsr b grade, t a = 25c tue long - term stability 40 ppm fsr drift after 1000 hours at t a = 1 25c relative acc uracy (inl) ?0.0035 0.0015 +0.0035 % fsr c grade ?0. 012 0.006 +0.0 12 % fsr b grade differential nonlinearity (dnl) ?1 +1 lsb guaranteed mon otonic offset error ?0.021 +0.021 % fsr ?0.007 0.0012 +0.007 % fsr t a = 25c offset error tc 3 0.5 ppm fsr/c gain error ?0.03 +0.03 % fsr ?0.023 0.0006 +0.023 % fsr t a = 25c data sheet ad5421 rev. f | page 5 of 36 parameter 1 min typ max unit test conditions/comments gain error tc 3 1 ppm fsr/c full - scale error ?0.047 +0.047 % fsr ?0.028 0.0017 +0.028 % fsr t a = 25c full - scale error tc 3 1 ppm fsr/c downscale alarm current 3. 08 3.21 ma upscale alarm current 22.78 23 ma 4 ma to 20 ma and 3.8 ma to 21 ma ranges 23.99 24.01 ma 3.2 ma to 24 ma r ange output characteristics 3 loop compliance voltage 4 loop? + 5.5 v reg out < 5.5 v, loop current = 24 ma loop? + 12.5 v reg out = 12 v, loo p current = 24 ma loop current long - term stability 100 ppm fsr drift after 1000 hours at t a = 125c, loop current = 12 ma , internal r set 15 ppm fsr drift after 1000 hours at t a = 125c, loop current = 12 ma , external r set loop current error vs. reg out l oad current 1.2 a/ma loop current = 12 ma, load current from reg out = 5 ma resistive load 0 2 k ? see figure 20 for a load line graph inductive load 50 mh stable operation power supply sensitivity 0.1 a/v loop c urrent = 12 ma output impedance 12 400 m? output tc 3 ppm fsr/c loop c urrent = 12 ma, i nternal r set 1 ppm fsr/c loop current = 12 ma, external r set output noise 0.1 hz to 10 hz 50 n a p - p 500 hz to 10 khz 0.2 mv rms hart bandwidth; measured across 500 ? load noise spectral density 195 na/hz at 1 khz 256 na/hz at 10 khz reference input (refin pin) 3 reference input voltage 5 2.5 v for specified performance dc input impedance 7 5 800 m? reference outputs refout1 pin output voltage 2.498 2.5 2.503 v t a = 25c temperature coefficie nt 1.5 4 ppm/c c grade 2 8 ppm/c b grade 4 10 ppm/c a grade output noise (0.1 hz to 10 hz) 3 7.5 v p -p noise spectral density 3 245 nv/hz at 1 khz 70 nv/hz at 10 khz outpu t voltage drift vs. time 3 200 ppm drift after 1000 hours at t a = 125c capacitive load 3 10 nf recommended operation load current 3 , 6 4 ma short - circuit c urrent 3 6.5 ma short circuit to com power supply sensitivity 3 2 12 v/v thermal hysteresis 3 285 ppm first temperature cycle 5 ppm second temperature cy cle load regulation 3 0.1 0.2 m v/ma measured at 0 ma and 1 ma loads output impedance 0.1 ? refout2 pin output voltage 1.18 1.227 1.28 v t a = 25c output impedance 72 k ? ad5421 data sheet rev. f | page 6 of 36 parameter 1 min typ max unit test conditions/comments reg out output voltage r egulator o ut put output voltage 1.8 12 v see table 10 output voltage tc 3 110 ppm/c output voltage accuracy ?4 2 + 4 % externally available current 3 , 6 3.15 ma assuming 4 ma flowing in the l oop and during hart communications short - circuit current 23 ma line regulation 3 500 v/v internal nmos 10 v/v external nmos load regulation 3 8 mv/ma inductive load 50 mh stable operation capacitive load 2 10 f recommended operation adc a ccuracy die temperature 5 c v loop input 1 % dv dd output can be over driven up to 5.5 v output voltage 3.17 3.3 3.48 v externally available current 3 , 6 3.15 ma assuming 4 ma flow ing in the loop and during hart communications short - circuit current 7 .7 ma load regulation 45 mv/ma measured at 0 ma and 3 ma loads digital inputs 3 sclk, sync , sdin, ldac input high voltage, v ih 0.7 iodv dd v input low voltage , v i l 0.25 iodv dd v hysteresis 0.21 v io dv dd = 1.8 v 0 .63 v io dv dd = 3.3 v 1.46 v io dv dd = 5.5 v input current ?0.015 + 0.015 a per pin pin capacitance 5 pf per pin digital outputs 3 sdo pin output low voltage, v ol 0.4 v output high voltage , v oh iodv dd ? 0.5 v high impedance leakage current ? 0.0 1 + 0.0 1 a hi gh impedance output capacitance 5 pf fau lt pin output low voltage, v ol 0.4 v output high voltage , v oh iodv dd ? 0.5 v fau lt t hresholds i loop under i loop ? 0.01% fsr ma i loop over i loop + 0.01% fsr ma t emp 140c 133 c fault removed when temperature 125c t emp 100c 9 0 c fault removed when temperature 85c v loop 6v 0.3 v fault removed when v loop 0.4 v v loop 12v 0.6 v fault removed when v loop 0.7 v data sheet ad5421 rev. f | page 7 of 36 parameter 1 min typ max unit test conditions/comments power require ments reg in 5.5 52 v with respect to lo op? iodv dd 1.71 5.5 v with respect to com quiescent current 260 300 a 1 temperature range: ?40c to +105c; typical at +25c. 2 total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperatu re) after factory calibration of the ad5421. system level total error can be reduced using the offset and gain registers. 3 guaranteed by design and characterization; not production tested. 4 the voltage between loop? and reg in must be 5.5 v or greater. 5 the ad5421 is factory calibrated with an external 2.5 v reference connecte d to refin. 6 this is the current that the output is capable of sourcing. the load current originates from the loop and, therefore, contrib utes to the total current consumption figure. ad5421 data sheet rev. f | page 8 of 36 loop v oltage = 24 v; refin = refout 1 (2.5 v internal reference ) ; r l = 250 ? ; external nmos connected; a ll loop current r anges; all specifications t min to t max , unless otherwise noted . table 2 . parameter 1 , 2 c grade unit test conditions/comments min typ max accuracy , internal r set total unadjusted error (tue) 3 ?0.1 57 + 0.1 57 % fsr ?0.117 0.0 172 + 0. 117 % fsr t a = 25c relative accuracy (inl) ?0.004 + 0.00 4 % fsr ?0.004 0.0015 + 0.00 4 % fsr t a = 25c offset error ?0.0 4 +0. 0 4 % fsr ?0.0 25 0.00 25 + 0.0 25 % fsr t a = 25c offset error tc 1 ppm fsr /c gain error ?0.1 28 + 0.1 28 % fsr ?0.093 0.0 137 +0.093 % fsr t a = 25c gain error tc 5 ppm fsr /c full - scale error ?0 .157 + 0 .157 % fsr ?0. 117 0.0 172 + 0. 117 % fsr t a = 25c full - scale error tc 6 ppm fsr /c accuracy, external r set (24 k?) assumes ideal resistor total unadjusted error (tue) 3 ?0.133 +0. 133 % fsr ?0.133 0.0 2 52 +0. 133 % fsr t a = 25c relative acc uracy (inl) ?0.004 + 0.00 4 % fsr ?0.004 0.0015 + 0.00 4 % fsr t a = 25c offset error ?0.029 +0.029 % fsr ?0.029 0.0038 +0.029 % fsr t a = 25c offset error tc 0.5 ppm fs r /c gain error ?0.11 +0. 11 % fsr ?0.106 0.0 197 +0. 106 % fsr t a = 25c gain error tc 2 ppm fsr /c full - scale error ?0. 133 +0. 133 % fsr ?0. 133 0.0 252 +0. 133 % fsr t a = 25c full - scale error tc 2 ppm fsr /c 1 temperature range: ?40c to +105c; typical at +25c. 2 specification s guaranteed by design and characterization; not production tested. 3 total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperatu re) after factory calibration of the ad5421. system level tot al error can be reduced using the offset and gain registers. data sheet ad5421 rev. f | page 9 of 36 ac performance chara cte ristics loop v oltage = 24 v; refin = 2.5 v external; r l = 250 ? ; all specifications t min to t max , unless otherwise noted . table 3 . parameter 1 min typ max unit test conditions/comments dynamic performance loop current settlin g time 50 s to 0.1% fsr, c in = open circuit loop current slew rate 400 a /s c in = open circuit ac loop voltage sensitivity 1 .3 a/v 1200 hz to 2200 hz , 5 v p - p, r l = 3 k? 1 temperature range: ?40c to +105c; typical at +25c. timing characteristi cs loop v oltage = 2 4 v ; refin = 2.5 v external; r l = 250 ? ; all specifications t min to t max . table 4 . parameter 1 , 2 , 3 limit at t min , t max unit description t 1 33 ns min sclk cycle t ime t 2 17 ns mi n sclk high t ime t 3 17 ns min sclk low t ime t 4 17 ns min sync falling edge to sclk falling edge setup time t 5 1 0 ns min sclk falling edge to sync rising edge t 6 25 s min minimum sync high time t 7 5 ns min data setup t ime t 8 5 ns min data hold t ime t 9 2 5 s min sync rising edge to ldac falling e dge t 1 0 1 0 ns min ldac pulse width l ow t 1 1 7 0 ns max sclk rising edge to sdo valid (c l sdo = 30 pf) t 1 2 0 ns min sync falling edge to sclk rising edge setup time t 1 3 70 ns max sync rising edge to sdo tri state ( c l sdo = 30 pf) 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.2 v. 3 see figure 2 and figure 3 . table 5 . spi watchdog timeout periods parameter 1 min typ max unit t0 t1 t2 0 0 0 43 50 59 ms 0 0 1 87 100 117 ms 0 1 0 436 500 582 ms 0 1 1 873 1000 1163 ms 1 0 0 1746 2000 2326 ms 1 0 1 2619 3000 3489 ms 1 1 0 3493 4000 4652 ms 1 1 1 4366 5000 5814 ms 1 specifications guaranteed by design and characterization; not production tested. ad5421 data sheet rev. f | page 10 of 36 timing diagrams d15 d14 d13 d2 d1 d0 d14 d13 d2 d1 d15 1 2 89 10 11 12 22 23 24 ldac sync sdin sdo t 12 sclk t 1 t 2 t 3 t 8 t 7 t 4 t 6 t 11 t 13 t 5 t 9 t 10 09128-002 d0 d16 d23 figure 2. serial interface timing diagram sync sdin sdo sclk d23 d15 d0 18 92 4 d15 d0 d23 d0 d15 1 89 24 d16 d16 input word specifies register to be read undefined data specified register data clocked out nop or register address 09128-003 figure 3. readback timing diagram data sheet ad5421 rev. f | page 11 of 36 absolute maximum rat ings t a = 25c , unless otherwise noted. transient currents of up to 100 ma do not cause scr latch - up. table 6 . parameter rating reg in to com ?0.3 v to +60 v reg out to com ?0.3 v to +14 v digital inputs to com , range0, range1, r int /r ext , alarm_ current_direction, reg_sel0, reg_sel1, reg_sel2 ?0.3 v to dv dd + 0.3 v or +7 v (whichever is less) digital inputs to com sclk, sdin , sync , ldac ?0.3 v to iodv dd + 0.3 v or +7 v (whichever is less) digital outputs to com , sdo, fault ?0.3 v to iodv dd + 0.3 v or +7 v (whichever is less) refin to com ?0.3 v to +7 v refout1, refout2 ?0.3 v to +4.7 v v loop to com ?0.3 v to +60 v loop? to com ?5 v to +0.3 v dv dd to com ?0.3 v to +7 v iodv dd to com ?0.3 v to +7 v r ext1 , c in to com ?0.3 v to +4.3 v r ext2 to com ?0.3 v to +0.3 v drive to com ?0.3 v to +11 v operating temperature range (t a ) industrial ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max ) 125c power dissipation ( t j max ? t a ) / ja lead temperature , soldering (10 sec) jedec industry standard j - std -020 esd human body model 3 kv field induced charged device model 2 kv machine model 200 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 7 . thermal resistance package type ja jc unit 28- lead tssop_ep (re -28- 2) 32 9 c/w 32- lead lfcsp_wq (cp -32-11) 40 7 c/w esd caution ad5421 data sheet rev. f | page 1 2 of 36 pin configuration and function description s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sdo sclk sync fault ldac sdin iodv dd reg in drive v loop r ext1 r ext2 loop? dv dd alarm_current_direction r int /r ext com com range1 range0 c in refout1 refout2 reg_sel1 reg_sel2 reg_sel0 refin reg out top view (not to scale) ad5421 notes 1. the exposed paddle should be connected to the same potential as the com pin and to a copper plane for optimum thermal performance. 09128-004 figure 4. tssop pin configuration 09128-100 pin 1 indicator 1 sdin 2 ldac 3 fault 4 com 5 dv dd 6 alarm current direction 7 r int /r ext 8 range 0 24 v loop 23 loop? 22 r ext2 21 r ext1 20 c in 19 refout1 18 refout2 17 refin 9 range 1 10 com 11 com 12 nc 13 reg_sel2 14 reg_sel1 15 reg_sel0 16 nc 32 sync 31 sclk 30 sdo 29 iodv dd 28 reg out 27 reg in 26 drive 25 nc ad5421 top view (not to scale) notes 1. no connect. do not connect to this pin. 2. the exposed paddle should be connected to the same potential as the com pin and to a copper plane for optimum thermal performance. figure 5. lfcsp pin configuration table 8 . pin fu nction description s pin no. mnemonic description tssop lfcsp 1 29 iodv dd digital interface supply pin. digital thresholds are referenced to the voltage applied to this pin. a voltage from 1.71 v to 5.5 v can be applied to this pin. 2 30 sdo serial dat a output. used to clock data from the input shift register. data is clocked out on the rising edge of sclk and is valid on the falling edge of sclk. 3 31 sclk serial clock input. data is clocked into the input shift register on the falling edge of sclk. t his input operates at clock speeds up to 30 mhz . 4 32 sync frame synchronization input , active low. this is the frame synchronization signal for the serial interface. wh en sync is low, data is transferred on t he falling edge of sclk. the i nput shift register data is latched on the rising edge of sync . 5 1 sdin serial data input. data must be valid on the falling edge of sclk. 6 2 ldac load dac input , active low. t his pin is used to update the dac register and , consequently, the output current. if ldac is tied permanently low, the dac register is updated on the rising edge of sync . if ldac is held high during the write cycle, the input register is updated, but the output update is delayed until the falling edge of ldac . the ldac pin should not be left unconnected. 7 3 fau lt fault alert output pin , activ e high . this pin is asserted high when a fault is detected. detectable faults are loss of spi interface control, communication error (pec), l oop current out of range, insufficient loop voltage , and over temperature. for more information, see the fault alerts section. 8 5 dv dd 3.3 v digital p ower s upply o utp ut. this pin should be decoupled to com with 100 nf and 4.7 f capacitor s . 9 6 alarm_ current _ direction alarm current direction select. this pin is used to select whether the a larm current is upscale (22.8 ma / 24 ma) or downscale (3.2 ma). connecting this pin to dv dd selects an upscale a larm current (22.8 ma/24 ma); connecting this pin to com selects a downscale a larm current (3.2 ma). f or more information, see the power - o n d efault section . 10 7 r int /r ext current s etting r esistor select . when this pin is connected to dv dd , the internal current setting resistor is selected. when this pin is connected to com , the external current setting resistor is select ed. an external resistor can be connected between the r ext1 and r ext2 pins. 11 , 12 8, 10 range 0 , range 1 digital input pins. these two pins select the loop current range (see the loop current range selection section). data sheet ad5421 rev. f | page 13 of 36 pin no. mnemonic description tssop lfcsp 13, 14 4, 11, 12 com ground r eference p in for the ad5421. it is recommended that a 4.7 v zener diode be placed between the loop? and com pins. see the applications information section for more information. 15 , 16, 17 13, 14, 15 reg_sel2, reg_sel1, reg_sel0 these three pins together select the regulator output (reg out ) voltage (see the voltage regulator section). 18 17 refin reference voltage input. v refin = 2.5 v for specified performance. 19 18 refout2 interna l reference voltage output ( 1.22 v ). it is recommended to connect a 100 nf capacitor from this pin to com . 20 19 refout1 internal reference voltage output (2.5 v). it is recommended to connect a 100 nf capacitor from this pin to com. 21 20 c in external c apacitor connection and hart fsk input. an external capacitor connected from c in to com implements an output slew rate control function (see the loop current slew rate control section) . hart fsk signaling can also be coupled thro ugh a capacitor to this pin (see the hart communications section ) . 22 , 23 21, 22 r ext1 , r ext2 connection for e xternal c urrent s etting r esistor. a precisi on 24 k? resistor can be connected between these pins for improved performance. 24 23 loop? loop current return pin . as shown in figure 1 , the com and loop ? pins can be used to sense the loop current across the internal 52 ? res istor. n ote that the voltage measured at loop ? will be negative with respect to com. 25 23 v loop voltage input pin. voltage input range is 0 v to 2.5 v. the voltage applied to this pin is digitized to eight bits, which are available in the fault register. this pin can be used for general - purpose voltage monitoring, but it is intended for monitoring of the loop supply voltage. connecting the loop voltage to this pin via a 20:1 resist or divider allows the ad5421 to monitor and feedback the loop voltage. the ad5421 also generate s an alert if the loop voltage is close to the minimum operating value ( see the loop voltage fault section ) . 26 26 drive gate connection for external depletion mode mosfet. for more information, see the connection to loop power supply section. 27 27 reg in voltage regulator input. the loop voltage can be connected directly to this pin. or, to reduce on - chip power dissipation, an external pass transistor can be connected at this pin to stand off the loop voltage. for more information, see the connection to loop power supply section. 28 28 reg out voltage regulator output . pin selectable values are from 1.8 v to 12 v via the reg_sel0, reg_sel1, and reg_sel2 pins (see the voltage regulator section). if regout is driving a microconverter supply (see figure 49) , t his pin should be decoupled to com with a >1 f capacitor. n/a 1 9, 16, 25 nc no connect. do not connec t to this pin. epad epad exposed pad the exposed paddle should be connected to the same potential as the com pin and to a copper plane for optimum thermal performance . 1 n/a means not applicable. ad5421 data sheet rev. f | page 14 of 36 typical performance characteristics 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 60k 50k 40k 30k 20k 10k inl error (lsb) dac code v loop = 24v ext nmos r load = 250? t a = 25c 4ma to 20ma range ext v ref ext r set 09128-005 figure 6 . integra l nonlinearity error vs. code 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 60k 50k 40k 30k 20k 10k dnl error (lsb) dac code v loop = 24v ext nmos r load = 250? t a = 25c 4ma to 20ma range ext v ref ext r set 09128-006 figure 7 . differential nonlinearity error vs. code 0.01 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0 60k 50k 40k 30k 20k 10k total unadjusted error (% fsr) dac code 09128-007 v ref ext, r set ext, nmos ext, 24v v ref ext, r set ext, nmos int, 24v v ref ext, r set ext, nmos int, 52v v ref int, r set int, nmos ext, 24v v ref int, r set int, nmos int, 24v v ref int, r set int, nmos int, 52v r load = 250? t a = 25c 4ma to 20ma range figure 8 . total unadjusted error vs. code 0.015 ?0.010 ?0.005 0 0.005 0.010 ?40 85 60 35 10 ?15 offset error (% fsr) temperature (c) ext v ref , int r set ext v ref , ext r set int v ref , int r set int v ref , ext r set v loop = 24v 4ma to 20ma range r load = 250? ext nmos 09128-008 figure 9 . offset error vs. temperature 0.03 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 ?40 85 60 35 10 ?15 gain error (% fsr) temperature (c) ext v ref , int r set ext v ref , ext r set int v ref , int r set int v ref , ext r set v loop = 24v 4ma to 20ma range r load = 250? ext nmos 09128-009 fig ure 10 . gain error vs. temperature 0.0012 ?0.0008 ?0.0006 ?0.0004 ?0.0002 0 0.0002 0.0004 0.0006 0.0008 0.0010 ?40 85 60 35 max inl min inl 10 ?15 inl error (% fsr) temperature (c) ext v ref , int r set ext v ref , ext r set int v ref , int r set int v ref , ext r set v loop = 24v 4ma to 20ma range r load = 250? 09128-010 figure 11 . integral nonlinearity error vs. temperature data sheet ad5421 rev. f | page 15 of 36 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?40 85 60 35 max dnl min dnl 10 ?15 dnl error (lsb) temperature (c) v loop = 24v 4ma to 20ma range r load = 250 ? 09128-011 figure 12. differential nonlinearity error vs. temperature 0.04 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 ?40 85 60 35 10 ?15 total unadjusted error (% fsr) temperature (c) ext v ref , int r set ext v ref , ext r set int v ref , int r set int v ref , ext r set v loop = 24v 4ma to 20ma range r load = 250 ? ext nmos 09128-012 figure 13. total unadjusted error vs. temperature ?40 85 60 35 10 ?15 full-scale error (% fsr) temperature (c) ext v ref , int r set ext v ref , ext r set int v ref , int r set int v ref , ext r set v loop = 24v 4ma to 20ma range r load = 250 ? ext nmos 09128-013 0.04 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 figure 14. full-scale error vs. temperature 0.0006 ?0.0006 ?0.0004 ?0.0002 0 0.0002 0.0004 060 50 40 max inl min inl 30 20 10 inl error (% fsr) loop supply voltage (v) r load = 250 ? t a = 25c 3.8ma to 21ma range ext v ref ext r set 09128-014 figure 15. integral nonlinearity error vs. loop supply voltage 0.0029 0.0027 0.0025 0.0023 0.0021 0.0019 0.0017 0.0015 060 50 40 30 20 10 total unadjusted error (% fsr) loop supply voltage (v) r load = 250 ? t a = 25c 3.8ma to 21ma range ext v ref ext r set 09128-015 figure 16. total unadjusted error vs. loop supply voltage 0.0024 0.0022 0.0020 0.0018 0.0016 0.0014 0.0012 0.0010 060 50 40 30 20 10 offset error (% fsr) loop supply voltage (v) r load = 250 ? t a = 25c 3.8ma to 21ma range ext v ref ext r set 09128-016 figure 17. offset error vs. loop supply voltage ad5421 data sheet rev. f | page 16 of 36 0.0015 ?0.0025 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0 60 50 40 30 20 10 gain error (% fsr) loop supply voltage (v) r load = 250? t a = 25c 3.8ma to 21ma range ext v ref ext r set 09128-017 figure 18 . gain error vs. loop supply voltage 0.0030 0.0025 0.0020 0.0015 0.0010 0.0005 0 ?0.0005 0 60 50 40 30 20 10 full-scale error (% fsr) loop supply voltage (v) r load = 250? t a = 25c 3.8ma to 21ma range ext v ref ext r set 09128-018 figure 19 . full - scale er ror vs. loop supply voltag e 2000 0 250 500 750 1000 1250 1500 1750 0 50 40 30 20 10 load resistance (?) loop supply voltage (v) t a = 25c ext v ref i loop = 24ma ext r set operating area 09128-019 figure 20 . load resistance load line vs. loop supply voltage (voltage betwe en loop? and reg in ) 4.70 4.35 4.40 4.45 4.50 4.55 4.60 4.65 ?40 100 80 60 40 20 0 ?20 compliance voltage headroom (v) temperature (c) r load = 250? 3.2ma to 24ma range ext v ref i loop = 24ma 09128-020 figure 21 . compliance voltage headroom vs. temperature 7 6 5 4 3 2 1 0 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 loop current error (a) reg out load current (ma) v loop = 24v ext nmos r load = 250? t a = 25c i loop = 20ma 09128-021 figure 22 . loop current error vs. reg out load current 8 ?8 ?6 ?4 ?2 0 2 4 6 0 10 9 8 7 6 5 4 3 2 1 voltage across 250 ? load resistor (v) time (seconds) v loop = 24v ext nmos ext v ref i loop = 4ma r load = 250? t a = 25c 09128-022 figure 23 . loop current noise, 0.1 hz to 10 hz bandwidth data sheet ad5421 rev. f | page 17 of 36 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.6 0.8 0.4 0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 voltage across 500 ? load resistor (mv) time (seconds) v loop = 24v ext nmos int v ref i loop = 4ma r load = 500? t a = 25c 1.33mv p-p 0.2mv rms 09128-023 figure 24 . loop current noise, 500 hz to 10 khz bandwidth (hart bandwidth) 6 5 4 3 2 1 0 ?40 ?30 ?20 ?10 0 10 20 30 40 voltage across 250 ? load resistor (v) time (s) falling rising v loop = 24v ext nmos r load = 250? t a = 25c c in = open circuit 09128-025 figure 25 . full - scale loop current step 6 5 4 3 2 1 0 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 voltage across 250 ? load resistor (v) time (ms) falling rising v loop = 24v ext nmos r load = 250? t a = 25c c in = 22nf 09128-026 figure 26 . full - scale loop current s tep, c in = 22 nf 0.244 0.226 0.228 0.230 0.232 0.234 0.236 0.238 0.240 0.242 0 0.5 1.0 1.5 2.0 iodv dd current (a) digital logic voltage (v) decreasing increasing iodv dd = 1.8v t a = 25c 09128-027 figure 27 . iodv dd current vs. digital logic voltage, increasing and decreasing , iodv dd = 1.8 v 0.60 0.55 0.50 0.45 0.40 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 iodv dd current (a) digital logic voltage (v) iodv dd = 3.3v t a = 25c decreasing increasing 09128-028 figure 28 . iodv dd current vs. digital logic voltage, increasing and decreasing, iodv dd = 3.3 v 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0 6 5 4 3 2 1 iodv dd current (a) digital logic voltage (v) iodv dd = 5v t a = 25c decreasing increasing 09128-029 figure 29 . iodv dd current vs. digital logic voltage, increasing and decreasing, iodv dd = 5 v ad5421 data sheet rev. f | page 18 of 36 1.85 1.84 1.83 1.82 1.81 1.80 1.79 1.78 1.77 1.76 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 12 0 0.25 0.20 0.15 0.10 0.05 10 8 6 4 2 reg out voltage (v) reg out voltage change (mv) reg out load current (ma) reg out load current (ma) v loop = 24v ext nmos t a = 25c 09128-030 figure 30 . reg out voltage vs. load current 263.5 258.5 259.0 259.5 260.0 260.5 261.0 261.5 262.0 262.5 263.0 0 60 50 40 30 20 10 quiescent current (a) loop supply voltage (v) t a = 25c 09128-031 figure 31 . quiescent cur rent vs. loop supply voltage 266 257 258 259 260 261 262 263 264 265 ?40 100 80 60 40 20 0 ?20 quiescent current (a) temperature (c) v loop = 24v ext nmos v ih = iodv dd v il = com t a = 25c 09128-032 figure 32 . quiescent current vs. temperature 3.5 0 0 ?50 ?100 ?150 ?200 ?250 0.5 1.0 1.5 2.0 2.5 3.0 0 1 2 3 4 5 dv dd output voltage (v) dv dd output voltage change (mv) dv dd load current (ma) 09128-101 v loop = 24v ext nmos t a = 25c figure 33 . dv dd output voltage vs. load current 4 ?4 ?3 ?2 ?1 0 1 2 3 0 10 8 5 4 9 7 6 3 2 1 refout1 voltage noise (v) time (seconds) v loop = 24v ext nmos t a = 25c 09128-034 figure 34 . refout1 voltage noise, 0.1 hz to 10 hz bandwidth 3.0 2.5 2.0 1.5 1.0 0.5 0 1 ?5 ?4 ?3 ?2 ?1 0 0 7 6 5 4 3 2 1 refout1 voltage (v) refout1 voltage change (mv) refout1 load current (ma) v loop = 24v ext nmos t a = 25c 09128-035 figure 35 . refout1 voltage vs. load current data sheet ad5421 rev. f | page 19 of 36 2.5012 2.4994 2.4996 2.4998 2.5000 2.5002 2.5004 2.5006 2.5008 2.5010 ?40 100 80 60 40 20 0 ?20 refout1 voltage (v) temperature (c) 60 devices shown 09128-036 figure 36 . refout1 voltage vs. temperature, 60 devices shown (c grade device) 30 0 5 10 15 20 25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 population (%) temperature coefficient (ppm/c) mean tc = 1.5ppm/c 09128-037 figure 37 . refout1 temperature coe fficient histogram (c grade device) 250 0 50 100 150 200 ?40 100 80 60 40 20 0 ?20 adc code (decimal) die temperature (c) v loop = 24v ext nmos r load = 250? i loop = 3.2ma 09128-038 figure 38 . on - chip adc code vs. die temperature 250 200 150 100 50 0 0 2.5 2.0 1.5 1.0 0.5 adc code (decimal) v loop pin input voltage (v) v loop = 24v ext nmos t a = 25c 09128-039 figure 39 . on - chip adc code vs. v loop pin input voltage ad5421 data sheet rev. f | page 20 of 36 terminology tot a l un a dju s te d e r ror total unadjusted error (tue) is a measure of the total output error. tue consists of inl error, offset error, gain error, and output drift over temperature, in the case of maximum tue. tue is expressed in % fsr. relative accuracy or integral nonlinearity (inl) error relative accuracy, or integral nonlinearity (inl) error, is a measure of the maximum deviation in the output current from a straight line passing through the endpoints of the transfer function. inl error is expressed in % fsr. differential nonlinearity (dnl) error differential nonlinearity (dnl) error is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. offset error offset error is a measure of the output error when zero code is loaded to the dac register and is expressed in % fsr. offset error temperature coefficient (tc) offset error tc is a measure of the change in offset error with changes in temperature and is expressed in ppm fsr/c. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer function from the ideal and is expressed in % fsr. gain error temperature coefficient (tc) gain error tc is a measure of the change in gain error with changes in temperature and is expressed in ppm fsr/c. full-scale error full-scale error is a measure of the output error when full-scale code is loaded to the dac register and is expressed in % fsr. full-scale error temperature coefficient (tc) full-scale error tc is a measure of the change in full-scale error with changes in temperature and is expressed in ppm fsr/c. loop compliance voltage headroom loop compliance voltage headroom is the minimum voltage between the loop? and reg in pins for which the output current is equal to the programmed value. output temperature coefficient (tc) output tc is a measure of the change in the output current at 12 ma with changes in temperature and is expressed in ppm fsr/c. voltage reference thermal hysteresis voltage reference thermal hysteresis is the difference in output voltage measured at +25c compared to the output voltage measured at +25c after cycling the temperature from +25c to ?40c to +105c and back to +25c. the hysteresis is specified for the first and second temperature cycles and is expressed in mv. voltage reference temperature coefficient (tc) voltage reference tc is a measure of the change in the reference output voltage with a change in temperature. the voltage refer- ence tc is calculated using the box method, which defines the tc as the maximum change in the reference output voltage over a given temperature range. voltage reference tc is expressed in ppm/c as follows: 6 10 ? ? ? ? ? ? ? ? ? ? ? ? temp_range v v v tc ref_nom ref_min ref_max where: v ref_max is the maximum reference output voltage measured over the total temperature range. v ref_min is the minimum reference output voltage measured over the total temperature range. v ref_nom is the nominal reference output voltage, 2.5 v. temp_r ang e is the specified temperature range (?40c to +105c). data sheet ad5421 rev. f | page 21 of 36 theory of o peration the ad5421 is an integrated device designed for use in loop - powered, 4 ma to 2 0 ma smart transmitter applications. in a single chip, t he ad542 1 provides a 16 - bit dac and current amplifier for digital control of the loop current, a voltage regulator to power the entire transmitter, a voltage reference, f ault alert functions, a f lexible spi - compatible serial interface, g ain and offset adjust regis ters , as well as other features and functions. t he features of the ad5421 are described in the following sections . fault alerts the ad5421 provides a number of fault alert features. all faults are signaled to the controller via the fault pin and the fault register. i n the case of a loss of communication between the ad5421 and the m icro controller (spi fault), the ad5421 program s the loop current to an alarm value. if the controller detects that the fault pin is set high, it should then read the fault regist er to determine the cause of the fault. spi fault the spi f ault is asserted if there is no valid communication to any register o f the ad5421 for more than a user - defined period. t he user can program the time period using the spi watchdog timeout bits of th e control register. the spi f ault bit of the fault register indicates the fault on the spi bus. because this fault is caused by a loss of communication between the controller and the ad5421, the loop current is also forced to the alarm value. the directio n of the alarm current (downscale or upscale) is selected via the alarm_current_direction pin. connecting this pin to dv dd selects an upscale alarm current (22.8 ma/24 ma); connecting this pin to com selects a downscale alarm current (3.2 ma). packet erro r check ing to verify that data has been received correctly in noisy environ - ments, the ad5421 offers the option of error checking based on an 8 - bit cyclic redundancy check (crc) . packet error checking (pec) is enabled by writing to the ad5421 with a 32 - bit serial frame , where the least significant eight bi ts are the frame check sequence (fcs) . the device controlling the ad5421 should generate the 8 - bit fcs using the following polynomial: c( x ) = x 8 + x 2 + x + 1 the 8 - bit fcs is appended to the end of the d ata - word , and 32 data bits are sent to the ad5421 before sync is taken high. if the check is valid , the data is accepted. if the check fails, the fault pin is asserted and the pec bit of the f ault register is set. after the f ault re gister is read , the pec bit is reset low and the fault pin return s low. in the case of data read back , if the ad5421 is addressed with a 32- bit frame, it generate s the 8 - bit frame check sequence and append s it to the end of the 24 - bit data stream to create a 32 - bit data stream. sdin sync sclk update on sync high msb d23 lsb d0 24-bit d at a 24-bit d at a transfer?no error checking sdin fault sync sclk update after sync high only if error check passed fault pin goes high if error check fails msb d31 lsb d8 d7 d0 24-bit d at a 8-bit fcs 32-bit d at a transfer with error checking 09128-049 figure 40 . pec timing current loop fault the current loop (i loop ) fault is a sse rted when the actual loop current is not within 0.01 % fsr of the programmed loop current. if the measured loop current is les s than the programmed loop current, the i loop under bit of the fault register is set. i f the measured loop current is greater than the programmed loop current, the i loop o ver bit of the fault register is set. the fault pin is se t to logic high in either ca se. an i loop over condition occurs when the value of the load current sourced from the ad5421 (via reg out , refout1, refout2 , or dv dd ) is greater than the loop current that is programmed to flow in the loop. an i loop u nder condition occurs when there is in sufficient compliance voltage to support the programmed loop current, caused by excessive load resistance or low loop supply voltage. overtemperature fault there are two overtemperature alert bits in the fault register : t emp 100c and t emp 140 c. if the di e temperature of the ad5421 exceeds either 100c or 140c , the appropriate bit is set . if the t emp 14 0c bit is set in the fault register , the fault pin is set to logic high. ad5421 data sheet rev. f | page 22 of 36 loop voltage fault there are two loop voltage alert bits in the fault register : v loop 12v and v loop 6 v . if the voltage between the v loop and com pins falls below 0.6 v (corresponding to a 12 v loop supply value), the v loop 12v bit is set; this bit is cleared when the voltage returns above 0.7 v. similarly, if the voltage between the v loop and com pins falls below 0.3 v (corresponding to a 6 v loop supply value), the v loop 6 v bit is set; this bit is cleared when t he voltage returns above 0.4 v. if the v loop 6 v bit is set in the fault register, the fault pin is set to logic high. figure 41 illustrates how a resistor divider enables the monitor - ing of the loop supply with the v loop input. the recommended resistor divider consists of a 1 m? and a 19 m ? resistor that provide a 20:1 ratio , allowing the 2.5 v input range of the v loop pin to monitor loop supplies up to 50 v . with a 20:1 divider ratio , the preset v loop 6 v and v loop 12v alert bits of the fault register generate loop supply fau lts according to their stated values. i f another divider ratio is used, the fault bits generate faults at values that are not equal to 6 v and 12 v. 19m? 1m? r l loop? v loop com reg in v loop ad5421 09128-048 figure 41 . resistor divider connection at v loop pin eternal current set ting res istor the 24 k? resistor r set , shown in figure 1 , converts the dac output voltage to a current , which is then mirrored with a gain of 221 to the loop? pin. the stability of the loop current over temperature is dependent on the temperature coef ficient of r set . table 1 and table 2 outline the performance specifications of the ad5421 with both the internal r set resistor and an external , 24 k ? r set resistor. using the internal r set resistor, a t otal unad - justed error of better than 0.126% fsr can be expected. u sing an external resistor gives improved performance of 0.048% fsr. this specific ation assumes an ideal resistor; the actual performance depend s on the absolute value and temperature coeffi cient of the resistor used . for more information, see the d etermining the e xpected t otal e rror section. loop current range s election to select the loop current range, connect the range0 and range 1 pins to the com and dv dd pi ns , as shown in table 9 . table 9 . selecting the loop current range range 1 pin range 0 pin loop current range com com 4 ma to 20 ma com dv dd 3.8 ma to 21 ma dv dd com 3.2 ma to 24 ma dv dd dv dd 3.8 ma to 2 1 ma connection to loop p ower supply the ad5421 is powered from the 4 ma to 20 ma current loop . t ypically , the power supply is located far from the transmitter device and has a value of 24 v. the ad5421 can be connected directly to the loop power supply and can tolerate a voltage up to a maximum of 52 v (see figure 42) . r l loop? drive com reg in v loop ad5421 09128-050 figure 42 . direct connection of the ad5421 to loop power supply figure 42 shows how the ad5421 is connected d irectly to the loop power supply. an alternative power connection is shown in figure 43 , which shows a depletion mode n - channel mosfet connected between the ad5421 and the loop power supply. the use of this device keeps the volta ge drop across the ad5421 at approx imately 1 2 v, limiting the worst - case on - chip power dissi - pation to 288 mw (1 2 v 24 ma = 288 mw). if the ad5421 is connected directly to the loop supply as shown in figure 42, the potential wor st - case on - chip power dissipation for a 24 v loop power supply is 576 mw (24 v 24 ma = 576 mw). the power dissipation change s in proportion to the loop power supply voltage. r l 200k? loop? drive com reg in v loop ad5421 t1 dn2540 bsp129 09128-051 figure 43 . mosfet connecting the ad5421 to loop power supply data sheet ad5421 rev. f | page 23 of 36 on - chip adc the ad5421 contains an on - chip adc used to measure and feed back to the fault register either the temperature of the die or the voltage between the v loop and com pins. the s elect adc i nput bit (bit d8 ) of the c ontrol r egister selects the parameter to be converted. a conversion is initiated with command byte 00001000 (necessary only if auto fault readback is disa bled). this command byte powers on the adc and performs the conversion. a read of the fault register re turn s the conversion r esult. if auto readback of the fault register is required , the adc mus t first be powered up by setting the on - chip adc bit (b it d7 ) of the c ontrol register. because the fault pin can go high for as long as 30 s, care is required when performing a die temp erature measurement after a readback of the v loop voltage. when switching from a v loop measurement to a die temperature measurement, the fault pin should not be read within 30 s of switching, as a false trigger may occur (fault reg ister contents are unaff ected). voltage regulator the on - chip voltage regulator provides a regulated voltage out - put to supply the ad5421 and the remainder of the transmitter circuitry. the output voltage range is from 1.8 v to 12 v and is selected by the states of three digital input pins (see table 10). the regulator output is accessed at the reg out pin. table 10 . setting the voltage regulator output reg_sel2 reg_sel1 reg_sel0 regulated output voltage (v) com com com 1.8 com c om dv dd 2.5 com dv dd com 3.0 com dv dd dv dd 3.3 dv dd com com 5.0 dv dd com dv dd 9.0 dv dd dv dd com 12.0 loop current slew ra te control the rate of change of the loop current can be controlled by connecting an external capacitor between the c in pin and com . t his reduce s the rate of change of the loop current. the output resistance of the dac (r dac ) together with the c slew capacitor generate a time constant that determines t he response of the loop current ( see figure 44) . loop? r dac v-to-i circuitry c in c slew 09128-052 fig ure 44 . slew capacitor circuit the resistance of the dac is typically 15.22 k? for the 4 ma to 20 ma and 3.8 ma to 21 ma loop current ranges . t he dac resistance changes to 16.11 k? when the 3.2 ma to 24 ma loop current range is s elected. the time constant of the circuit is expressed as ? = r dac c slew taking five time constants as the required time to reach the final value, c slew can be determined for a desired response time, t , as follows: dac slew r t c = 5 where: t is th e desired time for the output current to reach its final value . r dac is the resistance of the dac core , either 15.22 k? or 16.11 k?, depending on the selected loop current range. for a response time of 5 ms, nf 68 220 , 15 5 ms 5 = for a response time of 1 0 ms, nf 133 220 , 15 5 ms 10 = the responses for both of these configurations are shown in figure 45. 6 5 4 3 2 1 0 ?2 22 18 14 10 6 2 9 2 / 7 $ * ( $ & 5 2 6 6 ? / 2 $ ' 5 ( 6 , 6 7 2 5 9 time (ms) c slew = 267nf c slew = 133nf c slew = 68nf 09128-053 figure 45 . 4 ma to 20 ma step with slew rate control the c in pin can also be used as a coupling input for hart fsk signal ing. the hart signal must be ac - coupled to the c in input. the capacitor through which the hart signal is coupled must be considered in the preceding calculations , where the total capacitance is c slew + c hart . for more information, see the hart communications s ection. ad5421 data sheet rev. f | page 24 of 36 power - on d efault the ad5421 powers on with all registers loaded with their default values and with the loop current in the alarm state set to 3.2 ma or 22.8 ma/24 ma (depending on the state of th e alarm_ current_direction pin and the selected range). the ad5421 remains in this state until it is programmed with new value s . the spi watchdog timer is enabled by default with a timeout period of 1 sec. if there is no communication with the ad5421 withi n 1 sec of power - on, the fault pin is set. hart communications the ad5421 can be interfaced to a highway addressable remote transducer (hart) modem to ena ble hart digital communica tions over the 2 - wire loop connection . figure 46 shows how the modem frequency shift keying (fsk) output is connected to the ad5421. 09128-054 r l 200k? loop? drive com c in reg in v loo p ad5421 hart_out hart_in hart modem c hart c slew figure 46 . connecting a hart modem to the ad5421 to achieve a 1 ma p - p fsk current signal on the loop, the voltage at the c in pin must be 111 mv p - p. assuming a 500 mv p - p output from the hart modem, this means th at th e signal must be attenuated by a factor of 4.5. the following equation can be used to calculate the values of the c hart and c slew capacitors. hart slew hart c c c 5 . 4 from this equatio n , the ratio of c hart to c slew is 1 to 3.5. this ratio of the capacitor values set s the amplitude of the hart fsk signal on the loop . t he absolute values of the capacitors set the response time of the loop current, as well as the bandwidth presented to the hart signal connected at the c in pin. the bandwidth must pass frequencies from 500 hz to 10 khz . the two capacitors and the internal impedance, r dac , form a high - pass filter . t he 3 db f requenc y of this high - pass filter should be less than 500 hz and can b e calculated as follows: slew hart dac db c c r f u u s u 2 1 3 t o achieve a 500 hz high - pass 3 db frequency c ut off, the com - bined values of c hart and c slew should be 21 nf. t o ensure the correct hart signal amplitude on the current loop , t he final values for the capacit ors are c hart = 4.7 nf and c slew = 16.3 nf. output noise during silence and analog rate of change t he ad5421 ha s a direct influence on two important specifi - cations relating to the hart communications protocol : o utput n oise d uring s ilence and a nalog r ate o f c hange. figure 24 shows the measurement of the ad5421 output noise in the hart extended bandwidth ; t he noise measurement is 0.2 mv rms, within the required 2.2 mv rms value. to meet the a nalog r ate of c hange specification , the rate of change of the 4 ma to 20 ma current must be slow enough so that it does not interfere with the hart digital signaling. t his is determined by forcing a full - scale loop current change through a 500 ? load resistor and applying the resulting voltage s ignal to the hart digital filter (hcf_tool - 31). the peak amplitude of the signal at the filter output must be less than 150 mv. to achieve this, the rate of change of the loop current must be restricted to less than approximately 1.3 ma/ms. the output of the ad5421 naturally slew s at approximately 880 ma/ms, a rate that is far too great to comply with the hart specifications. to reduce the slew rate , a capacitor can be connected from the c in pin to com , as described in the loop cur rent slew rate control section. to reduce the slew rate enough so that the hart specification is met, a capacitor value in the region of 4.7 f is required, resulting in a full - scale transition time of 500 ms. many applications regard this time as too slo w, in which case the slew rate need s to be digitally controlled by writing a sequence of codes to the dac register so that the output response follows the desired curve. figure 47 shows a digitally controlled full - scale step and the resulting filter output . in figure 47, it can be seen that the peak amplitude of the filter output signal is less than the required 150 mv , and the transition time is approximately 30 ms. 12 10 8 6 4 2 0 150 ?150 ?100 ?50 0 50 100 ?50 ?30 ?10 10 30 50 voltage across 500? load resistor (v) output of hart digital filter (mv) hcf_tool-31 time (ms) 09128-060 figure 47 . digitally controlled full - scale step and resulting ha rt digital filter output signal data sheet ad5421 rev. f | page 25 of 36 figure 48 shows t he circu it diagram for this measurement. the 47 nf and 168 nf capacitor values for c hart and c slew provide adequate filtering o f the digital steps , ensuring that they do not cause interference. 09128-061 r l loop? com c in reg in v loop ad5421 from hart modem 47nf 168nf figure 48 . circuit diagram for figure 47 ad5421 data sheet rev. f | page 26 of 36 s erial i nterface the ad5421 is controlled by a versatile , 3 - wire serial interface that operat es at clock rates up to 3 0 mhz . it is compatible with the spi, qspi ? , microwire ? , and dsp standards. figure 2 shows the timing diagram. the interface operate s with either a continuous or non continuous gated burst clock. the write sequence begins with a falling edge of the sync signal ; data is clocked in on the sdin data line on the falling edge of sclk. on the rising edge of sync , the 24 bits of data are latched ; the data is transferred to the addressed register and the programmed function is executed ( either a change in dac output or mode of operation). if packet error checking on the spi interface is required using cyclic redundancy c odes, an additional eight bits must be written to t he ad5421 , creating a 32- bi t serial interface . in this case , 32 bits are written to the ad5421 before sync is brought high. input shift register the input shift register is 24 bits wide (32 bits wide if crc error checking of the data is required). data is loaded into the device msb first as a 24 - /32 - bit word under the control of a serial clock input, sclk. the input shift register consists of an 8 - bit address/ command byte, a 16 - bit data - word , and an optional 8 - bit crc , as shown in table 12 and table 13. the a ddress /command byte decoding is described in table 11. table 11 . address/command byte functions address/command byte function 00000001 write to dac r egister 00000010 write to c ontrol r egister address/command byte function 00000011 write to o ffset a djust r egister 00000100 write to g ain a djust register 00000101 load dac 00000110 force a larm c urrent 00000111 reset (i t is recommended to wait 50 s after a device reset before writing the next command) 00001000 initiate v loop / t emp erature m easurement 00001001 no o peration 10000001 read dac r egister 10000010 read c ontrol r egister 10000011 read o ffset a djust r egister 10000100 read g ain a djust r egister 10 000101 read f ault r egister the 16 bits of the data - word written following a l oad dac, f orce alarm current, r eset, i nitiate v loop /temp erature measurement , or n o operation command byte are dont cares (see table 12 and table 13) . re gister re adback to re a d back a register, b it d11 of the c ontrol register must be set to l ogic 1 to disable the automatic readback of the f ault register. the 16 bits of the data - word written following a read command are dont ca res (see table 12 and table 13) . the register data addressed by the read command is clocked out of sdo on the subsequent write command ( s ee figure 3 ). table 12 . input shift register msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address / command byte data - word table 13 . input shift register with crc msb lsb d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address / command byte data - word crc data sheet ad5421 rev. f | page 27 of 36 dac r egister the dac register is a read/write register and is add ressed as described in table 11 . the data programmed to the dac register determines the loop current , as shown in the ideal output transfer function section and in table 15. ide al output transfer function the transfer function describing the relationship between the data programmed to the dac register and the loop current is expressed by the following three equations. for the 4 ma to 20 ma output range, the loop current can be ex pressed as follows: ma 4 2 ma 16 16 d i loop + ? ? ? ? ? ? ? ? = for the 3.8 ma to 21 ma output range, the loop current can be expressed as follows: ma 8 . 3 2 ma 2 . 17 16 d i loop + ? ? ? ? ? ? ? ? = f or the 3.2 ma to 24 ma output range, the loop current can be expressed as follows : ma 2 . 3 2 ma 8 . 20 16 d i loop + ? ? ? ? ? ? ? ? = where d is the decimal value of the dac register. table 14 . dac register bit map msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16 - bit data table 15. relationship of dac r egister c ode to ideal loop current (gain = 65,536 ; offset = 0) dac register code ideal loop current (ma) 4 ma to 20 ma range 3.8 ma to 21 ma range 3.2 ma to 24 ma range 0x0000 4 3.8 3.2 0x0001 4.00024 3.80026 3.2003 0x7fff 11.9997 12.39974 13.5997 0x8000 12 12.4 13.6 0xfffe 19.9995 20.99947 23.9994 0xffff 19.9997 20.99974 23.9997 ad5421 data sheet rev. f | page 28 of 36 c ontrol r egister the c ontrol register is a read/write register and is addressed as described in table 11 . the data progra mmed to the c ontrol register determines the mode of operation of the ad5421. table 16 . control register bit map msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 spi watchdog timeout spi watchdog timer au to fault readback alarm on spi fault set min loop current select adc input on - chip adc power down internal reference v loop fault alert reserved t0 t1 t2 table 17 . control register bit descriptions control bit s descriptio n spi w atchdog t imeout the t0, t1, and t2 bits allow the user to program the watchdog timeout period. the watchdog timer is reset when a valid write to any ad5421 register occurs or when a nop command is written. t0 t1 t2 timeout period 0 0 0 50 ms 0 0 1 100 ms 0 1 0 500 ms 0 1 1 1 sec ( d efault) 1 0 0 2 sec 1 0 1 3 sec 1 1 0 4 sec 1 1 1 5 sec spi watchdog timer 0 = spi watchdog timer is enabled (default) . 1 = spi watchdog timer is disabled . auto f ault r eadback this bit specifies whether the fault register contents are automatically clocked out on the sdo pin on each write operation. (the fault register can always be addressed for readback.) 0 = f ault register contents are clocked out on the sdo pin (default) . 1 = f ault register contents are not clocked out on the sdo pin. alarm on spi f ault this bit specifies whether the loop current is forced to the a larm value when an spi fault is detected (that is, the watchdog timer times out). when an spi fault is detected, the spi fault bit of the f ault register and the fault pin are always set . 0 = loop current is forced to the a larm value when an spi fault is detected ( d efault) . 1 = loop current is not forced to the a larm value when an spi fault is detected . set m in l oop c urrent 0 = n ormal operat ion (default) . 1 = l oop current is set to its minimum value so that the total current flowing in the loop consists only of the operating current of the ad5421 and its associated circuitry . select adc i nput 0 = on - chip adc measures the voltage between the v loop and com pin s (default). 1 = on - chip adc measures the temperature of the ad5421 die. on - chip adc 0 = o n - chip adc is disabled (default) . 1 = o n - chip adc is enabled . power d own i nternal r eference 0 = i nternal voltage reference is powered up (default) . 1 = i nternal voltage reference is powered down and an external voltage reference source is required. v loop f ault a lert this bit specifies whether the fault pin is set when the voltage between the v loop and com pins falls to approximately 0.3 v. (t he v loo p 6v bit of the f ault register is always set.) 0 = fau lt pin is not set when the v loop ? com voltage falls to approx imately 0.3 v. 1 = fau lt pin is set when the v loop ? com voltage falls to approx imately 0.3 v. data sheet ad5421 rev. f | page 29 of 36 fault r egister the read - only fault registe r is addressed as described in table 11 . the bits in the fault register indicate a range of possible fault conditions. table 18 . fault register bit map msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d 7 d6 d5 d4 d3 d2 d1 d0 spi pec i loop over i loop under temp 140c temp 100c v loop 6v v loop 12v v loop /temperature value table 19 . fault register bit descriptions fault alert fau lt pin set description spi yes this bit is set high to indicate the loss of the spi interface signaling . this fault occurs if there is no valid communication to the ad5421 over the spi i nterface for more than the user - defined timeout period. the occurrence of this fault also force s the loop current to the a larm value if b it d10 of the c ontrol register is at logic 0. the alarm current direction is determined by the state of the alarm_current_direction pin. pec (packet error check) yes this bit is set high when an error in the spi communication is detected us ing cyclic redundancy check (crc) error detection. see the packet error checking section for more information. i loop over yes this bit is set high when the actual loop current is greater than the programmed loop current. i loop u nder yes this bit is set high when the actual loop current is less than the programmed loop current. temp 140c yes this bit is set high to indicate an over temperature fault. this bit is set if the die temperatu re of the ad5421 exceeds approx imately 140c . t his bit is cleared when the temperature returns below approx imately 125c . temp 100c no this bit is set high to indicate an increasing temperature of the ad5421. this bit is set if the die temperature of the ad5421 exceeds approx imately 100c . t his bi t is cleared when the temperature returns below approximately 85c . v loop 6v yes this bit is set high when the voltage between the v loop and com pins falls below approximately 0.3 v (representing a 6 v loop supply voltage with 20:1 resistor divider connected at v loop ). this bit is cleared when the voltage returns above approximately 0.4 v. v loop 12v no this bit is set high when the voltage between the v loop and com pins falls below approximately 0.6 v (r epresenting a 12 v loop supply voltage with 20:1 resistor divider connected at v loop ). t his bit is cleared when the voltage returns above approx imately 0.7 v . v loop / t emper - ature v alue n/a these eight bit s re present either the voltage between the v loop and com pins or the ad5421 die temperature , depending on the setting of bit d8 of the control register (see the on - chip adc transfer function equations section). 8 - b it v alue v loop ? com voltage (v) die temperature (c) 00000000 0 + 312 11111111 2.49 ? 86 on - chip adc transfer function equations the transfer function equation for the measurement of the voltage between the v loop and com pins is as follows : v loop ? com = (2.5/256) d where d is the 8 - bit digital code returned by the on - chip adc. the transfer function equation for the die temperature is as follows: die temperature = ( ? 1.559 d ) + 312 where d is the 8 - bit digital code returned by the on - chip adc . ad5421 data sheet rev. f | page 30 of 36 offset a djust r egister the o ffset adjust register is a read/write register and is addressed as described in table 11. table 20 . offset adjust register bit map msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16 - bit offset adjust data table 21 . offset adjust register a djustment r ange offset adjust register data digital offset adjustment (lsbs) 65535 + 32767 65534 + 32766 32769 + 1 32768 ( d efault) 0 32767 ? 1 1 ? 32767 0 ?32768 gain adjust register the gain adjust register is a read/write register and is addressed as described in table 11. table 22 . gain adjust register bit map msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16 - bit gain adjust data table 23 . gain adjust register a djustment r ange gain adjust register data digital gain adjustment a t full - scale output (lsbs) 65535 ( d efault) 0 65534 ?1 32769 ? 32767 32768 ?32768 32767 ?32769 1 ?6 5534 0 ?6 5535 data sheet ad5421 rev. f | page 31 of 36 transfer function equations with offset and gain adjust values when the o ffset adjust and g ain adjust register values are taken into accoun t, the transfer equations can be exp ressed as follows. for the 4 ma to 20 ma output range, the loop current can be expressed as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = d gain i loop 16 16 2 2 ma 16 ( ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + 768 , 32 2 ma 16 ma 4 16 offset for the 3.8 ma to 21 ma output range, the loop current can be expressed as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = d gain i loop 16 16 2 2 ma 2 . 17 ( ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + 768 , 32 2 ma 2 . 17 ma 8 . 3 16 offset for the 3.2 ma to 24 ma output range, the loop current can be expressed as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = d gain i loop 16 16 2 2 ma 8 . 20 ( ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + 768 , 32 2 ma 8 . 20 ma 2 . 3 16 offset where: d is the decimal value of the dac register. gain is the decimal value of the gain adjust r egister. offset is the decimal value of the offset adjust register. note that the offset adjust register cannot adjust the zero - scale output value downward. ad5421 data sheet rev. f | page 32 of 36 applications information figure 49 shows a typical connection diagram for the ad5421 configured in a hart capable smart transmitter. such a hart enabled smart transmitter was developed by analog devices as a reference demo circuit. this circuit, whose block diagram is shown in figure 50, was verified and registered as an approved hart solution by the hart communication foundation. to reduce power dissipation on the chip, a depletion mode mosfet (t1), such as a dn2540 or bsp129, can be connected between the loop voltage and the ad5421, as shown in figure 49. if a low loop voltage is used, t1 does not need to be inserted, and the loop voltage can connect directly to reg in (see figure 42). in figure 49, all interface signal lines are connected to the micro- controller. to reduce the number of interface signal lines, the ldac signal can be connected to com, and the sdo and fault lines can be left unconnected. however, this configuration disables the use of the fault alert features. under normal operating conditions, the voltage between com and loop? does not exceed 1.5 v, and the voltage at loop? is negative with respect to com. if it is possible that the voltage at loop? may be forced positive with respect to com, or if the voltage difference between loop? and com may be forced in excess of 5 v, a 4.7 v low leakage zener diode should be placed between com and the loop? pin, as shown in figure 49, to protect the ad5421 from potential damage. determining the expected total error the ad5421 can be set up in a number of different configu- rations, each of which achieves different levels of accuracy, as described in table 1 and table 2. with the internal voltage reference and internal r set enabled, a maximum total error of 0.157% of full-scale range can be expected for the c grade device over the temperature range of ?40c to +105c. other configurations specify an external voltage reference, an external r set resistor, or both an external voltage reference and external r set resistor. in these configurations, the specifications assume that the external voltage reference and external r set resistor are ideal. therefore, the errors associated with these components must be added to the data sheet specifications to determine the overall performance. the performance depends on the specifications of these components. 09128-055 hart_out adc_ip ref ad5700/ad5700-1 47nf 168nf 300pf v cc r l 200k ? loop? r ext1 r ext2 drive com refout1 refin reg_sel0 reg_sel1 reg_sel2 reg in iodv dd dv dd reg out v loop ad5421 19m ? 1m ? v loop aducm360 sync sclk sdin sdo r int /r ext alarm_current_direction range1 range0 fault ldac com txd rxd rts cd r1 r1 470 ? 1.2m ? 150k ? 1.2m ? 150pf optional resistor t1 optional mosfet dn2540 bsp129 0.1f sets regulator voltage c in 10f 0.1f 1f 0.1f v z = 4.7v 4.7f refout2 optional emc filter 1f dgnd agnd figure 49. ad5421 application diagram for hart capable smart transmitter data sheet ad5421 rev. f | page 33 of 36 09128-200 adc 0 pressure sensor simulation temperature sensor pt100 3.3v adc 1 adc dac aducm360 sram flash clock reset watchdog t1: cd t2: rts t3: com t4: test spi uart ad5700 ad5421 v cc hart_out ref adc_ip 3.3v 3.3v v dd c in c_hart c_slew hart input filter com v-regulator temperature sensor com reg in v loop loop? test connector + ? 50? hart modem micro- controller watchdog timer lexc dgnd agnd figure 50 . block diagram analog devices hart - enabled smart transmitter reference demo circuit ad5421 data sheet rev. f | page 34 of 36 to determine the absolute worst - case ov erall error , the reference and r set errors can be directly summed with the specified ad5421 maximum error. for example, when using an external reference and external r set resistor, the maximum ad5421 error is 0.048% of ful l- scale range . assuming th at the a bsolute errors for th e voltage reference and r set resistor are , respectively , 0.04% and 0.05% with t emperature c oefficients of 3 ppm/c and 2 ppm/c , respectively, the o verall worst - case error is as follows: worst - case error = ad5421 error + v ref absolute error + v ref tc + r set absolute error + r set tc worst - case error = 0.048% + 0.04% + [(3/10 6 ) 100 145]% + 0.05% + [(2/10 6 ) 100 145]% = 0.21% fsr this is the absolute worst - case value when the ad5421 operat es over the temperature range of ?4 0c t o + 105c . a n error of this value is very unlikely to occur because the temperature coeffi - cients of the individual components do not exhibit the same drift polarity , and , therefore, an element of cancel ation occur s. for this reason , the tc values should be added in a root of squares fashion. a further improvement ca n be gained by performing a two - point calibration at zero scale and full scale , thus reducing the absolute errors of the voltage reference and r set resistor to a combined error of 1 lsb or 0.001 5% fsr. after performing this calibration , the total maximum error becomes total error = fsr % 102 . 0 %) 029 . 0 ( %) 0435 . 0 ( % 0015 . 0 % 048 . 0 2 2 = + + + to reduce this error value further, a voltage reference and r set resistor with lower tc specifications must be chosen. thermal and s upply co nsi derations the ad5421 is designed to operate at a maximum junction temp - erature of 125c. to ensure reliable and specified operation over the lifetime of the product, i t is important that the device not be opera ted under conditions that cause the junction t emperature to exceed this value . excessive junction temperature can occur if the ad5421 experiences elevated voltages across its terminals while regulating the loop current at a high value. the resulting junction temperature depend s on the ambient tempera ture. table 24 provides the bounds of operation at maximum ambient temperature and maximum supply voltage. this information is displayed graphically in figure 51 and figure 52. these figures assume that the exposed paddle is connected to a copper plane of approx imately 6 cm 2 . 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 40 60 80 100 power dissipation (w) ambient temperature (c) 09128-103 tssop lfcsp figure 51 . maximum power dissipation vs. ambient temperature 60 50 40 30 20 10 0 40 50 60 70 80 90 100 supply voltage (v) ambient temperature (c) 09128-102 lfcsp tssop figure 52 . maximum supply voltage vs. amb ient temperature table 24 . thermal and supply considerations (external m osfet n ot co nnected) parameter description 32- lead lfcsp 28- lead tssop maximum power dissipation maximum permitted power dissipation when operating at an amb ient temperature of 105c mw 500 40 105 125 = ? = ? ja a max j t t mw 625 32 105 125 = ? = ? ja a j max t t maximum ambient temperature maximum permitted ambient temperature when operating from a supply of 52 v while regulating a loop current of 22.8 ma = ? ja d max j p t ( ) ( ) c 77 40 0228 . 0 52 125 = ? c 87 ) 32 ) 0228 . 0 52 (( 125 ) ( = ? = ? ja d max j p t maximum supply voltage maximum permitted supply voltage when operating at an ambient temperature of 105c while regulating a loop current of 22.8 ma v 21 40 0228 . 0 105 125 = ? = ? ja loop a max j i t t v 27 32 0228 . 0 105 125 = ? = ? ja loop a max j i t t data sheet ad5421 rev. f | page 35 of 36 outline dimensions compliant to jedec standards mo-220-whhd. 1 0.50 bsc 3.50 ref bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or 3.65 3.50 sq 3.45 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min 04-02-2012- a figure 53 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 11) dimensions shown in millimeters c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 5 3 - a e t 0 5 - 0 8 - 2 0 0 6 - a 2 8 1 5 1 4 1 e x p o s e d p a d ( p i n s u p ) 9 . 8 0 9 . 7 0 9 . 6 0 4 . 5 0 4 . 4 0 4 . 3 0 6 . 4 0 b s c 3 . 0 5 3 . 0 0 2 . 9 5 5 . 5 5 5 . 5 0 5 . 4 5 f o r p r o p e r c o n n e c t i o n o f t h e e x p o s e d p a d , r e f e r t o t h e p i n c o n f i g u r a t i o n a n d f u n c t i o n d e s c r i p t i o n s s e c t i o n o f t h i s d a t a s h e e t . p i n 1 i n d i c a t o r b o t t o m v i e w t o p v i e w 1 . 2 0 m a x s e a t i n g p l a n e 0 . 6 5 b s c 0 . 3 0 0 . 1 9 0 . 1 5 m a x 0 . 0 5 m i n c o p l a n a r i t y 0 . 1 0 1 . 0 5 1 . 0 0 0 . 8 0 0 . 2 0 0 . 0 9 0 . 2 5 8 0 0 . 7 5 0 . 6 0 0 . 4 5 figure 54 . 28 - lead thin shrink small outline package, exposed pad [tssop_ep] (re - 28 - 2) dimensions shown in millimeters ad5421 data sheet rev. f | page 36 of 36 ordering guide model 1 temperature range package description package option ad5421acpz - reel7 ?40c to +105c 32- lead lfcsp_wq cp -32-11 ad5421bcpz - reel7 ?40c to +105c 32- lead lfcsp_wq cp -32-11 ad5421brez ?40c to +105c 28- lead tssop_ep re -28- 2 ad5421brez - reel ?40c to +105c 28- lead tssop_ep re -28- 2 ad5421 b rez - reel7 ?40c to +105c 28- lead t ssop_ep re -28- 2 ad5421crez ?40c to +105c 28- lead tssop_ep re -28- 2 ad5421 c rez -rl ?40c to +105c 28- lead tssop_ep re -28- 2 ad5421 c rez - rl7 ?40c to +105c 28- lead tssop_ep re -28- 2 eval - ad5421s dz evaluation board 1 z = rohs compliant part. ? 2011 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09128 - 0- 1/13(e) |
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