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asahi kasei [ak5406] ms0592-e-01 2008/07 1 ak5406 80msps triple adc for displays general description the ak5406 is an rgb graphic & d-termin al signal process device in which integrates 10-bit 80mhz ad converters. the device has on-chip 3 channels adcs , voltage reference circuit, programmable gain offset amplifiers and black loop function which automatically sustains clamp level to an ar bitrarily set value. features ? adcs 80 msps max. (internally 10-bit, output is reduced to 8-bit) ? 0.5v ~ 1.0v input signal range ? black loop (automatic offset adjust) function ? low clock jitter ? on-chip sync separation function ? power down function ? low power dissipation ? 3.3v 0.3v power supply ? cmos ? -40 to 85 ? package 80-lqfp ? pedestal clamp and mid-point clamp function clamp pga 10bit adc sync processing control serial i/f vref flt sd a scl a 0 coast rin gin bin dtclk vsynco rout7~0 gout7~0 bout7~0 pvdd dvdd dvss a vdd a vss 10 8 8 8 reset hsync bypass hsynco the same as rch the same as rch vsync black loop sogout clamp bias sogin test test2 fig. 1 block diagram
asahi kasei [ak5406] ms0592-e-01 2008/07 2 functional block description table 1 : block description block function clamp to clamp pedestal level of input signal during clamp period. pga programmable gain amplifier. it has 8-bit resolution. full-scale input range of adc can be pre-set from 0.5v to 1v. adc 10-bit 80 msps ad converter. black loop a loop to settle pedest al level to the black set value. can be disable by register setting. vref to generate internal reference voltage. control serial i/f control register with i 2 c interface (400khz). to generate timing signals such as adc operating clock, from horizontal / vertical sync signal inputs. slicer comparator to slice sync signal part in sync-on-green signal. sync processing pll pll to generate pixel clock from horizontal sync signal coast gen to generate coast signal from vsync. clamp gen to generate clamp signal from hsync. clp coast to execute coast processing on clamp signal. sync sep to separate vsync from slicer output. fig. 2 sync processing slicer pll sogin hsync v sync coast hsynco sogout v synco coast hsync sel 1 0 1 0 dtcl k coast gen clamp gen to clp clamp sel 1 0 clamp sogout sel 1 0 clp coast v sync sel 1 0 hsync sel 1 0 sync separator coastgen 1 0
asahi kasei [ak5406] ms0592-e-01 2008/07 3 pin allocations 80 lqfp top view gout6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 gout5 gout4 gout3 gout2 gout1 gout0 nc nc dvss dvdd bout7 bout6 bout5 bout4 bout3 bout2 bout1 bout0 nc gout7 80 dvss 79 dvdd 78 nc 77 nc 76 rout0 75 rout1 74 rout2 73 rout3 72 rout4 71 rout5 70 rout6 69 rout7 :w 68 dtcl k 67 hsynco 66 sogout 65 vsynco 64 dvdd 63 dvss 62 resetn 61 a vss 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 a vdd bypass sda scl a 0 rin a vss a vdd a vdd a vss sogin gin a vss a vdd a vdd a vss bin a vdd a vss nc 21 dvss 22 dvdd 23 clamp 24 a vss 25 test2 26 pvdd 27 a vss 28 coast 29 hsync 30 v sync 31 a vss 32 flt 33 pvdd 34 pvdd 35 a vss 36 bias 37 test 38 a vdd 39 a vss 40
asahi kasei [ak5406] ms0592-e-01 2008/07 4 pin functions table 2 : pin functions pin name i/o functions output pins 64 hsynco do horizontal sync output. hsync output which is re-configured hsync input signal by internal timing. it is phase-synchronized with dtclk. when phase of dtclk is modified by clock phase adjust register setting, this output phase also changes in sync with it. 62 vsynco do vertical sync output. either vsync input or sync separator could be output. 63 sogout do sync-on-green slice comparator output. serial interface (i 2 c) pins 57 sda di/ do data i/o pins 56 scl di clock 55 ao di address 61 resetn di register initializatio n signal input ( active low ). data pins 68 ~ 75 80, 1 ~ 7 12 ~ 19 rout7 ~r out0 gout7 ~ gout0 bout7 ~ bout0 do red channel adc outputs green channel adc outputs blue channels adc outputs bit 7 is the msb. they are output in sync with dtclk. when dtclk phase is modify by clock adjust register setting, these output phases also change in sync with it. data clock pins 65 dtclk do strobe clock for data and hsynco. it is generated by pll and synchronized with internal adc sampling clock. its phase changes in accordance with clock phase adjust register setting. it is phase-synchronized with hsynco and data. input pins 54 48 43 rin gin bin ai red channel analog input. green channel analog input. blue channel analog input. 0.5v ~ 1.0v full scale input. each input signal is ac-coupled to each pin and clamp operation is executed. 30 hsync di horizontal sync input. reference clock input to ge nerate dtclk clock by the on-chip pll (it is also possible to input sync-on-green signal on sogin pin as reference clock). active polarity of input signal is selectable by register setting. leading edge is used for this and trailing edge is ignored. 31 vsync di vertical sync input. 49 sogin ai sync-on-green input. comparator input pin to extract sync signal from sync-on-green signal. comparator threshold level is adjustable by register setting (10 ~ 320mv / step). when this pin is not used, connect to avdd directly or connect to avss via a 1nf capacitor.
asahi kasei [ak5406] ms0592-e-01 2008/07 5 38 test di test pin. connect to avss. this pin has an on-chip pull-down resistor. 29 coast di clock control coast input. upon application of this coast input, pll stops to synchronize with horizontal sync signal and starts to self-run the oscillation. it is also possible to use internally generated timing from vsync, without using this pin. connect to avss when not used. 24 clamp di external clamp input. input pin to select timing in order to clamp video input to an internal, pre-set value. 26 test2 di test pin. connect to pvdd through mos sw internally. decoupling capacitor etc. connection pins 58 bypass ao bypass capacitor connect ion pin for reference voltage. connect a 0.1uf capacitor between this pin and avss. 37 bias ao bias current pin for internal analog circuit. connect a 6.8k ? 1% resistor between this pin and avss. 33 flt ao external filter connection pin for pll. this pin is internally fixed to pvdd at power-down mode. power supply pins 39 42 45 46 51 52 59 avdd pwr analog power supply pins. 11 23 67 78 dvdd pwr digital power supply pins. 27 34 35 pvdd pwr power supply pins for pll. 25 28 32 36 40 41 44 47 50 53 60 avss pwr analog ground pins. 10,22 66,79 dvss pwr digital ground pins. nc pins 8,9, 20,21 76,77 nc nc nc pins. left open. ai : analog input pin, ao : analog output pin di : digital input pin, do : digital output pin, pwr : power supply / ground pin di pins be free from hi-z input. do pins set to be hi-z output state by register setting.
asahi kasei [ak5406] ms0592-e-01 2008/07 6 absolute maximum ratings table 3 : absolute maximum ratings (avss, dv ss = 0v : all voltages are referenced to ground level) item symbol min max unit note power supplies analog digital pll avdd dvdd pvdd -0.3 -0.3 -0.3 4.5 4.5 4.5 v v v input current (excluding power supply pins) iin 10 ma analog input voltage vin avss-0.3 avdd+0.3 v rin, gin, bin, sogin digital input voltage vinl avss-0.3 avdd+0.3 v sda, scl, a0, resetn digital input voltage vinl2 avss-0.3 pvdd+0.3 v vsync, hsync, clamp, coast, test, test2 input voltage at hi-z condition (data output pin) vonl dvss-0.3 dvdd+0.3 v rout,gout,bo ut, hsynco, vsynco, sogout, dtclk storage temperature tstg -65 150 c (note) operation under a condition exceeding above limits may cause permanent damage to the device. normal operation is not guaranteed under the above, extreme conditions. recommended operating conditions at the power-up, the ak5406 device must be reset using resetn pin. table 4 : recommended operating conditions (avss, dvss = 0v : all voltages ar e referenced to ground level) item symbol min typ max unit note power supplies analog digital pll avdd dvdd pvdd 3.0 3.0 3.0 3.3 3.3 3.3 3.6 3.6 3.6 v v v operating temperature range ta -40 85 c
asahi kasei [ak5406] ms0592-e-01 2008/07 7 electrical characteristics 1) analog characteristics (avdd = dvdd = pvdd = 3.3v, ta = 25c, sampling frequency at 80 msps, input signal frequency = 1mhz, input signal amp litude = -2 dbfs unless otherwise noted ) table 5. item symbol conditions min typ max unit input range at maximum gain at minimum gain irng1 irng2 1.0 0.5 v v input full scale matching irngm at minimum gain 10 %fs static characteristics differential non-linearity integral non-linearity offset dnl inl vof (note 1) (note 1) 0.5 1.0 1.0 3.0 47 lsb lsb lsb dynamic characteristics s/n cross-talk snr ct input frequency = 7.5mhz 46 55 db dbc pll jitter tj (note 2) 300 ps rms power dissipation analog digital pll total at power-down ia id ip it ipd (note 3) (note 4) 180 24 15 219 1.5 290 2.6 ma ma ma ma ma (note 1) measured at gain = 80h (address : 08h, 09h, 0ah) (note 2) vco range = 2h, charged pump current = 3h (address : 05h), pll div : 2200(897h), fh=33.75khz, clk=74.25mhz (note 3) capacitive loadings cl = 15pf ( dtclk pin ) cl = 5pf ( rout, gout, bout, hsynco, vsynco pins ) (note 4) during power-down, sog slicer & slicer vref and i 2 c control circuits are active.
asahi kasei [ak5406] ms0592-e-01 2008/07 8 2) digital input / output dc characteristics table 6 : digital dc characteristics (avdd = dvdd = pvdd = 3.0 ~ 3.6v, avss = dvss= 0v, ta = -40 ~ 85c) item symbo l condition min ty p max unit high level input voltage vih a0, resetn pins 0.7avdd v low level input voltage vil a0, resetn pins 0.3avdd v high level input voltage vihp vsync, hsync, coast, clamp pins 0.7pvdd v low level input voltage vilp vsync, hsync, coast, clamp pins 0.3pvdd v input pin leakage current ilikg hsync,vsync,cl amp, coast pins 10 ua high level output voltage voh rout, gout, bout, hsynco, vsynco, sogout pins ioh=-1ma dvdd-0.5 v low level output voltage vol rout, gout, bout, hsynco, vsynco, sogout pins iol=1ma 0.5 v dtclk pin high level output voltage vohc dtclk pin ioh= -4ma dvdd-0.5 v dtclk pin low level output voltage volc dtclk pin iol= 4ma 0.5 v hi-z leakage current ioz rout, gout, bout hsynco, vsynco, sogout, dtclk pins at hi-z output 10 ua i 2 c high level input voltage vih2 sda, scl pins 0.7avdd v i 2 c low level input voltage vil2 sda, scl pins 0.3avdd v i 2 c low level output voltage vol2 sda pin, iol=3ma 0.4 v
asahi kasei [ak5406] ms0592-e-01 2008/07 9 3) switching characteristics table 7 : switching characteristics (avdd = dvdd = pvdd = 3.0 ~ 3.6v, avss = dvss = 0v, ta = -40 ~ 85c, cl of dtclk pin = 15pf, cl of rout, gout, bout, hsynco pins = 5pf) item symbol condition min typ max unit conversion speed maximum minimum fsmax fsmin 80 9 msps msps dtclk duty 42 50 58 % data skew tskw referenced to the falling edge of dtclk output (note 1) -1.0 4.0 ns hsync input frequency 15 110 khz reset timing trst after the power-up 1 us (note 1) 1/2 of vdd referenced dtcl k rout7 0, gout7 0, bout7 0, hsynco tskw pwr resetn trst fig. 4 output timing fig. 5 reset timing
asahi kasei [ak5406] ms0592-e-01 2008/07 10 4) serial i/f switching characteristics table 8 : serial i/f switching characteristics (avdd = dvdd = pvdd = 3.0 ~ 3.6v, avss = dvss = 0v, ta = -40 ~ 85c) item symbol condition min typ max unit bus free time t buf 1.3 us hold time (start condition) t hd:sta 0.6 us clock pulse low time t low 1.3 us input signal rise time t r 300 ns input signal fall time t f 300 ns setup time (start condition) t su:sta 0.6 us setup time (stop condition) t su:sto 0.6 us the above i 2 c bus related timings are i 2 c bus specifications, and they are not the device limits. for details, refer to i 2 c bus specifications. sda t f t buf t hd:st a scl t r t low t su:st a t f t r t su:sto fig. 6 serial control timing
asahi kasei [ak5406] ms0592-e-01 2008/07 11 table 9. (avdd = dvdd = pvdd = 3.0 ~ 3.6v, avss = dvss = 0v, ta = -40 ~ 85c) item symbol condition min typ max unit data setup time t su:dat 100 (note 1) ns data hold time t hd:dat 0.0 0.9 (note 2) us clock pulse high time t high 0.6 us (note 1) when to use in i 2 c bus standard mode, t su:dat 250ns must be satisfied. (note 2) when the ak5406 is used on non-extended t low bus (used at t low = minimum specification), this condition must be satisfied. sda t hd:dat scl t high t su:dat fig. 7 serial control timing (#2)
asahi kasei [ak5406] ms0592-e-01 2008/07 12 functional description adc 10-bit 80 msps a/d converter, ou tput is reduced to 8-bit. reset operation reset operation must be executed after the power-up. reset pulse can be fed in asynchronous fashio n, with a pulse width of longer than 1 us. right after the reset operation, re gisters are set to their default. pll function the pixel clock is re-produced by pll based on hsync to be input. the ak5406 is corresponds from 9mhz to 80m hz of frequency by adjusting charged pump current as pll parameter. the example of charged pump current calculat ion is shown below, and the closest value is setting to register (address 0x03 bit 5:3). ak5406 pll cpcurrent (cpi) calculation : cpi = ((2pi*fh)/nfratio)^2*c*n*p / kvco; fh : pll reference signal (horizontal sync signalin [hz] ) nfratio : set to each natural frequency reference signal is divided and set to 13. c: 0.082uf n: pll divide ratio (register address 0x01, 0x02) p: 4:<9-32mhz>, 2:<32-64mhz>, 1: <64-80mhz> clock frequency range. kvco: 130mhz pll coast funtion the pixel clock is re-produced by pll based on hsync to be input. coast mode is to cease its pll tracking operation and to let vco self-run. there are 2 modes in coast function ? one is hsync pulse duration coast where the duration time is selected from pre-vsync timing as start point and post-vsync timing as stop point, and the other is to input directly on coast pin a signal to notify its timing. ( refer to timing diagram 3 ) coast timing ) clamp function this is a function to adjust reference level of ac-coupled input signal to match with the ak5406 internal reference level. it is required to specify a specific period where reference level of input signal is being input. it is selectable to specify the period by external clamp pin or by register setting. if the clamp period is specified by register, the position and the period from the trailin g edge of hsync are set to the register. ( refer to timing diagram 4 ) clamp timing #1) during the clamp period the analog clamp circuit (clamp block) and the black loop circuit (black loop block) are operational at the same timing at the default setting. it is possible to set the analog clamp at the first half of clamp period and black loop at the other half during the clamp period by regi ster setting. ((refer to timing diagram 5) clamp timing #2) clamp function can be coaste d as in the case of pll (( refer to timing diagram 6) clamp coast). it is also possible by register setting to clamp the minimum value in accordance with rgb signals or to clamp the center value in accordance with yuv signals (refer to register address 10h). gain adjust function adc full-scale input range is adjustable within 0.5v ~ 1v by pga (programmable gain amplifier). pga has an 8-bit resolution. sync separation function
asahi kasei [ak5406] ms0592-e-01 2008/07 13 vsync is extracted from the internal slicer output. black loop function, offset adjust function with a help of black loop operation during the clamp period, offset of internal circuit can be eliminated and clamp level is retained to the set value. black level is arbitrarily pre-settable for each of 3 channels independently, in the range from ?4 to +20 by black loop setting value setting register. in addition to enabling black loop function always during the clamp period, it is also possible to control black loop function to op erate or to hold the condition by register setting. black loop function can be completely disabled. only in this case, each of channel offset ad just registers is valid and external offset adjustment is enabled. gain offset control diagram below shows its relation. 1.0 0.5 0.0 00h ffh gain input volta g e (v) offset = 1ffh offset = 1ffh offset = 0ffh offset = 0ffh offset = 000h offset = 000h fig. 8 gain offset control
asahi kasei [ak5406] ms0592-e-01 2008/07 14 control serial i/f this is a control register with i 2 c serial interface. an external pull-up resistor should be connected on sda pin. data on sda line is captured at the rising edge of scl. make certain that data on sda line changes state only during scl at low condition. when sda changes state while scl is at high co ndition, it is interp reted to be a start condition if the change occurs at the falling tr ansition, and it is to be a stop condition if it occurs at the rising transition.
asahi kasei [ak5406] ms0592-e-01 2008/07 15 [i 2 c slave address] i 2 c slave address is selectable to be either 1001100 or 1001101 by ao pin setting. table 10 : i 2 c address a0 pin i 2 c slave address lo 1001100 hi 1001101 [i 2 c write sequence] when the slave address of the ak5406 write mode is received at the first byte, sub-address at the second byte and da ta at the third & succeeding bytes are received. there are 2 operations in write sequence ? (a) single byte write sequence 1b s 8b data w sub address a a stp a 1b 8b 1b 8b slave address (b) multiple byte (m bytes) write sequence ( sequential write operation ) 1b s 8b data(n) slave address w sub address(n) a a stp a 1b 8b 1b 8b data(n+1) a 1b 8b data(n+m ) a 1b 8b (c) read sequence when the slave address of the ak5406 read mode is received at the first byte, data at the second & succeeding bytes transmitted from the ak5406. 1b s 8b data1 slave address w sub address(n) a a stp a 1b 8b 1b 8b data2 a 1b 8b data n a 1b 8b rs 1b 8b slave address r a abbreviation terms listed above mean : s,rs start condition a 0:acknowledge (sda low) a 1:not acknowledge (sda high) stp stop condition r/w 1:read, 0:write to be controlled by the master devi ce. to be output by micro-computer normally. to be controlled by the slave de vice. to be output by the ak5406. fig. 9a single byte write sequence fig. 9b sequential write fig. 9c read sequence
asahi kasei [ak5406] ms0592-e-01 2008/07 16 timing charts 1) output timing dtcl k d0 r(g,b)out hsync (adclk) px0 px1 px2 d1 d2 hsynco r(gb)in pipe-line delay (12 clocks ) register set value (hsynco width) -1 2 clocks leading edge d3 2) 4 : 2 : 2 output mode timing dtcl k y0 gout hsync (adclk) px0 px1 px2 y1 y2 hsynco r(gb)in pipe-line register ( 12 clocks ) register set value ( hsynco width ) -1 2 clocks u0 rout v1 u2 u/v alternative output leading edge fig. 10 output timing reference register address 07h : (hsynco width) 0eh : hsync pol, hsynco pol reference register address 15h : output format fig. 11 4 : 2 : 2 output mode timing
asahi kasei [ak5406] ms0592-e-01 2008/07 17 3) coast timing when coast pin is not used coast (internal) vsync hsync (csync) register (pre-cost) set value (m) register (post-coast) set value (n) 1 2 3 mm-1 m-2 1 2 3 n n-1 n-2 8 pixels clock period 8 pixels clock period coast period (note) since pre-coast time is counted, based on # of lines in the previous field, there is a case in the interlaced signal mode that coast period may slightly differ between odd field case and even field case. *525i mode coast example coast (internal) vsync hsync (csync) 264 263 262 259 1 2 3 4 525 524 1 2 3 4 5 6 7 8 9 10 11 12 5 6 7 8 261 260 258 257 coast (internal) vsync hsync (csync) 265 264 261 2 3 4 5 263 262 264 265 266 267 268 269 270 271 272 273 274 261 6 7 8 263 262 259 258 260 1 265 264 line # retained (internal) line no. line no. [field 1] [field 2] 264 265 line # retained (internal) 265-6=259 264-6=258 in case of register pre-coast = 6, register post-coast = 5 equivalent pulse period vertical sync period equivalent pulse period fig. 13 coast timing fig. 14 coast timing ( 525i mode coast example ) reference register address 0fh : coast sel, coast pol 12h : pre coast 13h : post coast
asahi kasei [ak5406] ms0592-e-01 2008/07 18 when coast pin is used input signal fed on coast pin is used as is, as internal coast signal. coast hsync leading edge to be coasted normal leading edge without coast 4) clamp timing 1 when clamp pin is not used clamp (internal) hsync adclk (internal) register (clp place) set value (m) register (clp duration) set value (n) trailing edge when clamp pin is used externally feds clamp timing pulse from clamp pin. clamp timing pulse be sampled by adclk then used internally. i nternal clamp clamp adclk (internal) fig. 15 coast timing ( when coast pin is used ) fig. 17 clamp timing fig. 16 clamp timing reference register address 0fh : clamp sel, clamp pol 05h : clp place 06h : clp duration
asahi kasei [ak5406] ms0592-e-01 2008/07 19 5) clamp timing 2 when register (loop disable) is set to value (m) other than 0, the clamp period is divided into 2 half where it is possible that the clamp circuit operational at first half of the period (m pixels clock) an d black loop at the other half. when m = 0 (reset value), the clamp circuit and the black loop are operate at the same timing. clamp (internal) adcl k (internal) clamp circuit operation register (loop disable) set value block loop operation 1 2 m m-1 m-2 6) coast timing for clamp register post-clpcoast set value(n) coast (internal) vsync hsync (csync) register pre-clpcoast set value(m) 1 2 3 m m-1 1 2 3 n clamp coast period (note) since pre clpcoast time is counted, based on # of lines in the previous field, there is a case in the interlaced signal mode that coast period may slightly differ between odd field and even field case. for details, refer to (3) coast timing section. fig. 19 clamp coast timing reference register address 26h : pre clpcoast 27h : post clpcoast fig. 18 clamp timing (#2)
asahi kasei [ak5406] ms0592-e-01 2008/07 20 control register table 11 : register map sub adrs r/w or ro bits default value register name function 00h ro 7:0 10101110 chipid device id number 01h r/w 7:0 01101001 pll div msb upper 8-bit pll divider ratio[11:4] 02h r/w 7:4 1101**** pll div lsb lower 4-bit pll divider ratio[3:0] 03h r/w 7:6 5:3 01****** **001*** pll vco pll cp bit [7:6] pll vco range bit [5:3] pll charged pump current 04h r/w 7:3 10000*** phadj clock phase adjust (1lsb = t/32) 05h r/w 7:0 10000000 clp place clamp position 06h r/w 7:0 10000000 clp duration clamp period 07h r/w 7:0 00100000 hsynco width hsynco pulse width 08h r/w 7:0 10000000 red gain red channel gain adjust 09h r/w 7:0 10000000 green gain green channel gain adjust 0ah r/w 7:0 10000000 blue gain blue channel gain adjust 0b-0dh ro 7:0 00000000 reserved 0eh r/w 6 5 3 2 0 *1****** **0***** ****0*** *****0** *******0 hsync pol hsynco pol hsync sel vsync pol vsync sel bit 6 : hsync input polarity setting ( 0 : low 1 : hi ) bit 5 : hsynco output polarity setting ( 0 : hi 1 : low ) bit 3 : hsync select ( 0 : hsync 1: sync-on-green ) bit 2 : vsynco inversion ( 0 : inv 1 : no inv ) bit 0 : vsync select ( 0 at power-down(pdn=0) ) (0 : vsync 1 : sync separator signal ) 0fh r/w 7 6 5 3 1 0******* *1****** **0***** ****1*** ******1* clamp sel clamp pol coast sel coast pol pdn bit 7: clamp signal select ( 0:hsync 1:clamp pin ) bit 6: clamp polarity ( 0 : hi 1 : low ) bit 5: coast select ( 0 : coast pin 1 : vsync ) bit 3: coast polarity setting ( 0 : low 1 : hi ) bit 1: power-down ( 0 : power-down 1 : normal operation ) 10h r/w 7:3 2 1 0 10111*** *****0** ******0* *******0 sogth red clp lvl green clp lvl blue clp lvl sync-on- green threshold level setting bit 2: red channel clamp level setting ( 0 : minimum value 1 : mid value ) bit 1: green channel clamp level setting ( 0 : minimum value 1 : mid value ) bit 0: blue channel clamp level setting ( 0 : minimum value 1 : mid value )
asahi kasei [ak5406] ms0592-e-01 2008/07 21 sub adrs r/w or ro bits default value register name function 11h r/w 7:0 00100000 ssepth sync separator threshold level setting 12h r/w 7:0 00000000 pre coast pre-coast 13h r/w 7:0 00000000 post coast post-coast 14h ro 7:0 00000000 reserve reserved 15h r/w 1 ******1* output format bit1 : output format (0: 4:2:2, 1:4:4:4) 16h r/w 7:0 ******** don?t care 17h r/w 0 *******1 red offset (msb) red channel offset adjust (msb) 18h r/w 7:0 00000000 red offset (lsb) red channel offset adjust (lsb) 19h r/w 0 *******1 green offset (msb) green channel offset adjust (msb) 1ah r/w 7:0 00000000 green offset (lsb) green channel offset adjust (lsb) 1bh r/w 0 *******1 blue offset (msb) blue channel offset adjust (msb) 1ch r/w 7:0 00000000 blue offset (lsb) blue channel offset adjust (lsb)
asahi kasei [ak5406] ms0592-e-01 2008/07 22 table 12 : black loop registers sub adrs r/w or ro bits default value register name function 1dh r/w 0 *******0 red blk lvl (msb) red channel black loop setting value (msb) 1eh r/w 7:0 00000000 red blk lvl (lsb) red channel black loop setting value (lsb) 1fh r/w 0 *******0 green blk lvl (msb) green channel black loop setting value (msb) 20h r/w 7:0 00000000 green blk lvl (lsb) green channel black loop setting value (lsb) 21h r/w 0 *******0 blue blk lvl (msb) blue channel black loop setting value (msb) 22h r/w 7:0 00000000 blue blk lvl (lsb) blue channel black loop setting value (lsb) 23h r/w 7:5 4:3 2 1 0 000***** ***00*** *****0** ******0* *******0 lbw loopoffrng loopmode loophold vsync update black loop bandwidth black loop coring bandwidth control black loop mode (0 : loop enable 1 : loop disable) retention of black loop condition (0 : active 1 : condition retained) limit black level update frequency to every 64 vsync 24h r/w 6 5 4:3 2 1 0 *0****** **0***** ***11*** *****0** ******0* *******0 coastgen sel clpbw fixed bit sogout pol sogout sel dofix coastgen input setting (0: vsync 1 : sync sep ) clamp bandwidth setting used in fixed condition. write ?11? when to write. sogout polarity ( 0 : normal 1 : inverted ) sogout signal select ( 0 : sog 1 : hsync ) output level at power-down mode ( 0 : fixed low 1 : fixed high ) 25h r/w 7:0 00000000 loop disable black loop off period during clamp period 26h r/w 7:0 00000000 pre clpcoast pre-coast for clamp signal 27h r/w 7:0 00000000 post clpcoast post-coast for clamp signal 28h r/w 7:6 5:4 11****** **11**** data drive clock drive rout,gout,bout,hsynco,vsynco, sogout pin drivability dtclk pin drivability 29h r/w 7:6 5:3 2:1 0 10****** **101*** *****00* *******0 reserved in range reserved reserved reserved accelerate range control of black loop setting reserved reserved do not write value other than ?0? 2ah r/w 6:0 *0111001 reserved reserved 2bh r/w 3:0 ******00 reserved 2ch ro 7:0 00000000 reserved
asahi kasei [ak5406] ms0592-e-01 2008/07 23 test register ak5406 has test register address 0x20 ~ 0x30, which could be accessed in normal mode. do not write without default. 2dh r/w 7:0 00000000 test default value : 0x00 2eh r/w 7:0 00000000 test default value : 0x00 2fh r/w 7:0 00100000 test default value : 0x20 30h r/w 7:0 00000000 test default value : 0x00 default value of ak5406 adr r/w default adr r/w default 00h ro aeh 20h r/w 00h 01h r/w 69h 21h r/w 00h 02h r/w d0h 22h r/w 00h 03h r/w 48h 23h r/w 00h 04h r/w 80h 24h r/w 18h 05h r/w 80h 25h r/w 00h 06h r/w 80h 26h r/w 00h 07h r/w 20h 27h r/w 00h 08h r/w 80h 28h r/w f0h 09h r/w 80h 29h r/w a8h 0ah r/w 80h 2ah r/w 39h 0bh ro 00h 2bh r/w 00h 0ch ro 00h 2ch ro 00h 0dh ro 00h 0eh r/w 40h 0fh r/w 4ah 10h r/w b8h 11h r/w 20h 12h r/w 00h 13h r/w 00h 14h ro 00h 15h r/w 02h 16h r/w 00h 17h r/w 01h 18h r/w 00h 19h r/w 01h 1ah r/w 00h 1bh r/w 01h 1ch r/w 00h 1dh r/w 00h 1eh r/w 00h 1fh r/w 00h
asahi kasei [ak5406] ms0592-e-01 2008/07 24 description of register contents default value is meshed sub address 00h chip id when it is read, device id number (adh) is returned. sub address 01h ~ 02h pll div default : 69dh 01h [7:0] 02h [7:4] decimal notation of 01h [7:0]&02h [7:4] pll multiplier ratio 00h 0h 0 00h 1h 1 : : : 0dh dh 221 inhibited 0dh eh 222 223 0dh fh 223 224 0eh 0h 224 225 : : : : ffh fh 4095 4096 ?set-value plus one? becomes multiplier ratio of pll. write operation of msb side bits ( sub addr ess 01h ) does not initiate pll operation, and after lsb side data ( sub address 02h ) is written, a multiplier ratio becomes valid and pll operation is executed. sub address 03h [7:6] pll vco [7:6] pll vco operating range 00 9~32mhz 01 32~64mhz 10 64~80mhz 11 inhibited [5:3] pll cp [5:3] pll charge pump current 000 50ua 001 100ua 010 150ua 011 250ua 100 350ua 101 500ua 110 750ua 111 inhibited
asahi kasei [ak5406] ms0592-e-01 2008/07 25 sub address 04h phadj [7:3] adc sampling clock phase 00h -180 01h -168.75 : : 0eh -22.5 0fh -11.25 advances 10h standard 11h +11.25 12h +22.5 : : 1eh +157.5 1fh +168.75 delayed each single step is equal to 11.25 degrees. a larger number reflects direction of a bigger delay. sub address 05h clp place default : 80h sub address 06h clp duration default : 80h clamp timing can be internally genera ted when clamp sel is set to ?0?. the periods of clamping is start from tra iling edge of hsync after the delayed of clp place pixels and its continue according to the setting of clp duration pixels value. (refer to timing chart 4) do not set clp duration to ?0? when clp place is set to ?0?,?1?,?2? value. sub address 07h hsynco width default : 20h this is to set the pulse width of horizontal sync signal which is re-configured by pll and is output on hsynco pin ( refer to timing charts 1 & 2 ). do not write this register value to ?0?. sub address 08h ~ 0ah red (green,blue) gain [7:0] input range [vpp] gain 00h 0.377 01h 0.380 02h 0.383 : : 7fh 0.751 80h 0.754 81h 0.757 : : fdh 1.123 feh 1.126 ffh 1.129 high gain low gain (note) pga gain is shown by 543/(128 + n) where (n = 0 ~ 255(dec)). pga gain is set until adc input range becomes 1.6vpp.
asahi kasei [ak5406] ms0592-e-01 2008/07 26 sub address 0eh [6] hsync pol [6] hsync input pin polarity 0 active low ( leading edge to fall ) 1 active high ( leading edge to rise ) [5] hsynco pol [5] hsynco output pin polarity 0 active high ( leading edge to rise ) 1 active low ( leading edge to fall ) [3] hsync sel [3] hsync signal to be input to pll signal to be input to sync separator 0 hsync pin hsync pin 1 sync-on-green slicer output sync-on-green slicer output [2] vsync pol [2] vsynco output pin polarity 0 inverted vsync 1 normal vsync [0] vsync sel [0] vsync select 0 vsync 1 sync separator signal (note) sync separator circuit is in power down, when bit 1 of pdn register at sub address 0fh is ?0?.
asahi kasei [ak5406] ms0592-e-01 2008/07 27 sub address 0fh [7] clamp sel [7] clamp signal to be used at clp 0 internally generated signal from hsync 1 clamp pin [6] clamp pol [6] clamp input pin polarity 0 active high 1 active low [5] coast sel [5] signal to be used as pll coast 0 coast pin 1 internally generated signal from vsync [3] coast pol [3] coast input pin polarity 0 active low 1 active high [1] pdn [1] power-down control operating functional blocks 0 power-down vref sync-on-green slicer 1 normal operation total circuit sub address 10h [7:3] sogth default : 17h [7:3] sog slicer threshold level (upward direction from sog clamp level) 00h 320mv 01h 310mv : : 1eh 20mv 1fh 10mv [2:0] red(green,blue) clp lvl input clamp level 0 minimum level 1 center level
asahi kasei [ak5406] ms0592-e-01 2008/07 28 sub address 11h ssepth [7:0] sync separator threshold level ffh feh : wider pulse width 20h standard : 01h 00h narrower pulse width sub address 12h pre coast sub address 13h post coast parameters in order to internally genera te pll coast signal from vsync are set. it is valid only when the coast sel bit is ?1?. in the pre-coast register, # of preceding hsync periods to be coasted prior to vsync signal, is set and in the post coast register, # of succeeding hsync periods to be coasted after vsync signal , is set (refer to timing chart 3). sub address 15h [1] outformat [4] output format 0 4:2:2 1 4:4:4 input & output signals vs channel relation is listed in the following table when 4:2:2 output format is selected ( refer to timing chart 1 & 2 ). channel input signal output signal red v u/v green y y blue u hi-z
asahi kasei [ak5406] ms0592-e-01 2008/07 29 sub address 17h ~ 1ch red(green, blue)offset [0],[7:0] offset adjust ( addition / subtraction ) values 1ffh -64 lsb 1feh -63.75 lsb : : 100h -0.25 lsb 0ffh 0 lsb 0feh +0.25 lsb : : 001h +63.5 lsb 000h +63.75 lsb offset of each channel is ad justed in 9-bit resolution. its center value is 0ffh and it is adjusted in 1/4 lsb per single step. offset adjust is valid only when blac k loop is disable ( loop mode = 1 ). data write of msb bits does not affect the operation and data value becomes valid when data write of lsb bits is made. sub address 1dh ~ 22h red (green, blue) blk lvl blklvl black loop setting values [0], [7:0] at minimum clamp level setting (clp lvl = 0) at center clamp level setting (clp lvl=1) 011111111 inhibited inhibited 011111110 inhibited inhibited : : : 001010001 inhibited : 001010000 20 : 001001111 19.75 : : : 000011101 7.25 inhibited 000011100 7 135 000011011 6.75 134.75 : : 000000010 0.5 128.5 000000001 0.25 128.25 000000000 0 128 (200h) 111111111 -0.25 127.75 111111110 -5 127.5 : : : 111110001 -3.75 124.25 111110000 -4 124 111101111 inhibited 123.75 : : 111100001 : 120.25 111100000 : 120 111011111 : inhibited : : : 100000001 inhibited inhibited 100000000 inhibited inhibited data write of msb bits does not affect op eration, and data value becomes valid when data write of lsb bits are made.
asahi kasei [ak5406] ms0592-e-01 2008/07 30 sub address 23h [7:5] loopbw loopbw black loop bandwidth 011 010 : 001 fast 000 standard 111 : 101 100 slow [4:3] loopoffrng loopoffrng black level coring control 00 no coring 01 0.25 lsb 10 1.5 lsb 11 1.0 lsb [2] loopmode loopmode black loop mode 0 black loop enable (blk lvl register valid) 1 black loop disable (offset register valid) [1] loophold loophold black loop condition 0 black loop operation 1 hold of black loop condition [0] vsync update vsync update update timing of the black loop offset correction 0 corrected value of black loop offset is updated at every hsync timing 1 corrected value of black loop offset is updated at every 64 vsync timing *offset integrator of the black loop is updated at every hsync timing, regardless of this bit setting. only the update timing of the offset correction amounts which is added or subtracted to/from the adc output is altered by this bit.
asahi kasei [ak5406] ms0592-e-01 2008/07 31 sub address 24h [6] coastgen sel coastgen sel coastgen input setting 0 vsync pin 1 sync separator output (note) when coastgen sel is set to ?1?, pl ease select the sync separator signal for vsync sel at sub address 0eh bit ?0?. [5] clpbw clp bw clamp input / output current clamp bandwidth 0 600ua standard 1 150ua slow [4:3] ?1? is written to each of these 2 bits. [2] sogout pol sogout pol signal polarity to be output on sogout pin 0 non-inverted 1 inverted (note) polarity of the selected signal by sogout sel register is altered when it is output on sogout pin. [1] sogout sel sogout sel signal to be output on sogout pin 0 sog slicer output 1 input signal on hsync pin [0] dofix dofix output level at power-down 0 fixed low 1 fixed high (note) compatible pins : rout7-0, gout7-0, bout7-0, , hsynco, vsynco, sogout, dtclk.
asahi kasei [ak5406] ms0592-e-01 2008/07 32 sub address 25h loop disable when this register value(m) is set to value ot her than ?0?, it is possible to divide the clamp period into two half, where the first ha lf is clamp circuit operational (m pixels clock) and black loop operation in the other half. (refer to timing chart 5) when set this register value, the value mu st be smaller than clp duration value. sub address 26h pre clpcoast default : 00h sub address 27h post clpcoast default : 00h parameters to coast clamp signal are set. in the pre coast register, # of preceding hsync periods to be coasted after vsync signal, is set in the post clpcoast regi ster, # of succeeding hsync periods to be coasted after vsync signal, is set. (refer to timing chart 6) sub address 28h [7:6] data drive data drive rout, gout, bout, hsynco, vsynco, sogout pin drivability 00 hi-z 01 hi-z 10 max x 1/4 11 max [5:4] clock drive clock drive dtclk pin drivability 00 hi-z 01 hi-z 10 max x 1/4 11 max sub address 29h [3:1] in range in range accelerate range control of black loop setting 000 no acceleration 001 non-boosted bandwidth when it settles within 0.25 lsb 010 non-boosted bandwidth when it settles within 0.5 lsb 011 non-boosted bandwidth when it settles within 0.75 lsb 100 non-boosted bandwidth when it settles within 1 lsb 101 non-boosted bandwidth when it settles within 2 lsb 110 non-boosted bandwidth when it settles within 3 lsb 111 non-boosted bandwidth when it settles within 4 lsb sub address 2ah [6:0] reserve 1 default : 39h sub address 2bh [3:0] reserve 1 default : 00h reserved.
asahi kasei [ak5406] ms0592-e-01 2008/07 33 recommended external component connection examples ( part 1 ) av d d av ss pvdd av ss dvdd dvss a nalog power supply digital ground 0.1uf 0.1uf 0.1uf a nalog ground digital power suppl y flt a nalog power supply 2.7k ? 82nf 8.2nf fig. 17 recommended external component connection examples
asahi kasei [ak5406] ms0592-e-01 2008/07 34 recommended external component connection examples ( part 2 ) rin gin sogin bypass bias a nalo g ground 0.1uf 0.1uf 6.8k ? 1% analog ground 0.1uf 0.1uf 1nf fig. 18 recommended external component connection examples ( part 2 ) bin
asahi kasei [ak5406] ms0592-e-01 2008/07 35 package marking xxxxaaa 4 a k 5 0 6 q x contents of xxxxaaa xxxx: production date (numbers) aaa : lot number (alphabet)
asahi kasei [ak5406] ms0592-e-01 2008/07 36 0 b10b 0.50 0.200.1 1 20 21 40 41 60 61 80 12.00.2 14.0 0.2 12.00.2 14.00.2 1.25typ 0.08 m 0.125 +0.10 -0.05 0.500.2 1.85max 0.10 +0.15 -0.10 1.400.2 0.10 package outline dimensions
asahi kasei [ak5406] ms0592-e-01 2008/07 37 important notice these products and their specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval und er the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akemd products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whos e failure to function or perform may reasonably be expected to result, whether di rectly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standard s of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for a pplications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. it is the responsibility of the buyer or dist ributor of akemd products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibilit y and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.

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