S1C33L15 cmos 32-bit application specific controller 32-bit risc cpu-core optimized for soc (epson s1c33 pe) (max. 90 mhz operation) 1kb instruction cache and 1kb data cache 100kb ram (including cache and battery backup ram) programmable operating clock using pll (division ratio: 1/1 to 1/16, multiplication rate: 1 to 16) hardware multimedia accelerator (64-bit internal processing) multifunctional calculation module (multiply and accumulation, matrix, and vector computations) i 2 s audio interface with one input and one output channel (supports 24-bit format) 16-ch. dma controller (triggered with peripheral circuits) sdram controller with burst control abundant serial interfaces (uart 2c h., fsio (serial i/f with fifo, supports irda1.0) 2ch., efsio( extended serial i/f with fifo, supports iso7816 mode/irda1. 0) 2ch., spi 4ch., dcsio (i 2 c bus master i/f emulator) 4ch.) 4ch. of 16-bit pwm control time rs with igbt control function 4ch. of 8-bit programmable timers nand flash interface infrared remote controller 16m/64k-color tft, 64k-color stn, and monochrome stn lcd controller max. resolution by internal vram (80kb) : 320 240, 8 bpp (256 colors) max. resolution by external memory : 640 480, 24 bpp (full color) two-screen overlay display by picture-in-picture (pip) ? descriptions the S1C33L15 is a high performance 32-bit controller with 16m/ 64k tft/64k cstn lcd contro ller and hardware arithmetic accelerator for multimedia applications. it is suitable for use in applications with an lcd panel and audio functions, such as electronic dictionaries, audio players, image viewers, and mobile equipment. the S1C33L15 supports various small to middle-size lcd panel s, not only 256-color qvga display by using the 100kb internal memory but also full-color vga display by using a la rge external memory. also it has a hardware pip function that overlays one image on another to lighten the l oad on the drawing process in the applicati on. this makes it possible to simply create the lcd panel display routine. the hardware arithmetic accelerator and the i 2 c interface for input/output can be used for decode processing of various audio formats. the on-chip in terface modules, mmc controlle r, nand flash controller and spi, can be used for image display or audio player applications using media cards. furthe rmore, the abundant interfaces and remote controller are used to realize electronic equipment that supports various user interfaces. the S1C33L15 not only operates as an lcd control processor on a standalone basis but also it can be used as an lcd controller by connecting it to an external host pr ocessor via the host processor interface (hif). the S1C33L15 is equipped with the 32-bit risc cpu core c33, 2kb instruction/data caches, 100kb ram, dma controller, memory controller (sram/sdram), various timers, r eal-time clock and general-purpose i/o ports as its basic functions, so it can also be used as a high performance general-purpose cpu. these S1C33L15 functions are implemented by epson so c (system on chip) design technology using 0.18 m multi-vth. cmos process.
S1C33L15 2 seiko epson corporation ? features technology ? 0.18 m al-4-layers vth. mi xed cmos process technology cpu ? epson original c33 pe 32-bit risc cpu-core with amba bus, optimized for soc ? the maximum operating-clock frequency: 90 mhz ? internal two-stage pipeline ? instruction set: 125 instructi ons (16-bit fixed length) ? cache: 1 kb of instruction cache + 1 kb of data cache ? memory space - up to 4 gb (32-bit address space) accessible embedded memory (ram) ? 16 kb iram1 can be used as high-speed general-purpose ram. 2 kb used for cache. not accessible by udma. ? 64 kb iram2 can be used as general-purpose ram or vram . accessible by the cpu, lcdc, hif, and udma. ? 16 kb iram3 can be used as general-purpose ram or vram . accessible by the cpu, lcdc, hif, and udma. ? 2 kb dstram can be used as a general-purpose ram. 256 byte s used for debugging. accessible by the cpu and udma. ? 2 kb bbram can be used retain data with a power supply separated from the system. mini cache controller (minicache) ? 4-way set associative method 1 kb in struction cache and the 1 kb data cache ? lru replacement algorithm ? automatic lock function during debug mode and the interrupt process of specified priority ? write-through function with 1-word buffer * a part of iram1 is used for cache memory. lcd controller (lcdc) ? supports color tft panels of up to 24 bits and co lor/monochrome stn lcd panels of up to 16 bits. ? supports typical resolutions up to vga class, in cluding 640 x 480 (vga) and 320 x 240 (qvga) (settings can be made to suit the target panel). ? supports displays of up to a maximum of 16 m colors (t ft), 64 k colors (color stn), and 16- to 2-grayscale (monochrome stn). ? setup example using internal vram (80 kb): 320 x 240, 8 bpp (256 colors) ? setup example using external memory: 640 x 480, 24 bpp (full color) ? picture-in-picture (pip) with magic color function (specified color transparency) enables two-screen overlay display control (8/16 bpp modes) ? picture-in-picture (pip) function enables tw o screen overlay display control (32 bpp mode) ? provides a look-up table (lut) function to control the intensit y/grayscale level. universal dma controller (udma) ? two channels of high-speed dma and up to 14 channels of table dma ? dual-address transfer (specifying source and destination addresses) ? can specify single or successive transfer mode. ? high-performance burst transfer func tion coupled with sdram controller ? programmable transfer unit by specifying one or four by tes, one or four half words, or one or four words. ? built-in dma trigger system with link function. ? can select software triggers or hardware triggers of various peripheral circuits sram controller (sramc) ? max. 8 chip enable signals are available to connect external devices. ? allows connection of flash rom, sram, and other external devices (such as an lcd driver). ? 24-bit address bus and 8/16-bit selectable data bus ? programmable bus access wait cycle (1 to 15 cycles) ? supports little endian access ? memory mapped i/o ? a part of memory space (area 6) is reserved for on-chip peripheral modules.
S1C33L15 seiko epson corporation 3 ? supports either a0 or bs (bus strobe) access type ? supports external wait request via the #wait pin sdram controller (sdramc) ? max. 90 mhz 16-bit sdram interface ? supports 16 m bits (2 mb) to 512 m bits (64 mb) sdram ? incorporates iqb (instruction q ueue buffer) and dqb (data queue buffer). ? optimized multi access request reduces average read latency. ? selectable cas latency from 1, 2 and 3 ? supports burst transfer ? selectable synchronous clock from the same frequency and the double frequency as cpu clock. ? built-in 12-bit auto-refresh counter ? intelligent self-refresh func tion for low power operation high-level calculation module (calculation module) ? vector calculation (addition/ subtraction/mu ltiplication) ? sum-of-products operation (mac) ? matrix operation (2 x 2, 3 x 3, 4 x 4) ? affine transformation (3 x 3 + 3) ? butterfly operation ? supports signed 32-bit integers, uns igned 32-bit integers, and 32-bit fix ed-point numbers with saturation. i 2 s audio interface (i2s) ? supports for universal audio i 2 s bus interface. ? internal i 2 s interface with 1 input channel and 1 output channel ? supports data formats up to 24 bits. ? the output channel can be used to cont rol the dac device clock, word clock and bit clock respectively (an external clock can be used). ? fifo (24 bits x 2 channels x 4) provided for each of the i/o channels ? supports dma transfer. * connection to an external dac/adc device is requir ed in order to output audio signals to speakers or earphones or to input sound from a microphone. host processor interface (hif) ? 8-bit asynchronous interface allows external hos t processor to control S1C33L15 peripheral circuits. ? hardware semaphore enables mutual exclusion. clock management unit (cmu) ? selectable system clock source (from osc3, pll, and osc1) ? can control on/off of the osc3 and osc1 oscillator circuits ? can control the system clock division ratio (1/1 to 1/ 32) and the pll frequency multiplic ation rate (x 1 to x 16) ? clock control during the standby mode (sleep or halt mode) ? can control external bus clock and the divide-by ratio between the clocks of internal core and peripheral circuit interrupt controller (itc) ? 16 channels of interrupt control reserved for s1c33 pe core ? supports 48 channels of interrupt source s (some are reserved for system use). watchdog timer (wdt) ? 30-bit watchdog timer to generate an nmi (non maskable interrupt) or a reset ? programmable watchdog timer overflow per iod (nmi or reset interrupt period) ? the watchdog timer overflow signal can be output outside the ic. 16-bit timer (t16) ? four channels of 16-bit timer/c ounter with pwm control function ? digital dac function is available usi ng the pwm output and ex ternal rc filter ? incorporates four channels of output co mparator allowing for the igbt control 8-bit timer (t8) ? four channels of programm able 8-bit timer/counter * up to two channels are used as a baud rate counter for serial interface (uart).
S1C33L15 4 seiko epson corporation serial interface (uart, sif, and efsio) uart ? two channels of uart ? supports full-duplex communication with built-in 2-by tes receive data buffer and 1-byte transmit buffer. ? transfer rate: 150 to 115200 bps, data length: 7 or 8 bits, parity mode: even, odd, or no parity, stop bit: 1 or 2 bits ? parity error, framing error, and overrun error detectable sif (serial interface) ? 2 channels of clock sync./async. serial interface ? contains 4 bytes of receive data buffer and 2 bytes of transmit data buffer for each channel ? built-in irda 1.0 interface. ? equipped with a baud-rate generator (12-bit programmable timer). efsio (extended serial interface with fifo ? 2 channels of clock sync./async. serial interface ? includes fifo (4 bytes of receive data buffer and 2 bytes of transmit data buffer are available for each channel). ? built-in irda 1.0 interface. ? contains a baud-rate generator (12-bit timer). ? supports iso7816 mode. - alternative data sequence(msb first or lsb first) - supports memory card interface com patible with iso7816-3 t=0 & t=1 protocol - programmable baud-rate and guard-time settings - supports iso7816 acknowledge and automatic repeat transmission spi (serial peripheral interface) ? four channels of spi ? supports both master and slave modes. ? data length: eight bits fixed (msb first) ? data transfer timing (clock phase and polarity va riations) is selectable from among 4 types. ? supports receive bit mask function and dma transfer. dcsio (i 2 c master emulator) ? four channels of i/o ports with a serial shifter ? can emulate the i 2 c master ? detects i/o level to drive a state machine ? emulates single-wire or double-wire communication protocol with software ? supports dma transfer. real-time clock (rtc) ? contains time counters (seconds, minutes, and hours) and calendar counters (days, days of the week, months, and year). ? the counters can be read and written by bcd data. ? selectable from 24-hour and 12-hour modes ? operable on an independent power supply (rtcvdd = 1.8 v typical) separated from system power (lvdd) ? provides the wakeup output pin and #s tby input pin to control standby/wakeup general-purpose i/o ports control (gpio) ? can control up to 96 i/o ports. ? can control built-in pull-up resistors by setting resisters (excepts some ports). * i/o ports are shared with other peripheral circuit pins (for interfaces and timers). the number of actual i/o ports available depends on t he peripheral circuit used. slc/mlc nand flash interface for reed-solomon edc (card) ? 8-bit slc/mlc nand flash can be controlled. ? built-in hardware reed-solomon edc calculation for slc/mlc nand flash * the hardware reed-solomon ecc calculati on function supports error detection only. ? provides smartmedia control (#smrd and #smwr can be generated). ? supports nand flash booting.
S1C33L15 seiko epson corporation 5 infrared remote controller (remc) ? internal infrared remote controller with 1 input channel and 1 output channel ? the duty factor and pulse width can be configured in bit units to support va rious logical formats via software control. * a connection to an infrared receiver module is requi red to receive infrared remote control signals. operating voltage ? core voltage (lvdd): 1.65 to 1.95 v (1.8 v typical) ? i/o voltage (hvdd): 2.70 to 3.60 v (3.3 v typical) ? sdram voltage (busvdd): 2.30 to 3.60 v (3.3 v typical) ? rtc voltage (rtcvdd): 1.65 to 1.95 v (1.8 v typical) ? pll voltage (pllvdd): 1.65 to 1.95 v (1.8 v typical) operating temperature ? -40 to 85 deg. c current consumption ? in sleep mode: 1.0 a *1 ? in halt mode: 3.5 ma *2 ? during execution: 103.5 ma *3 *1 while only rtc is operating (power is suppli ed only to rtcvdd and not supplied to all others) *2 when pll = off, and all clocks are set to 48 mhz *3 when pclk = 45 mhz, mclk = sdclk = 90 mhz, and the clock is supplied to all peripheral circuits. * by controlling the clocks through the clock managem ent unit, power consum ption can be reduced. shipping form ? pfbga12u-180 (12 mm x 12 mm x 1.2 mm, and 0.8 mm pitch between balls) ? qfp20-184pin (20 mm x 20 mm x 1.4 mm, and 0.4 mm pitch between pins) ? chip
S1C33L15 6 ? block diagram semiconductor operations division seiko epson corporation ic sales department ic international sales group 421-8 hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 notice: no part of this material may be reproduced or duplicated in any fo rm or by any means without the written permission of seiko ep son. seiko epson reserves the right to make c hanges to this material without notice. se iko epson does not assume any liability of a ny kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, furt her, there is no representation that this material is app licable to products requiring high level reliab ility, such as, medical products. moreo ver, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that any thing made in accordance with this material will be free from any patent or copy right infringement of a third party. this material or portio ns thereof may contain technology or the subject relati ng to strategic products under the control of the foreign exchange and foreign trade la w of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government ag ency. all brands or product names mentioned herein are trademarks and/ or registered trademarks of t heir respective companies. ?seiko epson corporation 2009, all rights reserved. http://www.epson.jp/device/semicon_e/ ? epson semiconductor website document code: 411214301 first issue apr, 2008 revised dec, 2009 in ja p an s1 c33 l15 c33pe core minicache calculation module udma hif lcdc pll cmu itc i 2 s memc reg. udma reg. timer (t 16/t8) sio (uart/sif/efsio) spi dcsio card remc lcdc reg. hif reg. wdt gpio misc rt c sdramc sr am c memory controller (memc) boot sequencer bbram arbiter iram-1 (16kb) host processor lcd panel rt cv dd external memory dstram (2kb) iram-2 (64kb) iram-3 (16kb) vram a3ram arbiter bbr am (2kb) s1 c33 l15 c33pe core minicache calculation module udma hif lcdc pll cmu itc i 2 s memc reg. udma reg. timer (t 16/t8) sio (uart/sif/efsio) spi dcsio card remc lcdc reg. hif reg. wdt gpio misc rt c sdramc sr am c memory controller (memc) boot sequencer bbram arbiter iram-1 (16kb) host processor lcd panel rt cv dd external memory dstram (2kb) iram-2 (64kb) iram-3 (16kb) vram a3ram arbiter bbr am (2kb)
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