fdmc8878 n-channel power trench ? mosfet ?2 0 1 2 fairchild semiconductor corpora tion fdmc887 8 rev. d 4 www.fairchi ldsemi.com 1 fdmc8878 n-channel power trench ? mosfet 30v, 16.5a, 14m features max r ds( on) = 14 m at v gs = 10v , i d = 9.6a max r ds( on) = 17 m at v gs = 4.5v , i d = 8.7a low profile - 0.8 rohs compliant general description this n-channel mosfet is a rugged gate version of fairchild se miconductors advanced power trench process. it has been optimized for power management applications. application dc - dc conversion mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics pac kage marking and ordering information symbol parame ter ratings units v ds dr ain to source voltage 30 v v gs gate to source v oltage 20 v i d dr ain current -continuous (package limited) t c = 25 c 16.5 a -continuous (silicon limited) t c = 25c 38 -continuous t a = 25c (note 1a) 9.6 -pulsed 60 p d power dissip ation t c = 25c 3 1 w power di s sipation t a = 25c (note 1a) 2.1 t j , t st g opera ting and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case 4 c/w r ja t hermal re s istance, junction to ambient (note 1a) 60 device marking device package reel size tape width quantity fdmc8878 fdmc8878 4 3 2 1 5 6 7 8 s s s g d d d d mlp 3.3x3.3 13 12 mm 3 000 unit s july 2012 mm max in mlp 3.3x3.3 1 2 3 4 5 d d d d g s s s bottom top mlp 3.3x3.3 6 7 8 pin 1
fdmc8878 n-channel power trench ? mosfet electrical characteristics t j = 25c unless otherw ise noted sy mbol parameter test conditions min typ max units of f characteristics bv dss drain to s ource breakdown voltage i d = 250 a, v gs = 0v 30 v bv dss t j breakdown v olt age temperature coefficient i d = 250 a , reference d to 25c 20 mv/ c i dss zer o gate v olt age drain current v ds = 2 4 v, 1 a v gs = 0v t j = 125c 1 00 i gss gate to sour ce le akage current v gs = 20v, v ds = 0v 100 na on cha racteristics v gs( th) gate to sour ce threshold v o ltage v gs = v ds , i d = 250 a 1 1.7 3 v v gs( th) t j gate to sour ce threshold v o ltage temperature coefficient i d = 25 0 a, referen ced to 25c -5.7 mv/c r ds(on ) drain to source on resistance v gs = 10v, i d = 9.6a 9.6 14.0 m v gs = 4.5v, i d = 8.7a 12.1 17.0 v gs = 10v, i d = 9.6a , t j = 125 c 13.5 20.0 g fs forwar d t r ansconductance v ds = 5v , i d = 9.6a 35 s dyn amic ch arac teristics c iss input c ap acit ance v ds = 15v, v gs = 0v, f = 1mhz 230 pf c os s output cap c rs s reverse t r g gate resist ance f = 1mhz 1.1 swit ching char acter istics t d(o n) t u rn-on de lay time v dd = 15v , i d = 9. 6a v gs = 10v, r gen = 6 81 6 ns t r rise t ime 41 0 ns t d(o ff ) t u rn-of f delay time 20 36 ns t f f all t i me 310ns q g( to t ) t ot al gate charge v gs = 10v , v dd = 15v , i d = 9.6a 18 26 nc q gs gate to source gate c harge 2.8 nc q gd gate to dr ain miller charge 3.9 nc drain-source diode characteristics v sd source to d rain diode forward v olt age v gs = 0v, i s = 9.6a (no te 2) 0.8 1.2 v t rr rever se recovery t i me i f = 9.6a, di/dt = 100a/ s 23 35 ns q rr reverse recovery char ge 14 21 nc notes: 1: r ja is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is d etermined by the user's board design. 2: pulse test: pulse width < 30 0 s, duty cycle < 2.0%. a. 6 0c/w when mounted on a 1 in 2 pad of 2 oz copper b. 135c/w when mounted on a minimum pad of 2 oz copper ?2 0 1 2 fairchild semiconductor corporation fdmc887 8 rev. www.fairchildsemi.com 2 d 4 1000 1 acit ance 183 255 pf ransfer capacitance 118 180 pf
fdmc8878 n-channel power trench ? mosfet typical characteristics t j = 25c u nless otherw ise noted fi gure 1. 0 123 4 0 10 20 30 40 50 60 v gs = 3v v gs = 4 v v gs = 4. 5v v gs = 3 .5 v v gs = 10 v pu l se duration = 80 s du t y c ycle = 0.5%max i d , d rai n current (a) v ds , dra i n to source voltage (v) on-reg ion characteristics figure 2. 0 1 0 20 30 40 50 60 0.5 1.0 1.5 2.0 2.5 v gs = 3.5v v gs = 3 v v gs = 1 0v v gs = 4 v v gs = 4 . 5v pu l se duration = 80 s dut y cycle = 0 .5%max no rm a lized drain to source on-resistance i d , dra i n current(a) n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -75 - 50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 9.6a v gs = 10v normalized d r ain to source on-resistance t j , j unct ion temperature ( o c ) vs ju nc tion temperature figure 4. 3456 78 910 5 10 15 20 25 30 p u lse duration = 80 s du t y cycle = 0.5%max t j = 125 o c t j = 25 o c i d = 9. 6a r ds(o n) , drai n to source on-resistance ( m ) v gs , ga te t o source voltage (v) o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 01234 0 10 20 30 40 50 60 pul se du ration = 80 s du t y cycle = 0.5%max t j = -5 5 o c t j = 25 o c t j = 1 50 o c i d , d rai n current (a) v gs , ga t e to source voltage (v) v dd = 5 v figu re 6. 0.0 0.2 0 .4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 t j = - 55 o c t j = 2 5 o c t j = 150 o c v gs = 0 v i s , rever se drain current (a) v sd , bo dy di ode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current ?2 0 1 2 fairchild semiconductor corporation fdmc887 8 rev. www.fairchildsemi.com 3 d 4
fdmc8878 n-channel power trench ? mosfet 4 fi gu re 7. 05 10 1 5 20 0 2 4 6 8 10 v dd = 20v v dd = 15v v gs , gat e to source voltage(v) q g , g a t e charge(nc) v dd = 10v i d = 9 .6 a gate ch arge cha racteristics figure 8. 0. 11 1 0 10 0 1000 f = 1m h z v gs = 0 v ca pac ita nce (pf) v ds , d ra i n to source voltage (v) c rss c oss c iss 3 000 30 50 c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0 .0 1 0.1 1 10 1 10 t j = 2 5 o c t j = 1 25 o c t av , tim e in avalanche(ms) i as , avalanche curre nt(a) 20 80 u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 2 4 6 8 10 12 r ja = 6 0 o c/ w v gs = 4.5v v gs = 1 0v i d , dr ai n current (a) t a , a m bient temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs ambient temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e operating area 0.1 1 10 0.0 01 0. 01 0.1 1 10 1s dc 10s 100 ms 10m s 1m s 100 us o p e ration in this area may be limited by r ds(on ) si ng le pu lse t j = ma x ra te d t a = 25 o c i d , dr ai n cu rrent (a) v ds , dr a in to source voltage (v) 80 80 figu re 12. 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 1 10 10 0 v gs = 1 0 v si n g le pulse p ( pk ) , peak t ransient pow er (w) t , pu lse width (s) 300 0. 5 t a = 25 o c i = i 25 for temper atures above 25 o c dera te peak curren t as follows: 150 t a C 125 ----- ----------------- - s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25c u nless otherw ise noted ?2 0 1 2 fairchild semiconductor corporation fdmc887 8 rev. www.fairchildsemi.com d 4
fdmc8878 n-channel power trench ? mosfet 5 figure 13. transient th ermal response curve 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 0.0 1 0. 1 1 dut y cycle - descending order norm a l ized thermal impedance, z ja t , rect angular pulse duration (s) d = 0. 5 0.2 0.1 0.05 0.02 0.01 si ngl e pul se 2 0.003 p dm t 1 t 2 notes: dut y factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a typical characteristics t j = 25c u nless otherw ise noted www.fairchi ldsemi.c om ?20 1 2 fairchild semiconductor corporation fdmc887 8 rev. d 4
fdmc8878 n-channel power trench ? mosfet 6 dimensional outline and pad layout ?20 1 2 fairchild semiconductor corporation fdmc887 8 re v. www.fairchildsemi.c om d 4
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fdmc8878 n-channel power trench ? mosfet 7 ?201 2 fairchild semiconductor corporation fdmc887 8 re v. www.fairchildsemi.c om d 4
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