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dual input network clock generator/synchronizer ad9549 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2007 C 2010 analog devices, inc. all rights reserved. features flexible r eference i nputs input frequencies : 8 khz to 750 mhz two reference inputs loss of r eference indicators auto and m anual h oldover modes auto and m anual s witchover modes smooth a - to - b phase transition on outputs excellent stability in holdov er mode programmable 16 + 1- bit i nput d ivider, r differential hstl c lock o utput output frequencies to 750 mhz low j itter clock doubler for frequencies of > 400 mhz single - ended cmos output for frequencies of < 1 50 mhz programmable digital loop f ilter (< 1 hz to ~100 khz) high speed d igitally c ontrolled o scillator (dco) core direct digital synthesizer ( dds ) with integrated 14 - bit dac excellent d ynamic p erformance programmable 16 + 1- bit f eedback d ivider, s software controlled power - down available 64 - lead lfcsp package applications network s ynchronization reference c lock j itter c leanup sonet/sdh c locks up to oc - 192, i ncluding fec stratum 3/3e r eference c locks wireless b ase station, c ontrollers cable i nfrastructure data c ommunications general description the ad95 49 provides synchronization for many systems , including synchronous optical networks (sonet/sdh). the ad9549 generates an output clock, synchronized to one of two external input references. the external references may contain significant time jitter, also specified as phase noise. using a digitally controlled loop and holdover circuitry, the ad9549 continues to generate a clean (low jitter ), valid output clock during a loss of reference condition, even when both references have failed. the ad9549 operates o ver a n industrial temperature range of ? 40c to +85c. basic block diagram fdbk_in dac_out ad9549 refa_in refb_in s1 to s4 out out_cmos r digital interface filter system clock multiplier serial port, i/o logic reference monitors and switching digital pll r, s dividers holdover clock output drivers 06744-001 figure 1.
ad9549 rev. d | page 2 of 76 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 basic block diagram ........................................................................ 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 dc specifications ......................................................................... 4 a c specifications .......................................................................... 6 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 13 input/output termination recommendations .......................... 16 theory of operation ...................................................................... 17 overview ...................................................................................... 17 digital pll core (dpllc) ........................................................ 17 phase detector ............................................................................ 21 digital loop filter coeffici ents ................................................ 22 closed - loop phase offset ......................................................... 24 lock detection ............................................................................ 24 reference monitors .................................................................... 26 reference switchover ................................................................. 27 holdover ...................................................................................... 29 output frequency range control ............................................ 32 reconstruction filter ................................................................. 32 fdbk_in inputs ........................................................................ 33 ref erence inputs ......................................................................... 33 sysclk inputs ........................................................................... 33 harmonic spur reduction ........................................................ 35 out put clock drivers and 2 frequency multiplier ............. 36 frequency slew limiter ............................................................. 37 frequency estimator .................................................................. 37 status and warnings ................................................................... 39 thermal performance .................................................................... 41 power - up ......................................................................................... 42 power - on reset .......................................................................... 42 programming sequence ............................................................ 42 power supply partitioning ............................................................. 43 3.3 v supplies .............................................................................. 43 1.8 v supplies .............................................................................. 43 serial control port ......................................................................... 44 serial control port pin descriptions ....................................... 44 operation of serial control port .............................................. 44 the instruction word ( 16 bits) ................................................ 45 msb/lsb first transfers ........................................................... 45 i/o register map ............................................................................ 48 i/o r egister descriptions .............................................................. 53 serial port configuration (register 0x0000 to register 0x0005) ........................................................................................ 53 power - down and reset (register 0x0010 to register 0x0013) ....................................................................................................... 53 system clock (register 0x0020 to register 0x0023) ............. 54 digital pll control and dividers (register 0x0100 to register 0x0130) ......................................................................... 55 free - run (single - tone) mode (register 0x01a0 to register 0x01ad) ...................................................................................... 61 reference selector/holdover (register 0 x01c0 to register 0x01c3) ........................................................................................ 62 doubler and output drivers (register 0x0200 to register 0x0201) ........................................................................................ 63 monitor (register 0x0300 to regi ster 0x0335) ....................... 64 calibration (user - accessible trim) (register 0x0400 to register 0x0410) ......................................................................... 70 harmonic spur reduction (register 0x0 500 to register 0x0509) ........................................................................................ 71 applications information .............................................................. 73 sample applications circuit ..................................................... 73 outline dimensions ....................................................................... 74 ordering guide .......................................................................... 74
ad9549 rev. d | page 3 of 76 revision history 12 /10rev. c to rev. d changes to i avdd (pin 19, pin 23 to pin 26, pin 29, pin 30, pin44, pin 45) parameter ................................................................. 4 changes to total power dissipation parameter and added endnote 4 ........................................................................................... 5 changes to pin 59 description ...................................................... 11 changes to direct digital synthesizer (dds) section ............... 20 changes to power-up section ....................................................... 42 changes to address 0x0002 default value (in table 13) ........... 48 changes to address 0x0400 and address 0x40e default values (in table 13) ..................................................................................... 52 5/10rev. b to rev. c deleted 64-lead lfcsp (cp-64-1) .................................. universal changes to sysclk pll enabled/minimum differential input level parameter, table 2 ................................................................... 6 updated outline dimensions ........................................................ 74 changes to ordering guide ........................................................... 74 1/10rev. a to rev. b changes to i/o register map section, introduction and table 13 ............................................................................................. 48 changes to register 0x0405 to register 0x0408reserved section .............................................................................................. 70 added register 0x0406part version section ........................... 71 12/09rev. 0 to rev. a added 64-lead lfcsp (cp-64-7) ................................... universal changes to total power dissipation parameter ............................ 5 changes to serial port timing specifications and propagation delay parameters ........................................................ 8 added exposed paddle notation to figure 2; changes to table 4 ............................................................................................... 10 corrected dds phase offset resolution from 16 bits to 14 bits throughout; change to figure 25 .................................... 20 changes to phase lock detection section .................................. 24 change to figure 30 ........................................................................ 25 changes to loss of reference and reference frequency monitor sections ............................................................................. 26 change to output frequency range control section ............... 32 change to figure 46 ........................................................................ 36 changes to frequency estimator section .................................... 37 changes to programming sequence section .............................. 42 changes to power supply partitioning section ........................... 43 change to serial control port section ......................................... 44 changes to figure 54 ...................................................................... 46 added exposed paddle notation to outline dimensions and changes to ordering guide ........................................................... 74 8/07revision 0: initial version
ad9549 rev. d | page 4 of 76 specifications dc specifications av dd = 1.8 v 5%, avdd3 = 3.3 v 5%, dvdd = 1.8 v 5%, dvdd_i/o = 3.3 v 5%. avss = 0 v, d v s s = 0 v , unl ess otherwise noted. table 1 . parameter min typ max unit test conditions/comments supply voltage dvdd_i/o ( pin 1) 3.135 3.30 3.465 v dvdd ( pin 3, pin 5, pin 7) 1.71 1.80 1.89 v avdd3 ( pin 14, pin 46, pin 47, pin 49) 3.13 5 3.30 3.465 v avdd3 ( pin 37) 1.71 3.30 3.465 v pin 37 is typically 3.3 v, but can be set to 1.8 v avdd ( pin 11, pin 19, pin 23 to pin 26, pin 29, pin 30, pin 36, pin 4 2, pin 44, pin 45, pin 53) 1.71 1.80 1.89 v supply current i avdd3 ( pin 14) 4 .7 5.6 ma refa, refb b uffers i avdd3 ( pin 37) 3.8 4.5 ma cmos o utput c lock d river at 3.3 v i avdd3 ( pin 46, pin 47, pin 49) 26 29 ma dac output current source , f s = 1 g sps i avdd ( pin 36, pin 42) 21 26 ma fdbk _in in put , hstl o utput c lock d river (o utput d oubler turned on) i avdd ( pin 11) 12 15 ma r ef a and r ef b input buffer 1.8 v supply i avdd (pin 19, pin 23 to pin 26, pin 29, pin 30, pin 44, pin 45) 215 281 ma aggregate analog supply, including system clock pll i avdd ( pin 53) 41 49 ma dac p ower s upp ly i dvdd ( pin 3, pin 5, pin 7) 254 265 ma digital c ore i dvdd_i/o ( pin 1) 4 6 ma digital i/o (varies dynamically) logic inputs (except pin 32) pin 9, pin 10, pin 54 to pin 61, pin 63 , pin 64 input high voltage (v ih ) 2.0 dvdd_i/o v input low vol tage (v il ) dvss 0.8 v input current (i inh , i inl ) 60 200 a at v in = 0 v and v in = dvdd_i/o maximum input capacitance (c in ) 3 pf clkmodesel (pin 32) logic input pin 32 only input high voltage (v ih ) 1.4 avdd v input low voltage (v il ) avss 0.4 v input current (i inh , i inl ) ? 18 ? 50 a at v in = 0 v and v in = avdd maximum input capacitance (c in ) 3 pf logic outputs pin 62 and the following bidirectional pins: pin 9, pin 10, pin 54, pin 55, pin 63 output high voltage (v oh ) 2.7 dvdd _ i/o v i oh = 1 ma output low voltage (v ol ) dvss 0.4 v i ol = 1 m a reference inputs pin 12, pin 13, pin 15, pin 16 input capacitance 3 pf input resistance 8.5 11.5 14.5 k? differential at r egister 0x 0 40f[1:0] = 00 differential operation co mmon mode input voltage 1 1.5 (a pplicable w hen dc -c oupled ) avdd3 ? 0.2 v differential operation ; n ote that lvds signals must be ac - coupled differential input voltage swing 1 500 mv p-p d ifferential operation single - ende d operation r egister 0x 0 40f[1:0] = 10 input voltage high (v ih ) 2.0 avdd3 v input voltage low (v il ) avss 0.8 v threshold voltage avdd3 ? 0 .66 avdd3 ? 0.82 avdd3 ? 0.98 v r egister 0x 0 40f[1:0] = 10 (o ther settings possible ) input current 1 ma si ngle - ended operation fdbk _in input pin 40, pin 41 input capacitance 3 pf input resistance 18 22 26 k? differential differential input voltage swing 2 225 mv p-p ?12 db m into 50 ? ; m ust be ac - coupled
ad9549 rev. d | page 5 of 76 parameter min typ max unit test conditions/comments system clock input system c lock inputs should always be ac - coupled (both single - ended and d ifferential ) sysclk pll bypassed input capacitance 1.5 pf single - ended, each pin input resistance 2.4 2.6 2.8 k? differential internally generated dc bias voltage 2 0.93 1.17 1.38 v differential input voltage swing 3 632 mv p-p 0 dbm into 50 ? sysclk pll enabled input capacitance 3 pf single - ended, each pin input resistance 2.4 2.6 2.8 k? differential internally generated dc bias voltage 2 0.93 1.17 1.38 v differential input voltage swing 3 632 mv p-p 0 dbm into 50 ? crystal resonator with sysclk pll enabled motional resistance 9 100 ? 25 mhz, 3.2 mm 2.5 mm at cut clock output drivers hstl output driver differential output voltage swing 1080 1280 1480 mv output d river static ; see figure 12 for output swing vs. frequency common - mode output voltage 2 0.7 0.88 1.06 v cmos output driver output driver static ; see figure 13 and figure 14 for output swing vs. frequency output voltage high (v oh ) 2.7 v i oh = 1 ma , (pin 37) = 3.3 v output vol tage low (v ol ) 0.4 v i ol = 1 ma , (pin 37) = 3.3 v output voltage high (v oh ) 1.4 v i oh = 1 ma , (pin 37) = 1.8 v output voltage low (v ol ) 0.4 v i ol = 1 ma , (pin 37) = 1.8 v total power dissipation all blocks running 4 1060 1310 mw worst case o ver supply, temperature, process power - down mode 24 70 mw using either the p ower -d own and enable register (register 0x0010) or the pwrdown pin digital power - down mode 565 713 mw default with sysclk pll enabled 955 mw after reset or power - up with f s = 1 ghz, s4 = 0, s1 to s3 = 1, f sysclk = 25 mhz default with sysclk pll disabled 945 1115 mw after reset or power - up with f s = 1 ghz, s1 to s4 = 1 with refa or refb power - down 1105 mw one reference still powered up with hstl clock driver power - dow n 1095 mw with cmos clock driver power - down 1107 mw 1 must be 0 v relative to avdd3 (pin 14) and 0 v relative to avss (pin 33, pin 43). 2 relative to avss (pin 33, pin 43). 3 must be 0 v relative to avdd (pin 36) and 0 v relative to avss (pin 33, pin 43). 4 typical measurement done with only refa and hstl output doubler turned off.
ad9549 rev. d | page 6 of 76 ac specifications f s = 1 ghz, dac r set = 10 k , p ower supply pins within the range specified in the dc specifications section , unless otherwise noted . table 2 . parameter min typ max unit test conditions/comments reference inputs pin 12, pin 13 , pin 15, and pin 16 frequency range (sine w ave) 10 750 mhz min imum recommended slew rate: 40 v/ s frequency range (cmos) 0.008 50 mhz frequency range (lvpecl) 0.008 725 mhz frequency range (lvds) 0.008 725 mhz lvds must be ac - coupled ; l ower freq uency bound may be higher , d epending on the size of the decoupling capacitor minimum slew rate 0.04 v/ns minimum pulse width high 620 ps minimum pulse width low 620 ps fdbk _in input pin 40, pin 41 input frequency range 10 400 mhz minim um differential input level 225 mv p-p ?12 db m into 50 ? ; m ust be ac - coupled minimum slew rate 40 v/ s system clock input pin 27, pin 28 sysclk pll bypassed input frequency range 250 1000 mhz m aximum f out is 0.4 f sysclk duty cycle 45 55 % minimum differential input level 632 mv p-p 0 dbm into 50 ? sysclk pll enabled vco frequency range , low band 700 810 mhz when in the range, u se the low vco band exclusively vco frequency range , auto band 810 900 mhz when in the rang e, use the vco auto band select vco frequenc y range , high band 900 1000 mhz when in the range, use the high vco band exclusively maximum input rate of system clock pfd 2 00 mhz without sysclk pll doubler input frequency range 11 200 mhz multiplication range 4 66 integer multiples of 2, maximum pfd rate and system clock frequency must be met minimum differential input level 632 mv p-p 0 dbm into 50 ? with sysclk pll doubler input frequency range 6 100 mhz multiplication range 8 132 integer multiples of 8 input duty cycle 50 % deviating from 50% duty cycle may adversely affect spurious performance. minimum differential input level 632 mv p-p 0 dbm into 50 ? crystal resonator with sysclk pll enabled crystal resonator frequency range 10 50 mhz at cut, fundamental mode resonator maximum crystal motional resistance 100 ? see the sysclk inputs se ction for recommendations clock drivers hstl output driver frequency range 20 725 mhz se e figure 12 f or maximum toggle rate duty cycle 48 52 % rise time /fall time (20 - 80%) 115 165 ps 100 ? termi nation acro ss out/outb, 2 pf load jitter (12 khz to 20 mhz) 1.0 ps f in = 19.44 mhz, f out = 155.52 mhz. 50 mhz s ystem c lock input (s ee figure 3 to figure 11 for t est condi tions ) hstl output driver with 2 multiplier frequency range 400 725 mhz duty cycle 45 55 % rise time /fall time (20 % to 80%) 115 165 ps 100 ? termi nation across out/outb, 2 pf load sub h armonic spur level ? 35 dbc w ithout correction jitter (12 khz to 20 mhz) 1.1 ps f in = 19.44 mhz, f out = 622.08 mhz , 50 mhz s ystem c lock input (see figure 3 to figure 11 for test conditions)
ad9549 rev. d | page 7 of 76 parameter min typ max unit test conditions/comments cmos output driver (avdd3/pin 37) @ 3.3 v frequency range 0.008 150 mhz see figure 14 for maximum toggle rate duty cycle 45 55 65 % with 20 pf load and up to 150 mhz rise time /fall time (20 - 80%) 3 4.6 ns with 20 pf load cmos output driver (avdd3/pin 37) @ 1.8 v frequency range 0.008 40 mhz see figure 13 for maximum toggle rate duty cycle 45 55 65 % with 20 pf load and up to 40 mhz rise time /fall time (20% to 80%) 5 6.8 ns with 20 pf load holdover frequency accuracy see the holdover section output frequency slew limiter slew rate resolution 0.54 11 1 hz/sec p = 2 16 for minimum; p = 2 5 for maximum slew rate range 0 3 10 16 hz/sec p = 2 16 for minimum; p = 2 5 for maximum reference monitors loss of reference monitor operating frequency range 7.63 10 3 1 67 10 6 hz minimum frequency er ror for continuous ref present indication ? 16 ppm f ref = 8 khz minimum frequency error for continuous ref present indication ? 19 % f ref = 155 mhz maximum frequency error for continuous ref lost indication ? 32 ppm f ref = 8 khz maximum frequency err or for continuous ref lost indication ? 35 % f ref = 155 mhz reference quality monitor operating frequency range 0 .008 150 mhz frequency resolution ( n ormalized) 0.2 ppm f ref = 8 khz; ool d ivider = 65, 535 for minimum ; ool d ivider = 1 for max (se e the reference frequency monitor section ) frequency resolution ( n ormalized) 408 ppm f ref = 155 mhz; ool d ivider = 65, 535 for minimum; ool d ivider = 1 for maximum validation timer see the reference validation timers section timing r ange 32 10 ?9 137 s ec p io = 5 timing r ange 65 10 ?6 2.8 10 5 s ec p io = 16 dac output characteristics dco frequency r ange (1 st nyquist z one ) 10 450 mhz dpll loop bandwidth sets lower limit output resistance 50 ? s ing le - ended (each pin internally termi nated to avss) output capacitance 5 pf full - scale output current 20 31.7 ma r ange depends on dac r set resistor gain error ? 10 +10 % fs output offset 0.6 a voltage compliance range avss ? 0.50 +0.5 avss + 0.50 outputs not dc -s horted to v ss digital pll minimum o pen -l oop b andwidth 0.1 hz d ependent on the frequency of refa/ ref b, the dac sample rate, and the p - , r - , and s - divider values maximum o pen -loop b andwidth 100 khz d ependent on the frequency of refa/ ref b, the dac sample rate , a nd the p - , r - , and s - divider values minimum p hase m argin 0 10 d egrees d ependent on the frequency of refa/ ref b, the dac sample rate, and the p - , r - , and s - divider values maximum p hase m argin 85 90 d egrees d ependent on the frequency of refa/ ref b, the dac sample rate, and the p - , r - , and s - divider values pfd i nput f requency r ange ~0.008 ~24.5 mhz feedforward d ivider r atio 1 131,070 1, 2, , 65,535 or 2, 4, , 131,070 feedback d ivider r atio 1 131,070 1, 2, , 65,535 or 2, 4, , 131,070
ad9549 rev. d | page 8 of 76 parameter min typ max unit test conditions/comments lock detect ion phase lock detector time threshold programming range 0 2097 s fpfd_g ain = 200 time threshold resolution 0.488 ps fpfd_g ain = 200 lock time programming range 32 10 ?9 275 s ec i n power -of- 2 steps unlock time programming range 192 10 ?9 67 10 ?3 s ec i n power -of- 2 steps frequency lock detector normali zed frequency threshold programming range 0 0.0021 fpfd_g ain = 200; normalized to (f ref /r) 2 ; see the frequency lock detection section for details normalized frequency threshold programming resolution 5 10 ? 13 fpfd_g ain = 200; normalized to (f ref /r) 2 ; see the frequency lock detection section for details lock time programming range 32 10 ?9 275 s ec i n power -of- 2 steps unlock time programming range 192 10 ?9 67 10 ?3 s ec i n power -of- 2 s teps digital timing specifications time required to enter power - down 15 s time required to leave power - down 18 s reset a ssert to high - z time for s 1 to s4 configuration pins 60 ns time from rising edge of reset to h igh - z on the s1, s2, s 3, and s4 configuration pins reset d eassert to low- z t ime for s 1 to s 4 configuration pins 30 ns time from falling edge of reset to low- z on the s1, s2, s3, and s4 configuration pins serial port timing specifications sclk clock rate (1/t clk ) 25 50 mhz refer to figure 58 for all write - related serial port parameters , m aximum sclk rate for read back is governed by t dv sclk pulse width high, t hi gh 8 ns sclk pulse width low, t lo w 8 ns sdo /sdio to sclk setup time , t ds 1.93 ns sdo /sdio to sclk hold time, t dh 1.9 ns sclk falling edge to valid data on sdio/sdo, t dv 11 ns refer to figure 56 csb to sclk setup time, t s 1.34 ns csb to sclk hold time, t h ? 0.4 ns csb minimum pulse width high, t pwh 3 ns io_update pin setup t ime from sclk rising edge of the final b it t clk s ec t clk = p eriod of sclk in hz io_update pin hold time t clk s ec t clk = p eriod of sclk in hz propagation delay fdbk _in to hstl output driver 2.8 ns fdbk _in to hstl output driver with 2 frequency multiplier enabled 7.3 ns fdbk _in to cmos output driver 8.0 ns fdbk _in t hrough s - divider to cmos output driver 8.6 ns frequency tuning word update, io_update pin r ising edge to dac output 60/fs ns fs = system clock f requency in ghz
ad9549 rev. d | page 9 of 76 absolute maximum rat ings table 3. parameter rating analog supply voltage (avdd) 2 v digital supply voltage (dvdd) 2 v digital i/o supply voltage (dvdd_i/ o) 3.6 v dac supply voltage ( avdd3 pins ) 3.6 v maximum digital input voltage ?0.5 v to dvdd_i/o + 0.5 v storage temperature ?65c to +150c operating temperature range ?40c to +85c lead temperature (soldering , 10 sec) 300c junction temperature 150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of t his specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jb jc unit 64- lead lfcsp 25.2 13.9 1.7 c/w typical note that the exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal perfor - mance. see the thermal performance section for more information. esd caution
ad9549 rev. d | page 10 of 76 pin configuration and function d escriptions pin 1 indic at or 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 nc nc a vdd pfd_vrb pfd_vrt pfd_rset a vdd a vdd a vdd a vdd sysclk sysclkb a vdd a vdd loop_fi lter clkmodese l 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 sclk sdio sdo csb io_upd a te reset pwrdown holdover refselect s4 s3 a vdd avss dac_outb dac_out a vdd3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dvdd_i/o dvss dvdd dvss dvdd dvss dvdd dvss s1 s2 a vdd re f a_in re f a_inb a vdd3 refb_in refb_inb notes 1. nc = no connect. 2. the exposed therma l die on the bot t om of the p ackage provides the analog ground for the p ar t . this exposed p ad must be connected t o ground for proper oper a tion. dac_rset a vdd3 a vdd3 a vdd a vdd avss a vdd fdbk_in fdbk_inb avss out_cmos a vdd3 a vdd out outb avss 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 06744-002 ad9549 top view (not to scale) figure 2. pin configuration table 5 . pin function descriptions pin no. input/ output pin type mnemonic description 1 i power dvdd_i/o i/o digital supply . 2, 4, 6, 8 i power dvss digital gro und. connect to g round . 3, 5, 7 i power dvdd digital supply . 9, 10, 54, 55 i/o 3.3 v cmos s1, s2, s3, s4 configurable i/o p ins . these pins are configured under program control (see the status and warnings section ) and do not hav e internal pull - up/pull- down resistors. 11, 19, 23 to 26, 29, 30, 36, 42, 44, 45, 53 i power avdd analog supply . connect to a nominal 1.8 v s upply . 12 i differential i nput refa_in frequency/phase reference a input. this internally biased input is typical ly ac - coupled and , when configured as such, can accept any differential signal with single - ended swing between 0.4 v and 3.3 v. if dc - coupled, lvpecl or cmos input is preferred. 13 i differential i nput refa_inb complementary frequency/phase reference a in put . complementary signal to the input provided on p in 12. if using a single - ended, dc - coupled cmos signal into refa_in, bypass this pin to ground with a 0.01 f capacitor. 14, 46, 47, 49 i power avdd3 analog supply . connect to a nominal 3.3 v supply . 15 i differential i nput refb_in frequency/phase reference b input. this internally biased input is typically ac - coupled and , when configured as such , can accept any differential signal with single - ended swing between 0.4 v and 3.3 v. if dc - coupled, lvpecl or cmos input is preferred. 16 i differential i nput refb_inb complementary frequency/phase reference b input . complementary signal to the input provided on p in 15. if using a single - ended, dc - coupled cmos signal into ref b _in, bypass this pin to ground with a 0.01 f capacitor. 17, 18 nc no connect. these are excess, unused pins that can be left floating .
ad9549 rev. d | page 11 of 76 pin no. input/ output pin type mnemonic description 20, 21 o pfd_vrb, pfd_vrt these pins must be capacitively decoupled. see the phase detector pin connections section for details. 22 o current set r esistor pfd_rset conn ect a 5 k ? re sistor from this pin to g round (see the phas e detector pin connections section). 27 i differential i nput sysclk system clock input. the system clock input has internal dc b iasing and should always be ac - coupled, except when using a crystal. single - ended 1.8 v cmos can also be used , but it may introduce a spur caused by an input duty cycle that is not 50%. when using a crystal, tie the clkmodesel pin to avss, and connect crystal di rectly to this pin and pin 28. 28 i differential i nput sysclkb complementary system clock . complementary signal to the input provided on p in 27. use a 0.01 f capacitor to ground on this pin if the signal provided on pin 27 is single - ended. 31 o loop_filter syst em clock multiplier loop filter . when using the frequency multiplier to drive the s ystem c lock, an external loop filter must be constructed and atta ched to this pin. this pin should be pulled down to ground with a 1 k ? res istor when the system clock pll is bypassed. see figu re 44 for a diagram of the system clock pll loop filter. 32 i 1.8 v cmos clkmodesel clock mode select. set to gnd when connecting a crystal to the system clock input (pin 27 and pin 28). pull up to 1.8 v when using either an oscillator or an external clock source. this pin can be left floating when the system clock pll is bypassed. (see the sysclk inputs section for details on the use of this pin.) 33, 39, 43, 52 o gnd avss analog ground . connect to g round. 34 o 1.8 v hstl outb complementary hstl output . see the specifications and primary 1.8 v differential hstl driver sections for details. 35 o 1.8 v hstl out hstl output . see the specifications and primary 1.8 v differential hstl driver sections for details. 37 i power avdd3 analo g supply for cmos output driver. this pin is normally 3.3 v but can be 1.8 v. this pin should be powered even if the cmos driver is not used. see the power supply partitioning section for power supply partitioning. 38 o 3.3 v cmos out_cmos cmos output . see the specifications and the output clock drivers and 2 frequency multiplier section s . this pin is 1.8 v cmos if pin 37 is set to 1.8 v. 40 i differential i nput fdbk_ inb complementary feedback input. in standard operating mode, this pin is connect ed to the filtered dac_out b output . this internally biased input is typically ac - coupled, and when configured as such, can accept any differential signal whose single - ended sw ing is at least 400 mv. 41 i differential i nput fdbk_in feedback input . in standard operating mode, this pin is connected to the filtered dac_out output . 48 o current set r esistor dac_rset dac o ut put c urrent s etting r esistor. connect a resistor (usually 10 k ? ) from this pin to gnd . see the dac output section. 50 o differential o utput dac_out dac o ut put . this signal should be filtered and sent back on chip through fdbk_in input. this pin has an internal 50 ? pull - d own resistor. 51 o differential o utput dac_outb com ple mentary dac o utput . this signal should be filtered and sent back on chip through fdbk_inb input. this pin has an internal 50 ? pull - down resistor. 56 i/o 3.3 v cmos refselect reference select i nput . in manual mode, the refselect pin operate s as a high impedance input pin; and in automatic mode, it operates as a low impedance output pin. logic 0 (low) indicates/selects r ef a. logic 1 (high) indicates/selects r ef b. there is no internal pull - up/pull- down resistor on this pin. 57 i/o 3.3 v cmos holdover holdover (active h igh) . in manual holdover mode, this pin is used to force the ad9549 into holdover mode. in automatic holdover mode, it indicates holdover status. there is no internal pull - up/pull- down resistor on this pi n. 58 i 3.3 v cmos pwrdown power - down . when this active high pin is asserted, the device becomes inactive and enters the full power - down state. this pin has an internal 50 k ? pull - d own resistor. 59 i 3.3 v cmos reset chi p reset. when this active high pin is asserted, the chip goes into reset. note that on power - up, it is recommended that the user assert a high to low edge after the power supplies reach a threshold and stabilize. this pin has an internal 50 k ? pull - do wn resistor.
ad9549 rev. d | page 12 of 76 pin no. input/ output pin type mnemonic description 60 i 3.3 v cmos io_update i/o update . a logic transition from 0 to 1 on this pin transfers data from the i/o port registers to the control registers (see the write sec tion). this pin has an internal 50 k ? pull - down resistor. 61 i 3.3 v cmos csb chip select . active low. when programming a device, this pin must be held low. in systems where more than one ad9549 is present, this pin enables individual programming of each ad9549 . this pin has an internal 100 k ? pull - up resistor. 62 o 3.3 v cmos sdo seria l data output . when the device is in 3- wire mode, data is read on this pin. there is no internal pull - up/pull- down resistor on this pin. 63 i/o 3.3 v cmos sdio serial data input/output . when the device is in 3- wire mode, data is written via this pin. in 2 - wire mode, data reads and writes both occur on this pin. there is no internal pull - up/pull- down resistor on this pin. 64 i 3.3 v cmos sclk serial programming clock . d ata clock for serial programming. this pin has an internal 50 k ? pull - down resistor. exposed die pad o gnd epad analog ground. the exposed thermal pad on the bottom of the package pro - vides the analog ground for the part. this exposed pad must be connected to ground for proper operation.
ad9549 rev. d | page 13 of 76 typical performance characteristics unless otherwise noted , avdd, avdd3, and dvdd are at nominal supply voltage; f s = 1 ghz, dac r set = 10 k. 06744-003 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) rms jitter (12khz to 20mhz): 0.18ps rms jitter (50khz to 80mhz): 0.24ps figure 3 . additive phase noise at hstl output driver , sysclk = 1 ghz (sysclk pll bypassed) , f ref = 19.44 mhz, f out = 311.04 mhz, dpll loop bw = 1 khz 06744-004 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) rms jitter (12khz to 20mhz): 0.36ps rms jitter (50khz to 80mhz): 0.42ps figure 4 . additive phase noise at hstl output driver , sysclk = 1 ghz (sysclk pll bypassed) , f ref = 19.44 mhz , f out = 622.08 mhz, dpll l oop bw = 1 khz , hstl output doubler enabled 06744-005 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) rms jitter (12khz to 20mhz): 1.01ps rms jitter (50khz to 80mhz): 1.04ps figure 5 . additive phase noise at hstl output driver , sysclk = 1 ghz (sysclk pll enabled d riven by r&s sma100 signal generator at 50 mhz ), f ref = 19.44 mhz , f out = 311.04 mhz, dpll loop bw = 1 khz 06744-006 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) rms jitter (12khz to 20mhz): 1.09ps rms jitter (50khz to 80mhz): 1.14ps figure 6 . additive phase noise at hstl output driver , sysclk = 1 ghz (sysclk pll enabled and d riven by r&s sma100 signal ge nerator at 50 mhz), f ref = 19.44 mhz , f out = 622.08 mhz, dpll l oop bw = 1 khz , system clock doubler enabled, hstl doubler enabled 06744-007 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) rms jitter (12khz to 20mhz): 1.0ps rms jitter (50khz to 80mhz): 1.2ps figure 7 . additive phase noise at hstl output driver , sysclk = 1 ghz (sysclk pll e nabled and d riven by r&s sma100 a t 50 mhz ), f ref = 19.44 mhz , f out = 155.52 mhz , sysclk doubler enabled , dpll loop bw =1 khz 06744-008 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) rms jitter (12khz to 20mhz): 1.07ps rms jitter (50khz to 80mhz): 1.16ps figure 8 . additive phase noise at hstl output driver , sysclk = 1 ghz (sysclk pll e nabled and d riven by r&s sma100 signal generator at 50 mhz ), f ref = 8 khz, f out = 155.52 mhz , dpll loop bw = 10 hz
ad9549 rev. d | page 14 of 76 06744-009 10 30 50 70 90 system clock pll input frequency (mhz) 2.0 1.5 1.0 0.5 0 12khz to 20mhz rms jitter (ps) figure 9 . 12 khz to 20 mhz rm s jitter vs . system clock pll input frequency , sysclk = 1 ghz, f ref = 19.44 mhz, f out = 155.52 mhz 06744-010 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) rms jitter (12khz to 20mhz): 1.26ps rms jitter (50khz to 80mhz): 1.30ps figure 10 . additive phase noise at hstl output driver , sysclk = 1 ghz (sysclk pll e nabled and d riven by a 25 mhz fox crystal osc illator ), f ref = 19.44 mhz, f out = 155.52 mhz , dpll l oop bw = 1 khz 06744-011 10 100 1k 10k 100k 1m 10m freq uency offset (hz) ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) rms jitter (12khz to 20mhz): 4.2ps figure 11 . additive phase noise at hstl output driver , sysclk = 500 mhz ( sysclk pll d isabled ), f ref = 10.24 mhz, f out = 20.48 mhz , dpll l oop bw = 1 khz
ad9549 rev. d | page 15 of 76 06744-012 0 200 400 600 800 frequency (mhz) 650 600 550 500 450 amplitude (mv) nom skew 25c, 1.8v supply slow skew 90c, 1.7v supply figure 12 . hstl output driver single -e nded peak -to- peak amplitude vs. toggle rate (100 a cross d ifferential p air) 06744-013 0 10 20 30 40 frequency (mhz) 2.5 2.0 1.5 1.0 0.5 0 amplitude (v) nom skew 25c, 1.8v supply (20pf) slow skew 90c, 1.7v supply (20pf) figure 13 . cmos output driver peak -to- peak amplitude vs. toggle rate (avdd3 = 1.8 v) with 20 pf load 06744-014 0 50 100 150 frequency (mhz) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 amplitude (v) nom skew 25c, 3.3v supply (20pf) slow skew 90c, 3.0v supply (20pf) figure 14 . cmos output driver peak -to- peak amplitude vs. toggle rate (avdd3 = 3.3 v) with 20 pf load 06744-015 0 0.5 1.0 1.5 2.0 2.5 time (ns) 0.4 0.6 0.2 0 ?0.2 ?0.4 ?0.6 amplitude (v) frequency= 600mhz t rise (20 80%) = 104ps t fall (80 20%) = 107ps v p-p = 1.17v diff. duty cycle = 50% figure 15 . typical hstl output waveform, nominal conditions, dc - coupled, differential probe a cross 100 load 06744-016 0 20 40 60 80 100 time (ns) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 amplitude (v) frequency= 20mhz t rise (20 80%) = 5.5ns t fall (80 20%) = 5.9ns v p-p = 1.8v duty cycle = 53% figure 16 . typical cmos output driver waveform (@ 1.8 v), nominal conditions, estimated capacitance: 5 pf 06744-017 0 10 20 30 40 50 time (ns) 3.3 2.8 2.3 1.8 1.3 0.8 0.3 ?0.2 amplitude (v) frequency= 40mhz t rise (20 80%) = 2.25ns t fall (80 20%) = 2.6ns v p-p = 3.3v duty cycle = 52% figure 17 . cmos output driver waveform (@ 3.3 v), nominal conditions, estimated capacitance: 5 pf, f out = 20 mhz
ad9549 rev. d | page 16 of 76 input/ output termination r ecommendations downstream device (high-z) ad9549 1.8v hstl output 100? 06744-018 0.01f 0.01f figure 18 . ac - coupled hstl output driver downstream device (high-z) ad9549 1.8v hstl output 50? 50? 06744-019 avdd/2 figure 19 . dc - coupled hstl output driver ad9549 self-biasing ref input 0.01f 0.01f 100? (optional) 06744-020 figure 20 . reference input ad9549 self-biasing fdbk input 0.1f 0.1f 100? (optional) 06744-021 figure 21 . fdbk _in input
ad9549 rev. d | page 17 of 76 theory of operati on 06744-022 dds/dac frequency tuning word slew limit prog. digital loop filter pfd r freq est. s lock detect 2 digital pll core holdover control logic low noise clock multiplier sysclk port input ref monitor irq and status logic ool and lor ref_cntrl external analog low-pass filter digital interface holdover sysclk fdbk_in dac_out out out_cmos s1 to s4 refb_in refa_in refselect amp figure 22 . detailed block diagram overview the ad9549 provides a clocking output that is directly related in phase and frequency to the selected (active) reference (refa or ref b) but has a phase noise spectru m primarily gove rned by the system clock. a wide band of reference frequencies is supported. jitter exist ing on the active reference is greatly reduced by a programmable digital filter in the d igital phase -l ocked l oop (pll), which is the core of this product. the ad9549 s upports both manual and automatic holdover. while in holdover, the ad9549 continue s to provide an output as long as the system clock is maintained. the frequency of the output during hold - over is an average of the steady state output frequency prior to hol dover. also offered are manual and automatic switchover modes for changing between the two references , should one become suspect or lost. a digitally controlled oscillator (dco) is implemented using a d irect d igital s ynthesizer (dds) with an integrated ou tput digital - to - analog converter (dac) , clocked by the system clock. a bypassable pll - based fre quency multiplier is present , enabling use of an inexpensive, low frequency source for the system clock. for best jitter performance, the system clock pll should be bypassed ; and a low noise , high frequen cy system clock should be provided direc tly. sampling theory sets an upper bound for the dds output frequency at 50% of f s (where f s is the dac sample rate), but a practical limitation of 40% of f s is generally r ecommended to allow for the selectivity of the required off - chip reconstruction filter. the output signal from the reconstruction filter is fed back to the ad9549 , both to complete the pll and to be processed through the output circuitry. the output circui try includes hstl and cmos output buffers, as well as a frequency doubler for designs that must pro vide frequencies above the nyquist level of the dds. the individual functional blocks are described in the following sections. digital pll core (dpllc) the digital phase -l ocked l oop c ore (dpllc) includes the fre quency estimation block and the digital phase lock control block driving the dds. the start of the dpllc signal chain is the reference signal, f r , which appears on refa or ref b inputs. the frequency o f this signal can be divided by an integer factor of r via the feedforward divider. the output of the feedforward divider is routed to the phase/frequency detector (pfd). therefore, the frequency at the input to the pfd is given by r f f r pfd =
ad9549 rev. d | page 18 of 76 the pfd outputs a time series of digital words that are routed to the digital loop filter. the digital filter implem entation offers many advantages: the filter response is determined by numeric coefficients rather than by discrete component values; there i s no aging of components and , therefore, no dri ft of component value over time; t here is no thermal noise in the loop filter ; and there is no control node leakage current (which causes reference feed through in a traditional analog pll). the output of the l oop filter is a time series of digital words. these words are applied to the frequency tuning input of a dds to steer the dco frequency. the dds provides an analog output signal via an integrated dac, effectively mimicking the operation of an analog voltag e- controlled oscillator ( vco ). the dpllc can be programmed to operate in conjunction with an internal frequency estimator to help decrease the time required to achieve lock. when the frequency estimator is employed, frequency acqui sition is accomplished i n the following two - step process: 1. an estimate is made of the frequency of f pfd . the phase lock control loop is essentially inoperative during the frequency estimation process. when a frequency estimate is made, it is delivered to the dds so that its output frequency is approximately equal to f pfd multiplied by s (the modulus of the feedback divider). 2. the phase lock control lo op becomes active and acts as a servo to acquire and hold phase lock with the reference signal. as mentioned in step 1, the dpllc incl udes a feedback divider that allows the dco to operate at an integer multiple (s) of f pfd . this establishes a nominal dco frequency (f dds ), given by r dds f r s f ? ? ? ? ? ? = dds external dac reconstruction filter fdbk_in pins cci loop filter . samples delivered at sysclk rate samples delivered at the clk rate phase detector (time-to- digital converter) pfd div clk ref input sysclk dac_out pins 06744-023 s r p figure 23 . digital pll block diagram feedforward divider (divide - by - r) the feedforward divider is an integer divider that allows frequency prescaling of the ref s ource input signal while maintaining the desired low jitter performance of the ad9549 . the feedforward divider is a programmable modulus divider with v ery low jitter injection. the divider is capable of handling input frequencies as high as 750 mhz. the divider depth is 16 bits , cascaded with an additional divide - by -2. t herefore , t he divider is capable of integer division from 1 to 65,535 (index of 1) or from 2 to 131,070 (index of 2). the div ider is programmed via the i/o register m ap to trigger on either the rising (default) or falling edge of the ref s ource input signal. note that the value stored in the r-d ivider register is one less than the actual r - divider, so setting the r-d ivider register to 0 result s in an r -d ivider that is equal to 1 . there is a lower bound on the value of r that is imposed by the phase frequency detector within the dpllc , which has a maxi - mum operating frequency of f pfd[ max] , a s explained in the fine phase detector section. the r -d ivid er/2 bit must be set when refa or ref b is greater than 400 mhz. the user must also ensure that r is chosen so that it satisfies the inequality . ? ? ? ? ? ? ? ? ][ ceil maxpfd r f f r the upper bound is ? ? ? ? ? ? khz 8 floor r f r wh ere the ceil(x) function yields the nearest integer x. for example, if f r = 155 mhz and f pfd[ max] = 24.5 mhz, then ceil (155/24.5) = 7, so r must be 7. feedback divider (divide - by - s) the feedback divider is an integer divider allowing frequency multiplication of the ref signal that appears at the input of the phase detector. it is capable of handling frequencies well above the nyquist limit of the dds. the divider depth is 16 bits , cas - caded with an additional divide - by -2. t herefore , t he divider is capable of integer division from 1 to 65,535 (index of 1) or from 2 to 131,070 (index of 2). the div ider is programmed via the i/o register m ap to trigger on either the rising (default) or falling edge of the feed back signal. note that the value stored in the s-d ivider register is one less than the actual r - divider, so setting the s -d ivider register to 0 result s in an s - divider equal to 1. the feedback divider must be programmed within certain boundaries. the s -d iv ider/2 bit must be set when fdbk_in is greater than 400 mhz. the upper boun dary on the feedback divider is the lesser of the maximum programmable value of s and the maximum practical output frequency of the dds (~ 40% f s ). two equations are given : s max1 for a feedback divider index of 1 and s max2 for an index of 2. ? ? ? ? ? ? ? ? = 535,65, %40 min r s max1 f rf s or ? ? ? ? ? ? ? ? = 070,131, %40 min 2 r s max f rf s w here r is the modulus of the feedforward divider, f s is the dac sample rate, and f r is the input reference frequency.
ad9549 rev. d | page 19 of 76 the dco has a minimum fre quency, f dco [min] (see the dac o utput characteristics section of the ac specifications table). this minimum frequency imposes a lower bound, s min , on the feedback divider value , as well. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 1, ma x ][ r min dco min f f r s note that r educed d co frequencies result in worse jitter performance (a consequence of the reduced slew rate of the sinusoid generated by the dds). forward and reverse fec clock scaling the f eedforward divider (d ivide - by - r) and f eedback d ivider (d ivide - by - s) enable fec clock scaling. for instance, to multiply the incomin g signal by 25 5/237, set the s - divider to 255 and the r- divider to 237. b e careful to abide by the limita tions on the r - and s -d ividers, and make sure the p hase d etector input frequency is within specified lim its. phase detector the phase detector is composed of two detectors: a coarse phase detector and a fine phase detector. the two detectors operate in parallel. both detectors measure the duration ( t) of the pulses generated by a conventional thre e- state p hase/frequency detector . together, the fine and coarse phase detectors produce a digital word that is a time - to - digital conversion of the separation between the edge transitions of the pre scaled reference signal and the feedback signal. if the fine phase detector is able to produce a valid result, this result alone serves as the phase error measurement. if the fine phase detector is in either an overflow or underflow condition, the phase error measurement uses the coarse phase detector instead. digital loop filter the digital loop filter integrates and low - pass filters the digital phase error values delivered by the phase detector. the loop fi lter response mimics that of a second - order r c network used to filter the output of a typical phase detector and cha rge pump combination , as shown in figure 24 . r2 c2 c1 loop filter vco phase/ frequency detector change pump clk 06744-024 figure 24 . typical analog pll block diagram the building blocks implemented on the ad9549 , however, are digital. a time - to - digital converter that produces di gital values proportional to the edge timing error between the clk and feedback signals replaces the phase - frequency detector and charge pump. a digital filter that processes the edge timing error samples from the time - to - digital converter replaces the lo op filter. a dds replaces the vco, which produces a frequency that is linearly related to the digital value provided by the loop filter. this is shown in figure 25 with some additional detail. the samples provided by the time - to -d igital converter are delivered to the loop filter at a sample rate equal to the clk frequency ( that is , f r /r). the loop filter is intended to oversample the time - to - digital converter output at a rate determined b y the p- divider. the value of p is programma ble via the i/o register m ap. it is stored as a 5 - bit number, p io . the value of p io is related to p by the equation p = 2 pio where 5 p io 16. hence, the p - divider can provide divide ratios between 32 and 65, 536 in power - of - 2 steps. with a dac sample rate of 1 ghz , the loop filter sample rate can range from as low as 15.26 khz to a maximum of 31.25 mhz. coupled to the loop fil ter is a cascaded comb integrator (cci) filter that provides a sample rate translation between the loop filter sample rate (f s /p) and the dds sample rate, f s . the choice of p is important because it controls both the response of the cci filter and the samp le rate of the loop filter. t o understand the method for determining a useful value for p, it is first necessary to examine the tran sfer function of the cci filter. 2 p 1( 1 )( ? ? ? ? ? ? ? ? = ? j j cci ep e h or 0 , ) cos( 1 ) cos( 11 0 ,1 )( 2 > ? ? ? ? ? ? ? ? ? ? = = p p h cci to evaluate the response in terms of abs olute f requency, make the substitution s f f = 2 where f s is the dac sample rate , and f is the frequency at which h cci is to be evaluated. analysis of this function reveals that the cci magnitude response follows a low - pass characteristic tha t consists of a series of p lobes. the lobes are bounded by null points occurring at frequency mul - tiples of f s / p. the peak of ea ch successive lobe is lower than its predecessor over the frequency range between dc and one - half f s . for frequencies greater t han one - half f s , the response is a re flection about the vertical at one - half f s . furthermore, the first lobe ( which appears between dc and f s /p) exhibits a monotonically decreasing response. that is, the magnitude is unity at dc , and it steadily decreases with frequency until it vanishes at the first null point (f s /p) .
ad9549 rev. d | page 20 of 76 06744-025 dac (14-bit) angle to amplitude conversion 14 19 19 48 48 48 14 phase offset qd 48-bit accumulator frequency tuning word (ftw) f s i-set dac+ dac? figure 25 . dds block diagram the null points imply the existence of transmission zeros placed at finite frequencies. while transmission zeros placed at infinity yield minimal phase delay, zeros placed closer to dc result in increased phase delay. hence, the position of the first null point has a significant impact on the phase delay introduced by the cci filter. this is an important consideration because excessive phase delay negatively impacts the overall closed - loop response. as a rule of thumb, choose a value for p so that the frequency of the first null point (f s /p) is the greater of 80 the desired loop bandwidth or 1.5 the frequency of clk (f r /r) . the value of p thus calculated (p max ) is the largest usable value in practice. because p is programmed as p io , it is necessary to define p max in terms of p io so that p iomax can be determined. the condition p io p iomax ensures that the impact of the phase delay of t he cci filter on the phase margin of the loop does not exceed 5. p iomax can be expressed as ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ref s loop s iomax f f f f p 3 2 logfloor, 80 logfloor,16 min ,5 max 2 2 with a properly chosen value for p, the closed - loop response of the digital pll is primarily determined by the response of the digital loop filter. flexibility in controlling the loop filter response translates directly into flexibility in the range of applications satisfied by the architecture of the ad9549 . the ad9549 e valuation s oftware automatically sets the value of the p - divider based on the users input criteria. therefore, the formulas are provided here mainly to assist in understanding how the part works. direct digital synthesizer (dds) one of the primary building blocks of the digital pll is a direct digital synthesizer (dds). the dd s behaves like a sinusoidal signal generator. the frequency of the sinusoid generated by the dds is determined by a frequency tuning word (ftw), which is a digital ( that is , numeric) value. unlike an analog sinusoidal generator, a dds uses digital building blocks and operates as a sampled system. thus, it requires a sampling clock (f s ) that serves as the fundamental timing source of the dds . the accumulator behaves as a modulo -2 48 counter with a programmable step size that is determined by the ftw . a block diagram of the dds is shown in figure 25 . the input to the dds is a 48 - bit ftw that provides the accumulator with a seed value. on each cycle of f s , the accumulator adds the value of the ftw to the running total of its output. for exam ple, given ftw = 5, the accumulator count s in increments of 5 sec , incrementing on each f s cycle. over time, the accumulator reach es the upper end of its capacity (2 48 in this case), a t which point , it rolls over, retaining the excess. the average rat e at which the accumulator rolls over establishes the frequency of the output sinusoid. the average rollover rate of the accumulator is given by the following equation and establishes the output frequency (f dds ) of the dds: s dds f ftw f ? ? ? ? ? ? = 48 2 solvi ng this equation for ftw yields ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = s dds f f ftw 48 2 round for example, given that f s = 1 ghz and f dds = 19.44 mhz, then ftw = 5,471,873,547,255 ( 0x04fa05143bf7). the relative phase of the sinusoid can be controlled numerically , as well. this is accomplished usi ng the phase offset input to the dds (a programmab le 14 - bit value ( phase); see the i/o register map section ). the resulting pha se offset, ? (radians), is given by ? ? ? ? ? ? ? =? 14 2 2 phase the dds can be operated in either open - loop or closed - loop mode, via the close l oop bit in the pll control register (register 0x0100, bit 0) . there are two open - loop modes: single t one and h oldover. in s ingle -t one m ode, the dds behaves like a frequency synthesizer and uses the value stored in the ftw0 register to determine its output frequency. alternatively, t he ftw and phase values can be determined by the device itself using the frequency estimator. because s ingle -t one mode ignores the reference inputs, it is very useful for generating test signals to aid in debugging. single t one mode must be activated manually via re gister programming. note that due to the internal architecture of the ad9549, the lsb of the 48 - bit tuning word becomes a dont care when operating the dds in single - tone mode. this results in an effective frequency resolution of 7 hz with the dac system clock equal to 1 ghz.
ad9549 rev. d | page 21 of 76 in h oldover mode, the ad9549 uses past tuning words when the loop is closed t o determine its ou tput frequency. therefore , the loop must be successfully closed for h oldover m ode to work. switching in and out of h oldover m ode can be e ither automatic or manual, depending on register settings. typically, the ad9549 operates in closed - loop mode. in closed - loop mode, the ftw values come from the output of the digital loop filter and vary with time. the dds frequency is steered in a manner similar to a conventional vco - based pll. note that i n closed - loop mode, the dds phase offset capability is inoperative. dac output the output of the digital core of the dds is a time series of numbers representing a sinusoidal waveform. this series is tran slated to an analog signal by means of a digital - to -analog converter (dac). the dac outputs its signal to two pins driven by a balanced current source architecture (see the dac output diagram in figure 26). the peak output current derives from the combi - nation of two factors. the first is a reference current (i dac_ref ) established at the dac_rset pin , and the second is a scale factor programmed into the i/o register m ap. 06744-026 switch control code i fs /2 i fs /2 avdd3 avss current switch array current switch array iout ioutb 50? 50? i fs /2 + i code i fs /2 ? i code i fs 49 50 51 52 figure 26 . dac output pins the va lue of i dac_ref is set by connecting a resistor (r dac_ref ) between the dac_rset pin and ground. the dac_rset pin is internally connected to a virtual voltage reference of 1.2 v nominal, so the reference current can be calculated by refdac refdac r i _ _ 2.1 note that t he recommended value of i dac_ref is 120 a, which leads to a recommended value for r dac_ref of 10 k . the scale factor consists of a 10 - bit binary number (fsc) programmed into the dac f ull-s cale c urrent register (address 0x040b and address 0x040c) in the i/o register m ap. the full - scale dac out put current (i dac_fs ) is given by 1024 192 72 _ _ fsc ii refdac fs dac using the recommended value of r dac_ref , the full - scale dac output current can be set with 10 - bit granularity over a range of approximately 8.6 ma to 31.7 ma. t he default value is 20 ma . phase detec tor coarse phase detector the coarse phase detector uses the dac sample rate (f s ) to determine the edge timing deviation between the ref signal and the feedback signal generated by the dds. hence, f s sets the timing resolution of the coarse phase detector. at the recommended rate of f s = 1 ghz, the coarse phase detector spans a range of over 131 s (sufficient to accommodate ref signal frequencies as low as 8 khz). the phase gain of the coarse phase detector is controlled via the i/o r egisters by means of t wo numeric entries. the first is a 3- bit , power - of - 2 scale factor, pds. the second is a 6 - bit linear scale factor, pdg. pdg f f r phasegain pds r s cpd 6 2 fine phase detector the fine phase detector operat es on a divided down version of f s as its sampling time base. the sample rate of the fine phase detector is set using a 4 - bit word (pfd_div) in the i /o register m ap (register 0x0023) and is given by )_(4 divpfd f rate sample detector phasefine s the default value of pfd_div is 5, so for f s = 1 ghz, the default sample rate of the fine phase detector is 50 mhz. the upper bound on the maximum allowable input frequency to the phase detector (f pfd[ max] ) is 49% of the sample rate, or )_(8 ][ divpfd f f s maxpfd therefore, f pfd[ max] is 25 mhz in the preceding example. the fine phase detector uses a p roprietary technique to determine the phase deviation between the ref signal and feedback signal. the phase gain of the fine phase detector is controlled by an 8- bit scale factor (fpfd_gain) in the i/o register map (register 0x0404) . the nominal (def ault) value of fpfd_gain is 200 an d establishes the phase gain as r fp f gain fpfd r d phasegain )_ )( 102( 7 10 u
ad9549 rev. d | page 22 of 76 phase detector gain matching although the fine and coarse phase detectors use different means to make a timing measurement, it is essential that both have equivalent phase gain. without proper gain matching , the closed - loop dynamics of the system cannot be properly controlled. hence, the goal is to make phasegain cpd = phasegain fpd . this leads to gain fpfd pdg f pds s _)102()2( 7 10 6 = + which simplifies to s pds f gain fpfd pdg _)1016( 2 7 = typically, f pfd_gain is established first , and then pdg and pds are calculated. the proper choice for pds is given by ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = s f gain fpfd pds 2 _ 10 log round 7 2 the final value of pds must satisfy 0 pds 7. the proper choice for pdg is calculated using the following equation: ? ? ? ? ? ? ? ? = ? s pds f gain fpfd pdg 4 7 2 _10 round the final value of pdg must satisfy 0 pdg 63. for example, let f s = 700 mhz and fpfd_gain = 200; then pds = 1 and pdg = 23. note that the ad9549 e valuation s oftware calculate s register values that have the phase detector gains already matched. phase detector pin connections there are three pins associated with the phase detector that must be connected to external components. figure 27 shows the recommended component values and their connections. 06744-027 10f 0.1f pfd_vrt pfd_rset pfd_vrb ad9549 0.1f 0.1f 4.99k ? 20 21 22 figure 27 . phase detector pin connections digital loop filter coefficients t o provide the desired flexibility, the loop filter has been designed with three programmable coefficients ( , , and ). the coefficients , along with p (where p = 2 p io ), completely define the response o f the filter, which is given by ? ? ? ? ? ? ? ? ++??+ ??+ = )1()2( )1( )( 2 ee ?e h j j j loopfilter to evaluate the response in terms o f absolute frequency, substitute s f pf = 2 w here p is th e divide ratio of the p- divider, f s is the dac sample rate, and f is the frequency at which the function is to be evaluated . the loop filter coefficients are determined by the ad9549 evaluation software according to three parameters: ? is the desire d close d- loop phas e margin (0 < < /2 rad ). ? f loop is the desired open - loop bandwidth (hz) . ? f dds is the desired output frequency of the dds (hz) . note that f dds can also be expressed as f dds = f r (s/r). the three coefficients are calculated according to paramete rs via the following equations: ) tan( 4 pf c ?= |f )( 2 1 = |fff gain fpfd cdds )( _10 2 7 38 ? ? ? ? ? ? ? ? ?= w here : ) sin( 1 1)( f += s loop c f f f = fpfd_gain is the value of the gain scale factor for the f ine p hase d etector as programmed into t he i/o register map . note that t he range of loop filter coefficients is limited as follows: 0 < < 2 23 (~ 8.39 10 6 ) ?0.125 < < 0 ?0.125 < < 0 the preceding constraints on and constrain the closed - loop phase margin such that both and assume negative values. even though and are limited to negative quantities, the values as programmed are positive. the negative sign is assumed internally. note that t he closed - loop phase margin is limited to the range of 0 < < 90 because and are negative.
ad9549 rev. d | page 23 of 76 the three coefficients are implemented as digital elements, neces sitating quantized values. determination of the programmed coefficient values in this context follows. the quantized coefficient is composed of three factors, where 0 , 1 , and 2 are the programmed values for the coefficient. ( )( ) 2 1 0 quantized ? ? ? ? ? ? ? = 22 2048 the boundary values for eac h are 0 0 4095, 0 1 22, and 0 2 7. the optimal values of 0 , 1 , and 2 are ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 4095 2048 log ceil ,22 min ,0 max 2 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+ ? ? ? ? ? ? = 11 4095 logfloor,7 min ,0 max 2 1 2 ( ) { } [ ] 11 2 round ,4095 min ,0 max +? = 12 0 the magnitude of the quantized coefficient is composed of two factors ( ) ( ) ) 15 ( 2 +? = 1 0 quantized where 0 and 1 are the programm ed values for the coefficient. the boundary values for each are 0 0 4095 and 0 1 7. the optimal values of 0 and 1 are ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 15 4095 logfloor,7 min ,0 max 2 1 ( ) { } [ ] 15 2 round ,4095 min ,0 max + = 1 0 the magnitude of the quantized coeffic ient is composed of two factors. ( ) ( ) ) 15 ( 2 +? = 1 0 quantized w here 0 and 1 are the programmed values for the coefficient . t he boundary values for each are 0 0 4095 and 0 1 7. the optimal values of 0 and 1 are ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 15 4095 logfloor,7 min ,0 max 2 1 ( ) { } [ ] 15 2 round ,4095 min ,0 max + = 1 0 the min(), max(), floor(), ceil() and round() f unctions are defined as follows: ? the function min(x 1 , x 2 , x n ) chooses the smallest value in the list of arguments. ? the function max(x 1 , x 2 , x n ) chooses the largest value in the list of argum ents. ? the function ceil (x) increases x to the next higher integer if x is not an integer ; otherwise , x is unchanged. ? the function floor(x) reduces x to the next lower integer if x is not an integer ; otherwise , x is unchanged. ? the function round(x) round s x to the nearest integer. to demonstrate the wide programmable range of the loop filter bandwidth, consider the following design example. the system clock frequency (f s ) is 1 ghz, the input reference frequency (f r ) is 19.44 mhz, the dds output frequency (f dds ) is 155.52 mhz, and the required phase margi n ( ) is 45. f r is within the nominal bandwidth of the phase detector (25 mhz), and f dds /f r is an integer (8), so the prescal e r is not required. t herefore , r = 1 and s = 8 can be used for the feedforward and feedback dividers, respectively. note that i f f dds /f r is a n on integer, then r and s must be chosen such that s/r = f dds /f r with s and r both constrained to integer values. for example, if f r = 10 mhz and f dds = 155.52 mhz, then the optimal choice for s and r is 1944 and 125, respectively . the open - loop ba ndwidth range under the defined conditions spans 9.5 hz to 257.5 khz. the wide dynamic range of the loop filter coefficients allows for programming of any open - loop bandwidth within this range under these conditions. the resulting closed - loop bandwidth ran ge under the same conditions is approximately 12 hz to 359 khz. the resulting loop filter coefficients for the upper loop bandwidth , along with the necessary programming values , are shown as follows: = 4322509.4784981 0 = 2111 ( 0x83f) 1 = 22 ( 0x16) 2 = 0 ( 0x0 0) = ? 0.10354689386232 0 = 3393 (0xd41) 1 = 0 (0x00) 0 = 4095 (0xfff) = ?0.12499215775201 1 = 0 (0x00)
ad9549 rev. d | page 24 of 76 the resulting loop filter coefficients for the lower loop bandwidth , along with the n ecessary programming values, are shown as fol lows: = 0.005883404361345 0 = 1542 ( 0x606 ) 1 = 0 ( 0x00 ) 2 = 7 ( 0x07 ) = ? 0.000003820176667 0 = 16 (0x10) 1 = 7 (0x07) = ?0.00000461136116 0 = 19 (0x13) 1 = 7 (0x07 ) the ad9549 e valuation s oftware generates these coefficients automatica lly based on the users desired loop characteristics. closed- loop phase offset the ad9549 provides for limited control over the phase offset between the reference input signal and the output signal by adding a constant phase offset value to the output of the phase detector. an adder is included at the output of the phase detector to support this , as shown in figure 28 . the value of the constant (pll offset ) is set via the d pll phase o ffset bits . 06744-028 phase offset value phase detector loop filter to cci filter clk feedback figure 28 . input phase offset adder pll offset is a function of the phase detector gain and the desired amount of timing offset ( t offset ). it is given by pll offset = t offset (2 10 10 7 fpfd_gain fpfd_gain is described in the fine phas e detector section. for example, suppose that fpfd_gain = 200, f clk = 3 mhz, and 1 of phase offset is desired. first, the value of t offset must be determined , as follows: ps 9.925 mhz 3 1 360 1 360 deg = ? ? ? ? ? ? = =? clk offset t t having determined t offset , 1896)200102 ps( 9.925 7 10 = = offset pll the r esult has been rounded because pll offset is restricted to integer values. note that t he pll offset value is programmed as a 14 - bit, twos complement number. however, the user must ensure that the magnitude is constrained to 12 bits, such that: ?2 11 pll off set < +2 11 the preceding constraint yields a timing adjustment range of 1 ns. this ensures that the phase offset remains within the bounds of the fine phase detector. lock detection phase lock detection during the phase locking process, the output of the phase detector tends toward a value of 0 , which indicates perfect alignment of the phase detector input signals. as the control loop works to maintain the alignment of the phase detector input signals, the output of th e phase detector wanders around 0. th e phase lock detector tracks the absolute value of the digital samples generated by the phase detector. these samples are compared to the p hase l ock d etect t hreshold value (pldt) programmed in the i/o register map . a false state at the output of the compar ator indicates that the absolute value of a sample exceeds the value in the threshold bits . a true state at the output of the comparator indicates alignment of the phase detector input signals to the degree specified by the lock detection threshold. 06744-029 absolute value digital comparator control logic unlock timer lock timer phase lock detect threshold y x close loop phase lock detect reset p-divider clock phase detector samples i/o registers 3 5 figu re 29 . phase lock detector block diagram the p hase l ock d etect threshold value is a 32 - bit number stored in the i/o register map . ( ) gain fpfd t pldt _ 102 round 7 10 ?= w here t is the maximum allowable timing error between the signals at the inp ut to the phase detector and the value of fpfd_gain is as described in the fine phase detector section. for example, suppose that f r /r = 3 mhz, fpfd_gain = 200, and the maximum timing deviation is given as 1. this yields a t va lue of ( ) )103(360 1 360 360 1 6 == =? r r f r trt the resulting phase lock detect threshold is 1896 )103(360 200102 round 6 7 10 = ? ? ? ? ? ? ? ? = pldt hence, 1896 ( 0x 00000768) is the va lue that must be stored in the phase lock detect t hreshold bits .
ad9549 rev. d | page 25 of 76 the phase lock detect signal is generated once the control logic observes that the output of the comparator has been in the true state for 2 x periods of the p -d ivider clock (see the digital loop filter section for a description of the p -d ivider). when the phase lock detect signal is asserted, it remains assert ed until cleared by an unlock event or by a device reset . the duration of the lock detection p rocess is programmable via the phase lock watchdog t imer bits . the interval is controlled by a 5- bit number, x (0 x 20). the abso lute duration of the phase lock detect interval is s x lock f p t 2 = hysteresis in the phase lock detection process is controlled by specifying the minimum duration that qualifies as an unlock event. an unlock event is declared when the control logic observes that the output of the comparator has been in the false state for 2 y + 1 periods of the p -d ivider clock (provided that the phase lock detect signal has been asserted). detection of an unlock event clears the phase lock detect signal, and the phas e lock detection process is automatically restarted. the time required to declare an unlock event is programmable via the phase unlock watchdog t imer bits . the interval is controlled by a 3 - bit number, y (0 y 7). the absolute duration of t he unlock detection interval is s y unlock f p t 1 2 + = figure 31 shows the basic timing relationship between the reference signal at the input to the phase detector, the phase error magnitude, the output of the comparator, and the output of t he phase lock detector. the example shown here assumes that x = 3 and y = 1. note that t he phase and frequency lock detectors may erroneously indicate phase/frequency lock while in holdover. therefore, the user should use the phase and frequency lock signa ls in conjunc - tion with either the reference input valid or the holdover active signals to indicate phase/frequency lock. frequency lock detection frequency lock detection is similar to phase lock detection, with the exception that the difference between s uccessive phase samples is the source of information. a running difference of the phase samples serves as a digital approximation to the time - derivative of the phase samples, which is analogous to frequency. the formula for the frequency lock detect thresh old value (fldt) is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?= 2 7 10 _ 102 round r f r gain fpfd f fldt where f r is the frequency of the active reference, r is the value of the reference prescaler, and f is the maximum frequency deviation of f r that is considered to indicate a frequency - locked condition ( f 0). 06744-031 absolute value differencer digital comparator control logic unlock timer lock timer frequency lock detect threshold y x close loop frequency lock detect reset p-divider clock phase detector samples i/o registers 3 5 figure 30 . frequency lock detection 06744-030 f r /r f s /p 0 threshold comparator phase error magnitude samples lock timer (x = 3) unlock timer (y = 1) 8 8 4 locked threshold figure 31 . lock/unlock detection timing
ad9549 rev. d | page 26 of 76 for example, if f r = 3 mhz, r = 5, fpfd _gain = 200 , and a fre - quency lock threshold of 1% is spec ified , the frequency lock detect thres hold value is ( ) 667,170 10 3 5 200102103%1 round 2 6 7 10 6 = ? ? ? ? ? ? ? ? ? ? ? ? = fldt hence, 170 , 667 ( 0x 00029aab) is the value that should be stored in the frequency lock detect t hreshold bits . the duration of the frequency lock/unlock detection process is controlled in exactly the same way as the phase lock/unlock detection process in the previous section. however, different control registers are used : namely, the frequency l ock/unlock watchdog t imer bit s. reference monitors loss of reference the ad9549 can set an alert when one or both of t he reference signals are not present. each of the two reference inputs (refa, refb) has a dedicated lor ( l oss of r eference) circuit enabled via the i/o register map . detection of an lor condition sets the appropriate lor bit in both a status register and a n irq status register in the i/o register map . the lor state is also in ternally available to the multipurpose status pins (s1 to s 4) of the ad9549 . by setting the appropriate bit in the i/o register map , the user can assign a status pin to each of the lor flags. this provides a means to control external hardware based on the state of the lor flags directly. the lor circuits are internal watchdog timers that have a programmable period. the period of the timer is set via the i/ o register m ap so that its perio d is longer than that of the monitored reference signal. the rising edge of the reference signal continuously resets the watchdog timer. if the timer reaches a full count, this indicates that the reference was either lost or its period was longer than the timer period. lor does not differentiate between these. the period for each of the lor timers is controlled by a 16 - bit word in the i/o register map . the period of the timer clock ( t clk ) is 2/f s . therefore, the period of the watchdog timer ( t wd ) is t wd = ( 2/ f s ) n w here n is the value of the 16 - bit word stored in the i/o register map for the appropriate lor circuit. choose the value of n so that the watchdog period is greater than the input reference peri od, expressed mathematically as ? ? ? ? ? ? ? ? > r s f f floorn 2 where f r is the frequency of the input reference. the value of n results in establishing two frequencies : o ne for which the lor signal is never triggered (f present ), and one for which the lor signal is always active (f lost ). using these fre - quencies , th e lor signal in termittently toggle s between states. the values of the two frequency bounds are )1(2 ? = n f f s present n f f s lost 2 = note that when n is chosen to be 1 2 floor + ? ? ? ? ? ? ? ? r s f f , the lor circuit is capable of indicating an lor condit ion in little more than a single input reference period. for example, if f s = 1 ghz and f r = 2.048 mhz, then the smallest usable n value is 2451 )10048.2(2 10 floor 6 9 =+ ? ? ? ? ? ? ? ? = min n this yields the following values for f present and f lost : f present = 2,04 9, 1 80 f lost = 2,0 40,816 note that n should be chosen sufficiently large to account for any acceptable deviation in the period of the input reference signal. notice that the value of n is inversely proportional to the reference frequency, meaning that as the reference frequ ency goes up, the precision for adjusting the threshold goes down. proper operation of the lor circuit requires that n be no less than 3. therefore, the highest reference frequency for which the lor circuit function s properly is given by 6 s lor[max] f f = reference frequency monitor the ad9549 can set an alert whenever one or both of the reference inputs drift in frequency beyond user - specified limits. each of the two references has a dedicated o ut of l imits (ool) circuit enabled/disabled via the i/o register map . detection of an ool condition sets the appropriate ool bit in both a status register and an irq status register in the i/o register map . the user c an also assign a status pin (s1 to s4) to each of the ool flags by setting the appropriate bit in the i/o register map . this provides a means to control external hardware based on the state of the ool flags directly. each reference monitor contains three main building blocks: a programmable reference divider, a 32 - bit counter, and a 32 - bit digital c omparator. digital comparator 32-bit counter 16-bit ool divider 06744-032 gate clk f s f r lower limit upper limit ool 4 figure 32 . reference monitor
ad9549 rev. d | page 27 of 76 the following f our values are needed to calculate the correct values of the reference monitor: ? s ystem clock frequency, f s (usually 1 ghz) ? r eference input frequency, f r (in hz) ? e rror bound, e (1% = 0.01) ? m onitor window size (w) the monitor window size is the difference between the maximum and minimum number of counts accumulated between adjacent edges of the reference input. if this window is too small, random variations cause the ool detect or to indicate incorrectly that a reference is out of limits. however, the time required to determine if the reference frequency is valid increases with window size. a window size of a t least 20 is a good starting point. the four input values mentioned previously are used to calculate the ool d ivider (d) and ool nominal value (n), which , in turn , are used to calculate the ool u pper l imit (u) and ool l ower l imit (l) , according to the following formulas: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = e w f f d s r 5 1 ceil ,535,65 min ,1 max 4 d f f n r s = )floor()floor( w nl ? = )floor() ceil( w nu += the timing accuracy is dependent on two factors. the first is the inherent accuracy of f s because it serves as the time base for the r eference m onitor. as such, the accuracy of the r eference m onitor can be no better than the accuracy of f s . the second factor is the value of w, which must be sufficiently large ( 20) so that the timer resolves the deviation between a nominal value of f r and a value that is out of limits. as an example, let f r = 10 mhz, = 0.05 %, f s = 1 ghz, and w = 20. the limits are then d = 79 lower limit = 1980 upper limit = 2020 next, let = 0.0 005% . then the limits are d = 7999 lower limit = 199980 upper limit = 200020 note that the number of counts (and time) required to make this measurement has increased by 100 . in addition, it is recommended that d be an odd number. reference switchover the ad9549 supports dual input reference clocks. reference switchover can be accomplished eit her automatically or manually by appropriately programming the automatic s elector bit in the i/o register map (register 0x01c0, bit 2 ). transition to a newly selected reference depends on a number of factors: ? state of the refselect pin ? state of the r ef _ab bit (register 0x01c1[ 2]) ? state of the enable ref input o verride bit (register 0x01c1 [3]) ? holdover status a functional diagram of the reference switchover and holdover logic is shown in figure 33. 06744-033 1 0 1 0 autorefsel override refpin autohold override hldpin 1 0 1 0 ref_ab hldovr derived refsel state derived holdover state refselect holdover state machine to reference switching control logic to holdov er control logic active refsel state active holdover state figure 33 . reference switchover and holdover logic in manual mode, the active reference is determined by an exter - nally applied logic level to the refselect pin. in automatic mode, an internal state machine determines which reference is active, and the refselect pin becomes an output indicating which reference the state mach ine is using. the user can override the active reference chosen by the internal state machine via the enable ref input o verride bit. the r ef _ab bit is then used to select the desired reference. when in override, it is important to note that the refselect pin does not indicate the phys ical reference selected by the r ef _ab bit. instead, it indicates the reference that the internal state machine would select if the device were not in the override mode. this allows the user to force a reference switchover by m eans of the programming registers while monitoring the response of the state machine via the refselect pin. the same type of operation (manual/automatic and override) also applies to the holdover function, as shown in the r eference s witchover l ogic diagram ( see figure 33 ). the dashed arrows in the diagram indicate that the state machine output is available to the refselect and holdover pins when in override mode .
ad9549 rev. d | page 28 of 76 use of line card mode to eliminate runt pulses when two references a re not in exact phase alignment and a transition is made from one to the other, it is possible that an ex tra pulse may be generated. this depends on the relative edge placement of the two references and the point in time that a switch - over is initiated. to eliminate the extra pulse problem , an enable line card m ode bit is provided (register 0x01c1, bit 4 ). the l ine c ard m ode logic is shown in figure 34 . when the e na ble line c ard bit is set to 0 , reference switch over occurs on c ommand without consider ation of the relative edge placement of the references. this means that there is the possibility of an extra pulse. however, when this bit is set to 1, the timing of the reference switch over is executed conditionally , as shown in figure 35 . 06744-034 1 0 0 1 enable line card mode 1 0 ref in from reference selection logic dq refa_in refb_in selected reference figure 34 . reference switchover control logic note that when the line card mode is enabled, the rising edges of the alternate reference are used to clock a latch. the latch holds off the actual transition until the next rising edge of the alternate reference. figure 35 shows a timing diagram that demonstrates the difference between reference switchover with the line card mode enabled and disabled. if enabled, when the reference switchover logic is given the command to switch to the alternate reference, an actual transition does not occur until the next rising edge of the alter - nate reference. this action eliminates the spurious pulse that can occur when the line card mode is disabled. 06744-035 ref selection stalled until next rising edge of refb select refb select refa refa in refb in from reference selection logic ref in ref in disabled enabled 1 1 2 2 3 3 4 1 2 3 4 1 2 3 4 4 5 line card mode figure 35 . reference switchover timing effect of reference input switchover on output clock this section covers the transient behavior of the ad9549 during a clock switchover event. this is also applicable whe n the ad9549 leaves holdover a nd reverts to being locked to a reference input. there is no phase disturbance entering holdover mode. switching reference inputs with different phases cause s a transient frequency disturbance at the output of the pll. the mag nitude of this disturbance depends on the frequency of the reference inputs, the magnitude of the phase offset between the two references, and the digital pll loop bandwidth. 06744-036 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 time (s) 31 29 27 25 23 21 19 phase (s) reference switching: 10ns delta @ 0.2hz bandwidth, 70 phase margin figure 36 . output phase vs. ti m e for a reference swit chover figure 36 shows the output phase as a function of time for a reference switchover event. in this example, reference a and reference b are both 30.72 mhz and have a 10 ns (102) phase offset. the digital pll loop bandwidth is 0.2 hz. the frequency disturbance is the slope of the shift in figure 36. the maximum slope is 4.75 divisions in one second of time, which gives the following transient frequency error, as suming that the output is also 30.72 mh z: hz 292.0 s1 105 s1 divs 75.4 = = = ? ? = x y m the maximum freque ncy error for this transient is ppm 0095.0 mhz 72.30 hz 292.0 = = cyerror maxfrequen t o apply this to a general case, the designer should calculate the maximum time difference between two reference edges that are 180 apart. the preceding c alculation of the slope, m, becomes 0.5 hz, not 0.292 hz , for a phase shift of 180 . next, the frequency error must be scaled for the loop bandwidth used. the frequency error for 1 khz is 5000 greater than for 0.2 hz, so the peak frequency error for the p receding example of 102 is 47.4 ppm, and 81.3 ppm for a 180 phase error between the reference inputs.
ad9549 rev. d | page 29 of 76 when calculating frequency error for a hitless switchover environment such a s stratum 3, as defined in telcordia gr - 1244- core, the designer must consi der the frequency err or budget for the entire system. the frequency disturbance caused by a reference clock switchover in the ad9549 contribute s to this budget. it is also critical that the designer differentiate between appli - cations that require the output clock to track the input clock , as opposed to applications that require the pll to smooth out transient disturbances on the input. based on all of the preceding considerations, the ad9549 digital pll architecture allows the designer to choose a loop ba ndwidth tailored to meet the requirements for a given application. the loop bandwi dth can range from 0.1 hz up to 100 khz, provided that the loop bandwidth is never more than 1/10 th of the phase detector frequency. holdover holdover control and frequency a ccuracy holdover functionality provides the user with a means of maintaining the output clock signal even in the absence of a reference signal at the ref a or ref b input. in holdover mode, the output clock is generated from the sysclk input (via the dds) by directly applying a frequency tuning word to the dds. the frequency accuracy of the ad9549 is exactly the frequency accuracy of the system clock input. transfer from normal operation to holdover mode can be accom plished either manually or automatically by appropriately programming the a utomati c h oldover bit (register 0x01c0 , bit 0, 0 = m anual, 1 = a uto ). the actual transfer to holdover operation, however, depends on the state of the holdover pin and the state of the enable holdover override and holdover on /o ff control register bits (register 0x01c1, bits 1:0 ). manual ho ldover is established when the automatic h oldover bit is a l ogic 0 (default). in manual mode, holdover is determined by the state of the holdover pin (0 = n ormal, 1 = h oldover). the holdover pin is configured as a high impedance (>100 k ) input pin to accommodate manual holdover operation. automati c holdover is invoked when the automatic h oldover bit is a l ogic 1. in automatic mode, the holdover pin is configured as a low impedance output with its logic state indicating the hold over stat e as determined by the internal state machine (0 = n ormal, 1 = h oldover). in automatic holdover operation , the user can override the internal st ate machine by programming the enable holdover o verride bit to a l ogic 1 and the holdover m ode bit (register 0x0 01c0[4]) to the desired state ( 0 = normal, 1 = holdover ). however, the hold over pin does not indicate the forced holdover state in the override condition but continues to indicate the holdover state as chosen by the internal state machine (even though the state machine choice is overridden). this allows the user to force a holdover state by means of the programming registers while monitoring the response of the state machine via the holdover pin. a diagram of the reference switchover and holdover logic is s hown in figure 33. note that t he default state for the reference switchover bits is as follows: automatic h oldover = 0, enable holdover o verride = 0, and holdover m ode = 0.
ad9549 rev. d | page 30 of 76 06744-037 4 3 2 1 reset faila & validb & autorefsel & ovrdrefpin failb & valida & autorefsel & ovrdrefpin refb & holdover refa & holdover refb & holdover refa & holdover validb & autorcov & ovrdhldpin valida & autorcov & ovrdhldpin faila & validb & autorefsel & autorcov & ovrdrefpin & ovrdhldpin failb & valida & autorefsel & autorcov & ovrdrefpin & ovrdhldpin faila & autohold & ovrdhldpin & (validb or autorefsel or ovrdrefpin) failb & autohold & ovrdhldpin & (valida or autorefsel or ovrdrefpin) refa: refb: holdover: faila: failb: valida: validb: reference a selected reference b selected holdover state reference a failed reference b failed reference a validated reference b validated ovrdrefpin: ovrdhldpin: autorefsel: autorcov: autohold: ||: &: %: override ref sel pin override holdover pin automatic reference select automatic holdover recovery automatic holdover entry logical or logical and logical not abbreviation key figure 37 . holdover state d iagram holdover and reference switchover state machine figure 37 shows t he interplay between the input re ference signals and holdover, as well as the various control signa ls and the four states . state 1 or state 2 is in effect w hen the device is not in the holdover condition, and state 3 or state 4 is in effect when the holdover condition is active. when refa is selected as the active reference, state 1 or state 3 is in effect. when refb is selected as the active reference, state 2 or state 4 is in effect. a transition between states depends on the reference switchover and holdover control register settings, the logic state of the refselect and holdover pins, and the occurrence of certain events (for example, a reference failure) . the state machine and its relationship to control register and external pin stimuli are shown in figure 37 . the state machine generates a derived reference selection and holdover state. the actual control signal sent to the refe rence switchover logic and the holdover logic, however, depends on the control signals applied to the muxes. the dashed path leading to the refselect and holdover pins is active when the auto matic mode is selected for reference selection and/or holdover as sertion.
ad9549 rev. d | page 31 of 76 reference validation timers each of the two reference inputs has a dedicated validation timer. the status of these timers is used by the holdover state machine as part of the decision making process for reverting to a previously faulty referen ce. for example, suppose that a reference fails ( that is , an lor or ool condition is in effect) and that the device is programm ed to revert automatically to a valid reference when it recovers. when a reference returns to normal operation, the lor and ool c onditions are no longer true. however, the state machine is not immediately notified of the clearing of the lor and ool condition s. instead, when both the lor and ool conditions are cleared, the validation timer for that particular reference is started. ex piration of the validation timer is an indication to the state machine that the reference is then available for selection. however, even though t he reference is then flagged as valid, actual transition to the recovered reference depends on the programmed s ettings of the various holdover control bits. the validation timers are controlled via the i/o register map . the user should be careful to make sure the validation timer is at least two periods of the reference clock. although there are two independent val idation timers, the programmed informa - tion is shared by b oth. the desired time interval is controlled via a 5- bit word (t) such that 0 t 31 (default is t = 0). the duration of th e validation timers is given by ( ) 12 1 ?= + t 0 recover t t w here t 0 is the s ample rate of the digit al loop filter, whose period is s p 0 f t io 2 = s ee the digital loop filter section for more information. holdover operation when the holdover condition is asserted, the dds output frequency is no lo nger controlled by the phase lock feedback loop. instead, a static frequency tuning word (ftw) is applied to the dds to hold it at a specified frequency. the source of the static ftw depends on the status of the appropriate control register bits. during no rmal operation, the holdover averager and s ampler monitors and accumulates up to 65 , 000 ftw values as they are generated, and , upon entering holdover, the holdover state machine ca n use the averaged tuning word or the last valid tuning word. exiting holdo ver mode is similar to the manner in which it is entered. if manual holdover control is used, when the holdover pin is deasserted, the phase detector starts comparing the holdover signal with the reference input signal and start s to adjust the phase/freque ncy using the holdover signal as its starting point. the behavior of the holdover state machine when it is automa ti- cally exiting holdover mode is very similar. the primary difference is that the reference monitor is continuously monitoring both reference inputs and , as soon as one becomes valid, the ad9549 automatically switches to that input. the output frequency in h oldover mode depends on the frequency of the sysclk input source and the value of the ftw applied to the dds. therefore, the stability of t he output signal is completely dependent on the stability of the sysclk source (and the sysclk pll m ultiplier, if enabled). note that it is very important to power down an unused reference input to avoid chattering on that input. in addition , the reference validation timer must be set to at least one full cycle of the signal coming out of the reference divider. holdover sampler and averager (hsa) if activated via the i/o register map , the hsa continuously monitors the data generated by the digital loop fil ter in the background. it should be noted that the loop filter data is a time sequence of frequency adjustments ( f) to the dds. the output of the hsa is routed to a read - only register in the i/o register map and to the holdover control logic. the first of these destinations (the r ead - only register) serves as a trace buffer that can be read by the user and the data processed externally. the second destination (the holdover control logic) uses the output of the hsa to peg the dds at a specific frequency upon entry into the holdover state. hence, the dds assume s a frequency specified by the last value generated by the hsa just prior to entering the holdover state. the state of the output mux is established by programming the i/o register map . the default state is such that the f values pass through the hsa unaltere d. in this mode, the output sample rate is f s /p, the same as the sample rate of the digital loop filter. n ote that p is the divide ratio of the p- divider (see the digital loo p filter section ), and f s is the dac sample rate. alternatively, the mux can be set to select the averaging path. in this mode, a block average is performed on a sequence of samples. the length of the sequence is determined by program - ming the value of y (a 4 - bit number stored in the i/o register map ) and has a value of 2 y + 1 . in averaging mode, the output sample rate is given by f s / (p 2 y + 1 ). when the number of f samples that are specified by y has been collected, the averaged result is delivered to a two - stage pipeline. the last stage of the pipeline contains the value that is delivered to the holdover control logic when a transition into the holdover state occ urs. the pipeline is a guar antee t hat the averaged f value delivered to the holdover control logic has not been interrupted by the transition into the holdover state. the pipeline provides an inherent delay of t = p 2 y + 1 /f s . hence, the dds hold frequency is the average as it appeared t to 2 t seconds prior to entering the holdover state. note that the user has some control over the duration of t because it is dependent on the programmed value of y.
ad9549 rev. d | page 32 of 76 output frequency ran ge control under normal operati ng condit ions, the output frequency is dynamically changing in response to the output of the digital loop filter. the loop filter can steer the dds to any frequency between dc and f s /2 (with 48 - bit resolution). however, the user is given the option of plac ing limits on the tuning range of the dds via two 48 - bit registers in the i/o register map : the ftw upper limit and the ftw lower l imit . if the tuning word input exceeds the upper or lower frequency limit boundaries, the tuning word is clipped to the appro priate value. the default setting for these registers is f s /2 and dc , respectively. the frequency word tuning limits should be used with caution because they may make the digital loop unstable. it may be desirable to limit the output range of the dds to a narrow band of frequencies (for example, to achieve better jitter performance in conjunction with a band pass filter). see the use of narrow -b and filter for high performance section for more information about this feature. 06744-038 dds/dac loop filter phase detector ref in s r external reconstruction filter dds/dac loop filter phase detector ref in s r external reconstruction filter frequency limiter low pass band pass figu re 38 . application of the frequency limiter reconstruction filte r the origin of the output clock signal produced by the ad9549 is the combined dds and dac. the dac output signal appears as a sinusoid sampled at f s . the frequency of the sinusoid is deter - mined by the frequency tuning word (ftw) that appears at the input to the dds. the dac output is typically passed through an external reconstruction filter that serves to remove the artifacts of the sampling process and other spurs outside the filter bandwidth. the signal is then brought back on - chip to be converted to a square wave that is routed internally to the output clock driver or the 2 dll multiplier. because the dac constitutes a sampled system, its output must be filtered so that the analog waveform accurately represents the digital samples supplied to the dac input. the unfiltered dac o utput contains the desired base band signal, which extends from dc to the nyquist frequency (f s /2). it a lso contains images of the base band signal that theoretically extend to infinity. not e that the odd images (shown in figure 39 ) are mirror images of the base band signal. furthermore, the entire dac output spectrum is affected by a sin( x )/x response, which is caused b y the sample - and - hold nature of the dac output signal. the response of the reconstruction filter should preserve the base band signal (i mage 0), while completely rejecting all other images. however, a practical filter implementation typically exhibit s a re latively flat pass band that covers the desired output frequency plus 20%, roll s off as steeply as possible, and then maintain s significant (though not complete) rejection of the remaining images. because the dac output signal serves as the feedback signal for the digital pll, the design of the r econstruction filter can have a significant impact on the overall jitter performance. hence, good filter design and implementation techniques are important for obtaining the best possible jitter results. use of narr ow -b and filter for high performance a distinct advantage of the ad9549 architecture is its ability to constrain the frequency output range of the dds. this allows the user to employ a narrow - band reconstruction filter instead of the low - pass response shown in figure 39, resulting in less jitter on the output. for example, suppose that the nominal output frequency of the dds is 150 mhz. one might then choose a 5 mhz narrow band filter centered at 150 mhz. by using the ad9549 's dds f requency limiting feature, the user can constrain the output frequency to 150 mhz 4.9 mhz (which allows for a 100 khz margin at the pass - band edges). this ensures that a feedback signal is always present for the digital pll. such a design is extremely di fficult to implement with conventional pll architectures. primary signal filter response sin(x)/x envelope spurs image 0 image 1 image 2 image 3 image 4 0 ?20 ?40 ?60 ?80 ?100 magnitude (db) f s /2 f s 3 f s /2 2 f s 5 f s /2 f base band 06744-039 figure 39 . dac spectrum vs. reconstruction filter response
ad9549 rev. d | page 33 of 76 fdbk _in inputs the feedback pins , fdbk_in and fdbk_inb, serve as the input to the feedback path of the digit al pll. typically, these pins are used to receive the signal generated by the dds after it has been band - limited by the external reconstruction filter. a diagram of the fdbk input pins is provided in figure 40, which includes som e of the internal components used to bias the input circuitry. note that the fdbk input pins are internally biased to a dc level of ~1 v. care should be taken to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance. 06744-040 15k? 15k? ~1pf ~1pf to s-divider and clock output section v ss ~1v v ss ~2pf + fdbk_in fdbk_inb figure 40 . differential fdbk inputs reference inputs reference clock receiver the r eference c lock receiver is the point at which the user supplies the input clock signal that the s ynchronizer synthesizes int o an output clock. the clock receiver circuit is able to handle a relatively broad range of input levels as well as frequencies from 8 khz up to 750 mhz. figure 41 is a diagram of the refa and ref b input pins, which includes some of the internal components used to bias the input circuitry. note that the ref input pins are internally biased by a dc source, v b . care should be taken to ensure that any external connections do not disturb the dc bias because such a disturbance may sig n ificantly degrade performance. note that support for redundant reference clocks is achieved by using the two reference clock receivers (refa and refb). 06744-041 8k? 8k? ~1pf ~1pf to reference monitor and switching logic v b v ss + refa_in (or refb_in) refa_inb (or refb_inb) v dd 1pf gnd figure 41 . reference inputs t o accommodate a variety of input signal condit ions , the value of v b is programmable via a pair of bits in the i/o register map . table 6 gives the value of v b for the bit pattern in register 0x040f. table 6 . setting of input bias voltage (v b ) refer ence bias level , register 0x 040f[1:0] v b 00 (default) avdd3 ? 800 mv 01 avdd3 ? 400 mv 10 avdd3 ? 1600 mv 11 avdd3 ? 1200 mv sysclk inputs functional description the sysclk pins are where an external time base is connected to the ad9549 for generating the internal high frequency system clock (f s ). the sysclk inputs can be operated in one of three modes: x sysclk pll bypassed x sysclk pll e na bled with in put signal generated externally x crystal r esonator with sysclk pll enabled a functional diagram of the system clock generator is shown in figure 42. 06744-042 1 0 1 0 1 0 bipolar edge detector 2 2 with crystal resonator 2 2 1 0 2 2 2 sysclk pll enabled with external drive sysclk pll bypassed sysclk pll multiplier 1 0 2 reference frequency doubler (i/o register bit) pd sysclk pll (i/o register bit) dac sample clock loop_filter sysclk sysclkb clkmodesel 2 figure 42 . system clock generator block diagram
ad9549 rev. d | page 34 of 76 the sysclk pll multiplier path is enabled by a logic 0 (default) in the pd sysclk pll bit of the i/o register map . the sysclk pll multiplier can be driven from the sy sclk input pins by one of two means depending on the logic level applied to the 1.8v cmos clkmodesel pin. when clkmodesel = 0, a crystal can be connected directly across the sysclk pins. when clkmodesel = 1, the maintaining amp is disabled, and an external frequency source (oscillator, signal generator, etc.) can be connected directly to the sysclk input pins. note that clkmodesel = 1 does not disable the system clock pll. the maintaining amp on the ad9549 sysclk pins is intended for 25 mhz, 3.2 mm 2.5 mm at cut fundamental mode crystals with a maximum motional resistance of 100 . the following crystals, listed in alphabetical order, meet these criteria (as of the revision date of this data sheet): ? avx/kyocera cx3225sb ? ecs ecx - 32 ? epson/toyocom tsx - 3225 ? fo x fx3225bs ? ndk nx3225sa note that while these crystals meet the preceding criteria according to their data sheets, analog devices , inc. , does not guarantee their operation with the ad9549 , nor does analog devices endorse one supplier of crystals over anoth er. when the sysclk pll multiplier path is disabled, the ad9549 must be driven by a high frequency signal source (500 mhz to 1 ghz). the signal thus applied to the sysclk input pins becomes the internal dac sampling clock (f s ) after passing through an inte rnal buffer. sysclk pll doubler the sysclk pll m ultiplier path offers an optional sysclk pll d oubler. this block comes before the sysclk pll m ultiplier and acts as a frequency doubler by generating a pulse on each edge of the sysclk input signal. the sysc lk pll m ultiplier locks to the falling edges of this regenerated signal. the impetus for doubling the frequency at the input of the sysclk pll m ultiplier is that an improvement in overall phase noise performance can be realized. the main drawback is that the doubler output is not a rectangular pulse with a constant duty cycle even for a perfectly symmetric sysclk input signal. this results in a sub harmonic appearing at the same frequency as the sysclk input signa l, and the magnitude of the sub har - monic can be quite large. when employing the doubler, care must be taken to ensure that the loop bandwidth of the sysclk pll m ultiplier adequately suppress es the su b harmonic. the benefit offered by the doubler depe nds on the magnitude of the sub harmonic, the loop bandwidth of the sysclk pll m ultiplier, and the overall phase noise requirements of the specific application. in many applications, the ad9549 clock output is applied to the input of another pll, and the sub harmonic is often suppressed by the relatively na rrow bandwidth of the downstream pll. note that g enerally, the benefits of the sysclk pll d oubler are realized for sysclk inpu t frequencies of 25 mhz and above. sysclk pll multiplier when the sysclk pll m ultiplier path is employed, the frequency applied t o the sysclk input pins must be limited so as not to exceed the maximum input frequency of the sysclk pll phase detector. a block diagram of the sysclk generator is shown in figure 43 . 06744-043 phase frequency detector charge pump vco 2 n ~2pf (n = 2 to 33) k vco (hi/lo) 2 i cp (125a, 250a, 375a) sysclk pll multiplier loop_filter from sysclk input dac sample clock 1ghz figure 43 . block diagram of the sysclk pll the sysclk pll m ultiplier has a 1 ghz vco at its core. a phase/ frequency detector (pfd) and charge pump provide the steering signal to the vco in typical pll fashion. the pfd operates on the falling edge transi tions of the input signal, which means that the loop locks on the negative edges of the reference signal. the charge pump gain is controlled via the i/o register map by selecting one of three possible constant current sources ranging from 125 a to 375 a in 125 a steps. th e center frequency of the vco is also adjustable via the i/o register map and provides high/low gain selection. the feedback path from vco to pfd consists of a fixed divide - by - 2 prescaler followed by a programmable divide - by - n block, where 2 n 33. this limits the overall divider range to any even integer from 4 to 66, inclusive. the value of n is program med via the i/o register map via a 5 - bit word that spans a range of 0 to 31, but the internal logic automatically adds a bia s of 2 to the value entered, extending the range to 33. care should be taken when choosing these values so as to not exceed the maximum input frequency of the sysclk pll phase detector or sysclk pll d oubler. these values can be found in the ac specifications section .
ad9549 rev. d | page 35 of 76 external loop filter ( sysclk pll) the loop bandwidth of the sysclk pll m ultiplier can be adjusted by means of three external components , as shown in figure 44. the nominal gain of the vco is 800 mhz/v . the recommended co mponent values are shown in table 7 . they establish a loop bandwidth of approximately 1.6 mhz with the charge pump current set to 250 a . the default case is n = 40 and assumes a 25 mhz sysclk input frequency and generates an internal dac sampling frequency (f s ) of 1 ghz. 06744-044 charge pump ~2pf loop_filter c2 r1 c1 external loop filter vco ad9549 ferrite bead avdd 29 26 31 figure 44 . external loop filter for sysclk pll table 7. recommen ded loop filter values for a nominal 1.5 mhz sysclk pll loop bandwidth multiplier r1 series c1 shunt c2 <8 390 ? 1 nf 82 pf 10 470 ? 820 pf 56 p f 20 1 k ? 390 pf 27 p f 40 (default) 2.2 k ? 180 pf 10 pf 60 2.7 k ? 120 pf 5 pf detail of sysclk differe ntial inputs a diagram of the sysclk input pins is provided in figure 45. included are details of the internal components used to bias the input circuitry. these components have a direct effect on the static levels at the sysclk i nput pins. this information is intended to aid in determining how best to interface to the device for a given application. note that the sysclk pll b ypassed and sysclk pll e nabled input paths are internally biased to a dc level of ~1 v. care should be take n to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance. gener ally, it is recommended that the sysclk inputs be ac - coupled to the signal source (except when using a crystal resonator). h armoni c spur reduction the most significant spurious signals produced by the dds are harmonically related to the desired output frequency of the dds. the source of these harmonic spurs can usually be traced to the dac, and the spur level is in the ?60 dbc range. this ratio rep resents a level that is about 10 bits below the full - scale output of the dac (10 bits down is 2 ?10 , or 1/1024). to reduce such a spur require s combining the original signal with a replica of the spur , but offset in phase by 18 0. this idea is the foundation of the technique used to reduce harmonic spurs in the ad9549 . because the d ac has 14 - bit resolution, a ?60 dbc spur can be sy nthesized using only the lower four bits of the dac full - scale range. that is, the 4 lsbs can creat e an output level that is app roximately 60 db below the full - scale level of the dac (commensurate with a ?60 dbc s pur). this fact gives rise to a means of digitally reducing harmonic spurs or their aliased images in the dac output spectrum by digitally add ing a sinusoid at the input of the dac with similar magnitude as the offending spur but shifted in phase to produce destructive interference. 06744-045 500? 500? ~1.5pf ~1.5pf internal clock v ss ~1v v ss ~2pf + sysclk pll bypassed 1k? 1k? ~3pf ~3pf internal clock v ss ~1v v ss ~2pf + sysclk pll enabled amp internal clock crystal resonator with sysclk pll enabled mux sysclk sysclkb figure 45 . differential sysclk inputs although the worst spurs tend to be harmonic in origin, the fact that the dac is part of a sampled system results in the possibility of some harmonic spurs appearing in non harmonic locations in the output s pectrum. for example, if the dac is sampled at 1 ghz and generates an o utput sinusoid of 170 mhz, t he fifth harmonic would nor mally be at 850 mhz. however, because of the sampling process, this spur appears at 150 mhz, only 20 mhz away from the fundamental. hence when attempting to reduce dac spurs , it is important to know the actual location of the har monic spur in the dac output spectrum based on the dac sample rate so that its harmonic number can be reduced.
ad9549 rev. d | page 36 of 76 06744-046 0 1 1 0 14 14 19 19 qd 48 14 dac (14-bit) i-set dds+ dds? 4 9 4 9 8 8 shift 1 0 shift headroom correction harmonic spur cancellation ch1 harmonic number ch1 cancellation phase offset ch2 harmonic number ch2 cancellation phase offset ch1 cancel l ation magnitude ch2 cancellation magnitude ch1 gain ch2 gain spur cancellation enable angle to amplitude conversion dds phase offset 14 48 48-bit accumulator dds 48-bit frequency turning word (ftw) sysclk 2-channel harmonic frequency generator ch1 ch2 figure 46 . spur reduction technique the mechanics of perfo rming harmonic spur reduction are shown in figure 46 . it essentially consists of two additional dds cores operating in parallel with the original dds. this enables the user to reduce two dif ferent harmonic spurs from the second to the 15 th with nine bits of phase offset control ( ) and eight bits of ampli - tude control. the dynamic range of the cancellation signal is further aug - mented by a gain bit associated with each channel. when this bit is set, the magnitude of the cancellation signal is doubled by employing a 1 - bit left - shift of t he data. however, the shift operation reduces the granularity of the cancellation signal magnitude. note that the full - scale amplitude of a cancellation spur is approximately ?60 dbc when the gain bit is a logic 0 and approximately ?54 dbc when the gain bit is a logic 1. output clock drivers and 2 frequency multiplier there are two output drivers provided by the ad9549 . the primary supports differential 1.8 v hstl output level s while the secondary supports either 1.8 v or 3.3 v cmos levels, depending on whether pin 37 is driven at 1.8 v or 3.3 v. the primary differential driver nominally provides an output voltage with 100 load applied differentially (v dd ? v ss = 1.8 v). the source impedance of the driver is approximately 100 for most of the output clock period; during transition between levels, the source impedance reaches a maximum of about 500 . the driver is designed to support output frequencies of up to and beyond the oc - 12 network rate of 622.08 mhz. the output clock can also be powered down by a control bit in the i/o register map . primary 1.8 v differential hstl driver the dds produces a sinusoidal clock signal that is sampled at the system clock rate. this dds outp ut signal is routed off chip , where it is passed through an an alog filter and brought back on chip for buffering and, if necessary, frequency doubling. where possible, for the best jitter performance, it is recommended that the upconverter be bypassed. the 1.8 v hstl output driver should be ac - coupled, with 100 termination at the destination. the driver design has low jitter injection for frequencies in the range of 50 mhz to 750 mhz. r efer to the ac specifications section fo r the exact frequency limits. 2 f requency multiplier the ad9549 can be configured via the i/o register map with an internal 2 delay -l ocked l oop (dll) multiplier at the input of the primary clock driver. the extra octave of frequency gain allows the ad954 9 to provide output clock frequencies that exceed the range available from the dds alone. these settings are found in register 0x 0010 and register 0x0200. the input to the dll consists of the filtered dds output signal after it has been squared up by an in tegrated clock receiver circuit. the dll can accept input frequencies in the range of 200 mhz to 400 mhz.
ad9549 rev. d | page 37 of 76 single-ended cmos output in addition to the high speed differential output clock driver, the ad9549 provides an independent, single-ended output, cmos clock driver. it serves as a relatively low speed (<150 mhz) clock source. the origin of the signal generated by the cmos clock driver is determined by the appropriate control bits in the i/o register map. the user can select one of two sources under program control. one source is the signal generated by the dds after it has been externally filtered and brought back on chip. in this configura- tion, the cmos clock driver generates the same frequency as appears at the output of the dds. note that in this configuration, the dds output frequency must not exceed 50 mhz. the other source is the output of the feedback divider (s-divider). in this configuration, the cmos clock driver generates the same frequency as the input reference after optional prescaling by the r-divider (that is, f cmos = f r /r), which is inherently limited to a maximum of 25 mhz. frequency slew limiter the frequency slew limiting capability enables users to specify the maximum rate of frequency change that appears at the output. the function is programmable via the i/o register map. program control a bit to enable/disable the function (the default condition is disable) and a register that sets the desired slew rate. the frequency slew limiter is located between the digital loop filter and the cci filter, as shown in figure 47. the frequency slew limiter sets a boundary on the rate of change of the output frequency of the dds. the frequency slew limiting constant, k slew , is a 48-bit value stored in the i/o register map. the value of the constant is determined by ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t f f k s p slew io 2 48 2 round where: p io is the value stored in the i/o register map for the p-divider. f s is the dac sample rate. f/t is the desired frequency slew rate limitation. for example, if f s = 1 ghz, p io = 9, and f/t = 5 khz/sec, then ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 29 948 105( )10( 2 round slew k = 721 the resulting slew rate can be calculated as ? ? ? ? ? ? ? ? ? ? io p s slew f k t f 48 2 2 the preceding example yields f/t = 5.003 khz/sec. frequency estimator the frequency estimation function automatically sets the dds output frequency so that the feedback frequency (f dds /s) and the prescaled reference frequency (f ref_in /r) are matched within an error tolerance ( 0 ). its primary purpose is to allow the pll to quickly lock when the reference frequency is not known. the error tolerance is defined as a fractional error and is controlled by a 16-bit programmable value (k) via the i/o register map. the precision of any frequency measurement is dependent on the following two factors: ? the timing resolution of the measurement device (t) ? the duration of the measurement (t meas ) the frequency estimator uses f s as its measurement reference, so t = 1/f s (that is, t = 1 ns for a 1 ghz dac sample rate). the duration of the measurement is controlled by k, which establishes a measurement interval that is k cycles of the measured signal such that t meas = kr/f ref_in . the frequency estimator uses a 17-bit counter to accumulate the number of t periods within the measurement interval. the finite capacity of the counter puts an upper limit on the duration of the measurement, which is constrained to t max = 2 17 /f s . if f s = 1 ghz, this equates to ~131 s. the fact that the measurement time is bounded by t max means there is a limit to the largest value of k (k max ) that can be used without causing the counter to overflow. the value of k max is given by k max = floor ? ? ? ? ? ? ? ? 535,65 where: r s f rf ? r is the modulus of the feedforward divider. f r is the input reference frequency. 06744-047 1 0 frequency slew limit enable frequency slew limiter f/ t slew limit value digital loop filter cci filter to dds p sysclk time to digital converter (phase detector) from ?s?-divider ref in r figure 47. frequency slew limiter
ad9549 rev. d | page 38 of 76 the measurement error ( ) associated with the frequency estimator depends on the choice of the measurement interval parameter (k). these are related by ( ) 1 1 floor ? ? = k k with a specified fractional error ( 0 ), only those values of k for which 0 result s in a frequency estimate that meets the require ments. a plot of vs. k (for a given ) takes on the general form that is shown in figure 48. bounded by envelope 0 0 1 1 2 16 < 0 for some k (k 0 < k < k 1 ) > 0 for all k < k 0 < 0 for all k > k 1 k lo k 0 k hi k 1 k 06744-048 figure 48 . frequency estimator vs. k an iterative technique is necessary to determine the exact values of k 0 and k 1 . however, a closed form exists for a conservative estimate of k 0 (k lo w ) and k 1 (k hi gh ). ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 0 low ? k 1 1 1 ceil ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 0 high ? k 1 1 2 ceil as an example, consider the following system conditions : f s = 400 mhz r = 8 f re f_in = 155.52 mhz 0 = 0.00005 (that is, 50 ppm) these conditions yield k max = 3185, which is the largest k value that can be programmed without causing the frequency estimator counter to overflow. with k = k max , t meas = 163.84 s, and = 30.2 ppm , k max generally (but not alwa ys) yield s the smallest value of , but this comes at the cost of the largest measurement time (t meas ). if the measurement time must be reduced, then k hi gh can be used instead of k max . this yields k hi gh = 1945, t meas = 100.05 s, and = 39.4 ppm. the measurement time can be further reduced (though marginally) by using k 1 instead of k hi gh . k 1 is found by solving the 0 inequality iteratively. to do so, start with k = k hi gh and decrement k successively while evaluating the inequality for each va lue of k. stop the process the first time that the inequality is no longer satisfied a nd add 1 to the value of k thus obtained. the result is the value of k 1 . for the preceding example, k 1 = 1912, t meas = 98.35 s, and = 39.8 ppm. if a further reduction of the measurement time is necessary, k 0 can be used. k 0 is found in a manner similar to k 1 . start with k = k lo w and increment k successively while evaluating the inequality for each value of k. stop the p rocess the first time that the inequality is satisf ied. the result is the value of k 0 . for the preceding example, k 0 = 1005, t meas = 5 1.70 s, and = 49.0 ppm. i f external frequency division exists between th e dac output and the fdbk_in pins , t he frequency estimator should not be used because it will calculate the wrong initial frequency.
ad9549 rev. d | page 39 of 76 06744-049 1 0 1 0 1 0 refab lor refab ool refab invalid refab phase lock frequency lock irq ref invalid phase lock freq. lock ref lor ref ool irq status pin (1 of 4) status pin control register (1 of 4) refa lor refa ool refa invalid refb lor refb ool refb invalid phase lock detect frequency lock detect irq internal status flags figure 49 . status pin c ontrol status and warnings status pins four pins (s1 to s4) are reserved for providing device status information to the external environment. these four pins are individually programmable (via the serial i/o port) as an or' e d combination of six possible status indications. each pin has a dedicated group of control register bits that determine which internal status flags are used to provide an indication on a particular pin , as shown in figure 49. reference monitor status in the ca se of reference monitoring status information, a pin can be programmed for either r ef a or r ef b, but not both. in addition, the or' e d output configuration allows the user to combine multiple status flags into a single status indication. for example, if both the lor and ool control register bits are true, the status pin associated with that particular control register give s an indication if either the lor or ool status flag is asserted for the selected reference (a or b). default dds output frequency on powe r- up the four status pins (s1 to s4) provide a completely separate function at power - up. they can be used to define the output frequency of the dds at power - up even though the i/o registers have not yet been programmed. this is made possible because the s t atus pins are designed wit h bidirectional drivers. at power - up , internal logic initiates a reset pulse of about 10 ns. during this time, s1 to s4 briefly function as input pins and can be driven externally. any logic levels thus applied are transferred to a 4 - bit register on the falling edge of the internally initiated pulse. the falling edge of the pulse also returns s1 to s4 to their normal function as output pins. the same behavior occurs when the reset pin is asserted manually. setting up s1 to s4 for default dds start - up is accomplished by connecting a resistor to each pin (either pull - up or pull - down) to produce the desired bit pattern, yielding 16 possible states that are used both to address an internal 8 16 rom and to select the sysclk m ode (see table 8 ). the rom contains eight 16- bit dds frequency tuning words (ftws), one of which is selected by the state of the s1 to s3 pins. the selected ftw is transferred to the ftw0 register in the i/o register map without the need f or an i/o update . this ensures that the dds generates the selected frequency even if the i/o registers have not been programmed. the state of the s4 pin selects whether the internal s ystem c lock is generated by means of the internal sysclk pll multiplier o r not (see the sysclk inputs section for details).
ad9549 rev. d | page 40 of 76 the dds output frequency listed in table 8 assumes that the internal dac sampling frequency (f s ) is 1 ghz. these frequencies scale 1:1 with f s , meaning that other startup frequencies are available by varying the sysclk frequency. at startup, the internal frequency multiplier defaults to 40 when the xtal/pll m ode is selected via the s tatus p ins. note that when using this mode, the digital pll loop is sti ll open, and the ad9549 is acting as a frequency synthesizer. the frequency dividers and dpll loop filter must still be programmed before closing the loop. table 8. default power -u p frequency options for 1 ghz system clock status pi n sysclk input mode output frequency ( mhz ) s4 s3 s2 s1 0 0 0 0 xtal/pll 0 0 0 0 1 xtal /pll 38.87939 0 0 1 0 xtal /pll 51.83411 0 0 1 1 xtal /pll 61.43188 0 1 0 0 xtal /pll 77.75879 0 1 0 1 xtal /pll 92.14783 0 1 1 0 xtal /pll 122.87903 0 1 1 1 xtal /pll 155.51758 1 0 0 0 direct 0 1 0 0 1 direct 38.87939 1 0 1 0 direct 51.83411 1 0 1 1 direct 61.43188 1 1 0 0 direct 77.75879 1 1 0 1 direct 92.14783 1 1 1 0 direct 122.87903 1 1 1 1 direct 155.51758 interrupt request (irq) any one of the four status pins (s1 to s4) can be programmed as an irq pin. if a status pin is programmed as an irq pin, the state of the internal irq flag appears on that pin. an irq flag is internally generated based on the change of state of any one of the internal st atus flags. the individual status flags are route d to a read - only i/o register (s tatus r egister) so that the user can interrogate the status of any of these flags at any time. furthermore, each status flag is monitored for a change in state. in some cases, only a change of state in one direction is necessary ( for example , the f requency e stimate d one flag), but in most cases, the status flags are monitored for a change of state in either direction (see figure 50 ). whether or not a particular state change is allowed to generate an irq is dependent on th e state of the bits in the irq m ask register. the user programs the mask to enable those events, which are to constitute cause for an irq. if an unmasked event occurs, it trigger s t he irq latch and the irq flag is asserted (active high). the state of the irq f lag is made available externally via one of the programmable status pins (see the status pins section). the automatic assertion of the irq f lag causes the contents of the s tatus r egister to be transferred to the irq status register. the user can then read the irq status r egister any time after the indication of an irq event ( that is , assertion of the irq flag). by noting the bit that is set in the irq register , the cause of the irq event can be determined. once the irq r egister has been read, the user must set the irq r eset bit in the appropriate control register via the serial i/o port. this restores the irq f lag to its default state, clears the irq stat us register, and resets the edge detection logic that monitors the status flags in prepa ration for the next state change . 06744-050 20 qd irq reg. 0 irq edge detect edge detect edge detect edge detect edge detect edge detect edge detect edge detect edge detect edge detect edge detect new ref freq. est. done enter holdover exit holdover phase locked phase unlocked freq. locked freq. unlocked refa lor refa lor refb lor refb lor refa ool refa ool refb ool refb ool refa valid refa invalid refb valid refb invalid status register status flags ref selected (a/b) frequency est. done holdover phase lock frequency lock refa lor refb lor refa ool refb ool refa valid refb valid rst irq reset 11 irq mask register s figure 50 . interrupt request logic
ad9549 rev. d | page 41 of 76 thermal performance table 9 . thermal paramete rs symbol thermal characteristic u sing a jedec51 - 7 p lus jedec51 - 5 2s2p test board value unit ja junction -to -a mbient t hermal r esistance, 0.0 m/s ec air flow p er jedec jesd51 -2 ( s till a ir) 25.2 c/w jma junction -to -a mbient t hermal r esistance, 1.0 m/s ec air flow p er jedec jesd51 -6 ( m oving a ir) 22.0 c/w jma junction -to -a mbient t hermal r esistance, 2.0 m/s ec air flow p er jedec jesd51 -6 ( m oving a ir) 19.8 c/w jb junction -to -b oard t hermal r esistance, 1.0 m/s ec air flow p er jedec jesd51 -8 ( m oving a ir) 13.9 c/w jc junction -to -c ase t hermal r esistance (die - to - heat sink) p er mil - std 883, method 1012.1 1.7 c/w jt junction -to -t op - of -p ackage c haracterization p arameter, 0 m/s ec air flow p er jedec jesd51 -2 ( s till a ir) 0.1 c/w the ad9549 is specified for a case temperature (t case ). to e nsure that t case is not exceeded, an airflow source can be used. u se the following equation t o determine the j unction t empera - ture on the application pcb: t j = t case + ( jt pd ) w here: t j is the j unction temperature (c) . t case is the c ase temperature (c) measured by customer at top center of package . jt is the value f rom table 9 . pd is the p ower dissipation (see the total power dissipation parameter in the specifications section). value s of ja are provided for package comparison and pcb design considerations. ja c an be used for a first - order appr oximation of t j by the equation t j = t a + ( ja pd ) w here t a is the a mbient temperature (c) . value s of jc are provided for package comparison and pcb design considerations when an external heat sink is required. value s o f jb are provided for package comparison and pcb design considerations. the values in table 9 apply to both 64 -lead package options.
ad9549 rev. d | page 42 of 76 power-up power - on reset on initial power - up , it is recommended that the user apply a reset p ulse, at least 75 ns in duration, on pin 59 after both of the following two conditions are met: ? the 3.3 v supply is greater than 2.35 v 0.1 v. ? the 1.8 v supply is greater than 1.4 v 0.05 v. the high - to - low transition of the reset pulse is the active e dge of the pulse and therefore the user is afforded the option of holding reset high during power C up. less than 1 ns after reset goes high, the s1 to s4 configuration pins go high impedance and remain high impedance until reset is deactivated. this allows strapping and configuration during reset. because of this reset sequence, external power supply sequenc - ing is not critical. programming sequence the following sequence should be used when initializing the ad9549 : 1. apply p ower. after the power supplies rea ch a threshold and stabilize, it is recommended that an active high pulse be asserted on the reset pin (pin 59), initiating a hard reset. 2. it is important to be sure that the desired configuration registers have s ingle -t one mode set (r egister 0x 0100, bit 5 ) and that the c lose l oop bit (r egister 0x0100[0]) is cleared. if the c lose l oop bit is set on initial loading, the ad9549 attempt s to lock the loop before it has been configured. 3. when the registered are loaded, the ool ( o ut of limits) and lor (loss of ref erence) ca n be monitored to e nsure that a valid reference signal is present on r efa or r ef b. if a valid reference is present, register 0x 0100 can be reprogrammed to clear s ingle -t one m ode and lock the loop. 4. automatic h oldover mode can then be used to make the ad9549 immune to any disturba nce on the reference inputs. use t he following sequence when changing frequencies in the ad9549 : 1. open the loop and enter single - tone m ode via register 0x0100. 2. enter the new register settings. 3. write 0x 1e to register 0x0012. 4. when the registers are loaded, the ool ( o ut of limits) and lor (loss of reference) ca n be monitored to e nsure that a valid reference signal is present on r ef a or r efb. 5. if a valid reference is present, register 0x 0100 can be repro - grammed to clear s ingle -t one m ode and lock the loop. 6. automatic h oldover mode can then be used to make the ad9549 immune to any disturbance on the reference inputs. note the following: ? attempting to lock the loop without a valid reference can put the ad9549 into a state that re quires a reset, or at a mini mum, writing 0xff to register 0x0012 . ? automatic h oldover mode is not available unless the loop has been successfully closed. ? if the user desires to open and close the loop manually, it is recommended that 0x 1e to be written to register 0x0012 prior to closing the loop again .
ad9549 rev. d | page 43 of 76 power supply partiti oning the ad9549 features multiple power supplies, and their power consumption varies with its configuration. this section covers which power supplies can be gro uped together and how th e consumption of each power block varies with frequency. the numbers quoted here are for comparison only. refer to the specifications section fo r exact numbers. with each group , use bypass capacitors of 1 f in parallel with a 10 f. the recommendations here are for typical applications , and for these applications, there are four groups of power supplies: 3.3 v d igital, 3.3 v a nalog, 1.8 v d igital, and 1.8 v analog. a pplication s demanding the highest perfo rmance may require ad ditional power supply isolation. note that a ll power supply pins must receive power regardless of whether that block is used. 3.3 v supplies dvdd_ i/o (pin 1) and avdd3 (pin 14) although one of these pins is analog and the other is digi tal, these two 3.3 v supplies can be grouped together. the power consumption on pin 1 varies dynamic ally with serial port activity. avdd3 (pin 37) pin 37 is the cmos driver supply. it can be either 1.8 v or 3.3 v, and its power consumption is a function of the output frequency and loading of out_cmos (pin 38). if the cmos driver is used at 3.3 v, this supply should be isolated from other 3.3 v supplies with a ferrite bead to avoid a spur at the output frequency. if the hstl driver is not used, av dd3 (pin 3 7) can be connected (usin g a ferrite bead) to avdd3 (pin 46, pin 47, pin 49). if the hstl driver is used, connect av dd3 (pin 37) to pin 1 and pin 14 , using a ferr ite bead . if the cmos driver is used at 1.8 v, av dd3 (pin 37) can be connected to av dd (pin 36 ). if the cmos driver is not used, av dd3 (pin 37) can be tied directly to the 1.8 v av dd (p in 36) and the cmos drive r powered down using register 0x 0010. avdd3 ( pin 46, pin 47, pin 49) these are 3.3 v dac power supplies that typically consume about 25 ma. at a minimum, a ferrite bead should be used to isolate these from other 3.3 v supplies, with a separate regulator being ideal. 1.8 v supplies dvdd ( pin 3, pin 5, pin 7) these pins should be grouped together and isolated from the 1.8 v avdd supplies. for most applications, a ferrite bead provides sufficient isolation, but a separate regulator may be necessary for applications demanding the highest performance. the c urrent consumption of this group increases from about 160 ma at a system clock of 700 mhz to about 205 ma at a system clock of 1 ghz. there is also a slight (~5%) increase as f out increases from 50 mhz to 400 mhz. avdd (pin 11, pin 19, pin 23, pin 24, pin 36, pin 42, pin 44, and pin 45) these pins can be grouped together and should be isolated fr om other 1.8 v supplies. a separate regulator is recommended. at a minimum, a ferrite bead should be used for isolation. avdd (pin 53) this 1.8 v supply consumes about 40 ma. the supply can be run off the same regulator as 1.8 v avdd group, with a ferrite bead to isolate pin 53 from the rest of the 1.8 v avdd group. however, for applications demanding the highest performance, a separate regulator is recommended. avdd (pin 25, pin 26, pin 29, pin 30) these system clock pll power pins should be grouped togeth er and isolated from other 1.8 v avdd supplies . at a minimum, it is recommended that pin 25 and pin 30 be tied together and isolate d from the aggregate avdd 1.8 v supply with a ferrite bead. likewise, pin 26 and pi n 29 can also be tied together, with a fe rrite bead isolating them from the same aggregate 1.8 v supply. the loop filter for the system clock pll should directly connect to pin 26 and pin 29 (see figure 44). a pplications demanding the highest performance may require tha t these four pins be powered by their own ldo. if the system clock pll is bypassed, the loop filter pin (pin 31) should be pulled down to analog ground using a 1 k resistor. pin 25, pin 26, pin 29, and pin 30 should be included in the large 1.8 v avdd pow er supply group. in this mode, isolation of these pins is not critical, and these pins consume almost no power.
ad9549 rev. d | page 44 of 76 serial control port the ad9549 serial control port is a flexible, synchronous, serial co m munications port that allows an easy interface with m any industry - standard microcontrollers and microprocessors. single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad9549 serial control port can be configured for a single bidirectional i/o pin (sdio only) or for two unid i rectional i/o pins (sdio/sdo). note that m any s erial port operations (such as the frequency tuning w ord update) depend on presence of the dac system clock. serial control port pin descriptions sclk (serial clock) is the serial shift clock. this pin is an input. sclk is used to synchronize serial control port reads and writes. write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. this pin is internally pulled d own by a 30 k ? resistor to ground. the sdio pin (serial data input/output) is a dual - purpose pin that acts as input only or as input/output. the ad9549 defaults to bidirectional pins for i/o. alt ernatively, sdio can be used as a unidirectional i/o pin by writing to the sdo a ctive bit ( register 0x0000 , bit 0 = 1 ). in this case, sdio is the input, and sdo is the output. the sdo (seria l data out) pin is used only in the unidirectional i/o mode ( register 0x 0000, bit 0 = 1 ) as a separate output pin for reading back data. b idirectional i/o mode (using sdio as both input a nd output) is active by default ( the sdo active bit in register 0x00 00, bit 0 = 0 ). the csb (chip select bar) pin is an active low control that gates the read and write cycles. when csb is high, sdo and sdio are in a high impedance state. this pin is internally pulled up by a 100 k ? resistor to 3.3 v. it should not be left floating. see the operation of serial control port section on the use of the csb pin in a communica tion cycle. 06744-051 ad9549 serial control port sclk (pin 64) sdio (pin 63) sdo (pin 62) csb (pin 61) figure 51 . serial control port operation of serial control port framing a communication cycle with csb a communication cycle (a write or a read operation) is gated by the csb line. csb must be brought low to initiate a communica - tion cycle. csb stall high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred ( [ w1:w0 ] must be set to 00, 01, or 10 ; see table 10 ). in these modes, csb can temporarily ret urn high on any byte boundary, allowing time for the system controller to process the next byte. csb can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. during this period, the serial control port s tate machine enters a wait state until all data has been sent. if the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset by either completing the remain ing transfer or by returning the csb low fo r at least one complete sclk cycle (but fewer than eight sclk cycles). raising the csb on a non - byte boundary terminates the serial transfer and flushes the buffer. in the streaming mode ( [ w1:w0 ] = 11 ), any number of data bytes can be transferred in a cont inuous stream. the register address is automatically incremented or decremented (see the msb/lsb first transfers section). csb must be raised at the end of the last byte to be transferred, thereby ending the stream mode. commu nication cycle instruction plus data there are two parts to a communication cycle with the ad9549 . the first part writes a 16 - bit i n struction word into the ad9549 , coincident with the first 16 sclk rising edges. the instruction word provides the ad9549 ser ial control port with information regarding the data transfer, which is the second part of the commu - nication c y cle. the instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data tran s fer, and the starting register address for the first byte of the data transfer. write if the instruction word is for a write operation (i15 = 0 ), the second part is the transfer of data into the serial control port buffer of the ad9549 . the length of the transfer (1, 2, 3 bytes, or streaming mode) is indicated by two bits ( [ w1:w0 ] ) in the instruct ion byte. the lengt h of the transfer indicated by [ w1:w0 ] does not include the 2- byte instruction. csb can be raised after each sequence of eight bits to stall the bus (except af ter the last byte, where it ends the cycle) . when the bus is stalled, the serial transfer resumes when csb is lowered. stalling on non byte boundaries resets the serial control port. there are three types of registers on the ad9549 : buffered, live, and read - only. buffered (also referred to as mirrored) registers require an i /o update to transfer the new values from a temporary buffer on the chip to the actual register and are marked with an m in the type column of the register map . toggling the io_update pin or writing a 1 to the register u pdate bit ( register 0x 00 05, bit 0 ) causes the update to occur. because any number of bytes of data can be changed before issuing an update command, the update simultaneously enables all register changes occurring since any previous update. live registers do not require i/o update and update immediately after being written. read - only registers ignore write commands and are marked ro in the type c olumn of the register map. an ac in this column indi cates that the register is au to clearing.
ad9549 rev. d | page 45 of 76 read if the instruction word i s for a read operation (i15 = 1), the next n 8 sclk cycles clock out the data from the address specified in the instruction word, where n is 1, 2, 3, 4, as determined by [ w1:w0 ]. in this case, 4 is used for st reaming mode where four or more words are tran sferred per read. the data read back is valid on the falling edge of sclk. the default mode of the ad9549 serial control port is bidirec - tional mode, and the data read back appears on the sdio pin. it is possibl e to set the ad9549 to unidirectional mode by writing to the sdo active bit at register 0x 00 00[7] = 0; in that mode, the request ed data appears on the sdo pin. by default, a read request reads the register value that is currently in use by the ad9549 . howe ver, setting register 0x0004[0] = 1 cause s the buffered registers to be read instead. the buffered registers are the ones that take effect during the next i/o update . 06744-052 ad9549 core update registers toggle io_update pin sclk sdio sdo csb serial control port control registers register buffers figure 52 . relationship between serial control port register buffers and control registers of the ad9549 the ad9549 uses register 0x 00 00 to register 0x 0 509. although the ad9549 serial control port allows both 8 - bit and 16 - bit instructions, the 8 - bit i n struction mode provides access to only five address bits ([a4: a0 ]) , which restricts its use to address s pace 0x0000 to address space 0x00 31. the ad9549 de faults to 16- bit instru ction mode on power - up, and 8- bit instruction mode is not supported. the instruction word (16 bits) the msb of the instruction word is r/ w , which indicates whether the instruction is a read or a write. the next two bits, [ w1:w0 ], are the transfer length in bytes. the final 13 bits are the address ([ a12:a0 ] ) at which to begin the read or write operation. for a write, the inst ru c tion word is followed by the number of bytes of data indicated by bits[ w1:w0 ] , which is interpreted according to table 10. bits[ a12:a0 ] select the address within the register map that is written to or read from during the data transfer portion of the communic a tions cycle. the ad9549 uses all of the 13 - bit address space. for multibyte transfers, this addres s is the starting byte address. table 10 . byte transfer count w1 w0 bytes to transfer (excluding th e 2- byte instruction) 0 0 1 0 1 2 1 0 3 1 1 streaming mode msb/lsb first transf ers the ad9549 instruction word and byte data may be msb first or lsb first. the default for the ad9549 is msb first. the lsb first mode can be set by writing a 1 to regist er 0x 00 00[ 6] and requires that an i/o u pdate be executed. immediately after the lsb first bit is set, all serial control port operations are changed to lsb first order. when msb first mode is active, the instruction and data bytes must be written from msb to lsb. multibyte data transfers in msb first format start with an i n struction byte that includes the register address of the most significant data byte. subsequent data bytes must follow in order from high address to low address. in msb first mode, the se rial control port internal address generator decrements for each data byte of the multibyte transfer cycle. when lsb f irst = 1 (lsb first), the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb first format start with an i n struction byte that includes the register address of the least si g nificant data byte followed by multiple data bytes. the serial control port inte r nal byte address generator increments for each byte of the multibyte transfer cycle. the ad9549 ser ial control port register address decrements from the register a ddress just written toward 0x0000 for multi - byte i/o operations if the msb fir st mode is active (default). if the lsb first mode is a c tive, the serial control port register address increments from the address just written toward 0x 1fff for multibyte i/o operations. unused address es are not skipped during multibyte i/o operations . the user should write the default value to a reserved register and should write only 0 s to unmapped registers. note that i t is more efficient to issue a new write command than to write the default value to more than two consecutive re served (or unmapped) registers.
ad9549 rev. d | page 46 of 76 table 11. serial control port, 16 - bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 06744-053 csb sclk don't care sdio a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) d at a register (n ? 1) d at a figure 53 . serial control port write msb first , 16 - bit instruction, two bytes data cs sclk sdio sdo register (n) data 16-bit instruction header register (n ? 1) data register (n ? 2) data register (n ? 3) data a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 06744-060 fi gure 54 . serial control port read msb first, 16 - bit instruction, four bytes data 06744-055 t s don't care don't care w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 d4 d3 d2 d1 d0 don't care don't care r/w t ds t dh t hi t lo t clk t h csb sclk sdio figure 55 . serial control port write msb first, 16 - bit instruction, timing measurements 06744-056 dat a bit n ? 1 dat a bit n csb sclk sdio sdo t dv figure 56 . timing diagram for serial control port register read 06744-057 csb sclk don't care don't care 16-bit instruction header register (n) d at a register (n + 1) d at a sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/w w1w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 figure 57 . serial control port write lsb first, 16 - bit instruction, two bytes data
ad9549 rev. d | page 47 of 76 06744-058 csb sclk sdio t hi t lo t clk t s t ds t dh t h bit n bit n + 1 figure 58 . serial control port timing write table 12 . definitions of terms used in serial control port timing diagrams parameter description t clk period of sclk t dv read d ata v alid t ime ( t ime from falling edge of sclk to valid data on sdio/sdo) t ds setup time between data and rising edg e of sclk t dh hold time between data and rising edge of sclk t s setup time between csb and sclk t h hold time between csb and sclk t hi minimum period that sclk should be in a logic high state t lo minimum period that sclk should be in a logic low state
ad9549 rev. d | page 48 of 76 i/o register map all address and bit locations that are left blank in table 13 are unused. accessing reserved registers should be avoided. in cases where some of the bits in register are reserved, the user can rely on the default value in the i/o register map and write the same value back to the reserved bits in that register. table 13 . addr (hex) type 1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default (hex) serial port configuration and part i dentification 0x0000 serial config. sdo active lsb first (buffered) soft reset long inst. long inst . soft reset lsb first (buffered) sdo active 0x18 0x0001 reserved reserved 0x0002 ro part id part id 0x82 0x0003 ro 0x09 0x0004 serial options read buffer register 0x00 0x0005 ac register u pdate 0x00 power - down and r eset 0x0010 power - d own and enable pd hstl driver enable cmos driver enable output doubler pd sysclk pll pd refa pd refb full pd digital pd 0x00 0x0011 reserved reserved 0x0012 m, ac reset history reset irq reset fpfd reset cpfd reset lf reset cci reset dds reset 0x00 0x0013 m pd f und dds s-d iv / 2 reset r-d iv / 2 reset s- divider reset r- divider reset 0x00 system clock 0x0020 n- divider n-d ivider , bits [4:0] 0x12 0x0021 reserved reserved 0x0022 pll parameters vco auto range 2 reference vco range charge pump c urrent , bits [1:0] 0x04 0x0023 pfd divider pfd d ivider , bits [3:0] (relationship between sysclk and pfd clock) 0x0 5 dpll 0x 0 100 m pll control reserved single - tone mode disable freq. estimator enable freq. slew limiter reserved loop polarity close loop 0x30 0x0101 r- divider r-d ivider , bits [15:0] 0x00 0x0102 0x00 0x0103 falling edge triggered reserved r- divid er/2 0x00 0x0104 s- divider s-d ivider , bits [15:0] 0x00 0x0105 0x00 0x0106 falling edge triggered reserved s- divider/2 0x00 0x0107 m p- divider p- divider , bits [4:0] 0x05
ad9549 rev. d | page 49 of 76 addr (hex) type 1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default (hex) 0x0108 m loop coefficients alpha -0 , bits [7:0] 0x00 0x0109 m alpha -0 , bits [11:8] 0x00 0x010a m alpha -1 , bits [4:0] 0x00 0x010b m alpha -2 , bits [2:0] 0x00 0x010c m beta -0 , bits [7:0] 0x00 0x010d m beta -0 , bits [11:8] 0x00 0x010e m beta -1 , bits [2:0] 0x00 0x010f m gamma -0 , bits [7:0] 0x00 0x0110 m gamma -0 , bits [11:8] 0x00 0x0111 m gamma -1 , bits [2:0] 0x00 0x0112 reserved 0x00 0x0113 0x00 0x0114 0x00 0x0115 ro ftw estimate ftw e stimate , bits [47:0] (read only) lsb: register 0x0115 n/a 0x0116 ro n/a 0x0117 ro n/a 0x0118 ro n/a 0x0119 ro n/a 0x011a ro n/a 0x011b m ftw limits ftw lower l imit , bits [47:0] lsb: register 0x011b 0x00 0x011c m 0x00 0x011d m 0x00 0x011e m 0x00 0x011f m 0x00 0x0120 m 0x00 0x0121 m ftw upper l imit , bits [47:0] lsb: register 0x0121 0xff 0x0122 m 0xff 0x0123 m 0xff 0x0124 m 0xff 0x0125 m 0xff 0x0126 m 0x7f 0x0127 m slew limit frequency slew l imit , bits [47:0] lsb: register 0x0127 0x00 0x0128 m 0x00 0x0129 m 0x00 0x012a m 0x00 0x012b m 0 x00 0x012c m 0x00 0x012d reserved reserved 0x012e 0x012f 0x0130 free - run mode 0x01a0 reserved reserved 0x01a1 0x01a2 0x01a3 0x01a4 0x01a5
ad9549 rev. d | page 50 of 76 addr (hex) type 1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default (hex) 0x01a6 m ftw0 (open - loop frequency tuning word) ftw0 , bits [47:0] ls b: register 0x01a6 0x00 0x01a7 m 0x00 0x01a8 m 0x00 0x01a9 m 0x00 0x01aa m startup cond. 0x01ab m startup cond. 0x01ac and 0x01ad m phase (open loop only) dds phase w ord , bits [15:0] 0x00 reference selector/holdover 0x01c0 m automatic cont rol holdover mode reserved automatic selector automatic recover automatic holdover 0x00 0x01c1 m override enable line card mode enable ref input override ref_ab enable holdover override holdover on/off 0x00 0x01c2 averaging window ftw w indowed average size , bits [3:0] 0x00 0x01c3 reference validation reserved validation timer , bits [4:0] 0x00 doubler and output drivers 0x0200 hstl driver opol (polarity) reserved hstl output doubler , bits [1:0] 0x05 0x0201 cmos driver cmos mux 0x00 monitor 0x0300 ro status reserved pfd f req. too high pfd freq . too low freq. est. done ref selected free run ph. lock detected freq. lock detected n/a 0x0301 ro reserved refa valid refa lor refa ool refb valid refb lor refb ool n/a 0x0302 ro irq status pfd freq. too high pfd freq. too low freq. est. done ref selected free run phase lock detected freq. lock detected 0x00 0x0303 ro refa valid refa lor refa ool refb valid refb lor refb ool 0x00 0x0304 irq mask reserved ref changed le ave free run enter free run 0x00 0x0305 freq. e st. done phase unlock phase lock freq. unlock freq. lock 0x00 0x0306 reserved refa valid !refa valid refa lor !refa lor refa ool !refa ool 0x00 0x0307 reserved refb valid !refb valid refb lor !r efb lor refb ool !refb ool 0x00 0x0308 s1 p in config ref? ref? lor ref? ool ref? not valid phase lock freq. lock reserved irq 0x60 0x0309 s2 p in config ref? ref? lor ref? ool ref? not valid phase lock freq. lock reserved irq 0xe0 0x030a s3 p in config ref? ref? lor ref? ool ref? not valid phase lock freq. lock reserved irq 0x08 0x030b s4 p in config ref? ref? lor ref? ool ref? not valid phase lock freq. lock reserved irq 0x01 0x030c control enable refa lor enable refa ool enable refb lor enable refb ool enable phase lock det. enable frequency lock det . 0xa2
ad9549 rev. d | page 51 of 76 addr (hex) type 1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default (hex) 0x030e ro hftw average or i nstantaneous ftw , bits [47:0] (r ead only) lsb: register 0x030e (an i/o update is required to refresh these registers.) n/a 0x030f ro n/a 0x0310 ro n/a 0x031 1 ro n/a 0x0312 ro n/a 0x0313 ro n/a 0x0314 m phase lock phase lock detect t hreshold , bits [31:0] 0xff 0x0315 m 0x00 0x0316 m 0x00 0x0317 m 0x00 0x0318 m phase unlock watchdog timer , bits [2:0] phase lock watchdog t imer , bits [4:0] 0xf f 0x0319 m frequency lock frequency lock detect t hreshold , bits [31:0] 0x00 0x031a m 0x00 0x031b m 0x00 0x031c m 0x00 0x031d m frequency unlock watchdog t imer , bits [2:0] frequency lock watchdog t imer , bits [4:0] 0xff 0x031e m loss of reference refa lor d ivider , bits [15:0] 0xff 0x031f m 0xff 0x0320 m refb lor d ivider , bits [15:0] 0xff 0x0321 m 0xff 0x0322 m reference out of limits refa ool d ivider , bits [15:0] 0x00 0x0323 m 0x00 0x0324 m refa ool upper l imit , bits [31:0] 0xff 0x032 5 m 0xff 0x0326 m 0xff 0x0327 m 0xff 0x0328 m refa ool lower l imit , bits [31:0] 0x00 0x0329 m 0x00 0x032a m 0x00 0x032b m 0x00 0x032c m refb ool d ivider , bits [15:0] 0x00 0x032d m 0x00 0x032e m refb ool upper l imit , bits [31:0] 0xff 0x032f m 0xff 0x0330 m 0xff 0x0331 m 0xff 0x0332 m refb ool lower l imit , bits [31:0] 0x00 0x0333 m 0x00 0x0334 m 0x00 0x0335 m 0x00
ad9549 rev. d | page 52 of 76 addr (hex) type 1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default (hex) calibration (user - accessible trim) 0x0400 k- divider k-d ivider , bits [15:0] 0x01 0x0401 0x00 0x0402 m cpfd gain cpfd gain s cale , bits [2:0] 0x00 0x0403 m cpfd g ain , bits [5:0] 0x20 0x0404 fpfd g ain fpfd g ain , bits [7:0] 0xc8 0x0405 reserved reserved 0x0406 ro part version part version part version reserved 0x00 or 0x40 0x040 7 reserved reserved 0x0408 0x0409 m pfd offset dpll phase o ffset , bits [7:0] 0x00 0x040a m dpll phase o ffset , bits [13:8] 0x00 0x040b dac full - scale current dac full - scale c urrent , bits [7:0] 0xff 0x040c dac full - scale current , bits [9:8 ] 0x01 0x040d reserved reserved 0x040e reserved reserved 0x10 0x040f reference bias level dc input l evel , bits [1:0] 0x00 0x0410 reserved reserved harmonic spur reduction 0x0500 m spur a hsr - a enable amplitude gain 2 reserved spur a harmonic , bits [3:0] 0x00 0x0501 m spur a m agnitude , bits [7:0] 0x00 0x0502 m 0x00 0x0503 m spur a p hase , bits [7:0] 0x00 0x0504 m spur a p hase , bit 8 0x00 0x0505 m spur b hsr - b enable amplitude gain 2 reserved spur b harmonic[3:0] 0x00 0x0506 m spur b m agnitude , bits [7:0] 0x00 0x0507 m 0x00 0x0508 m spur b p hase , bits [7:0] 0x00 0x0509 m spur b p hase , bit 8 0x00 1 types of registers: ro = read - only, ac = autoclear, m = mirrored (also called buffered). a mirrored register needs an i/o update for the new value to take effect.
ad9549 rev. d | page 53 of 76 i/o register descrip tion s serial port configur ation ( reg ister 0x 0000 to reg ister 0x 0005) register 0x0000 s erial configuration table 14. bit s bit name description [ 7: 4] these bi t s are the mirror image of bits[3: 0 ]. 3 long i nstruction read -o nly. the ad9549 supports only long instructions. 2 soft r eset resets register map, except for register 0x0000. setting this bit forces a soft reset, meaning that s1 to s4 are not tristated, nor is their state read when this bit is cleared. the ad9549 assumes the values of s1 to s4 that were present during the last hard reset. this bit is not self -c learing, and all other registers are restored to their default values after a soft reset. 1 lsb f irst sets bit order for serial port. 1 = lsb first. 0 = msb first. i/o update must occur for msb first to take effect. 0 sdo a ctive enables sdo p in. 1 = sdo pin enabled (4 - wire serial port mode). 0 = 3 - wire mode. register 0x0001 reserved register 0x 0002 and register 0x0003 part id ( r ead o nly) register 0x 0004 serial options table 15. bit s bit name description 0 read buffer r egister fo r buffe red registers, serial port read back r eads from actual (active) registers instead of the buffer. 1 = reads the buffered values that take effect during the next i/o update . 0 = reads values that are currently in effect. register 0x0005 serial option s ( self -clearing) table 16. bit s bit name description 0 register u pdate software access to the register update pin function. writing a 1 to this bit is identical to performing an i/o update . power - down and reset (reg ister 0x 0010 to reg ister 0x 0013) register 0x0010 power - down and enable power - up d efault is d efined by the startu p p ins. table 17. bit s bit name description 7 pd hstl d river power down hstl output driver. 1 = hstl driver powered down. 6 enabl e cmos d river power up cmos output driver. 1 = cmos driver on. 5 enable output doubler power up output clock generator doubler. output doubler must still be en abled in register 0200 . 4 pd sysclk pll system clock multiplier power - down. 1 = system clock multiplier powered down. 3 pd refa power - down reference clock a input (and related circuits). 2 pd refb power - down reference clock b input (and related circuits). 1 full pd setting this bit is ide ntical to activating the pd pin and puts all blocks (exce pt serial port) into power - down mode. sysclk is turned off. 0 digital pd remove clock from most of digital section; leave serial port usable. in contrast to full pd, setting this bit does not debias inputs, allowing for quick wake - up.
ad9549 rev. d | page 54 of 76 register 0x0011 res erved register 0x0012 reset ( auto clear) to reset the entire chip, the user can also use the (non self - clearing) soft r eset bit in register 0x 0000. except for irq reset, the user normally would not need to use this bit . however, if the user attempts to lock the loop for the first time when no signal is p resent, the user should write 1 to b its [4:0] of this register before attempting to lock the loop again. table 18. bit s bit name description 7 history r eset setting this bit clears the ftw monitor and pipeline. 6 reserved reserved . 5 irq r eset clear irq signal and irq status monitor. 4 fpfd r eset fine phase frequency detector reset. 3 cpfd r eset coarse phase frequency detector reset. 2 lf r eset loop filter reset. 1 cci r eset casca ded comb integrator reset. 0 dds r eset direct digital synthesis reset. register 0x0013 reset ( c ontinued) ( not auto clear) table 19. bit s bit name description 7 pd f und dds setting this bit powers down the dds fundamental output b ut does not power down the spurs. it is used during tuning of the s pur k iller circuit. 3 s-d iv / 2 r eset asynchronous reset for s prescaler . 2 r-d iv / 2 r eset asynchronous reset for r prescaler . 1 s- divider r eset synchronous (to s - divider prescaler output) reset for integer divider. 0 r- divider r eset synchronous (to r - divider prescaler output) reset for integer divider. system clock (reg ister 0x 0020 to reg ister 0x 0023) register 0x0020 n- divider table 20. bit s bit name description [ 4: 0] n-d ivider these bits set the feedback divider for system clock pll. there is a fixed/2 preceding this block, as well as an offset of 2 added to this value. therefore, setting this register to 00000 translates to an overall feedback divider ratio of 4. see figure 43 . register 0x0021 reserved register 0x0022 pll parameters table 21. bit s bit name description 7 vco auto r ange automatic vco range selection. enabling this bit allows bit 2 of this registe r to be set automatically. [6:4] reserved reserved 3 2 r eference enables a frequency doubler prior to the sysclk pll and can be useful in reducing jitter induced by the sysclk pll. see figure 42 . 2 vco r ange select low range o r high range vco. 0 = low range (700 mhz to 81 0 mhz). 1 = high range (900 mhz to 1000 mhz). for system clock settings between 810 mhz and 900 mhz, use the vco auto range (bit 7) to set the correct vco range automatically. [ 1: 0] charge pump c urrent charg e pump current. 00 = 250 a. 01 = 375 a. 10 = off. 11= 125 a.
ad9549 rev. d | page 55 of 76 register 0x0023 pfd divider table 22. bit s bit name description [ 3: 0] pfd d ivider divide ratio for pfd clock from system clock. this is typically varied only in cases where the designer wishes to run the dpll phase detector fast while sysclk is run relatively slowly. the ratio is equal to pfd d ivider 4. for a 1 ghz system clock, the adc runs at 1 ghz/20 = 50 mhz, and the dpll phase d etector runs at half this speed , which , in this case , is 25 mhz. digital pll control and dividers (reg ister 0x 0100 to reg ister 0x0130) register 0x0100 pll control table 23. bit s bit name description [ 7: 6] reserved reserved 5 single - tone m ode setting this bit allows the ad9549 to output a tone open loop using ftw0 as dds tuning word. this b it must be cleared when bit 0 (close loop) is set. this is very useful in debugging when the signal coming into the ad9549 is questionable or nonexistent. 4 disabl e frequency estimator the frequency estimator is normally not used but is useful when the input frequency is unknown or needs to be qualified. this estimate appears in register 0x 0115 to register 0x 011a. the frequency estimator is not needed when ftw0 (reg ister 0x 01a6 to register 0x 01ab) is programmed. see the frequency estimator section. 3 enable frequency slew l imiter this bit enables the frequency slew limiter that controls how fast the tuning word can change and is useful for avoiding runt and stretched pulses during clock switchover and holdover transitions. these values are set in register 0x 0127 to register 0x 012c. see the frequency slew limiter section. 2 reserved reserved. 1 loop p olarity this b it reverses the polarity of the loop response. 0 close l oop setting this bit closes the loop. if bit 4 of this register is cleared, the frequency estimator is used. if this bit is cleared and the loop is opened, reset the cci and lf bits of register 0x0012 before closing the loop again. a valid input reference signal must be present the first time the loop is closed. if no input signal is present during the first time the loop is closed, the user must reset the digital pll blocks by writing 0xff to registe r 0x0012 before attempting to close the loop again. register 0x0101 r- divider (dpll feedforward divider) table 24. bit s bit name description [7:0] r-d ivider feedforward divider (also called the reference divider) of the dpll. div ide ratio = 1 ? 65, 536. see the feedforward divider (divide -by - r) section. if the desired feedforward ratio is greater than 65 , 536, or if the reference input signal on refa or refb is greater than 400 mhz, bit 0 of register 0x 0103 must be set. note that the actual r - divider is the value in this register plus 1; to have an r - divider of 1 , register 0x 0101 and register 0x 0102 must both be 0x00. register 0x 0101 is the least significant byte. register 0x0102 r- divider (dpll feedforward divider) (con tinued) table 25. bit s bit name description [15 :8] r-d ivider feedforward divider (also called the reference divider) of the dpll. divide ratio = 1 ? 65 ,536. see the feedforward divider (divide -by - r) section. if the desired feedforward ratio is greater than 65 , 536, or if the reference input signal on refa or refb is greater than 400 mhz, bit 0 of register 0x 0103 must be set. note that the actual r - divider is the value in this register plus 1; to have an r - divider of 1 , register 0x 0101 and register 0x 0102 must both be 0x00. register 0x 0101 is the least significant byte. register 0x0103 r- divider ( c ontinued) table 26. bit s bit name description 7 falling edge t riggered setting this bit inverts the reference clock before the r- divider. [ 6: 1] reserved reserved. 0 r-d ivider/2 setting this bit enables an additional /2 prescaler, effectively doubling the ra nge of the feedforward divider. if the desired feedforward ratio is greater than 65 , 536, or if the refer ence input signal on refa or ref b is greater than 400 mhz, then this bit must be set.
ad9549 rev. d | page 56 of 76 register 0x0104 s- divider (dpll feedback divider) table 27. bit s bit name description [7:0] s-d ivider feedback divider. divide ratio = 1 ? 65, 536. if the desired feedback ratio is greater than 65 , 536, or if the feedback signal on fdbk_in is g reater than 400 mhz, then bit 0 of register 0x 0106 must be set. note that the actual s - divider is the value in this register plus 1 , so to have an r - di vider of 1 , register 0x 0104 and register 0x 0105 must both be 0x00. register 0x 0 104 is the least significant byte. register 0x0105 s- divider (dpll feedback divider) (continued) table 28. bit s bit name description [15:8 ] s-d ivider feedback divider. divide ratio = 1 ? 65, 536. if the desired feedback ratio is greater than 65 , 536, or if the feedback signal on fdbk_in is g reater than 400 mhz, then bit 0 of register 0x 0106 must be set. note that the actual s - divider is the value in this register plus 1 , so to have an r - di vider of 1 , register 0x 0104 and register 0x 0105 must both be 0x00. register 0x 0 104 is the least significant byte. register 0x0106 s- divider (dpll feedback divider) (c ontinued) table 29. bit s bit name description 7 falling edge t r iggered setting this bit inverts the reference clock before s - divider. [ 6: 1] reserved reserved. 0 s-d ivider/2 setting this bit enables an additional /2 prescaler. see the feedback divider (divide -by -s) section. if the desired fe edback ratio is greater than 65 , 536, or if the feedback signal on fdbk_in is greater than 400 mhz, then this bit must be set. an example of this case is when the pll is locking to an image of the dac output that is above the nyquist frequency. register 0x0107 p- divider table 30. bit s bit name description [4:0] p-d ivider divide ratio . controls the ratio of dac sample rate to loop filter sample rate. see the digital loop filter section. loop filter sample r ate = dac sample rate/ 2^( d ivide r atio[4:0]). for the default case of 1 ghz dac sample rate, and p - divider [4:0] of 5, the loop filter sample rate is 31.25 mhz. note that t he dac sample rate is the same as s ystem c lock. register 0x0108 loop coefficients se e the digital loop filter coefficients section . note that t he ad9549 evaluation sof tware derive s these values. table 31. bit s bit name description [7:0] alpha -0 linear coefficient for alpha coefficient . register 0x 0109 loop coefficients (continued) table 32. bits bit name description [11 :8] alpha -0 linear coefficient for alpha coefficient .
ad9549 rev. d | page 57 of 76 register 0x010a loop coefficients ( c ontinued) table 33. bit s bit name description [4:0] alpha -1 power - of - 2 multiplier for alpha coefficient . register 0x010b loop coefficients ( c ontinued) table 34. bit s bit name description [2:0] alpha -2 power - of - 2 divider for alpha coefficient . register 0x01 0c loop coefficients ( c ontinued) table 35. bit s bit name description [7:0] beta -0 linear coefficient for beta coefficient . register 0x010d loop coefficients ( c ontinued) table 36. bit s bit name description [ 11:8 ] beta -0 linear coefficient for beta coefficient . register 0x010e loop coefficients ( c ontinued) table 37. bit s bit name description [2:0] beta -1 power - of - 2 divider for beta coefficient . register 0x010f loop coefficients ( c ontinued) table 38. bit s bit name description [7:0] gamma -0 linear coefficient for gamma coefficient . register 0x0 110 loop coefficients ( c ontinued) table 39. bit s bit name description [11:8 ] gamma -0 lin ear coefficient for gamma coefficient . register 0x0111 loop coefficients ( c ontinued) table 40. bit s bit name description [2:0] gamma -1 power - of - 2 divider for gamma coefficient . register 0x0112 to register 0x0114 reserved
ad9549 rev. d | page 58 of 76 registe r 0x0115 ftw estimate (read only) table 41. bit bit name description [7:0] ftw e stimate this frequency estimate is from the frequency estimator circuit and is informational only. it is useful for verifying the input reference frequency. see the frequency estimator section for a description. register 0x0116 ftw estimate (read only) (continued) table 42. bit bit name description [15:8 ] ftw e stimate this frequency estimate is from t he frequency estimator circuit and is informational only. it is useful for verifying the input reference frequency. see the frequency estimator section for a description. register 0x0117 ftw estimate (read only) (continued) table 43. bit bit name description [23:16 ] ftw e stimate this frequency estimate is from the frequency estimator circuit and is informational only. it is useful for verifying the input reference frequency. see the frequency estimator section for a description. register 0x0118 ftw estimate (read only) (continued) table 44. bit bit name description [31:24 ] ftw e stimate this frequency estimate is from the frequency estimator circuit and i s informational only. it is useful for verifying the input reference frequency. see the frequency estimator section for a description. register 0x0119 ftw estimate (read only) (continued) table 45. bit bi t name description [39 : 32 ] ftw e stimate this frequency estimate is from the frequency estimator circuit and is informational only. it is useful for verifying the input reference frequency. see the frequency estimator section for a description. register 0x011a ftw estimate (read only) (continued) table 46 . bit bit name description [4 7: 40 ] ftw e stimate this frequency estimate is from the frequency estimator circuit and is informational only. it is useful fo r verifying the input reference frequency. see the frequency estimator section for a description.
ad9549 rev. d | page 59 of 76 register 0x011b ftw lower limit table 47. bit s bit name description [7:0] ftw lower l imit l owest dds tuni ng word in closed - loop mode. this feature is recommended when a band - pass reconstruction filter is used. see the output frequency range control section. register 0x011c ftw lower limit (continued) table 48. bit s bit name description [15:8 ] ftw lower l imit l owest dds tuning word in closed - loop mode. this feature is recommended when a band - pass reconstruction filter is used. see the output frequency range control section. register 0x011d ftw lower limit (continued) table 49. bit s bit name description [23:16 ] ftw lower l imit l owest dds tuning word in closed - loop mode. this feature is recommended when a band - pass reconstruction filter is used. see the output frequency range control section. register 0x01 1e ftw lower limit (continued) table 50. bit s bit name description [31:24 ] ftw lower l imit l owest dds tuning word in closed - loop mode. this feature is recom mended when a band - pass reconstruction filter is used. see the output frequency range control section. register 0x01 1f ftw lower limit (continued) table 51. bit s bit name description [39:32 ] ftw lower l i mit l owest dds tuning word in closed - loop mode. this feature is recommended when a band - pass reconstruction filter is used. see the output frequency range control section. register 0x 0120 ftw lower limit (continued) table 52. bit s bit name description [47: 40] ftw lower l imit l owest dds tuning word in closed - loop mode. this feature is recommended when a band - pass reconstruction filter is used. see the output frequency range control section.
ad9549 rev. d | page 60 of 76 register 0x0121 ftw upper limit table 53. bit s bit name description [7:0] ftw u pper l imit highest dds tuning word in closed - loop mode. this feature is recommended when a band - pass reconstruction filter is used. see th e output frequency range control section. register 0x 0122 ftw upper limit (continued) table 54. bit s bit name description [15:8 ] ftw upper l imit highest dds tuning word in closed - loop mode. this feature is recommended when a band - pass reconstruction filter is used. see the output frequency range control section. register 0x0123 ftw upper limit (continued) table 55. bit s bit name description [23:16 ] ftw upper l imit highest dds tuning word in closed - loop mode. this feature is recommended when a band - pass reconstruction filter is used. see the output frequency range control section. register 0x0124 ftw upper limit (continued) ta ble 56. bit s bit name description [31:24 ] ftw upper l imit highest dds tuning word in closed - loop mode. this feature is recommended when a band - pass reconstruction filter is used. see the output frequency range control section. register 0x0125 ftw upper limit (continued) table 57. bit s bit name description [39:32 ] ftw upper l imit highest dds tuning word in closed - loop mode. this feature is recommended when a band - pass reconstruc tion filter is used. see the output frequency range control section. register 0x 0126 ftw upper limit (continued) table 58. bit s bit name description [ 47:40] ftw upper l imit highest dds tuning word in clo sed - loop mode. this feature is recommended when a band - pass reconstruction filter is used. see the output frequency range control section. register 0x0127 to register 0x012c frequency slew limit table 59 . bit s bit name description [ 47 :0] frequency slew l imit see the frequency slew limiter section. register 0x012d to register 0x0130 reserved
ad9549 rev. d | page 61 of 76 free - run (single - tone) mode (reg ister 0x 01a0 to reg ister 0x 01ad) register 0x01a0 to regi ster 0x01a5 reserved register 0x 01a6 ftw0 (frequency tuning word) table 60. bit bit name description [7:0] ftw0 f tw ( f requency t uning w ord) for dds when the loop is not closed (see register 0x0100 , bit 0) . also used as the initia l frequency estimate when the estimator is disabled (see register 0x0100 , bit 4) note that t he power - up default is defined by the startup of pin s1 to pin s4 (s ee the default dds output frequency on power -up section ). updates to the ftw results in an instantaneous frequency jump but no phase discontinuity. register 0x01a7 ftw0 (frequency tuning word) (continued) table 61. bit bit name description [15:8 ] ftw0 f tw ( f requency t uning w ord) for dds when th e loop is not closed (see register 0x0100 , bit 0) . also used as the initial frequency estimate when the estimator is disabled (see register 0x0100 , bit 4) note that t he power - up default is defined by the startup of pin s1 to pin s4 (s ee the default dds output frequency on power -up section). updates to the ftw results in an instantaneous frequency jump but no phase discontinuity. register 0x01a8 ftw0 (frequency tuning word) (continued) table 62. bit bit name description [23:16 ] ftw0 f tw ( f requency t uning w ord) for dds when the loop is not closed (see register 0x0100 , bit 0) . also used as the initial frequency estimate when the estimator is disabled (see register 0x0100 , bit 4) note that t he power - up default is defined by the startup of pin s1 to pin s4 (s ee the default dds output frequency on power -up section). updates to the ftw results in an instantaneous frequency jump but no phase discontinuity. register 0x01a9 ftw0 (fr equency tuning word) (continued) table 63. bit bit name description [31:24 ] ftw0 f tw ( f requency t uning w ord) for dds when the loop is not closed (see register 0x0100 , bit 0) . also used as the initial frequency estimate when the estimator is disabled (see register 0x0100 , bit 4) note that t he power - up default is defined by the startup of pin s1 to pin s4 (s ee the default dds output frequency on power -up section). updates to the ftw results in an instant aneous frequency jump but no phase discontinuity. register 0x01aa ftw0 (frequency tuning word) (continued) table 64. bit bit name description [39:32 ] ftw0 f tw ( f requency t uning w ord) for dds when the loop is not closed (see regis ter 0x0100 , bit 0) . also used as the initial frequency estimate when the estimator is disabled (see register 0x0100 , bit 4) note that t he power - up default is defined by the startup of pin s1 to pin s4 (s ee the default dds outpu t frequency on power -up section). updates to the ftw results in an instantaneous frequency jump but no phase discontinuity. register 0x01ab ftw0 (frequency tuning word) (continued) table 65. bit bit name description [4 7: 40] ftw0 f tw ( f requency t uning w ord) for dds when the loop is not closed (see register 0x0100 , bit 0) . also used as the initial frequency estimate when the estimator is disabled (see register 0x0100 , bit 4) note that t he power - up default is defined by the startup of pin s1 to pin s4 (s ee the default dds output frequency on power -up section). updates to the ftw results in an instantaneous frequency jump but no phase discontinuity.
ad9549 rev. d | page 62 of 76 register 0x 01ac to register 0x01ad phase table 66. bit s bit name description [7:0] dds phase w ord allows user to vary the phase of the dds output. see the direct digital synthesizer section. register 0x 01ac is the least significant byte of the phase offset wo rd (pow). note that a momentary phase discontinuity may occur as the phase passes through 45 intervals. active only when the loop is not closed. register 0x01ad phase (continued) table 67. bit s bit name description [15:8 ] dds ph ase word allows user to vary the phase of the dds output. see the direct digital synthesizer section. register 0x 01ac is the least significant byte of the phase offset word (pow). note that a momentary phase discontinuity may occu r as the phase passes through 45 intervals. active only when the loop is not closed. reference selector/ holdover (reg ister 0x 01c0 to r eg ister 0x 01c3) register 0x 01c0 automatic control table 68. bit s bit name description 4 holdov er mode this bit determines which f requency t uning w ord (ftw) is used in h oldover m ode. 0 = u s e last ftw at time of holdover. 1 = u se averaged ftw at time of holdover, which is the recommended setting. the number of averages used is set in register 0x01c2 . 3 reserved reserved. 2 automatic s elector setting this bit permits state machine to switch the active reference clock input. 1 automatic recover setting this bit permits state machine to leave holdover mode. 0 automatic holdover setting this bit perm its state machine to enter holdover (free - run) mode. register 0x 01c1 override table 69. bit s bit name description 4 enable line card m ode enables line card mode of reference switch mux, which eliminates the possibility of a runt pulse during switchover. see the use of line card mode to eliminate runt pulses section. 3 enable ref input o verride setting this bit disables automatic reference switchover, and allows user to switch references manually via bit 2 of this register. setting this bit overrides the refselect pin. 2 r ef_ab this bit selects the input when bit 3 of this register is set. 0 = ref a. 1 enable holdover override setting this bit disables automatic holdover and allows user to enter/exit holdover manually via bit 0 (see the description for bit 0 ). setting this bit overrides the holdover pin. 0 holdover on/off this bit controls the status of holdover when bit 1 of this register is set. register 0x 01c2 averaging window table 70 . bit s bit name description [3:0] ftw windowed average s ize this register sets the number of ftws (frequency tuning words) that are used for calculating the average ftw. bit 4 in register 0x 01c0 enables this feature. an average size of at least 32, 000 is recommended for most applications. the number of averages equals 2 (ftw windowed average size [3:0]) . these samples a re taken at the rate of (fs/2 pio ).
ad9549 rev. d | page 63 of 76 register 0x 01c3 reference validation table 71. bit s bit name descript ion [ 7: 5] reserved reserved. [ 4: 0] validation t imer the value in this register sets the time required to validate a reference after a n lor or ool event before the reference can be used as the dpll reference. this circuit uses the digital loop filter cloc k (see register 0x 0107). validation time = l oop filter clock period 2 (validation timer [4:0] +1) ? 1. assuming power - on defaults, the recovery time varies from 32 ns (00000) to 137 sec (11111). if longer valida - tion times are required, the user can make the p - divider larger. the user should be careful to set the validation timer to at least two periods of the ool evaluation period. the ool evaluation period is the period of reference input clock times the ool d ivider (register 0x 0322 to register 0x 0323). doubler and output d rivers (reg ister 0x 0200 to reg ister 0x 0201) register 0x0200 hstl driver table 72. bit s bit name description 4 opol output polarity . setting this bit inverts the hstl driver output polarity. [ 3: 2] reserved res erved. [ 1: 0] hstl output d oubler hstl output doubler. 01 = doubler disabled. 10 = d oubler enabled. when using doubler, register 0x0010[5] must also be set. register 0x0201 cmos driver table 73. bit s bit name description 0 cmos m ux user mux control. this bit allows the user to select whether the cmos driver output is divided by the s- divider. 0 = s- divider input sent to cmos driver. 1 = s- divider output sent to cmos driver. see figure 22 .
ad9549 rev. d | page 64 of 76 monitor (register 0x 0300 to reg ister 0x 0335) register 0x0300 s tatus this register contains the status of the chip. this register is read - only and live update. table 74. bit s bit name description 7 reserved reserved. 6 pfd f requency too h igh this flag indicates that the f requency estimator failed and detected a pfd frequency that is too high. this bit is relevant only if the user is relying on the f requency e stimator to determine the input frequency. 5 pfd f requency too l ow this flag indi cates that the f requency e stimator failed and detected a pfd frequency that is too low . this bit is relevant only if the user is relying on the f requency e stimator to determine the input frequency. 4 frequency estimator done true when the frequency estimator circuit has successfully estimated the input frequency. see the frequency estimator section. 3 reference s elected reference s elected . 0 = reference a is active. 1 = reference b is active. 2 free r un dpll is in holdover mode (free run) . 1 pha se lock d etect this flag indicates that the phase lock detect circuit has detected phase lock. the amount of phase adjustment is compared against a programmable threshold. note that this bit can be set in single tone and holdover modes a nd should be ignored in these cases. 0 frequency lock d etect this flag indicates that the frequency lock detect circuit has detected frequency lock. this feature compares the absolute value of the difference of two consecutive phase detector edges against a programmable threshold. because of this, frequency lock detect is more rigorous than phase lock detect, and it is possible to have phase lock detect without frequency lock detect. register 0x0301 status ( continued) this register contains the status of the chip. this register is read - only and live update . table 75. bit s bit name description 7 reserved reserved. 6 r efa v alid the r eference v alidation circuit has successfully determined that reference a is valid. 5 r ef a lor a lor (loss of reference) has occurred on reference a. 4 r ef a ool the ool (out of limits) circuit has determined that reference a is out of limits. 3 reserved reserved. 2 r ef b valid the reference validation circuit has successfully determined that reference b is valid. 1 r ef b lor a lor (loss of reference) has occurred on reference b. 0 r ef b ool the ool (out of limits) circuit has determined that reference b is out of limits. register 0x0302 and register 0x0303 i rq status these registers contain th e chip st atus (registers 0x 0300 and register 0x 0301) at the time of irq. these bits are cleared with an irq reset (see register 0x 0012, bit 5). register 0x0304 irq mask table 76. bit s bit name description [7:3] reserved reserved. 2 refer ence c hanged trigger irq when active reference clock selection changes . 1 leave free r un trigger irq when dpll leaves free - run (holdover) mode . 0 enter free r un trigger irq when dpll enters free - run (holdover) mode.
ad9549 rev. d | page 65 of 76 register 0x0305 irq mask ( c ontinued) table 77. bit s bit name description 4 frequency estimator d one trigger irq when the frequency estimator is done . 3 phase u nlock trigger irq on falling edge of phase lock signal . 2 phase l ock trigger irq on rising edge of phase l ock signal . 1 frequency u nlock trigger irq on falling edge of frequency lock signal . 0 frequency l ock trigger irq on rising edge of frequency lock signal . register 0x0306 irq mask ( c ontinued) table 78. bit s bit name description [7:6] reserved reserved. 5 r efa v alid trigger irq o n rising edge of reference as v alid . 4 !r efa v alid trigger irq on falling edge of reference as v alid . 3 r ef a lor trigger irq on rising edge of reference as lor . 2 !r ef a lor trigger irq on falling edge of r eference as lor . 1 r ef a ool trigger irq on rising edge of r eference as ool . 0 !refa ool trigger irq on falling edge of reference as ool. register 0x0307 irq mask ( c ontinued) table 79. bit s bit name description [7:6] reserved reserved. 5 r efb v alid trigger irq on rising edge of reference bs v alid . 4 !r efb v alid trigger irq on falling edge of reference bs v alid . 3 r efb lor trigger irq on rising edge of reference b s lor . 2 !r efb lor trigger irq on falling edge of r eference b s lor . 1 r efb ool trigger irq on rising edge of r eference b s ool . 0 !r efb ool trigger irq on falling edge of r eference b s ool . register0x0308 s1 pin configuration see the status and warnings s ection . the choice of input for a given pin must be all refa or all ref b and not a combination of both . table 80. bit s bit name description 7 r ef ? choose either r ef a (0) or r ef b (1) for use with bits [4:6] . 6 r ef ? lor select either r ef a (0) or r ef b (1) lor signal for output on this pin . 5 r ef ? ool select either r ef a (0) or r ef b (1) ool signal for output on this pin . 4 r ef ? not valid select either r ef a (0) or r ef b (1) . not valid signal for output on this pin . 3 phase l ock select phase lock signal for output on this pin . 2 frequency l ock select frequency lock signal for output on this pin. 1 reserved reserved. 0 irq select irq signal for output on this pin . register 0x0309 s2 pin configuration same as register 0x 0308, except applies to p in s2 . s ee table 80 . register 0x030a s3 pin configuration same as register 0x 0308, except applies to p in s3 . see table 80 . register 0x030b s4 pin configuration same as register 0x 0308, except applies to p in s4 . s ee table 80 .
ad9549 rev. d | page 66 of 76 register 0x030c control table 81. bit s bit name description 7 enable r ef a lor the r efa lor limits are set up in registers 0x 031e to register 0x031f. 6 enable r ef a ool the r efa oo l limits are set up in register 0x 0322 to register 0x032b. 5 enable r ef b lor the r efb lo r limits are set up in register 0x 0320 to register 0x0321. 4 enable r efb ool the r ef b oo l limits are set up in register 0x 032c to register 0x0335. [3:2] reserved reserved. 1 en able phase lock d etector register 0x0314 to register 0x0318 must be set up to use this (see the phase lock detection section). 0 enable frequency lock d etector register 0x 0319 must be set up to use this. see the frequency lock detection section. register 0x030d reserved register 0x030e hftw ( read only) table 82. bit s bit name description [ 7: 0] average or i nstantaneous ftw th ese read - only register s are the output of ftw monit or. average or instantaneous is determined by h oldover m ode (see bit 4, register 0x 01c0). these registers must be manually refreshed by issuing an i /o update. register 0x030f hftw (read only ) (continued) table 83. bits bit name de scription [15:8 ] average or i nstantaneous ftw these read - only registers are the output of ftw monitor. average or instantaneous is determined by h oldover m ode (see bit 4, register 0x 01c0). these registers must be manually refreshed by issuing an i /o updat e. register 0x0310 hftw (read only) (continued) table 84. bits bit name description [23:16 ] average or i nstantaneous ftw these read - only registers are the output of ftw monitor. average or instantaneous is determined by h oldover m ode (see bit 4, register 0x 01c0). these registers must be manually refreshed by issuing an i /o update. register 0x0311 hftw (read only) (continued) table 85. bits bit name description [31:24 ] average or i nstantaneous ftw these r ead - only registers are the output of ftw monitor. average or instantaneous is determined by h oldover m ode (see bit 4, register 0x 01c0). these registers must be manually refreshed by issuing an i /o update. register 0x0312 hftw (read only) (continued) table 86. bits bit name description [39:32 ] average or i nstantaneous ftw these read - only registers are the output of ftw monitor. average or instantaneous is determined by h oldover m ode (see bit 4, register 0x 01c0). these registers must be manually refreshed by issuing an i /o update. register 0x 0313 hftw (read only) (continued) table 87. bits bit name description [47:40 ] average or i nstantaneous ftw these read - only registers are the output of ftw monitor. average or instantaneous is determined by h oldover m ode (see bit 4, register 0x 01c0). these registers must be manually refreshed by issuing an i /o update.
ad9549 rev. d | page 67 of 76 register 0x0314 phase lock table 88. bit s bit name description [7:0] phas e loc k t hreshold see the phase lock detection section. register 0x0315 phase lock (continued) table 89. bits bit name description [15:8 ] phas e lock t hreshold see the phase loc k detection section. register 0x0316 phase lock (continued) table 90. bits bit name description [23:16 ] phas e lock t hreshold see the phase lock detection section. register 0x 0317 phase lock (contin ued) table 91. bits bit name description [31:24 ] phas e lock t hreshold see the phase lock detection section. register 0x0318 phase lock ( c ontinued) table 92. bit s bit name des cription [ 7:5 ] phase unlock watchdog t imer see the phase lock detection section. [ 4: 0] phase lock watchdog t imer see the phase lock detection section. register 0x0319 frequency lock table 93. bit s bit name description [7:0] frequency lock t hreshold see the frequency lock detection section register 0x031a frequency lock (continued) table 94. bits bit name description [15:8 ] fr equency lock t hreshold see the frequency lock detection section register 0x031b frequency lock (continued table 95. bits bit name description [31:16 ] frequency lock t hreshold see the frequency lock detection section register 0x 031c frequency lock (continued table 96. bits bit name description [39:32 ] frequency lock t hreshold see the frequency lock detection section register 0x031d frequency lock ( c ontinued) table 97. bit s bit name description [ 7:5 ] frequency unlock watchdog t imer see the frequency lock detection section. [ 4: 0] frequency lock watchdog t imer see the frequency lock detection section.
ad9549 rev. d | page 68 of 76 register 0x031e loss of reference table 98. bit s bit name description [7:0] r ef a l or d ivider see the loss of reference section. register 0x 031f loss of r eference (continued) table 99. bits bit name description [15:8 ] r ef a l or d ivider see the loss of reference section. register 0x0320 loss of reference ( c ontinued) table 100 . bit s bit name description [ 7:0 ] r efb lor d ivider see the loss of reference section. register 0x 0321 loss of reference ( c ontinued) table 101 . bits bit name description [ 15:8 ] r efb lor d ivider see the loss of reference section. register 0x0322 reference out of limits (ool) table 102 . bit s bit name description [7:0] r ef a ool d ivider see the reference frequency monitor sect ion. r0322 is the lsb, and r0323 is the msb. register 0x 0323 reference out of limits (ool) (continued) table 103 . bits bit name description [15:8 ] r efa ool d ivider see the reference frequency monitor section. r0322 is the lsb, and r0323 is the msb. register 0x 0324 reference ool ( c ontinued) table 104 . bit s bit name description [7:0] r ef a ool upper l imit s ee the reference frequency monitor section . register 0x0325 reference ool ( c ontinued) table 105 . bits bit name description [15:8 ] r efa ool upper l imit s ee the reference frequency monitor section. register 0x0326 reference ool ( c ontinued) ta ble 106 . bits bit name description [23:16 ] r efa ool upper l imit s ee the reference frequency monitor section. register 0x 0327 reference ool ( c ontinued) table 107 . bits bit nam e description [31:24 ] r efa ool upper l imit s ee the reference frequency monitor section.
ad9549 rev. d | page 69 of 76 register 0x0328 reference ool ( c ontinued) table 108 . bit s bit name description [7:0] r ef a ool lower l imit see the reference frequency monitor section. register 0x0329 reference ool ( c ontinued) table 109 . bits bit name description [15:8 ] r efa ool lower l imit s ee the reference frequency mo nitor section. register 0x032a reference ool ( c ontinued) table 110 . bits bit name description [23:16 ] r efa ool lower l imit s ee the reference frequency monitor section. register 0x 032b reference ool ( co ntinued) table 111 . bits bit name description [31:24 ] r efa ool lower l imit s ee the reference frequency monitor section. register 0x032c reference ool ( c ontinued) table 112 . bit s bit name description [7:0] r ef b ool d ivider see the reference frequency monitor section. register 0x 032c is the lsb, and r egister 0x032d is the msb. register 0x 032d reference ool ( c ontinued) table 113 . bits bit name description [15:8 ] r efb ool d ivider see the reference frequency monitor section. register 0x032c is the lsb, and register 0x032d is the msb. register 0x032e reference ool ( c ontinued) table 114 . bit s bit name description [7:0] r ef b ool upper l imit s ee the reference frequency monitor section. register 0x032f reference ool ( c ontinued) table 115 . bits bit name description [15:8 ] r efb ool upper l imit s ee the reference frequency monitor section. register 0x0330 reference ool ( c ontinued) table 116 . bits bit name description [23:16 ] r efb ool upper l imit s ee the reference frequency monitor section. register 0x 0331 reference ool ( c ontinued) table 117 . bits bit name description [31:24 ] r efb ool upper l imit s ee the reference frequency monitor section.
ad9549 rev. d | page 70 of 76 register 0x0332 reference ool ( c ontinued) table 118 . bits bit name description [7: 0] r efb ool lower l imit s ee the reference frequency monitor section. register 0x0333 reference ool ( c ontinued) table 119 . bits bit name description [15:8 ] r efb ool lower l imit s ee the reference frequency monitor section. register 0x0334 reference ool ( c ontinued) table 120 . bits bit name description [23:1 6] r efb ool lower l imit s ee the reference frequency monitor section. register 0x0335 reference ool ( c ontinued) table 121 . bit s bit name description [ 31:24 ] r ef b ool lower l imit s ee the reference frequency monitor section. calibration (user - accessible trim) (reg ister 0x 0400 to reg ister 0x 0410) register 0x0400 k- divider table 122 . bit s bit name description [7:0] k-d ivider the k - divider alters precision of frequenc y estimator circuit. see the frequency estimator section . register 0x 0401 k- divider (continued) table 123 . bits bit name description [15:8 ] k-d ivider the k - divider alters precision of freq uenc y estimator circuit. see the frequency estimator section . register 0x0402 cpfd gain table 124 . bit s bit name description [ 2: 0] cpfd gain s cale this register is the coarse phase frequency power -of - 2 multiplier (pds). see the phase detector section. note that the correct value for this register is calculated by filter design software provided with the evaluation board. register 0x0403 cpfd gain ( c ontinued) table 125 . bit s bit name description [ 5: 0] cpfd g ain this register is the coarse phase frequency linear multiplier (pdg). see the phase detector section. note that the correct value for this register is calculate d by filter design software provided with the evaluation board. register 0x0404 fpfd gain table 126 . bit s bit name description [ 7: 0] f pfd g ain this register is the fine phase frequency detector linear multiplier (alters charge pu mp current). see the fine phase detector section. note that the correct value for this register is calculated by filter design software provided with the evaluation board. register 0x0405 reserved
ad9549 rev. d | page 71 of 76 register 0x0406 part version table 127 . bits bit name description [7:6] part version 01b = ad9549, revision a 00b = ad9549, revision 0 [5:0] reserved n/a register 0x 040 7 to register 0x0408 reserved register 0x0409 pfd offset table 128 . bit s bit name description [7:0] dpll phase o ffset this register controls the static time offset of the pfd (phase frequency detector) in closed - loop mode. it has no effect when the dpll is open. register 0x 040a pfd offset (continued) table 129 . bits bit name description [13 :8] dpll phase o ffset this register controls the static time offset of the pfd (phase frequency detector) in closed - loop mode. it has no effect when the dpll is open. register 0x040b dac full - scale curren t table 130 . bit s bit name description [ 7: 0] dac f ull - scale c urrent d ac f ull - scale current , bits [7:0] . s ee the dac output section. register 0x040c dac full -s cale current (continued) table 131 . bit s bit name description [ 9:8 ] dac f ull - scale c urrent d ac f ull - scale current , bits [9:8]. s ee register 0x040b. register 0x040d to register 0x040e reserved register 0x040f reference bias level table 132 . bit s bit na me description [7:2] reserved reserved. [ 1: 0] dc input l evel t his register sets the dc bias level for the reference inputs. the value should be chosen such that v ih is as close as possible to, but does not exceed, 3.3 v. 00 = vdd3 ? 800 mv . 01 = vdd3 ? 4 00 mv . 10 = vdd3 ? 1.6 v . 11 = vdd3 ? 1.2 v . register 0x0410 reserved harmonic spur reduct ion (reg ister 0x 0500 to reg ister 0x 0509) see the h armonic spur reduction section.
ad9549 rev. d | page 72 of 76 register 0x0500 sp ur a table 133 . bit s bit name description 7 hsr- a e nable harmonic spur reduction a e nable . 6 amplitude g ain 2 [ 5: 4] reserved reserved. [ 3: 0] spur a h armonic spur a harmonic 1 to spur a harmonic 15 . register 0x0501 spur a ( c ontinued) table 1 34 . bit s bit name description [ 7: 0] spur a m agnitude linear multiplier for spur a magnitude . register 0x0503 spur a ( c ontinued) table 135 . bit s bit name description [7:0] spur a phase linear offset for spur a phase. register 0x0504 spur a (continued) table 136 . bit s bit name description 8 spur a p hase linear offset for spur a phase. register 0x0505 spur b table 137 . bit s bit name description 7 hsr- b e nable harmonic spur red uction b e nable . 6 amplitude g ain 2 [ 5: 4] reserved reserved. [ 3: 0] spur b h armonic spur b h armonic 1 to spur b harmonic 15 . register 0x0506 spur b ( c ontinued) table 138 . bit s bit name description [ 7: 0] spur b m agnitude line ar multiplier for spur b magnitude . register 0x0508 spur b ( c ontinued) table 139 . bit s bit name description [7:0] spur b phase linear offset for spur b phase. register 0x0509 spur b (continued) table 140 . bit s bit name description 8 spur b p hase linear offset for spur b phase.
ad9549 rev. d | page 73 of 76 applications information sample application s circuit clk clkb syncb low-pass filter ad9514 /1...../32 /1...../32 /1...../32 t out0/ out0b out1/ out1b out2/ out2b sysclk input a input b 06744-059 ad9549 dds/ dac ref a ref b diff hstl output fdbk_in fdbk_inb cmos output ldds/cmos lvpecl lvpecl figure 59 . ad9549 and ad9514 precision clock distribution circuit applications circuit features features of this applications circuit include the following : ? input f requencies d own to 8 khz; o utput f requencies u p to 400 mhz ? programmable l oop b andwidth down to < 1 hz ? automatic r edundant c lock s witchover with user -s electable rate - of -p hase a djustment ? auto matic s tratum 3/3e c lock h oldover, d epending on the configuration ? phase n oise ( f c = 122.3 mhz and 100 hz loop bandwidth ); 100 hz offset: ? 107 dbc/hz; 1 k hz offset: ? 142 dbc/hz; 100 khz offset: ? 157 dbc/hz; t wo z ero - delay o utputs with p rogrammable postd ivider and s ynchronization ? two a dditional outputs (nonzero delay) on the ad9549 ? programmable s kew a djustment on o ne ad9514 o utput
ad9549 rev. d | page 74 of 76 outline dimensions compliant to jedec standards mo-220-vmmd-4 062209-a 0.25 min 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max seating plane pin 1 indicator 5.36 5.21 sq 5.06 pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed pad bottom view 9.10 9.00 sq 8.90 8.85 8.75 sq 8.65 figure 60 . 64 - lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp - 64 -7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad 9549a bcpz ?40c to +85c 64- lead lead frame chip scale package [lfcsp_vq] cp -64 -7 ad9549 a bcpz - reel7 ?40c to +85c 64- lead lead frame chip scale package [lfcsp_vq cp -64 -7 ad9549 a /pcbz evaluation board 1 z = rohs compliant part.
ad9549 rev. d | page 75 of 76 notes
ad9549 rev. d | page 76 of 76 notes ? 2007 C 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06744 -0- 12 /10(d)

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