View ISP1507ABS_7570021.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the isp1507 is a universal serial bus (usb) on-the-go (otg) transceiver that is fully compliant with universal serial bus speci?cation rev. 2.0 , on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 and utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . the isp1507 can transmit and receive usb data at high-speed (480 mbit/s), full-speed (12 mbit/s) and low-speed (1.5 mbit/s), and provides a pin-optimized, physical layer front-end attachment to usb host, peripheral and otg devices. it is ideal for use in portable electronic devices, such as mobile phones, digital still cameras, digital video cameras, personal digital assistants (pdas) and digital audio players. it allows usb application-speci?c integrated circuits (asics), programmable logic devices (plds) and any system chip set to interface with the physical layer of the usb through a 12-pin interface. the isp1507 can interface to the link with digital i/o voltages in the range of 1.65 v to 3.6 v. the isp1507 is available in hvqfn32 package. 2. features n fully complies with: u universal serial bus speci?cation rev. 2.0 u on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 u utmi+ low pin interface (ulpi) speci?cation rev. 1.1 n interfaces to host, peripheral and otg device cores; optimized for portable devices or system asics with built-in usb otg device core n complete hi-speed usb physical front-end solution that supports high-speed (480 mbit/s), full-speed (12 mbit/s) and low-speed (1.5 mbit/s) u integrated 45 w 10 % high-speed termination resistors, 1.5 k w 5 % full-speed device pull-up resistor, and 15 k w 5 % host termination resistors u integrated parallel-to-serial and serial-to-parallel converters to transmit and receive u usb clock and data recovery to receive usb data up to 500 ppm u insertion of stuff bits during transmit and discarding of stuff bits during receive u non-return-to-zero inverted (nrzi) encoding and decoding u supports bus reset, suspend, resume and high-speed detection handshake (chirp) n complete usb otg physical front-end that supports host negotiation protocol (hnp) and session request protocol (srp) isp1507a; isp1507b ulpi hi-speed universal serial bus on-the-go transceiver rev. 01 19 may 2008 product data sheet
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 2 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver u integrated 5 v charge pump; also supports external charge pump or 5 v v bus switch u complete control over bus resistors u data line and v bus pulsing session request methods u integrated v bus voltage comparators u integrated cable (id) detector n highly optimized ulpi-compliant u 60 mhz, 8-bit interface between the core and the transceiver u supports 60 mhz output clock con?guration u integrated phase-locked loop (pll) supporting one crystal or clock frequency: 19.2 mhz (ISP1507ABS) and 26 mhz (isp1507bbs) u fully programmable ulpi-compliant register set u internal power-on reset (por) circuit n flexible system integration and very low current consumption, optimized for portable devices u power-supply input range is 3.0 v to 3.6 v u internal voltage regulator supplies 3.3 v and 1.8 v u charge pump regulator outputs 4.75 v to 5.25 v at a current of up to 50 ma, tunable using an external capacitor u supports external v bus charge pump or 5 v v bus switch: external v bus source is controlled using the psw_n pin; open-drain psw_n allows per-port or ganged power control digital fault input to monitor the external v bus supply status u pin chip_select_n 3-states the ulpi interface, allowing bus reuse for other applications u supports wide range interfacing i/o voltage of 1.65 v to 3.6 v; separate i/o voltage pins minimize crosstalk u typical operating current of 10 ma to 48 ma, depending on the usb speed and bus utilization; not including the charge pump u typical suspend current of 35 m a n full industrial grade operating temperature range from - 40 c to +85 c n 4 kv electrostatic discharge (esd) protection at pins dp, dm, id, v bus and gnd n available in a small hvqfn32 (5 mm 5 mm) restriction of hazardous substances (rohs) compliant, halogen-free and lead-free package 3. applications n digital still camera n digital tv n digital video disc (dvd) recorder n external storage device, for example: u magneto-optical (mo) drive u optical drive: cd-rom, cd-rw, dvd u zip drive n mobile phone n mp3 player
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 3 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver n pda n printer n scanner n set-top box (stb) n video camera 4. ordering information [1] the package marking is the ?rst line of text on the ic package and can be used for ic identi?cation. table 1. ordering information part package type number marking crystal or clock frequency name description version ISP1507ABS 507a [1] 19.2 mhz hvqfn32 plastic thermal enhanced very thin quad ?at package; no leads; 32 terminals; body 5 5 0.85 mm sot617-1 isp1507bbs 507b [1] 26 mhz hvqfn32 plastic thermal enhanced very thin quad ?at package; no leads; 32 terminals; body 5 5 0.85 mm sot617-1
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 4 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 5. block diagram fig 1. block diagram register map ulpi interface controller usb data serializer usb data deserializer hi-speed usb atx dm dp stp dir nxt data [7:0] 8 4 5 21 20 19 1, 23 to 26, 28, 31, 32 004aab035 clock 27 termination resistors id detector v bus comparators on-the-go module srp charge and discharge resistors 5 v charge pump supply power-on reset pll crystal oscillator voltage regulator band gap reference voltage rref 3 internal power v cc 11 reg3v3 reg1v8 14 18 reset_n global reset global clocks xtal2 xtal1 15 16 v cc(i/o) 2, 22, 30 interface voltage psw_n drv v bus external drv v bus id 7 v bus 13 fault 6 12 cpgnd 8 10 c_a c_b 9 isp1507 17 ulpi interface usb cable v ref chip_select_n 29 v bus valid external
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 5 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration hvqfn32; top view 004aab036 isp1507 transparent top view reset_n id cpgnd reg1v8 fault dir dp stp dm nxt rref v cc(i/o) v cc(i/o) data7 data0 data6 c_b c_a v cc psw_n v bus reg3v3 xtal1 xtal2 data1 data2 v cc(i/o) chip_select_n data3 clock data4 data5 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area table 2. pin description symbol [1] [2] pin type [3] description [4] data0 1 i/o pin 0 of the bidirectional ulpi data bus slew-rate controlled output (1 ns); plain input; programmable pull down v cc(i/o) 2 p i/o supply rail rref 3 ai/o resistor reference dm 4 ai/o data minus (d - ) pin of the usb cable dp 5 ai/o data plus (d+) pin of the usb cable fault 6 i input pin for the external v bus digital overcurrent or fault detector signal plain input; 5 v tolerant id 7 i identi?cation (id) pin of the micro-usb cable if this pin is not used, it is recommended to connect to reg3v3. plain input; ttl level cpgnd 8 p charge pump ground c_b 9 ai/o ?ying capacitor pin connection for the charge pump c_a 10 ai/o ?ying capacitor pin connection for the charge pump v cc 11 p input supply voltage or battery source psw_n 12 od active low external v bus power switch or external charge pump enable open-drain; 5 v tolerant
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 6 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver [1] symbol names ending with underscore n, for example, name_n, indicate active low signals. [2] for details on external components required on each pin, see bill of materials and application diagrams in section 16 . [3] i = input; o = output; i/o = digital input/output; od = open-drain output; ai = analog input; ao = analog output; ai/o = analog input/output; p = power or ground pin. [4] a detailed description of these pins can be found in section 7.9 . v bus 13 ai/o v bus pin of the usb cable 5 v tolerant reg3v3 14 p 3.3 v regulator output xtal1 15 ai crystal oscillator or clock input xtal2 16 ao crystal oscillator output reset_n 17 i active low, asynchronous reset input plain input reg1v8 18 p 1.8 v regulator output dir 19 o ulpi direction signal slew-rate controlled output (1 ns) stp 20 i ulpi stop signal plain input; programmable pull up nxt 21 o ulpi next signal slew-rate controlled output (1 ns) v cc(i/o) 22 p i/o supply rail data7 23 i/o pin 7 of the bidirectional ulpi data bus slew-rate controlled output (1 ns); plain input; programmable pull down data6 24 i/o pin 6 of the bidirectional ulpi data bus slew-rate controlled output (1 ns); plain input; programmable pull down data5 25 i/o pin 5 of the bidirectional ulpi data bus slew-rate controlled output (1 ns); plain input; programmable pull down data4 26 i/o pin 4 of the bidirectional ulpi data bus slew-rate controlled output (1 ns); plain input; programmable pull down clock 27 o 60 mhz clock output slew-rate controlled output (1 ns); plain input data3 28 i/o pin 3 of the bidirectional ulpi data bus slew-rate controlled output (1 ns); plain input; programmable pull down chip_select_ n 29 i active low chip select plain input v cc(i/o) 30 p i/o supply rail data2 31 i/o pin 2 of the bidirectional ulpi data bus slew-rate controlled output (1 ns); plain input; programmable pull down data1 32 i/o pin 1 of the bidirectional ulpi data bus slew-rate controlled output (1 ns); plain input; programmable pull down gnd die pad p ground supply; down bonded to the exposed die pad (heat sink); to be connected to the pcb ground table 2. pin description continued symbol [1] [2] pin type [3] description [4]
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 7 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 7. functional description 7.1 ulpi interface controller the isp1507 provides a 12-pin interface that is compliant with utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . this interface must be connected to the usb link. the ulpi interface controller provides the following functions: ? ulpi-compliant and register set ? allows full control over the usb peripheral, host and otg functionality ? parses usb transmit and receive data ? prioritizes usb receive data, usb transmit data, interrupts and register operations ? low-power mode ? control of the v bus charge pump or external source ? v bus monitoring, charging and discharging ? 6-pin serial mode and 3-pin serial mode ? generates rxcmds; status updates ? maskable interrupts ? control over the ulpi bus state, allowing pins to 3-state or attach active weak pull-down resistors for more information on the ulpi protocol, see section 9 . 7.2 usb data serializer and deserializer the usb data serializer prepares data to transmit on the usb bus. to transmit data, the usb link sends a transmit command and data on the ulpi bus. the serializer performs parallel-to-serial conversion, bit stuf?ng and nrzi encoding. for packets with a pid, the serializer adds a sync pattern to the start of the packet, and an eop pattern to the end of the packet. when the serializer is busy and cannot accept any more data, the ulpi interface controller deasserts nxt. the usb data deserializer decodes data received from the usb bus. when data is received, the deserializer strips the sync and eop patterns, and then performs serial-to-parallel conversion, nrzi decoding and discarding of stuff bits on the data payload. the ulpi interface controller sends data to the usb link by asserting dir, and then asserting nxt whenever a byte is ready. the deserializer also detects various receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and byte-alignment errors. 7.3 hi-speed usb (usb 2.0) atx the hi-speed usb atx block is an analog front-end containing the circuitry needed to transmit, receive and terminate the usb bus in high-speed, full-speed and low-speed, for usb peripheral, host and otg implementations. the following circuitry is included: ? differential drivers to transmit data at high-speed, full-speed and low-speed
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 8 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver ? differential and single-ended receivers to receive data at high-speed, full-speed and low-speed ? squelch circuit to detect high-speed bus activity ? high-speed disconnect detector ? 45 w high-speed bus terminations on dp and dm for peripheral and host modes ? 1.5 k w pull-up resistor on dp for full-speed peripheral mode ? 15 k w bus terminations on dp and dm for host and otg modes for details on controlling resistor settings, see t ab le 8 . 7.4 voltage regulator the isp1507 contains a built-in voltage regulator that conditions the v cc supply for use inside the isp1507. the voltage regulator: ? supports input supply range of 3. 0v isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 9 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver ? resistors to temporarily charge and discharge v bus . this is required for srp. ? charge pump to provide 5 v power on v bus . the downstream peripheral can draw its power from the isp1507 v bus . 7.6.1 id detector the id detector detects which end of the micro-usb cable is plugged in. the detector must ?rst be enabled by setting the id_pullup register bit to logic 1. if the isp1507 senses a value on id that is different from the previously reported value, an rxcmd status update will be sent to the usb link, or an interrupt will be asserted. ? if the micro-b end of the cable is plugged in, the isp1507 will report that id_gnd is logic 1. the usb link must change to peripheral mode. ? if the micro-a end of the cable is plugged in, the isp1507 will report that id_gnd is logic 0. the usb link must change to host mode. 7.6.2 v bus comparators the isp1507 provides three comparators, v bus valid comparator, session valid comparator and session end comparator, to detect the v bus voltage level. 7.6.2.1 v bus valid comparator this comparator is used by hosts and a-devices to determine whether the voltage on v bus is at a valid level for operation. the isp1507 minimum threshold for the v bus valid comparator is v a_vbus_vld . any voltage on v bus below v a_vbus_vld is considered a fault. during power-up, it is expected that the comparator output will be ignored. 7.6.2.2 session valid comparator the session valid comparator is a ttl-level input that determines when v bus is high enough for a session to start. peripherals, a-devices and b-devices use this comparator to detect when a session is started. the a-device also uses this comparator to determine when a session is completed. the session valid threshold of the isp1507 is v b_sess_vld , with a hysteresis of v hys(b_sess_vld) . 7.6.2.3 session end comparator the isp1507 session end comparator determines when v bus is below the b-device session end threshold. the b-device uses this threshold to determine when a session has ended. the session end threshold of the isp1507 is v b_sess_end . 7.6.3 srp charge and discharge resistors the isp1507 provides on-chip resistors for short-term charging and discharging of v bus . these are used by the b-device to request a session, prompting the a-device to restore the v bus power. first, the b-device makes sure that v bus is fully discharged from the previous session by setting the dischrg_vbus register bit to logic 1 and waiting for sess_end to be logic 1. then the b-device charges v bus by setting the chrg_vbus register bit to logic 1. the a-device sees that v bus is charged above the session valid threshold and starts a session by turning on the v bus power.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 10 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 7.6.4 charge pump the isp1507 uses a built-in charge pump to supply current to v bus at a nominal voltage of 5 v. the charge pump works as a capacitive dc-dc converter. an external holding capacitor, c cp(c_a)-(c_b) , is required between the c_a and c_b pins as shown in figure 3 , which also shows a typical otg v bus load. the value of c cp(c_a)-(c_b) depends on the amount of current drive required. if the internal charge pump is not used, the c cp(c_a)-(c_b) capacitor is not required. for details on the c_a and c_b pins, see section 7.9.8 . 7.7 band gap reference voltage the band gap circuit provides a stable internal voltage reference to bias the analog circuitry. the band gap requires an accurate external reference, r rref , resistor connected between the rref pin and gnd. for details, see section 16 . 7.8 power-on reset (por) the isp1507 has an internal power-on reset circuit that resets all internal logic on power-up. the ulpi interface is also reset on power-up. remark: when clock starts toggling after power-up, the usb link must issue a reset command over the ulpi bus to ensure correct operation of the isp1507. 7.9 detailed description of pins 7.9.1 data[7:0] the isp1507 is a physical layer (phy) containing a usb transceiver. data[7:0] is the bidirectional data bus. the usb link must drive data[7:0] to low when the ulpi bus is idle. when the link has data to transmit to the phy, it drives a nonzero value. the data bus can be recon?gured to carry various data types, as given in section 8 and section 9 . the data[7:0] pins can be 3-stated by driving pin chip_select_n to high. weak pull-down resistors are incorporated into the data[7:0] pins as part of the interface protect feature. for details, see section 9.3.1 . fig 3. external capacitors connection 004aab037 isp1507 v bus c_b c_a c cp(c_a)-(c_b) otg v bus 4.7 m f 0.1 m f
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 11 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 7.9.2 v cc(i/o) the input power pin that sets the i/o voltage level. for details, see section 12 , section 13 and section 16 . v cc(i/o) provides power to on-chip pads of the following pins: ? chip_select_n ? clock ? data[7:0] ? dir ? nxt ? reset_n ? stp 7.9.3 rref resistor reference analog i/o pin. a resistor, r rref , must be connected between rref and gnd, as shown in section 16 . this provides an accurate voltage reference that biases internal analog circuitry. less accurate resistors cannot be used and will render the isp1507 unusable. 7.9.4 dp and dm the dp (data plus) and dm (data minus) are usb differential data pins. these must be connected to the d+ and d - pins of the usb receptacle. 7.9.5 fault if an external v bus overcurrent or fault circuit is used, the output fault indicator of that circuit can be connected to the isp1507 fault input pin. the isp1507 will inform the link of v bus fault events by sending rxcmds on the ulpi bus. to use the fault pin, the link must: ? set the use_ext_vbus_ind register bit to logic 1. ? set the polarity of the external fault signal using the ind_compl register bit. ? set the ind_passthru register bit to logic 1. if the fault pin is not used, it is recommended to connect to gnd. 7.9.6 id for otg implementations, the id (identi?cation) pin is connected to the id pin of the micro-usb receptacle. as de?ned in on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 , the id pin dictates the initial role of the link. if id is detected as high, the link must assume the role of a peripheral. if id is detected as low, the link must assume a host role. roles can be swapped at a later time by using hnp. if the isp1507 is not used as an otg phy, but as a standard usb host or peripheral phy, the id pin must be connected to reg3v3. 7.9.7 cpgnd cpgnd indicates the analog ground for the on-board charge pump. cpgnd must always be connected to ground, even when the charge pump is not used.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 12 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 7.9.8 c_a and c_b the c_a and c_b pins are to connect the ?ying capacitor of the charge pump. the output current capability of the charge pump depends on the value of the capacitor used, as shown in t ab le 3 . for maximum ef?ciency, place capacitors as close as possible to pins. for details, see section 16 . if the charge pump is not used, c_a and c_b must be left ?oating (not connected). 7.9.9 v cc v cc is the main input supply voltage for the isp1507. decoupling capacitors are recommended. for details, see section 16 . 7.9.10 psw_n psw_n is an active low, open-drain output pin. this pin can be connected to an active low, external v bus switch or charge pump enable circuit to control the external v bus power source. an external pull-up resistor, r pullup , is required when psw_n is used. this pin is open-drain, allowing ganged-mode power control for multiple usb ports. for application details, see section 16 . if the link is in host mode, it can enable the external v bus power source by setting the drv_vbus_ext bit in the otg_ctrl register (see section 10.1.4 ) to logic 1. the isp1507 will drive psw_n to low to enable the external v bus power source. if the link detects an overcurrent condition (the v bus state in rxcmd is not 11b), it must disable the external v bus power source by setting drv_vbus_ext to logic 0. 7.9.11 v bus this pin acts as an input to v bus comparators, and also as a power pin for the charge pump, and srp charge and discharge resistors. when the drv_vbus bit in the otg_ctrl register (see section 10.1.4 ) is set to logic 1, the isp1507 drives v bus to a voltage of 4.4 v to 5.25 v, with a minimum output current capability of 8 ma. fig 4. charge pump capacitor table 3. recommended charge pump capacitor value c cp(c_a)-(c_b) i l (max) 22 nf 8 ma 270 nf 50 ma 004aab038 i l isp1507 v bus c_a c_b c cp(c_a)-(c_b)
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 13 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver the v bus pin requires a capacitive load as shown in section 16 . to prevent electrical overstress, it is strongly recommended that you attach a series resistor on the v bus pin (r vbus ). r vbus must not be attached when using the isp1507 internal charge pump. for details, see section 16 . 7.9.12 reg3v3 and reg1v8 regulator output voltage. these supplies are used to power the isp1507 internal digital and analog circuits, and must not be used to power external circuits. for correct operation of the regulator, it is recommended that you connect reg3v3 and reg1v8 to decoupling capacitors. for examples, see section 16 . 7.9.13 xtal1 and xtal2 xtal1 is the crystal input, and xtal2 is the crystal output. the allowed frequency on the xtal1 pin depends on the isp1507 product version. if the link requires a 60 mhz clock from the isp1507, then either a crystal must be attached, or a clock of the same frequency must be driven into xtal1, with xtal2 left ?oating. if a crystal is attached, it requires external load capacitors to gnd on each terminal of the crystal. for details, see section 16 . if at any time the system wants to stop the clock on xtal1, the link must ?rst put the isp1507 into low-power mode. the clock on xtal1 must be restarted before low-power mode is exited. 7.9.14 reset_n an active low asynchronous reset pin that resets all circuits in the isp1507. the isp1507 contains an internal power-on reset circuit, and therefore using the reset_n pin is optional. if reset_n is not used, it must be connected to v cc(i/o) . for details on using reset_n, see section 9.3.2 . 7.9.15 dir ulpi direction output pin. controls the direction of the data bus. by default, the isp1507 holds dir at low, causing the data bus to be an input. when dir is low, the isp1507 listens for data from the link. the isp1507 pulls dir to high only when it has data to send to the link, which is for one of two reasons: ? to send usb receive data, rxcmd status updates and register read data to the link. ? to block the link from driving the data bus during power-up, reset and low-power (suspend) mode. the dir pin can also be 3-stated by driving chip_select_n to high. for details on dir usage, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 .
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 14 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 7.9.16 stp ulpi stop input pin. the link must assert stp to signal the end of a usb transmit packet or a register write operation. when dir is asserted, the link can optionally assert stp to abort the isp1507, causing it to deassert dir in the next clock cycle. a weak pull-up resistor is incorporated into the stp pin as part of the interface protect feature. for details, see section 9.3.1 . the stp input will be ignored when chip_select_n is driven to high. for details on stp usage, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . 7.9.17 nxt ulpi next data output pin. the isp1507 holds nxt at low, by default. when dir is low and the link is sending data to the isp1507, nxt will be asserted to notify the link to provide the next data byte. when dir is at high and the isp1507 is sending data to the link, nxt will be asserted to notify the link that another valid byte is on the bus. nxt is not used for register read data or the rxcmd status update. the nxt pin can also be 3-stated by driving chip_select_n to high. for details on nxt usage, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . 7.9.18 clock a 60 mhz interface clock to synchronize the ulpi bus. the isp1507 provides two clocking options: ? a crystal attached between the xtal1 and xtal2 pins. ? a clock driven into the xtal1 pin, with the xtal2 pin left ?oating. for details on clock usage, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . 7.9.19 chip_select_n active low chip select pin. if chip_select_n is not used, it must be connected to gnd. for more information on using chip_select_n, see section 9.3.3 . 7.9.20 gnd (die pad) global ground signal, except for the charge pump that uses cpgnd. the die pad is exposed on the underside of the package as a ground plate. this acts as a ground to all circuits in the isp1507, except the charge pump. to ensure correct operation of the isp1507, gnd must be soldered to the cleanest ground available.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 15 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 8. modes of operation 8.1 ulpi modes the isp1507 ulpi bus can be programmed to operate in four modes. each mode recon?gures the signals on the data bus as described in the following subsections. setting more than one mode will lead to unde?ned behavior. 8.1.1 synchronous mode this is default mode. at power-up, and when clock is stable, the isp1507 will enter synchronous mode. the link must synchronize all ulpi signals to clock, meeting the set-up time and the hold time as de?ned in section 15 . a description of the ulpi pin behavior in synchronous mode is given in t ab le 4 . this mode is used by the link to perform the following tasks: ? high-speed detection handshake (chirp) ? transmit and receive usb packets ? read and write to registers ? receive usb status updates (rxcmds) for more information on various synchronous mode protocols, see section 9 . table 4. ulpi signal description signal name direction on isp1507 signal description clock o 60 mhz interface clock . if a crystal is attached or a clock is driven into the xtal1 pin, the isp1507 will drive a 60 mhz output clock. data[7:0] i/o 8-bit data bus . in synchronous mode, the link drives data[7:0] to low by default. the link initiates transfers by sending a nonzero data pattern called txcmd (transmit command). in synchronous mode, the direction of data[7:0] is controlled by dir. contents of data[7:0] lines must be ignored for exactly one clock cycle whenever dir changes value. this is called the turnaround cycle. data lines have ?xed direction and different meaning in low-power and serial modes.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 16 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 8.1.2 low-power mode when the usb is idle, the link can place the isp1507 into low-power mode (also called suspend mode). in low-power mode, the data bus de?nition changes to that shown in t ab le 5 . to enter low-power mode, the link sets the suspendm bit in the func_ctrl register (see section 10.1.2 ) to logic 0. to exit low-power mode, the link asserts the stp signal. the isp1507 will draw only suspend current from the v cc supply (see t ab le 46 ). during low-power mode, the clock on xtal1 may be stopped. the clock must be started again before asserting stp to exit low-power mode. after exiting low-power mode, the isp1507 will send an rxcmd to the link if a change was detected in any interrupt source, and the change still exists. an rxcmd may not be sent if the interrupt condition is removed before exiting. for more information on low-power mode enter and exit protocols, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . dir o direction : controls the direction of data bus data[7:0]. in synchronous mode, the isp1507 drives dir to low by default, making the data bus an input so that the isp1507 can listen for txcmds from the link. the isp1507 drives dir to high only when it has data for the link. when dir and nxt are high, the byte on the data bus contains decoded usb data. when dir is high and nxt is low, the byte contains status information called rxcmd (receive command). the only exception to this rule is when the phy returns register read data, where nxt is also low, replacing the usual rxcmd byte. every change in dir causes a turnaround cycle on the data bus, during which data[7:0] is not valid and must be ignored by the link. dir is always asserted during low-power and serial modes. stp i stop : in synchronous mode, the link drives stp to high for one cycle after the last byte of data is sent to the isp1507. the link can optionally assert stp to force dir to be deasserted. in low-power and serial modes, the link holds stp at high to wake up the isp1507, causing the ulpi bus to return to synchronous mode. nxt o next : in synchronous mode, the isp1507 drives nxt to high to throttle data. if dir is low, the isp1507 asserts nxt to notify the link to place the next data byte on data[7:0] in the following clock cycle. if dir is high, the isp1507 asserts nxt to notify the link that a valid usb data byte is on data[7:0] in the current cycle. the isp1507 always drives an rxcmd when dir is high and nxt is low, unless register read data is to be returned to the link in the current cycle. nxt is not used in low-power or serial mode. table 4. ulpi signal description continued signal name direction on isp1507 signal description table 5. signal mapping during low-power mode signal maps to direction description linestate0 data0 o combinatorial linestate0 directly driven by analog receiver linestate1 data1 o combinatorial linestate1 directly driven by analog receiver
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 17 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 8.1.3 6-pin full-speed or low-speed serial mode if the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed usb data, it can set the isp1507 to 6-pin serial mode. in 6-pin serial mode, the data[7:0] bus de?nition changes to that shown in t ab le 6 . to enter 6-pin serial mode, the link sets the 6pin_fsls_serial bit in the intf_ctrl register (see section 10.1.3 ) to logic 1. to exit 6-pin serial mode, the link asserts stp. this is provided primarily for links that contain legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path to high-speed. an interrupt pin is also provided to inform the link of usb events. if the link requires clock to be running during 6-pin serial mode, the clock_suspendm register bit must be set to logic 1. for more information on 6-pin serial mode enter and exit protocols, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . 8.1.4 3-pin full-speed or low-speed serial mode if the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed usb data, it can set the isp1507 to 3-pin serial mode. in 3-pin serial mode, the data bus de?nition changes to that shown in t ab le 7 . to enter 3-pin serial mode, the link sets the 3pin_fsls_serial bit in the intf_ctrl register (see section 10.1.3 ) to logic 1. to exit 3-pin serial mode, the link asserts stp. this is primarily provided for links that contain legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path to high-speed. an interrupt pin is also provided to inform the link of usb events. if the link requires clock to be running during 3-pin serial mode, the clock_suspendm register bit must be set to logic 1. for more information on 3-pin serial mode enter and exit protocols, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . reserved data2 o reserved; the isp1507 will drive this pin to low int data3 o active high interrupt indication; will be asserted whenever any unmasked interrupt occurs reserved data[7:4] o reserved; the isp1507 will drive these pins to low table 5. signal mapping during low-power mode continued signal maps to direction description table 6. signal mapping for 6-pin serial mode signal maps to direction description tx_enable data0 i active high transmit enable tx_dat data1 i transmit differential data on dp and dm tx_se0 data2 i transmit single-ended zero on dp and dm int data3 o active high interrupt indication; will be asserted whenever any unmasked interrupt occurs rx_dp data4 o single-ended receive data from dp rx_dm data5 o single-ended receive data from dm rx_rcv data6 o differential receive data from dp and dm reserved data7 o reserved; the isp1507 will drive this pin to low
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 18 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 8.2 usb and otg state transitions a hi-speed usb peripheral, host or otg device handles more than one electrical state as de?ned in universal serial bus speci?cation rev. 2.0 and on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 . the isp1507 accommodates various states through register bit settings of xcvrselect[1:0], termselect, opmode[1:0], dp_pulldown and dm_pulldown. t ab le 8 summarizes operating states. the values of register settings in t ab le 8 will force resistor settings as also given in t ab le 8 . resistor setting signals are de?ned as follows: ? rpu_dp_en enables the 1.5 k w pull-up resistor on dp ? rpd_dp_en enables the 15 k w pull-down resistor on dp ? rpd_dm_en enables the 15 k w pull-down resistor on dm ? hsterm_en enables the 45 w termination resistors on dp and dm it is up to the link to set the desired register settings. table 7. signal mapping for 3-pin serial mode signal maps to direction description tx_enable data0 i active high transmit enable dat data1 i/o transmit differential data on dp and dm when tx_enable is high receive differential data from dp and dm when tx_enable is low se0 data2 i/o transmit single-ended zero on dp and dm when tx_enable is high receive single-ended zero from dp and dm when tx_enable is low int data3 o active high interrupt indication; will be asserted whenever any unmasked interrupt occurs reserved data[7:4] o reserved; the isp1507 will drive these pins to low table 8. operating states and their corresponding resistor settings signaling mode register settings internal resistor settings xcvr select [1:0] term select opmode [1:0] dp_pull down dm_pull down rpu_ dp_en rpd_ dp_en rpd_ dm_en hsterm _en general settings 3-state drivers xxb xb 01b xb xb 0b 0b 0b 0b power-up or v bus isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 19 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver host low-speed suspend 10b 1b 00b 1b 1b 0b 1b 1b 0b host low-speed resume 10b 1b 10b 1b 1b 0b 1b 1b 0b host test j or test k 00b 0b 10b 1b 1b 0b 1b 1b 1b peripheral settings peripheral chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b peripheral high-speed 00b 0b 00b 0b 0b 0b 0b 0b 1b peripheral full-speed 01b 1b 00b 0b 0b 1b 0b 0b 0b peripheral high-speed or full-speed suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b peripheral high-speed or full-speed resume 01b 1b 10b 0b 0b 1b 0b 0b 0b peripheral test j or test k 00b 0b 10b 0b 0b 0b 0b 0b 1b otg settings otg device peripheral chirp 00b 1b 10b 0b 1b 1b 0b 1b 0b otg device peripheral high-speed 00b 0b 00b 0b 1b 0b 0b 1b 1b otg device peripheral full-speed 01b 1b 00b 0b 1b 1b 0b 1b 0b otg device peripheral high-speed and full-speed suspend 01b 1b 00b 0b 1b 1b 0b 1b 0b otg device peripheral high-speed and full-speed resume 01b 1b 10b 0b 1b 1b 0b 1b 0b otg device peripheral test j or test k 00b 0b 10b 0b 1b 0b 0b 1b 1b table 8. operating states and their corresponding resistor settings continued signaling mode register settings internal resistor settings xcvr select [1:0] term select opmode [1:0] dp_pull down dm_pull down rpu_ dp_en rpd_ dp_en rpd_ dm_en hsterm _en
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 20 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9. protocol description the following subsections describe the protocol for using the isp1507. 9.1 ulpi references the isp1507 provides a 12-pin ulpi interface to communicate with the link. it is highly recommended that you read utmi+ low pin interface (ulpi) speci?cation rev. 1.1 and utmi+ speci?cation rev. 1.0 . 9.2 power-on reset (por) an internal por is generated when reg1v8 rises above v por(trip) , for at least t w(reg1v8_h) . the internal por pulse will also be generated whenever reg1v8 drops below v por(trip) for more than t w(reg1v8_l) , and then rises above v por(trip) again. the voltage on reg1v8 is generated from v cc . to give a better view of the functionality, figure 5 shows a possible curve of reg1v8. the internal por starts with logic 0 at t0. at t1, the detector will see the passing of the trip level so that por turns to logic 1 and a delay element will add another t porp before it drops to logic 0. if reg1v8 dips from t2 to t3 for > t w(reg1v8_l) , another por pulse is generated. if the dip at t4 to t5 is too short, that is, < t w(reg1v8_l) , the internal por pulse will not react and will remain low. 9.3 power-up, reset and bus idle sequence figure 6 shows a typical start-up sequence. on power-up, the isp1507 performs an internal power-on reset and asserts dir to indicate to the link that the ulpi bus cannot be used. when the internal pll is stable, the isp1507 deasserts dir. the power-up time depends on the v cc supply rise time, the crystal start-up time, and pll start-up time t startup(o)(clock) . whenever dir is asserted, the isp1507 drives the nxt pin to low and drives data[7:0] with rxcmd values. when dir is deasserted, the link must drive the data bus to a valid level. by default, the link must drive data to low. when the isp1507 initially deasserts dir on power-up, the link must ignore all rxcmds until it resets the isp1507. before beginning usb packets, the link must set the reset bit in the func_ctrl register (see section 10.1.2 ) to reset the isp1507. after the reset bit is set, the isp1507 will assert dir until the internal reset completes. the isp1507 will automatically deassert dir and clear the reset bit when reset has completed. after every reset, an rxcmd is sent to the link to update usb status information. after this sequence, the ulpi bus is ready for use and the link can start usb operations. fig 5. internal power-on reset timing 004aaa751 reg1v8 t0 t1 t2 t3 t4 t5 v por(trip) t porp por t porp
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 21 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver if a crystal is attached or a clock is driven into the xtal1 pin, the isp1507 will drive a 60 mhz clock out from the clock pin when dir deasserts. this is shown as clock in figure 6 . the recommended power-up sequence for the link is as follows: 1. the link waits for 1 ms, ignoring all the ulpi pin status. 2. the link may start to detect dir status level. if dir is detected as low for three clock cycles, the link may send a reset command. the ulpi interface is ready for use.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 22 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.3.1 interface protection by default, the isp1507 enables a weak pull-up resistor on stp. if the stp pin is unexpectedly high at any time, the isp1507 will protect the ulpi interface by enabling weak pull-down resistors on data[7:0]. the interface protect feature prevents unwanted activity of the isp1507 whenever the ulpi interface is not correctly driven by the link. for example, when the link powers up more slowly than the isp1507. t1 = v cc and v cc(i/o) are applied to the isp1507. the isp1507 regulator starts to turn on. t2 = ulpi pads detect reg1v8 rising above the reg1v8 regulator threshold and are not in 3-state. these pads may drive either low or high. it is recommended that the link ignores the ulpi pins status during t pwrup . t3 = the por threshold is reached and a por pulse is generated. after the por pulse, ulpi pins are driven to a de?ned level. dir is driven to high and the other pins are driven to low. t4 = the internal pll is stabilized after t startup(pll) . if the 19.2 mhz or 26 mhz clock is started before por, the internal pll will be stabilized after t startup(pll) from por. the clock pin starts to output 60 mhz. the dir pin will transition from high to low. the dir pin will remain low before the link issues a reset command to the isp1507. t5 = the power-up sequence is completed and the ulpi bus interface is ready for use. fig 6. power-up and reset sequence required before the ulpi bus is ready for use clock txcmd dir data[7:0] stp nxt 004aaa885 reset command internal clocks stable internal reset rxcmd update bus idle d v cc v cc(i/o) reg1v8 internal reg1v8 detector internal por xtal1 t startup(pll) t1 t2 t3 t4 t5 t pwrup
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 23 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver the interface protect feature can be disabled by setting the intf_prot_dis bit to logic 1. 9.3.2 interface behavior with respect to reset_n the use of the reset_n pin is optional. when reset_n is asserted (low), the isp1507 will assert dir. all logic in the isp1507 will be reset, including the analog circuitry and ulpi registers. during reset, the link must drive data[7:0] and stp to low; otherwise unde?ned behavior may result. when reset_n is deasserted (high), the dir output will deassert (low) four or ?ve clock cycles later. figure 7 shows the ulpi interface behavior when reset_n is asserted (low), and subsequently deasserted (high). the behavior of figure 7 applies only when chip_select_n is asserted (low). if reset_n is not used, it must be connected to v cc(i/o) . 9.3.3 interface behavior with respect to chip_select_n at any time that chip_select_n is high, the isp1507 will 3-state data[7:0], nxt and dir. stp input will be ignored. the link can reuse these pins for other purposes. when chip_select_n is low, ulpi output pins operate normally. during normal operation, the pll is always powered, regardless of the level of chip_select_n. during power-up, if chip_select_n is high, the pll is not powered up to reduce power consumption. during power-up, if chip_select_n is low, the pll is powered and the isp1507 operates normally. if chip_select_n is high: ? the data[7:0], nxt and dir pins are 3-stated and ignored. ? if the isp1507 was previously in synchronous mode, the stp pin is ignored. if the isp1507 was previously in serial or suspend mode, stp is used to exit. ? the pull-down resistors on data[7:0] are disabled. ? the ulpi controller is forced into an idle state and any ulpi command is ignored. fig 7. interface behavior with respect to reset_n clock 004aaa720 stp reset_n data[7:0] dir nxt hi-z (input) hi-z (input) hi-z (input) hi-z (input) hi-z (link must drive) hi-z (link must drive)
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 24 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver fig 8. entering and exiting 3-state in normal mode clock 004aaa690 chip_ select_n entering 3-state mode exiting 3-state mode 3-stated pins data[7:0] dir nxt stp input ignored remark: clock timing is not to scale. fig 9. entering and exiting 3-state in suspend mode clock 004aaa691 chip_ select_n entering 3-state mode exiting 3-state mode 3-stated pins data[7:0] dir nxt stp txcmd data entering suspend mode exiting suspend mode suspendm input ignored
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 25 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.4 v bus power and fault detection 9.4.1 driving 5 v on v bus the isp1507 provides a built-in charge pump. to enable the charge pump, the link must set the drv_vbus bit in the otg_ctrl register (see section 10.1.4 ). the isp1507 also supports external 5 v supplies. the isp1507 can control the external supply using the active-low psw_n open-drain output pin. to enable the external supply by driving psw_n to low, the link must set the drv_vbus_ext bit in the otg_ctrl register to logic 1. the link can optionally set both the drv_vbus and drv_vbus_ext bits to logic 1 to enable the external supply. t ab le 9 summarizes settings to drive 5 v on v bus . 9.4.2 fault detection the isp1507 supports external v bus fault detector circuits that output a digital fault indicator signal. the indicator signal must be connected to the fault pin. to enable the isp1507 to monitor the digital fault input, the link must set the use_ext_vbus_ind bit in the otg_ctrl register (see section 10.1.4 ) and the ind_passthru bit in the intf_ctrl register (see section 10.1.3 ) to logic 1. for details, see figure 11 . the fault input pin is mapped to the a_vbus_vld bit in rxcmd. any changes for the fault input will trigger rxcmd carrying the fault condition with a_vbus_vld. 9.5 txcmd and rxcmd commands between the isp1507 and the link are described in the following subsections. 9.5.1 txcmd by default, the link must drive the ulpi bus to its idle state of 00h. to send commands and usb packets, the link drives a nonzero value on data[7:0] to the isp1507 by sending a byte called txcmd. commands include usb packet transmissions, and register reads and writes. once the txcmd is interpreted and accepted by the isp1507, the nxt signal is asserted and the link can follow up with the required number of data bytes. the txcmd byte format is given in t ab le 10 . any values other than those in t ab le 10 are illegal and may result in unde?ned behavior. various txcmd packet and register sequences are shown in later sections. table 9. otg_ctrl register power control bits drv_vbus drv_vbus_ext power source used 0 0 internal and external v bus power sources are disabled 1 0 internal v bus charge pump is enabled x 1 external 5 v v bus supply is enabled
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 26 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.5.2 rxcmd the isp1507 communicates status information to the link by asserting dir and sending an rxcmd byte on the data bus. the rxcmd data byte format is given in t ab le 11 . the isp1507 will automatically send an rxcmd whenever there is a change in any of the rxcmd data ?elds. the link must be able to accept an rxcmd at any time; including single rxcmds, back-to-back rxcmds, and rxcmds at any time during usb receive packets when nxt is low. an example is shown in figure 10 . for details and diagrams, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . an rxcmd may not be sent when exiting low-power mode or serial mode, if the interrupt condition is removed before exiting. table 10. txcmd byte format command type name command code data[7:6] command payload data[5:0] command name command description idle 00b 00 0000b noop no operation. 00h is the idle value of the data bus. the link must drive noop by default. packet transmit 01b 00 0000b nopid transmit usb data that does not have a pid, such as chirp and resume signaling. the isp1507 starts transmitting only after accepting the next data byte. 00 xxxxb pid transmit usb packet. data[3:0] indicates usb packet identi?er pid[3:0]. register write 10b 10 1111b extw extended register write command (optional). the 8-bit address must be provided after the command is accepted. xx xxxxb regw register write command with 6-bit immediate address. register read 11b 10 1111b extr extended register read command (optional). the 8-bit address must be provided after the command is accepted. xx xxxxb regr register read command with 6-bit immediate address. table 11. rxcmd byte format data name description and value 1 to 0 linestate linestate signals : for a de?nition of linestate, see section 9.5.2.1 . data0 linestate[0] data1 linestate[1] 3to2 v bus state encoded v bus voltage state : for an explanation of the v bus state, see section 9.5.2.2 . 5 to 4 rxevent encoded usb event signals : for an explanation of rxevent, see section 9.5.2.4 . 6 id set to the value of the id pin. 7 alt_int by default, this signal is not used and is not needed in typical designs. optionally, the link can enable the bvalid_rise and/or bvalid_fall bits in the pwr_ctrl register (see section 10.1.14 ). corresponding changes in bvalid will cause an rxcmd to be sent to the link with the alt_int bit asserted.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 27 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.5.2.1 linestate encoding linestate[1:0] re?ects the current state of dp and dm. whenever the isp1507 detects a change in dp or dm, an rxcmd will be sent to the link with the new linestate[1:0] value. the value given on linestate[1:0] depends on the setting of various registers. t ab le 12 shows the linestate[1:0] encoding for upstream facing ports, which applies to peripherals. t ab le 13 shows the linestate[1:0] encoding for downstream facing ports, which applies to host controllers. dual-role devices must choose the correct table, depending on whether it is in peripheral or host mode. [1] !squelch indicates inactive squelch. !hs_differential_receiver_output indicates inactive hs_differential_receiver_output. fig 10. single and back-to-back rxcmds from the isp1507 to the link clock rxcmd data [ 7:0 ] rxcmd rxcmd 004aaa695 dir stp nxt single rxcmd back-to-back rxcmds turnaround turnaround turnaround turnaround table 12. linestate[1:0] encoding for upstream facing ports: peripheral dp_pulldown = 0. [1] mode full-speed high-speed chirp xcvrselect[1:0] 01, 11 00 00 termselect 1 0 1 linestate[1:0] 00 se0 squelch squelch 01 fs-j !squelch !squelch and hs_differential_receiver_output 10 fs-k invalid !squelch and !hs_differential_receiver_output 11 se1 invalid invalid
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 28 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver [1] !squelch indicates inactive squelch. !hs_differential_receiver_output indicates inactive hs_differential_receiver_output. 9.5.2.2 v bus state encoding usb devices must monitor the v bus voltage for purposes such as overcurrent detection, starting a session and srp. the v bus state ?eld in the rxcmd is an encoding of the voltage level on v bus . the sess_end and sess_vld indicators in the v bus state are directly taken from internal comparators built-in to the isp1507, and encoded as shown in t ab le 11 and t ab le 14 . the a_vbus_vld indicator in the v bus state provides several options and must be con?gured based on current draw requirements. a_vbus_vld can input from one or more v bus voltage indicators, as shown in figure 11 . a description on how to use and select the v bus state encoding is given in section 9.5.2.3 . table 13. linestate[1:0] encoding for downstream facing ports: host dp_pulldown and dm_pulldown = 1. [1] mode low-speed full-speed high-speed chirp xcvrselect[1:0] 10 01, 11 00 00 termselect 1 1 0 0 opmode[1:0] x x 00, 01 or 11 10 linestate[1:0] 00 se0 se0 squelch squelch 01 ls-k fs-j !squelch !squelch and hs_differential_receiver_output 10 ls-j fs-k invalid !squelch and !hs_differential_receiver_output 11 se1 se1 invalid invalid table 14. encoded v bus voltage state value v bus voltage sess_end sess_vld a_vbus_vld 00 v bus isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 29 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.5.2.3 using and selecting the v bus state encoding the v bus state encoding is shown in t ab le 11 . the isp1507 will send an rxcmd to the link whenever there is a change in the v bus state. to receive v bus state updates, the link must ?rst enable the corresponding interrupts in the usb_intr_en_r_e and usb_intr_en_f_e registers. the link can use the v bus state to monitor v bus and take appropriate action. t ab le 15 shows the recommended usage for typical applications. standard usb host controllers: for standard hosts, the system must be able to provide 500 ma on v bus in the range of 4.75 v to 5.25 v. an external circuit must be used to detect overcurrent conditions. if the external overcurrent detector provides a digital fault signal, then the fault signal must be connected to the isp1507 fault input pin, and the link must do the following: 1. set the ind_compl bit in the intf_ctrl register (see section 10.1.3 ) to logic 0 or logic 1, depending on the polarity of the external fault signal. 2. set the use_ext_vbus_ind bit in the otg_ctrl register (see section 10.1.4 ) to logic 1. 3. if it is not necessary to qualify the fault indicator with the internal a_vbus_vld comparator, set the ind_passthru bit in the intf_ctrl register to logic 1. standard usb peripheral controllers: standard peripherals must be able to detect when v bus is at a suf?cient level for operation. sess_vld must be enabled to detect the start and end of usb peripheral operations. detection of a_vbus_vld and sess_end thresholds is not needed for standard peripherals. fig 11. rxcmd a_vbus_vld indicator source 004aaa698 v bus (0, x) (1, 0) fault ind_compl (1, 1) use_ext_vbus_ind, ind_passthru rxcmd a_vbus_vld a_vbus_vld comparator internal a_vbus_vld complement output fault indicator table 15. v bus indicators in rxcmd required for typical applications application a_vbus_vld sess_vld sess_end standard host yes no no standard peripheral no yes no otg a-device yes yes no otg b-device no yes yes
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 30 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver otg devices: when an otg device is con?gured as an otg a-device, it must be able to provide a minimum of 8 ma on v bus . if the otg a-device provides less than 100 ma, then there is no need for an overcurrent detection circuit because the internal a_vbus_vld comparator is suf?cient. if the otg a-device provides more than 100 ma on v bus , an overcurrent detector must be used and section standard usb host controllers applies. the otg a-device also uses sess_vld to detect when an otg b-device is initiating v bus pulsing srp. when an otg device is con?gured as an otg b-device, sess_vld must be used to detect when v bus is at a suf?cient level for operation. sess_end must be used to detect when v bus has dropped to a low level, allowing the b-device to safely initiate v bus pulsing srp. 9.5.2.4 rxevent encoding the rxevent ?eld (see t ab le 16 ) of the rxcmd informs the link of information related packets received on the usb bus. rxactive and rxerror are de?ned in usb 2.0 transceiver macrocell interface (utmi) speci?cation ver. 1.05 . hostdisconnect is de?ned in utmi+ speci?cation rev. 1.0 . a short de?nition is also given in the following subsections. rxactive: when the isp1507 has detected a sync pattern on the usb bus, it signals an rxactive event to the link. an rxactive event can be communicated using two methods. the ?rst method is for the isp1507 to simultaneously assert dir and nxt. the second method is for the isp1507 to send an rxcmd to the link with the rxactive ?eld in rxevent bits set to logic 1. the link must be able to detect both methods. rxactive frames the receive packet from the ?rst byte to the last byte. the link must assume that rxactive is set to logic 0 when indicated in an rxcmd or when dir is deasserted, whichever occurs ?rst. the link uses rxactive to time high-speed packets and ensure that bus turnaround times are met. for more information on the usb packet timing, see section 9.8.1 . rxerror: when the isp1507 has detected an error while receiving a usb packet, it deasserts nxt and sends an rxcmd with the rxerror ?eld set to logic 1. the received packet is no longer valid and must be dropped by the link. hostdisconnect: hostdisconnect is encoded into the rxevent ?eld of the rxcmd. hostdisconnect is valid only when the isp1507 is con?gured as a host (both dp_pulldown and dm_pulldown are set to logic 1), and indicates to the host controller when a peripheral is connected or disconnected. the host controller must enable hostdisconnect by setting the host_discon_r and host_discon_f bits in the usb_intr_en_r_e and usb_intr_en_f_e registers, respectively. changes in hostdisconnect will cause the phy to send an rxcmd to the link with the updated value. table 16. encoded usb event signals value rxactive rxerror hostdisconnect 00 0 0 0 01 1 0 0 11 1 1 0 10 x x 1
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 31 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.6 register read and write operations figure 12 shows register read and write sequences. the isp1507 supports immediate addressing and extended addressing register operations. extended register addressing is optional for links. note that register operations will be aborted if the isp1507 unexpectedly asserts dir during the operation. when a register operation is aborted, the link must retry until successful. for more information on register operations, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . 9.7 usb reset and high-speed detection handshake (chirp) figure 13 shows the sequence of events for usb reset and high-speed detection handshake (chirp). the sequence is shown for hosts and peripherals. figure 13 does not show all rxcmd updates and timing is not to scale. the sequence is as follows: 1. usb reset: the host detects a peripheral attachment as low-speed if dm is high and as full-speed if dp is high. if a host detects a low-speed peripheral, it does not follow the remainder of this protocol. if a host detects a full-speed peripheral, it resets the peripheral by writing to the function control register (see section 10.1.2 ). xcvrselect[1:0] = 00b (high-speed) and termselect = 0b are then set which drives se0 on the bus (dp and dm are connected to ground through 45 w ). the host also sets opmode[1:0] = 10b for correct chirp transmit and receive. the start of se0 is labeled t 0 . remark: to receive chirp signaling, the host must also consider the high-speed differential receiver output. the host controller must interpret linestate[1:0] as shown in t ab le 13 . 2. high-speed detection handshake (chirp) a. peripheral chirp: after detecting se0 for no less than 2.5 m s, if the peripheral is capable of high-speed, it sets xcvrselect[1:0] = 00b (high-speed) and opmode[1:0] = 10b (chirp). the peripheral immediately follows this with a txcmd (nopid), transmitting a chirp k for no less than 1 ms and ending no more ad indicates the address byte, and d indicates the data byte. fig 12. example of register write, register read, extended register write and extended register read clock dir data[7:0] nxt 004aaa710 d txcmd (extw) ad d immediate register write txcmd (regw) txcmd (regr) d ad txcmd (extw) d stp extended register write immediate register read extended register read
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 32 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver than 7 ms after reset time t 0 . if the peripheral is in low-power mode, it must wake up its clock within 5.6 ms, leaving 200 m s for the link to start transmitting the chirp k, and 1.2 ms for the chirp k to complete (worst case with 10 % slow clock). b. host chirp: if the host does not detect the peripheral chirp, it must continue asserting se0 until the end of reset. if the host detects the peripheral chirp k for no less than 2.5 m s, then no more than 100 m s after the bus leaves the chirp k state, the host sends a txcmd (nopid) with an alternating sequence of chirp ks and js. each chirp k or chirp j must last no less than 40 m s and no longer than 60 m s. c. high-speed idle: the peripheral must detect a minimum of chirp k-j-k-j-k-j. each chirp k and chirp j must be detected for at least 2.5 m s. the peripheral sets termselect = 0b and opmode[1:0] = 00b after seeing the minimum chirp sequence. the peripheral is now in high-speed mode and sees !squelch (01b on linestate). when the peripheral sees squelch (10b on linestate), it knows that the host has completed chirp and waits for hi-speed usb traf?c to begin. after transmitting the chirp sequence, the host changes opmode[1:0] to 00b and begins sending usb packets. for more information, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 .
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 33 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver timing is not to scale. fig 13. usb reset and high-speed detection handshake (chirp) sequence 004aaa711 k data [ 7:0 ] k j txcmd nopid j ... txcmd (regw) txcmd (regw) se0 k dir 00 stp nxt xcvr select term select 01 (fs) 00 (hs) op mode 00 (normal) 01 (chirp) 00 (normal) line state j (01b) se0 (00b) peripheral chirp k (10b) squelch (00b) host chirp k (10b) or chirp j (01b) squelch (00b) ulpi host k data [ 7:0 ] k txcmd nopid k ... se0 txcmd (regw) 00 k j k j k j txcmd (regw) 00 dir stp nxt xcvr select 01 (fs) 00 (hs) term select op mode 00 (normal) 10 (chirp) 00 (normal) line state j (01b) se0 (00b) peripheral chirp k (10b) !squelch (01b) host chirp k or j (10b or 01b) squelch (00b) squelch (00b) dp dm ulpi peripheral usb signals usb reset high-speed detection handshake (chirp) peripheral chirp host chirp hs idle t 0 rxcmds
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 34 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.8 usb packet transmit and receive an example of a packet transmit and receive is shown in figure 14 . for details on usb packets, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . 9.8.1 usb packet timing 9.8.1.1 isp1507 pipeline delays the isp1507 delays are shown in t ab le 17 . for a detailed description, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1, section 3.8.2.6.2 . 9.8.1.2 allowed link decision time the amount of clock cycles allocated to the link to respond to a received packet and correctly receive back-to-back packets is given in t ab le 18 . link designs must follow values given in t ab le 18 for correct usb system operation. examples of high-speed packet sequences and timing are shown in figure 15 and figure 16 . for details, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1, section 3.8.2.6.3 . fig 14. example of using the isp1507 to transmit and receive usb data clock txcmd data[7:0] rxcmd data dir stp nxt 004aab039 link sends txcmd isp1507 accepts txcmd link sends the next data; isp1507 accepts link signals end of data ulpi bus is idle isp1507 asserts dir, causing turnaround cycle isp1507 sends rxcmd (nxt low) isp1507 sends usb data (nxt high) isp1507 deasserts dir, causing turnaround cycle turnaround turnaround data table 17. phy pipeline delays parameter name high-speed phy delay full-speed phy delay low-speed phy delay rxcmd delay (j and k) 4 4 4 rxcmd delay (se0) 4 4 to 6 16 to 18 tx start delay 1 to 2 6 to 10 74 to 75 tx end delay (packets) 3 to 4 not applicable not applicable tx end delay (sof) 6 to 9 not applicable not applicable rx start delay 5 to 6 not applicable not applicable rx end delay 5 to 6 17 to 18 122 to 123
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 35 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver table 18. link decision times packet sequence high-speed link delay full-speed link delay low-speed link delay de?nition transmit-transmit (host only) 15 to 24 7 to 18 77 to 247 number of clock cycles a host link must wait before driving the txcmd for the second packet. in high-speed, the link starts counting from the assertion of stp for the ?rst packet. in full-speed, the link starts counting from the rxcmd, indicating linestate has changed from se0 to j for the ?rst packet. the timing given ensures inter-packet delays of 2 bit times to 6.5 bit times. receive-transmit (host or peripheral) 1 to 14 7 to 18 77 to 247 number of clock cycles the link must wait before driving the txcmd for the transmit packet. in high-speed, the link starts counting from the end of the receive packet; deassertion of dir or an rxcmd, indicating rxactive is low. in full-speed or low-speed, the link starts counting from the rxcmd, indicating linestate has changed from se0 to j for the receive packet. the timing given ensures inter-packet delays of 2 bit times to 6.5 bit times. receive-receive (peripheral only) 1 1 1 minimum number of clock cycles between consecutive receive packets. the link must be able to receive both packets. transmit-receive (host or peripheral) 92 80 718 host or peripheral transmits a packet and will time-out after this number of clock cycles if a response is not received. any subsequent transmission can occur after this time. fig 15. high-speed transmit-to-transmit packet timing 004aaa712 dp or dm data eop idle sync clock d n - 1 d n data [7:0] d0 txcmd d1 dir stp nxt tx end delay (two to five clocks) link decision time (15 to 24 clocks) tx start delay (one to two clocks) usb interpacket delay (88 to 192 high-speed bit times)
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 36 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.9 preamble preamble packets are headers to low-speed packets that must travel over a full-speed bus, between a host and a hub. to enter preamble mode, the link sets xcvrselect[1:0] = 11b in the func_ctrl register (see section 10.1.2 ). when in preamble mode, the isp1507 operates just as in full-speed mode, and sends all data with the full-speed rise time and fall time. whenever the link transmits a usb packet in preamble mode, the isp1507 will automatically send a preamble header at full-speed bit rate before sending the link packet at low-speed bit rate. the isp1507 will ensure a minimum gap of four full-speed bit times between the last bit of the full-speed pre pid and the ?rst bit of the low-speed packet sync. the isp1507 will drive a j for at least one full-speed bit time after sending the pre pid, after which the pull-up resistor can hold the j state on the bus. an example transmit packet is shown in figure 17 . in preamble mode, the isp1507 can also receive low-speed packets from the full-speed bus. fig 16. high-speed receive-to-transmit packet timing 004aaa713 dp or dm data eop idle sync clock d n - 4 d n - 3 data [7:0] d0 txcmd d1 dir stp nxt rx end delay (three to eight clocks) link decision time (1 to 14 clocks) tx start delay (one to two clocks) usb interpacket delay (8 to 192 high-speed bit times) d n - 2 d n - 1 d n turnaround
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 37 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.10 usb suspend and resume 9.10.1 full-speed or low-speed host-initiated suspend and resume figure 18 illustrates how a host or a hub places a full-speed or low-speed peripheral into suspend and sometime later initiates resume signaling to wake up the downstream peripheral. note that figure 18 timing is not to scale, and does not show all rxcmd linestate updates. the sequence of events for a host and a peripheral, both with isp1507, is as follows: 1. idle: initially, the host and the peripheral are idle. the host has its 15 k w pull-down resistors enabled (dp_pulldown and dm_pulldown are set to 1b) and 45 w terminations disabled (termselect is set to 1b). the peripheral has the 1.5 k w pull-up resistor connected to dp for full-speed or dm for low-speed (termselect is set to 1b). 2. suspend: when the peripheral sees no bus activity for 3 ms, it enters the suspend state. the peripheral link places the phy into low-power mode by clearing the suspendm bit in the func_ctrl register (see section 10.1.2 ), causing the phy to draw only suspend current. the host may or may not be powered down. 3. resume k: when the host wants to wake up the peripheral, it sets opmode[1:0] to 10b and transmits a k for at least 20 ms. the peripheral link sees the resume k on linestate, and asserts stp to wake up the phy. 4. eop: when stp is asserted, the isp1507 on the host side automatically appends an eop of two bits of se0 at low-speed bit rate, followed by one bit of j. the isp1507 on the host side knows to add the eop because dp_pulldown and dm_pulldown are set to 1b for a host. after the eop is completed, the host link sets opmode[1:0] to 00b for normal operation. the peripheral link sees the eop and also resumes normal operation. dp and dm timing is not to scale. fig 17. preamble sequence clock d0 txcmd (low-speed packet id) d1 data[7:0] dir stp nxt 004aaa714 dp or dm fs sync fs pre id idle (min 4 fs bits) ls sync ls pid ls d0 ls d1
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 38 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.10.2 high-speed suspend and resume figure 19 illustrates how a host or a hub places a high-speed enabled peripheral into suspend and then initiates resume signaling. the high-speed peripheral will wake up and return to high-speed operations. note that figure 19 timing is not to scale, and does not show all rxcmd linestate updates. timing is not to scale. fig 18. full-speed suspend and resume data [ 7:0 ] k txcmd nopid k ... txcmd (regw) dir stp nxt opmode 00b 10b 00b k txcmd line state j k se0 j clock data [ 7:0 ] txcmd (regw) linestate j linestate k se0 j dir stp nxt opmode 00b 10b 00b suspendm line state j k se0 j dp dm 004aab123 fs or ls host (xcvrselect = 01b (fs) or 10b (ls), dp_pulldown = 1b, dm_pulldown = 1b, termselect = 1b) fs or ls peripheral (xcvrselect = 01b (fs) or 10b (ls), dp_pulldown = 0b, termselect = 1b) usb signals (only fs is shown) idle suspend resume k eop idle
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 39 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver the sequence of events related to a host and a peripheral, both with isp1507, is as follows: 1. high-speed idle: initially, the host and the peripheral are idle. the host has its 15 k w pull-down resistors enabled (dp_pulldown and dm_pulldown are set to 1b) and 45 w terminations enabled (termselect is set to 0b). the peripheral has its 45 w terminations enabled (termselect is set to 0b). 2. full-speed suspend: when the peripheral sees no bus activity for 3 ms, it enters the suspend state. the peripheral link places the isp1507 into full-speed mode (xcvrselect is set to 01b), removes 45 w terminations, and enables the 1.5 k w pull-up resistor on dp (termselect is set to 1b). the peripheral link then places the isp1507 into low-power mode by clearing suspendm, causing the isp1507 to draw only suspend current. the host also changes the isp1507 to full-speed (xcvrselect is set to 01b), removes 45 w terminations (termselect is set to 1b), and then may or may not be powered down. 3. resume k: when the host wants to wake up the peripheral, it sets opmode to 10b and transmits a full-speed k for at least 20 ms. the peripheral link sees the resume k (10b) on linestate, and asserts stp to wake up the isp1507. 4. high-speed traf?c: the host link sets high-speed (xcvrselect is set to 00b) and enables its 45 w terminations (termselect is set to 0b). the peripheral link sees se0 on linestate and also sets high-speed (xcvrselect is set to 00b), and enables its 45 w terminations (termselect is set to 0b). the host link sets opmode to 00b for normal high-speed operation.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 40 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver timing is not to scale. fig 19. high-speed suspend and resume data [ 7:0 ] k txcmd nopid k ... txcmd (regw) dir stp nxt op mode 00b 10b 00b k txcmd (regw) clock data [ 7:0 ] txcmd (regw) linestate j linestate k se0 txcmd (regw) dir stp nxt op mode 00b 10b 00b suspendm line state dp dm 004aab124 ulpi hs host (dp_pulldown = 1b, dm_pulldown = 1b) ulpi hs peripheral (dp_pulldown = 0b) usb signals hs idle fs suspend resume k txcmd (regw) hs idle xcvr select 00b 01b 00b term select line state !squelch (01b) fs j (01b) !squelch (01b) squelch (00b) fs k (10b) xcvr select 00b 01b 00b term select !squelch (01b) squelch (00b) fs j (01b) !squelch (01b) squelch (00b) fs k (10b) squelch (00b)
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 41 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.10.3 remote wake-up the isp1507 supports peripherals that initiate remote wake-up resume. when placed into usb suspend, the peripheral link remembers at what speed it was originally operating. depending on the original speed, the link follows one of the protocols detailed here. in figure 20 , timing is not to scale, and not all rxcmd linestate updates are shown. the sequence of events related to a host and a peripheral, both with isp1507, is as follows: 1. both the host and the peripheral are assumed to be in low-power mode. 2. the peripheral begins remote wake-up by re-enabling its clock and setting its suspendm bit to 1b. 3. the peripheral begins driving k on the bus to signal resume. note that the peripheral link must assume that linestate is k (01b) while transmitting because it will not receive any rxcmds. 4. the host recognizes the resume, re-enables its clock and sets its suspendm bit. 5. the host takes over resume driving within 1 ms of detecting the remote wake-up. 6. the peripheral stops driving resume. 7. the peripheral sees the host continuing to drive resume. 8. the host stops driving resume and the isp1507 automatically adds the eop to the end of resume. the peripheral recognizes the eop as the end of resume. 9. both the host and the peripheral revert to normal operation by writing 00b to opmode. if the host or the peripheral was previously in high-speed mode, it must revert to high-speed before the se0 of the eop is completed. this can be achieved by writing xcvrselect[1:0] = 00b and termselect = 0b after linestate indicates se0.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 42 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.11 no automatic sync and eop generation (optional) this setting allows the link to turn off the automatic sync and eop generation, and must be used for high-speed packets only. it is provided for backward compatibility with legacy controllers that include sync and eop bytes in the data payload when transmitting packets. the isp1507 will not automatically generate the sync and eop patterns when opmode[1:0] is set to 11b. the isp1507 will still nrzi encode data and perform bit stuf?ng. an example of a sequence is shown in figure 21 . the link must always send packets using the txcmd (nopid) type. the isp1507 does not provide a mechanism to control bit stuf?ng in individual bytes, but will automatically turn off bit stuf?ng for eop when stp is asserted with data set to feh. if data is set to 00h when stp is asserted, the timing is not to scale. fig 20. remote wake-up from low-power mode data [ 7:0 ] linestate txcmd regw txcmd regw 00h txcmd nopid dir stp nxt xcvr select 01b (fs), 10b (ls) 00b (hs only) term select op mode 10b 00b data [ 7:0 ] linestate txcmd regw rxcmd 00h txcmd nopid rxcmd rxcmd txcmd regw dir stp nxt xcvr select 00b (hs), 01b (fs), 10b (ls) 00b (hs only) term select op mode 10b 00b ulpi host ulpi peripheral 004aaa718 0b (hs only) 0b (hs only)
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 43 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver phy will not transmit any eop. the isp1507 will also detect if the pid byte is a5h, indicating an sof packet, and automatically send a long eop when stp is asserted. to transmit chirp and resume signaling, the link must set opmode to 10b. 9.12 on-the-go operations on-the-go (otg) is a supplement to universal serial bus speci?cation rev. 2.0 that allows a portable usb device to assume the role of a limited usb host by de?ning improvements, such as a small connector and low power. non-portable devices, such as standard hosts and embedded hosts, can also bene?t from otg features. the isp1507 otg phy is designed to support all the tasks speci?ed in the otg supplement. the isp1507 provides the front-end analog support for host negotiation protocol (hnp) and session request protocol (srp) for dual-role devices. the supporting components include: ? built-in 5 v charge pump ? voltage comparators C a_vbus_vld C sess_vld (session valid, can be used for both a-session and b-session valid) C sess_end (session end) ? pull-up and pull-down resistors on dp and dm ? id detector indicates if micro-a or micro-b plug is inserted ? charge and discharge resistors on v bus the following subsections describe how to use the isp1507 otg components. fig 21. transmitting usb packets without automatic sync and eop generation clock data [7:0] txcmd 00h 00h 00h 80h pid d1 d2 d3 ... ... d n - 1 feh d n dir stp nxt ulpi signals txvalid txready txbit stuff enable dp, dm idle sync pid idle eop data payload 004aab125 utmi+ equivalent signals usb bus
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 44 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.12.1 otg charge pump a description of the charge pump is given in section 7.6.4 . when the controller is con?gured as an a-device, it can provide the v bus power by turning on the charge pump. control of the charge pump is described in section 9.4.1 and section 10.1.4 . 9.12.2 otg comparators the isp1507 provides comparators that conform to on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 requirements of v a_vbus_vld , v a_sess_vld , v b_sess_vld and v b_sess_end . in this data sheet, v a_sess_vld and v b_sess_vld are combined into v b_sess_vld . comparators are described in section 7.6.2 . changes in comparator values are communicated to the link by rxcmds as described in section 9.5.2.2 . control over comparators is described in section 10.1.5 to section 10.1.8 . 9.12.3 pull-up and pull-down resistors the usb resistors on dp and dm can be used to initiate data-line pulsing srp. the link must set the required bus state using mode settings in t ab le 8 . 9.12.4 id detection the isp1507 provides an internal pull-up resistor to sense the value of the id pin. the pull-up resistor must ?rst be enabled by setting the id_pullup register bit to logic 1. if the value on id has changed, the isp1507 will send an rxcmd or interrupt to the link by time t id . if the link does not receive any rxcmd or interrupt by t id , then the id value has not changed. 9.12.5 v bus charge and discharge resistors a pull-up resistor, r up(vbus) , is provided to perform v bus pulsing srp. a b-device is allowed to charge v bus above the session valid threshold to request the host to turn on the v bus power. a pull-down resistor, r dn(vbus) , is provided for a b-device to discharge v bus . this is done whenever the a-device turns off the v bus power. the b-device can use the pull-down resistor to ensure v bus is below v b_sess_end before starting a session. for details, refer to on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 . 9.13 serial modes the isp1507 supports both 6-pin serial mode and 3-pin serial mode, controlled by bits 6pin_fsls_serial and 3pin_fsls_serial of the intf_ctrl register (see section 10.1.3 ). for details, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1, section 3.10 . figure 22 and figure 23 provide examples of 6-pin serial mode and 3-pin serial mode, respectively.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 45 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver fig 22. example of transmit followed by receive in 6-pin serial mode data0 (tx_enable) data1 (tx_dat) data2 (tx_se0) data4 (rx_dp) data5 (rx_dm) data6 (rx_rcv) dp dm sync data eop transmit receive sync data eop 004aaa692 fig 23. example of transmit followed by receive in 3-pin serial mode data0 (tx_enable) data1 (tx_dat/ rx_rcv) dp data2 (tx_se0/ rx_se0) dm 004aaa693 sync data eop transmit receive sync data eop
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 46 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 9.14 aborting transfers the isp1507 supports aborting transfers on the ulpi bus. for details, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1, section 3.8.4 . 9.15 avoiding contention on the ulpi data bus because the ulpi data bus is bidirectional, avoid situations in which both the link and the phy simultaneously drive the data bus. the following points must be considered while implementing the data bus drive control on the link. after power-up and clock stabilization, default states are as follows: ? the isp1507 drives dir to low. ? the data bus is input to the isp1507. ? the ulpi link data bus is output, with all data bus lines driven to low. when the isp1507 wants to take control of the data bus to initiate a data transfer, it changes the dir value from low to high. at this point, the link must disable its output buffers. this must be as fast as possible so the link must use a combinational path from dir. the isp1507 will not immediately enable its output buffers, but will delay the enabling of its buffers until the next clock edge, avoiding bus contention. when the data transfer is no longer required by the isp1507, it changes dir from high to low and starts to immediately turn off its output drivers. the link senses the change of dir from high to low, but delays enabling its output buffers for one clock cycle, avoiding data bus contention.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 47 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 10. register map [1] read (r): a register can be read. read-only if this is the only mode given. [2] write (w): the pattern on the data bus will be written over all bits of a register. [3] set (s): the pattern on the data bus is or-ed with and written to a register. [4] clear (c): the pattern on the data bus is a mask. if a bit in the mask is set, then the corresponding register bit will be s et to zero (cleared). [1] read (r): a register can be read. read-only if this is the only mode given. [2] write (w): the pattern on the data bus will be written over all bits of a register. [3] set (s): the pattern on the data bus is or-ed with and written to a register. [4] clear (c): the pattern on the data bus is a mask. if a bit in the mask is set, then the corresponding register bit will be s et to zero (cleared). table 19. immediate register set overview field name size (bit) address (6 bit) references r [1] w [2] s [3] c [4] vendor_id_low 8 00h - - - section 10.1.1 on page 48 vendor_id_high 8 01h - - - product_id_low 8 02h - - - product_id_high 8 03h - - - func_ctrl 8 04h to 06h 04h 05h 06h section 10.1.2 on page 48 intf_ctrl 8 07h to 09h 07h 08h 09h section 10.1.3 on page 49 otg_ctrl 8 0ah to 0ch 0ah 0bh 0ch section 10.1.4 on page 51 usb_intr_en_r_e 8 0dh to 0fh 0dh 0eh 0fh section 10.1.5 on page 52 usb_intr_en_f_e 8 10h to 12h 10h 11h 12h section 10.1.6 on page 52 usb_intr_stat 8 13h - - - section 10.1.7 on page 53 usb_intr_l 8 14h - - - section 10.1.8 on page 53 debug 8 15h - - - section 10.1.9 on page 54 scratch 8 16h to 18h 16h 17h 18h section 10.1.10 on page 54 reserved (do not use) - 19h to 2eh section 10.1.11 on page 55 access extended register set 8 - 2fh - - section 10.1.12 on page 55 vendor-speci?c registers 8 30h to 3ch section 10.1.13 on page 55 pwr_ctrl 8 3dh to 3fh section 10.1.14 on page 55 table 20. extended register set overview field name size (bit) address (6 bit) references r [1] w [2] s [3] c [4] maps to immediate register set above 8 00h to 3fh section 10.2 on page 55 reserved (do not use) 8 40h to ffh
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 48 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 10.1 immediate register set 10.1.1 vendor id and product id registers 10.1.1.1 vendor_id_low register t ab le 21 shows the bit description of the register. 10.1.1.2 vendor_id_high register the bit description of the register is given in t ab le 22 . 10.1.1.3 product_id_low register the bit description of the product_id_low register is given in t ab le 23 . 10.1.1.4 product_id_high register the bit description of the register is given in t ab le 24 . 10.1.2 func_ctrl register this register controls utmi function settings of the phy. the bit allocation of the register is given in t ab le 25 . table 21. vendor_id_low - vendor id low register (address r = 00h) bit description bit symbol access value description 7 to 0 vendor_id_ low[7:0] r cch vendor id low : lower byte of the nxp vendor id supplied by usb-if; has a ?xed value of cch table 22. vendor_id_high - vendor id high register (address r = 01h) bit description bit symbol access value description 7 to 0 vendor_id_ high[7:0] r 04h vendor id high : upper byte of the nxp vendor id supplied by usb-if; has a ?xed value of 04h table 23. product_id_low - product id low register (address r = 02h) bit description bit symbol access value description 7 to 0 product_id_ low[7:0] r 04h product id low : lower byte of the nxp product id number; has a ?xed value of 04h table 24. product_id_high - product id high register (address r = 03h) bit description bit symbol access value description 7 to 0 product_id_ high[7:0] r 15h product id high : upper byte of the nxp product id number; has a ?xed value of 15h table 25. func_ctrl - function control register (address r = 04h to 06h, w = 04h, s = 05h, c = 06h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved suspendm reset opmode[1:0] term select xcvrselect[1:0] reset 0 1000001 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 49 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 10.1.3 intf_ctrl register the intf_ctrl register enables alternative interfaces. all of these modes are optional features provided for legacy link cores. setting more than one of these ?elds results in unde?ned behavior. t ab le 27 provides the bit allocation of the register. table 26. func_ctrl - function control register (address r = 04h to 06h, w = 04h, s = 05h, c = 06h) bit description bit symbol description 7 - reserved 6 suspendm suspend low : active low phy suspend. places the phy into low-power mode. the phy will power down all blocks, except the full-speed receiver, otg comparators and ulpi interface pins. to come out of low-power mode, the link must assert stp. the phy will automatically clear this bit when it exits low-power mode. 0b low-power mode 1b powered (default) 5 reset reset : active high transceiver reset. after the link sets this bit, the phy will assert dir and reset the digital core. this does not reset the ulpi interface or the ulpi register set. when reset is completed, the phy will deassert dir and automatically clear this bit, followed by an rxcmd update to the link. 0b do not reset (default) 1b reset the link must wait for dir to deassert before using the ulpi bus. does not reset the ulpi interface or the ulpi register set. 4 to 3 opmode[1:0] operation mode : selects the required bit-encoding style during transmit. 00b normal operation (default) 01b non-driving 10b disable bit-stuf?ng and nrzi encoding 11b do not automatically add sync and eop when transmitting; must be used only for high-speed packets 2 termselect termination select : controls the internal 1.5 k w full-speed pull-up resistor and 45 w high-speed terminations. control over bus resistors changes, depending on xcvrselect[1:0], opmode[1:0], dp_pulldown and dm_pulldown, as shown in t ab le 8 . 1 to 0 xcvrselect [1:0] transceiver select : selects the required transceiver speed. 00b enable the high-speed transceiver 01b enable the full-speed transceiver (default) 10b enable the low-speed transceiver 11b enable the full-speed transceiver for low-speed packets (full-speed preamble is automatically pre?xed)
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 50 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver table 27. intf_ctrl - interface control register (address r = 07h to 09h, w = 07h, s = 08h, c = 09h) bit allocation bit 7 6 5 4 3 2 1 0 symbol intf_ prot_dis ind_pass thru ind_ compl reserved clock_ suspendm reserved 3pin_fsls _serial 6pin_fsls _serial reset 0000 0000 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c table 28. intf_ctrl - interface control register (address r = 07h to 09h, w = 07h, s = 08h, c = 09h) bit description bit symbol description 7 intf_prot_dis interface protect disable : controls circuitry built into the isp1507 to protect the ulpi interface when the link 3-states stp and data[7:0]. when this bit is enabled, the isp1507 will automatically detect when the link stops driving stp. 0b enables the interface protect circuit (default). the isp1507 attaches a weak pull-up resistor on stp. if stp is unexpectedly high, the isp1507 attaches weak pull-down resistors on data[7:0], protecting data inputs. 1b disables the interface protect circuit, detaches weak pull-down resistors on data[7:0], and a weak pull-up resistor on stp. 6 ind_passthru indicator pass-through : controls whether the complement output is quali?ed with the internal a_vbus_vld comparator before being used in the v bus state in rxcmd. for details, see section 9.5.2.2 . 0b the complement output signal is quali?ed with the internal a_vbus_vld comparator (default). 1b the complement output signal is not quali?ed with the internal a_vbus_vld comparator. 5 ind_compl indicator complement : informs the phy to invert the fault input signal, generating the complement output. for details, see section 9.5.2.2 . 0b the isp1507 will not invert the fault signal (default). 1b the isp1507 will invert the fault signal. 4 - reserved 3 clock_suspendm clock suspend low : active low clock suspend. powers down the internal clock circuitry only. by default, the clock will not be powered in 6-pin serial mode or 3-pin serial mode. valid only in 6-pin serial mode and 3-pin serial mode. valid only when suspendm is set to logic 1, otherwise this bit is ignored. 0b clock will not be powered in 3-pin or 6-pin serial mode (default). 1b clock will be powered in 3-pin and 6-pin serial mode. 2 - reserved 1 3pin_fsls_serial 3-pin full-speed low-speed serial mode : changes the ulpi interface to a 3-bit serial interface. the phy will automatically clear this bit when 3-pin serial mode is exited. 0b full-speed or low-speed packets are sent using the parallel interface (default). 1b full-speed or low-speed packets are sent using the 3-pin serial interface. 0 6pin_fsls_serial 6-pin full-speed low-speed serial mode : changes the ulpi interface to a 6-bit serial interface. the phy will automatically clear this bit when 6-pin serial mode is exited. 0b full-speed or low-speed packets are sent using the parallel interface (default). 1b full-speed or low-speed packets are sent using the 6-pin serial interface.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 51 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 10.1.4 otg_ctrl register this register controls various otg functions of the isp1507. the bit allocation of the otg_ctrl register is given in t ab le 29 . table 29. otg_ctrl - otg control register (address r = 0ah to 0ch, w = 0ah, s = 0bh, c = 0ch) bit allocation bit 7 6 5 4 3 2 1 0 symbol use_ext_ vbus_ind drv_ vbus_ext drv_ vbus chrg_ vbus dischrg_ vbus dm_pull down dp_pull down id_pull up reset 00000110 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c table 30. otg_ctrl - otg control register (address r = 0ah to 0ch, w = 0ah, s = 0bh, c = 0ch) bit description bit symbol description 7 use_ext_vbus_ ind use external v bus indicator : informs the phy to use an external v bus overcurrent indicator. 0b use the internal otg comparator (default). 1b use the external v bus valid indicator signal input from the fault pin. 6 drv_vbus_ext drive v bus external : selects between the internal and external 5 v v bus supply. using an external charge pump or a 5 v supply is optional. 0b drive v bus using the internal charge pump. also ensures psw_n is not driven to low (default). 1b drive v bus using the external charge pump or the 5 v supply. drives psw_n to low. 5 drv_vbus drive v bus : signals the isp1507 to drive 5 v on v bus . if drv_vbus_ext is set to logic 1, then setting drv_vbus is optional. 0b do not drive v bus (default). 1b drive 5 v on v bus . 4 chrg_vbus charge v bus : charges v bus through a resistor. used for the v bus pulsing srp. the link must ?rst check that v bus is discharged (see bit dischrg_vbus), and that both the dp and dm data lines have been low (se0) for 2 ms. 0b do not charge v bus (default). 1b charge v bus . 3 dischrg_vbus discharge v bus : discharges v bus through a resistor. if the link sets this bit to logic 1, it waits for an rxcmd indicating that sess_end has changed from 0 to 1, and then resets this bit to 0 to stop the discharge. 0b do not discharge v bus (default). 1b discharge v bus .
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 52 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 10.1.5 usb_intr_en_r_e register the bits in this register enable interrupts and rxcmds to be sent when the corresponding bits in the usb_intr_stat register change from logic 0 to logic 1. by default, all transitions are enabled. t ab le 31 shows the bit allocation of the register. 10.1.6 usb_intr_en_f_e register the bits in this register enable interrupts and rxcmds to be sent when the corresponding bits in the usb_intr_stat register change from logic 1 to logic 0. by default, all transitions are enabled. see t ab le 33 . 2 dm_pulldown dm pull down : enables the 15 k w pull-down resistor on dm. 0b pull-down resistor is not connected to dm. 1b pull-down resistor is connected to dm (default). 1 dp_pulldown dp pull down : enables the 15 k w pull-down resistor on dp. 0b pull-down resistor is not connected to dp. 1b pull-down resistor is connected to dp (default). 0 id_pullup id pull up : connects a pull-up to the id line and enables sampling of the id level. disabling the id line sampler will reduce phy power consumption. 0b disables sampling of the id line (default). 1b enables sampling of the id line. table 30. otg_ctrl - otg control register (address r = 0ah to 0ch, w = 0ah, s = 0bh, c = 0ch) bit description continued bit symbol description table 31. usb_intr_en_r_e - usb interrupt enable rising edge register (address r = 0dh to 0fh, w = 0dh, s = 0eh, c = 0fh) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved id_gnd_r sess_ end_r sess_ valid_r vbus_ valid_r host_ discon_r reset 00011111 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c table 32. usb_intr_en_r_e - usb interrupt enable rising edge register (address r = 0dh to 0fh, w = 0dh, s = 0eh, c = 0fh) bit description bit symbol description 7 to 5 - reserved 4 id_gnd_r id ground rise : enables interrupts and rxcmds for logic 0 to logic 1 transitions on id_gnd. 3 sess_end_r session end rise : enables interrupts and rxcmds for logic 0 to logic 1 transitions on sess_end. 2 sess_valid_r session valid rise : enables interrupts and rxcmds for logic 0 to logic 1 transitions on sess_vld. 1 vbus_valid_r v bus valid rise : enables interrupts and rxcmds for logic 0 to logic 1 transitions on a_vbus_vld. 0 host_discon_ r host disconnect rise : enables interrupts and rxcmds for logic 0 to logic 1 transitions on host_discon.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 53 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 10.1.7 usb_intr_stat register this register (see t ab le 35 ) indicates the current value of the interrupt source signal. 10.1.8 usb_intr_l register the bits of the usb_intr_l register are automatically set by the isp1507 when an unmasked change occurs on the corresponding interrupt source signal. the isp1507 will automatically clear all bits when the link reads this register, or when the phy enters low-power mode. table 33. usb_intr_en_f_e - usb interrupt enable falling edge register (address r = 10h to 12h, w = 10h, s = 11h, c = 12h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved id_gnd_f sess_ end_f sess_ valid_f vbus_ valid_f host_ discon_f reset 00011111 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c table 34. usb_intr_en_f_e - usb interrupt enable falling edge register (address r = 10h to 12h, w = 10h, s = 11h, c = 12h) bit description bit symbol description 7 to 5 - reserved 4 id_gnd_f id ground fall : enables interrupts and rxcmds for logic 1 to logic 0 transitions on id_gnd. 3 sess_end_f session end fall : enables interrupts and rxcmds for logic 1 to logic 0 transitions on sess_end. 2 sess_valid_f session valid fall : enables interrupts and rxcmds for logic 1 to logic 0 transitions on sess_vld. 1 vbus_valid_f v bus valid fall : enables interrupts and rxcmds for logic 1 to logic 0 transitions on a_vbus_vld. 0 host_discon _f host disconnect fall : enables interrupts and rxcmds for logic 1 to logic 0 transitions on host_discon. table 35. usb_intr_stat - usb interrupt status register (address r = 13h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved id_gnd sess_end sess_ valid vbus_ valid host_ discon reset xxx00000 access rrrrrrrr table 36. usb_intr_stat - usb interrupt status register (address r = 13h) bit description bit symbol description 7 to 5 - reserved 4 id_gnd id ground : re?ects the current value of the id detector circuit. 3 sess_end session end : re?ects the current value of the session end voltage comparator. 2 sess_valid session valid : re?ects the current value of the session valid voltage comparator. 1 vbus_valid v bus valid : re?ects the current value of the v bus valid voltage comparator. 0 host_discon host disconnect : re?ects the current value of the host disconnect detector.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 54 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver remark: it is optional for the link to read this register when the clock is running because all signal information will automatically be sent to the link through the rxcmd byte. the bit allocation of this register is given in t ab le 37 . 10.1.9 debug register the bit allocation of the debug register is given in t ab le 39 . this register indicates the current value of signals useful for debugging. 10.1.10 scratch register this is an empty register for testing purposes; see t ab le 41 . table 37. usb_intr_l - usb interrupt latch register (address r = 14h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved id_gnd_l sess_ end_l sess_ valid_l vbus_ valid_l host_ discon_l reset 00000000 access rrrrrrrr table 38. usb_intr_l - usb interrupt latch register (address r = 14h) bit description bit symbol description 7 to 5 - reserved 4 id_gnd_l id ground latch : automatically set when an unmasked event occurs on id_gnd. cleared when this register is read. 3 sess_end_l session end latch : automatically set when an unmasked event occurs on sess_end. cleared when this register is read. 2 sess_valid_l session valid latch : automatically set when an unmasked event occurs on sess_vld. cleared when this register is read. 1 vbus_valid_l v bus valid latch : automatically set when an unmasked event occurs on a_vbus_vld. cleared when this register is read. 0 host_discon_l host disconnect latch : automatically set when an unmasked event occurs on host_discon. cleared when this register is read. table 39. debug - debug register (address r = 15h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved line state1 line state0 reset 00000000 access rrrrrrrr table 40. debug - debug register (address r = 15h) bit description bit symbol description 7 to 2 - reserved 1 linestate1 line state 1 : contains the current value of linestate 1. 0 linestate0 line state 0 : contains the current value of linestate 0.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 55 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 10.1.11 reserved registers 19h to 2eh are not implemented. operating on these addresses will have no effect on the phy. 10.1.12 access extended register set address 2fh does not contain register data. instead it links to the extended register set. the immediate register set maps to the lower end of the extended register set. 10.1.13 vendor-speci?c registers addresses 30h to 3fh contain vendor-speci?c registers. 10.1.14 pwr_ctrl register this register controls various aspects of the isp1507. see t ab le 42 . 10.2 extended register set addresses 00h to 3fh of the extended register set directly map to the immediate set. this means a read, write, set or clear operation to these extended addresses will operate on the immediate register set. addresses 40h to ffh are not implemented. operating on these addresses may result in unde?ned behavior of the phy. table 41. scratch - scratch register (address r = 16h to 18h, w = 16h, s = 17h, c = 18h) bit description bit symbol access value description 7 to 0 scratch [7:0] r/w/s/c 00h scratch : this is an empty register byte for testing purposes. software can read, write, set and clear this register. the functionality of the phy will not be affected. table 42. pwr_ctrl - power control register (address r = 3dh to 3fh, w = 3dh, s = 3eh, c = 3fh) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved bvalid_ fall bvalid_ rise reserved reset 00000000 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c table 43. pwr_ctrl - power control register (address r = 3dh to 3fh, w = 3dh, s = 3eh, c = 3fh) bit description bit symbol description 7 to 4 - reserved; the link must never write logic 1 to these bits. 3 bvalid_fall bvalid fall : enables rxcmds for high-to-low transitions on bvalid. when bvalid changes from high to low, the isp1507 will send an rxcmd to the link with the alt_int bit set to logic 1. this bit is optional and is not necessary for otg devices. this bit is provided for debugging purposes. the session valid comparator should be used instead. 2 bvalid_rise bvalid rise : enables rxcmds for low-to-high transitions on bvalid. when bvalid changes from low to high, the isp1507 will send an rxcmd to the link with the alt_int bit set to logic 1. this bit is optional and is not necessary for otg devices. this bit is provided for debugging purposes. the session valid comparator should be used instead. 1 to 0 - reserved; the link must never write logic 1 to these bits.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 56 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 11. electrostatic discharge (esd) 11.1 esd protection the pins that are connected to the usb connector (dp, dm, id, v bus and gnd) have a minimum of 4 kv esd protection. capacitors 0.1 m f and 1 m f must be connected in parallel from v bus to gnd to achieve this 4 kv esd protection (see figure 24 ). remark: capacitors 0.1 m f and 1 m f are also required by universal serial bus speci?cation rev. 2.0 . for details on the requirements for c vbus , see section 16 . 11.2 esd test conditions a detailed report on test setup and results is available on request. fig 24. human body esd test model r d 1500 w r c 1 m w high voltage dc source 0.1 m f1 m f v bus device under test c s 100 pf storage capacitor charge current limit resistor discharge resistance gnd a b 004aaa881
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 57 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 12. limiting values [1] the isp1507 has been tested according to the additional requirements listed in universal serial bus speci?cation rev. 2.0, section 7.1.1 . the short circuit withstand test and the ac stress test were performed for 24 hours, and the isp1507 was found to be fully operational after the test completed. [2] equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor (human body model jesd22-a114d). 13. recommended operating conditions [1] v cc(i/o) must be less than or equal to v cc . table 44. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 0.5 +4.6 v v cc(i/o) input/output supply voltage - 0.5 +4.6 v v i input voltage on pins stp, data[7:0], reset_n and chip_select_n - 0.5 v cc(i/o) + 0.5 v on pins v bus , fault and psw_n - 0.5 +6.0 v on pin xtal1 - 0.5 +2.5 v on pin id - 0.5 +4.6 v on pins dp and dm [1] - 0.5 +4.6 v v esd electrostatic discharge voltage pins dp, dm, id, v bus and gnd; i li < 1 m a [2] - 4+4 kv all other pins; i li < 1 m a [2] - 1.5 +1.5 kv i lu latch-up current - 0.5 v cc < v < +1.5 v cc - 100 ma t stg storage temperature - 40 +125 c table 45. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 3.0 3.3 3.6 v v cc(i/o) input/output supply voltage [1] 1.65 - 3.6 v v i input voltage on pins stp, data[7:0], reset_n and chip_select_n 0- v cc(i/o) v on pins v bus , fault and psw_n 0 - 5.5 v on pins dp, dm and id 0 - 3.6 v on pin xtal1 0 - 1.95 v t amb ambient temperature - 40 +25 +85 c t j junction temperature - 40 - +125 c
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 58 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 14. static characteristics [1] a continuous stream of 1 kb packets with minimum inter-packet gap and all data bits set to logic 0 for continuous toggling. table 46. static characteristics: supply pins v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v (reg3v3) voltage on pin reg3v3 3.0 3.3 3.6 v v (reg1v8) voltage on pin reg1v8 1.65 1.8 1.95 v v por(trip) power-on reset trip voltage 1.0 - 1.5 v i cc supply current charge pump disabled low-power mode; v bus valid detector disabled; 1.5 k w pull-up resistor on pin dp disconnected -3585 m a low-power mode; v bus valid detector disabled; 1.5 k w pull-up resistor on pin dp connected - 215 280 m a full-speed idle; no usb activity - 10 - ma high-speed idle; no usb activity - 19 - ma full-speed continuous data transmit; 50 pf load on pins dp and dm [1] -15-ma full-speed continuous data receive [1] -11-ma high-speed continuous data transmit; 45 w load on pins dp and dm to ground [1] -48-ma high-speed continuous data receive [1] -28-ma charge pump enabled i o(vbus) = 8 ma; charge pump supply current only -2023ma i o(vbus) = 0 ma; charge pump supply current only - 300 - m a i cc(i/o) supply current on pin v cc(i/o) ulpi interface pins are static - - 1 m a table 47. static characteristics: digital pins digital pins: clock, dir, stp, nxt, data[7:0], reset_n and chip_select_n; unless otherwise speci?ed. v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v il low-level input voltage - - 0.3 v cc(i/o) v v ih high-level input voltage 0.7 v cc(i/o) -- v i il low-level input current v i = 0 v - - 1 m a i ih high-level input current v i = v cc(i/o) --1 m a i li input leakage current - 1 +0.1 +1 m a output levels v ol low-level output voltage i ol = +2 ma - - 0.4 v
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 59 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver v oh high-level output voltage i oh = - 2ma v cc(i/o) - 0.4 - - v i oh high-level output current v o = v cc(i/o) - 0.4 v - 4.8 - - ma i ol low-level output current v o = 0.4 v 4.2 - - ma i oz off-state output current 0 v < v o isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 60 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver table 50. static characteristics: analog i/o pins (dp, dm) v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit original usb transceiver (low-speed and full-speed) input levels (differential receiver) v di differential input sensitivity voltage | v dp - v dm | 0.2 - - v v cm differential common mode voltage range includes v di range 0.8 - 2.5 v input levels (single-ended receivers) v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v output levels v ol low-level output voltage pull-up on pin dp; r l = 1.5 k w to 3.6 v 0.0 0.18 0.3 v v oh high-level output voltage pull-down on pins dp and dm; r l = 15 k w to gnd 2.8 3.2 3.6 v termination v term termination voltage for upstream facing port pull-up for 1.5 k w pull-up resistor 3.0 - 3.6 v resistance r up(dp) pull-up resistance on pin dp 1425 1500 1575 w high-speed usb transceiver input levels (differential receiver) v hssq high-speed squelch detection threshold voltage (differential signal amplitude) 100 - 150 mv v hsdsc high-speed disconnect detection threshold voltage (differential signal amplitude) 525 - 625 mv v hsdi high-speed differential input sensitivity | v dp - v dm | 300 - - mv v hscm high-speed data signaling common mode voltage range (guideline for receiver) includes v di range - 50 - +500 mv v hsoi high-speed idle level voltage - 10 - +10 mv v hsol high-speed data signaling low-level voltage - 10 - +10 mv output levels v hsoh high-speed data signaling high-level voltage 360 - 440 mv v chirpj chirp j level (differential voltage) 700 - 1100 mv v chirpk chirp k level (differential voltage) - 900 - - 500 mv leakage current i lz off-state leakage current - 1- +1 m a capacitance c in input capacitance pin to gnd - - 5 pf
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 61 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver [1] for high-speed usb and full-speed usb. resistance r dn(dp) pull-down resistance on pin dp 14.25 15 15.75 k w r dn(dm) pull-down resistance on pin dm 14.25 15 15.75 k w termination z o(drv)(dp) driver output impedance on pin dp steady-state drive [1] 40.5 45 49.5 w z o(drv)(dm) driver output impedance on pin dm steady-state drive [1] 40.5 45 49.5 w z inp input impedance exclusive of pull-up/pull-down (for low-/full-speed) 10--m w table 50. static characteristics: analog i/o pins (dp, dm) continued v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 51. static characteristics: charge pump v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit voltage v o(vbus) output voltage on pin v bus i o(vbus) = 50 ma; c cp(c_a)-(c_b) = 270 nf 4.65 5.0 5.25 v v l(vbus) leakage voltage on pin v bus charge pump disabled - - 0.2 v current i o(vbus) output current on pin v bus c cp(c_a)-(c_b) = 270 nf 45 75 - ma ef?ciency h cp charge pump ef?ciency i o(vbus) = 50 ma 60 72 78 % table 52. static characteristics: v bus comparators v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v a_vbus_vld a-device v bus valid voltage 4.4 4.5 4.65 v v b_sess_vld b-device session valid voltage for a-device and b-device 0.8 1.6 2.0 v v hys(b_sess_vld) b-device session valid hysteresis voltage 70 90 110 mv v b_sess_end b-device session end voltage 0.2 0.5 0.8 v
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 62 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver table 53. static characteristics: v bus resistors v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit r up(vbus) pull-up resistance on pin v bus connect to pin reg3v3 when chrg_vbus is logic 1 281 680 - w r dn(vbus) pull-down resistance on pin v bus connect to gnd when dischrg_vbus is logic 1 656 1100 - w r i(idle)(vbus)(a) idle input resistance on pin v bus (a-device) id pin low and charge pump disabled 40 57 80 k w r i(idle)(vbus)(b) idle input resistance on pin v bus (b-device) id pin high or charge pump enabled 170 240 310 k w table 54. static characteristics: id detection circuit v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t id id detection time 50 - - ms v th(id) id detector threshold voltage 0.8 1.2 2.0 v r up(id) id pull-up resistance id_pullup is logic 1 40 50 60 k w table 55. static characteristics: resistor reference v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v o(rref) output voltage on pin rref suspendm is logic 1 - 1.22 - v
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 63 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver i cc(cp) denotes charge pump supply current. fig 25. charge pump supply current as a function of v bus output current fig 26. v bus output voltage as a function of v bus output current v cc(cp) denotes charge pump supply voltage. i cc(cp) denotes charge pump supply current. fig 27. v bus output voltage as a function of charge pump supply voltage fig 28. charge pump supply current as a function of temperature 004aaa876 0 20 40 60 80 100 120 0 1020304050 v cc = 3.6 v 3.3 v 3.0 v i cc(cp) (ma) i o(vbus) (ma) 004aaa877 4.00 4.50 5.00 5.50 0 1020304050 v cc = 3.6 v 3.3 v 3.0 v v o(vbus) (v) i o(vbus) (ma) 004aaa878 4.00 4.50 5.00 5.50 3 3.1 3.2 3.3 3.4 3.5 3.6 i o(vbus) = 0 ma 8 ma 50 ma v o(vbus) (v) v cc(cp) (v) 004aaa879 100 102 104 106 108 - 40 - 20 0 +20 +40 +60 +80 +100 i o(vbus) = 50 ma t amb ( c) i cc(cp) (ma)
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 64 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 15. dynamic characteristics [1] the internal pll is triggered only on the positive edge from the crystal oscillator. therefore, the duty cycle is not critic al. table 56. dynamic characteristics: reset and clock v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit reset t w(por) internal power-on reset pulse width 0.2 - - m s t w(reg1v8_h) reg1v8 high pulse width 2 - - m s t w(reg1v8_l) reg1v8 low pulse width 11 - - m s t w(reset_n) external reset_n pulse width 200 - - ns t pwrup regulator start-up time 4.7 m f 20 % capacitor each on pins reg1v8 and reg3v3 --1ms crystal or clock applied to xtal1 f i(xtal1) input frequency on pin xtal1 ISP1507ABS - 19.2 - mhz isp1507bbs - 26 - mhz t jit(i)(xtal1)rms rms input jitter on pin xtal1 ISP1507ABS - - 200 ps isp1507bbs - - 300 ps d i(xtal1) input duty cycle on pin xtal1 applicable only when clock is applied on pin xtal1 [1] -50-% d f i(xtal1) input frequency tolerance on pin xtal1 - 50 200 ppm t r(xtal1) rise time on pin xtal1 only for square wave input - - 5 ns t f(xtal1) fall time on pin xtal1 only for square wave input - - 5 ns v (xtal1)(p-p) peak-to-peak voltage on pin xtal1 only for square wave input 0.566 - 1.95 v output clock characteristics f o(clock) output frequency on pin clock - 60 - mhz t jit(o)(clock)rms rms output jitter on pin clock - - 500 ps d o(clock) output clock duty cycle on pin clock 45 50 55 % t startup(pll) pll startup time - 650 - m s t startup(o)(clock) output clock start-up time measured from power good or assertion of pin stp 450 650 900 m s
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 65 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver table 57. dynamic characteristics: digital i/o pins v cc = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v cc(i/o) = 1.65 v to 1.95 v t su(data) data set-up time with respect to the rising edge of pin clock 20 pf total external load per pin 5.7 - - ns t h(data) data hold time with respect to the rising edge of pin clock 20 pf total external load per pin 0- - ns t d(data) data output delay with respect to the rising edge of pin clock 20 pf total external load per pin - - 7.8 ns t su(stp) stp set-up time with respect to the rising edge of pin clock 20 pf total external load per pin 4.5 - - ns t h(stp) stp hold time with respect to the rising edge of pin clock 20 pf total external load per pin 0- - ns t d(dir) dir output delay with respect to the rising edge of pin clock 20 pf total external load per pin - - 8.9 ns t d(nxt) nxt output delay with respect to the rising edge of pin clock 20 pf total external load per pin - - 8.9 ns v cc(i/o) = 3.0 v to 3.6 v t su(data) data set-up time with respect to the rising edge of pin clock 30 pf total external load per pin 3.3 - - ns t h(data) data hold time with respect to the rising edge of pin clock 30 pf total external load per pin 0.8 - - ns t d(data) data output delay with respect to the rising edge of pin clock 30 pf total external load per pin - - 5.5 ns t su(stp) stp set-up time with respect to the rising edge of pin clock 30 pf total external load per pin 3.4 - - ns t h(stp) stp hold time with respect to the rising edge of pin clock 30 pf total external load per pin 0.8 - - ns t d(dir) dir output delay with respect to the rising edge of pin clock 30 pf total external load per pin - - 6.6 ns t d(nxt) nxt output delay with respect to the rising edge of pin clock 30 pf total external load per pin - - 6.6 ns table 58. dynamic characteristics: analog i/o pins (dp and dm) v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit high-speed driver t hsr rise time (10 % to 90 %) 500 - - ps t hsf fall time (10 % to 90 %) 500 - - ps full-speed driver t fr rise time c l = 50 pf; 10 % to 90 % of | v oh - v ol | 4 - 20 ns t ff fall time c l = 50 pf; 10 % to 90 % of | v oh - v ol | 4 - 20 ns t frfm differential rise and fall time matching excluding the ?rst transition from the idle state 90 - 111.1 %
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 66 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver v crs output signal crossover voltage excluding the ?rst transition from the idle state 1.3 - 2.0 v low-speed driver t lr transition time: rise time c l = 200 pf to 600 pf; 1.5 k w pull-up on pin dm enabled; 10 % to 90 % of | v oh - v ol | 75 - 300 ns t lf transition time: fall time c l = 200 pf to 600 pf; 1.5 k w pull-up on pin dm enabled; 10 % to 90 % of | v oh - v ol | 75 - 300 ns t lrfm rise and fall time matching t lr /t lf ; excluding the ?rst transition from the idle state 80 - 125 % driver timing t plh(drv) driver propagation delay (low to high) tx_dat, tx_se0 to dp, dm; see figure 30 --11ns t phl(drv) driver propagation delay (high to low) tx_dat, tx_se0 to dp, dm; see figure 30 --11ns t phz driver disable delay from high level tx_enable to dp, dm; see figure 31 --12ns t plz driver disable delay from low level tx_enable to dp, dm; see figure 31 --12ns t pzh driver enable delay to high level tx_enable to dp, dm; see figure 31 --20ns t pzl driver enable delay to low level tx_enable to dp, dm; see figure 31 --20ns receiver timing differential receiver t plh(rcv) receiver propagation delay (low to high) dp, dm to rx_rcv, rx_dp and rx_dm; see figure 32 --17ns t phl(rcv) receiver propagation delay (high to low) dp, dm to rx_rcv, rx_dp and rx_dm; see figure 32 --17ns single-ended receiver t plh(se) single-ended propagation delay (low to high) dp, dm to rx_rcv, rx_dp and rx_dm; see figure 32 --17ns t phl(se) single-ended propagation delay (high to low) dp, dm to rx_rcv, rx_dp and rx_dm; see figure 32 --17ns table 58. dynamic characteristics: analog i/o pins (dp and dm) continued v cc = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values are at v cc = 3.3 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 67 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 15.1 ulpi timing ulpi interface timing requirements are given in figure 33 . this timing applies to synchronous mode only. all timing is measured with respect to the isp1507 clock pin. all signals are clocked on the rising edge of clock. fig 29. rise time and fall time fig 30. timing of tx_dat and tx_se0 to dp and dm fig 31. timing of tx_enable to dp and dm fig 32. timing of dp and dm to rx_rcv, rx_dp and rx_dm 004aaa861 v ol t hsr , t fr , t lr t hsf , t ff , t lf v oh 90 % 10 % 10 % 90 % 004aaa573 v ol v oh t phl(drv) t plh(drv) v crs v crs 0.9 v 0.9 v 1.8 v 0 v logic input differential data lines 004aaa574 v ol v oh t pzh t pzl t phz t plz v oh - 0.3 v v ol + 0.3 v v crs 0.9 v 0.9 v 1.8 v 0 v logic input differential data lines t plh(se) t phl(se) 004aaa575 v ol v oh t phl(rcv) t plh(rcv) v crs v crs 0.9 v 0.9 v 2.0 v 0.8 v logic output differential data lines fig 33. ulpi interface timing clock control in (stp) data in (8-bit) t su(stp) t h(stp) t su(data) t h(data) control out (dir, nxt) data out (8-bit) 004aaa722 t d(dir) , t d(nxt) t d(data) t d(dir) , t d(nxt)
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 68 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 16. application information [1] for detailed information and alternative interface options, refer to the interfacing to the isp1507 (an10080) application note. [2] for more information, contact murata. remark: in the following application diagrams, because the ulpi bus is not shared, the chip_select_n pin is connected to ground. in other applications, chip_select_n can be controlled by a link to 3-state the ulpi bus so that those pins can be used for other purposes. table 59. recommended bill of materials designator [1] application value comment c bypass highly recommended for all applications 0.1 m f- c cp(c_a)-(c_b) charge pump is used 22 nf (8 ma), 270 nf (50 ma); up to 470 nf (50 ma) - c ?lter highly recommended for all applications 4.7 m f 20 %; use a low esr capacitor (0.2 w to 2 w ) for best performance - c vbus mandatory for peripherals 0.1 m f and 1 m fto10 m f in parallel - mandatory for host 0.1 m f and 120 m f 20 % (min) in parallel - mandatory for otg 0.1 m f and 1 m fto6.5 m f in parallel - d esd recommended for all esd-sensitive applications ip4359cx4/lf wafer-level chip-scale package (wlcsp); esd iec 61000-4-2 level 4; 15 kv contact; 15 kv air discharge compliant protection r pullup recommended; for applications with an external v bus supply controlled by psw_n 4.7 k w (recommended) maximum value is determined by the voltage drop on psw_n caused by leakage into psw_n and the external supply control pin r rref mandatory in all applications 12 k w 1% - r vbus strongly recommended for peripheral or external 5 v applications only 1k w 5% - r xtal required only for applications driving a square wave into the xtal1 pin 47 k w 5 % used to avoid ?oating input on the xtal1 pin xtal crystal is used 19.2 mhz c l = 10 pf; r s < 220 w ; c xtal =18pf 26 mhz c l = 10 pf; r s < 130 w ; c xtal =18pf cstce26m0xk2***-r0 [2] c xtal is not required c (xtal)sq required only for applications driving a square wave into the xtal1 pin that has a dc offset 100 pf used to ac couple the input square wave to the xtal1 pin
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 69 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver (1) frequency is version dependent: ISP1507ABS: 19.2 mhz; isp1507bbs: 26 mhz. fig 34. using the isp1507 with an otg controller; internal charge pump is utilized and crystal is attached isp1507 data0 v cc(i/o) rref dm dp fault id cpgnd c_b c_a v cc psw_n data1 data2 v cc(i/o) chip_ select_n data3 clock data4 data5 data6 data7 v cc(i/o) nxt 12 11 10 9 8 7 6 5 4 3 2 1 21 22 23 24 25 26 27 28 29 30 31 32 004aab040 v bus reg3v3 xtal1 xtal2 16 15 14 13 stp dir reg1v8 reset_n 17 18 19 20 otg controller 5 4 3 2 1 data0 data1 data2 data3 data4 data5 data6 data7 clock nxt stp dir v cc(i/o) v cc c bypass r rref c vbus c bypass c xtal xtal (1) gnd (die pad) c xtal c bypass c filter c filter c cp(c_a)-(c_b) v bus d - d+ id gnd usb micro-ab receptacle 6 7 8 9 shield shield shield shield ip4359cx4/lf b1 a1 a2 b2 d esd c bypass c bypass c bypass
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 70 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver (1) frequency is version dependent: ISP1507ABS: 19.2 mhz; isp1507bbs: 26 mhz. fig 35. using the isp1507 with a standard usb host controller; external 5 v source with built-in fault and external square wave i nput on xtal1 isp1507 data0 v cc(i/o) rref dm dp fault id cpgnd c_b c_a v cc psw_n data1 data2 v cc(i/o) chip_select_n data3 clock data4 data5 data6 data7 v cc(i/o) nxt 12 11 10 9 8 7 6 5 4 3 2 1 21 22 23 24 25 26 27 28 29 30 31 32 004aab041 v bus reg3v3 xtal1 xtal2 16 15 14 13 stp dir reg1v8 reset_n 17 18 19 20 host controller usb standard-a receptacle v bus d - d+ gnd 4 3 2 1 data0 data1 data2 data3 data4 data5 data6 data7 clock nxt stp dir v cc(i/o) v cc gnd (die pad) in fault on out v bus switch r pullup c bypass r rref c vbus c bypass c filter c bypass c filter 5 6 shield shield +5 v ip4359cx4/lf b1 a1 a2 d esd c (xtal)sq f i(xtal1) (1) r xtal b2 c bypass c bypass c bypass
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 71 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver (1) frequency is version dependent: ISP1507ABS: 19.2 mhz; isp1507bbs: 26 mhz. fig 36. using the isp1507 with a standard usb peripheral controller; external crystal isp1507 data0 v cc(i/o) rref dm dp fault id cpgnd c_b c_a v cc psw_n data1 data2 v cc(i/o) chip_select_n data3 clock data4 data5 data6 data7 v cc(i/o) nxt 12 11 10 9 8 7 6 5 4 3 2 1 21 22 23 24 25 26 27 28 29 30 31 32 004aab042 v bus reg3v3 xtal1 xtal2 16 15 14 13 stp dir reg1v8 reset_n 17 18 19 20 peripheral controller usb standard-b receptacle v bus d - d+ gnd 4 3 2 1 data0 data1 data2 data3 data4 data5 data6 data7 clock nxt stp dir v cc(i/o) v cc gnd (die pad) c bypass c bypass c filter c xtal c xtal c bypass c filter r rref c vbus 5 6 shield shield ip4359cx4/lf b1 a1 a2 xtal (1) d esd r vbus b2 c bypass c bypass c bypass
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 72 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 17. package outline fig 37. package outline sot617-1 (hvqfn32) 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.25 2.95 y 1 5.1 4.9 3.25 2.95 e 1 3.5 e 2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot617-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot617-1 hvqfn32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area terminal 1 index area 01-08-08 02-10-18 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 73 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 74 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 18.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 38 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 60 and 61 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 38 . table 60. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 61. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 75 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 19. abbreviations msl: moisture sensitivity level fig 38. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 62. abbreviations acronym description asic application-speci?c integrated circuit atx analog usb transceiver cd-rw compact disc-rewritable eop end-of-packet esd electrostatic discharge esr effective series resistance fs full-speed hbm human body model hnp host negotiation protocol hs high-speed id identi?cation iec international electrotechnical commission ls low-speed nrzi non-return-to-zero inverted otg on-the-go pcb printed-circuit board phy physical layer [1] pid packet identi?er pld programmable logic device
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 76 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver [1] physical layer containing the usb transceiver. the isp1507 is a phy. 20. references [1] universal serial bus speci?cation rev. 2.0 [2] on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 [3] utmi+ low pin interface (ulpi) speci?cation rev. 1.1 [4] utmi+ speci?cation rev. 1.0 [5] usb 2.0 transceiver macrocell interface (utmi) speci?cation ver. 1.05 [6] electrostatic discharge (esd) sensitivity testing human body model (hbm) (jesd22-a114d) [7] interfacing to the isp1507 (an10080) 21. revision history pll phase-locked loop por power-on reset rxcmd receive command se0 single-ended zero sof start-of-frame srp session request protocol sync synchronous ttl transistor-transistor logic txcmd transmit command usb universal serial bus usb-if usb implementers forum ulpi utmi+ low pin interface utmi usb 2.0 transceiver macrocell interface utmi+ usb 2.0 transceiver macrocell interface plus table 62. abbreviations continued acronym description table 63. revision history document id release date data sheet status change notice supersedes isp1507a_isp1507b_1 20080519 product data sheet - -
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 77 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 22. legal information 22.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 22.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 22.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 22.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 23. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 78 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 24. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 3. recommended charge pump capacitor value .12 table 4. ulpi signal description . . . . . . . . . . . . . . . . . .15 table 5. signal mapping during low-power mode . . . . .16 table 6. signal mapping for 6-pin serial mode . . . . . . .17 table 7. signal mapping for 3-pin serial mode . . . . . . .18 table 8. operating states and their corresponding resistor settings . . . . . . . . . . . . . . . . . . . . . . . .18 table 9. otg_ctrl register power control bits . . . . . .25 table 10. txcmd byte format . . . . . . . . . . . . . . . . . . . . .26 table 11. rxcmd byte format . . . . . . . . . . . . . . . . . . . . .26 table 12. linestate[1:0] encoding for upstream facing ports: peripheral . . . . . . . . . . . . . . . . . .27 table 13. linestate[1:0] encoding for downstream facing ports: host . . . . . . . . . . . . . . . . . . . . . . .28 table 14. encoded v bus voltage state . . . . . . . . . . . . . .28 table 15. v bus indicators in rxcmd required for typical applications . . . . . . . . . . . . . . . . . . . . . .29 table 16. encoded usb event signals . . . . . . . . . . . . . .30 table 17. phy pipeline delays . . . . . . . . . . . . . . . . . . . . .34 table 18. link decision times . . . . . . . . . . . . . . . . . . . . .35 table 19. immediate register set overview . . . . . . . . . . .47 table 20. extended register set overview . . . . . . . . . . . .47 table 21. vendor_id_low - vendor id low register (address r = 00h) bit description . . . .48 table 22. vendor_id_high - vendor id high register (address r = 01h) bit description . . . .48 table 23. product_id_low - product id low register (address r = 02h) bit description . . . .48 table 24. product_id_high - product id high register (address r = 03h) bit description . . . .48 table 25. func_ctrl - function control register (address r = 04h to 06h, w = 04h, s = 05h, c = 06h) bit allocation . . . . . . . . . . . . . . . . . . .48 table 26. func_ctrl - function control register (address r = 04h to 06h, w = 04h, s = 05h, c = 06h) bit description . . . . . . . . . . . . . . . . . .49 table 27. intf_ctrl - interface control register (address r = 07h to 09h, w = 07h, s = 08h, c = 09h) bit allocation . . . . . . . . . . . . . . . . . . .50 table 28. intf_ctrl - interface control register (address r = 07h to 09h, w = 07h, s = 08h, c = 09h) bit description . . . . . . . . . . . . . . . . . .50 table 29. otg_ctrl - otg control register (address r = 0ah to 0ch, w = 0ah, s = 0bh, c = 0ch) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 30. otg_ctrl - otg control register (address r = 0ah to 0ch, w = 0ah, s = 0bh, c = 0ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .51 table 31. usb_intr_en_r_e - usb interrupt enable rising edge register (address r = 0dh to 0fh, w = 0dh, s = 0eh, c = 0fh) bit allocation . . . .52 table 32. usb_intr_en_r_e - usb interrupt enable rising edge register (address r = 0dh to 0fh, w = 0dh, s = 0eh, c = 0fh) bit description . .52 table 33. usb_intr_en_f_e - usb interrupt enable falling edge register (address r = 10h to 12h, w = 10h, s = 11h, c = 12h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 34. usb_intr_en_f_e - usb interrupt enable falling edge register (address r = 10h to 12h, w = 10h, s = 11h, c = 12h) bit description . . . 53 table 35. usb_intr_stat - usb interrupt status register (address r = 13h) bit allocation . . . . . 53 table 36. usb_intr_stat - usb interrupt status register (address r = 13h) bit description . . . . 53 table 37. usb_intr_l - usb interrupt latch register (address r = 14h) bit allocation . . . . . . . . . . . 54 table 38. usb_intr_l - usb interrupt latch register (address r = 14h) bit description . . . . . . . . . . 54 table 39. debug - debug register (address r = 15h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 40. debug - debug register (address r = 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 41. scratch - scratch register (address r = 16h to 18h, w = 16h, s = 17h, c = 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 42. pwr_ctrl - power control register (address r = 3dh to 3fh, w = 3dh, s = 3eh, c = 3fh) bit allocation . . . . . . . . . . . . . . . . . . . 55 table 43. pwr_ctrl - power control register (address r = 3dh to 3fh, w = 3dh, s = 3eh, c = 3fh) bit description . . . . . . . . . . . . . . . . . . 55 table 44. limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 45. recommended operating conditions . . . . . . . . 57 table 46. static characteristics: supply pins . . . . . . . . . . 58 table 47. static characteristics: digital pins . . . . . . . . . . 58 table 48. static characteristics: digital pin fault . . . . . 59 table 49. static characteristics: digital pin psw_n . . . . 59 table 50. static characteristics: analog i/o pins (dp, dm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 51. static characteristics: charge pump . . . . . . . . 61 table 52. static characteristics: v bus comparators . . . . 61 table 53. static characteristics: v bus resistors . . . . . . . . 62 table 54. static characteristics: id detection circuit . . . . 62 table 55. static characteristics: resistor reference . . . . . 62 table 56. dynamic characteristics: reset and clock . . . . 64 table 57. dynamic characteristics: digital i/o pins . . . . . 65 table 58. dynamic characteristics: analog i/o pins (dp and dm) . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 59. recommended bill of materials . . . . . . . . . . . . 68 table 60. snpb eutectic process (from j-std-020c) . . . 74 table 61. lead-free process (from j-std-020c) . . . . . . 74 table 62. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 63. revision history . . . . . . . . . . . . . . . . . . . . . . . . 76
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 79 of 81 nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 25. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 fig 2. pin con?guration hvqfn32; top view . . . . . . . . . .5 fig 3. external capacitors connection . . . . . . . . . . . . . .10 fig 4. charge pump capacitor . . . . . . . . . . . . . . . . . . . .12 fig 5. internal power-on reset timing . . . . . . . . . . . . . . .20 fig 6. power-up and reset sequence required before the ulpi bus is ready for use. . . . . . . . . . . . . . . .22 fig 7. interface behavior with respect to reset_n. . . .23 fig 8. entering and exiting 3-state in normal mode . . . .24 fig 9. entering and exiting 3-state in suspend mode. . .24 fig 10. single and back-to-back rxcmds from the isp1507 to the link. . . . . . . . . . . . . . . . . . . . . . . .27 fig 11. rxcmd a_vbus_vld indicator source . . . . . . .29 fig 12. example of register write, register read, extended register write and extended register read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 fig 13. usb reset and high-speed detection handshake (chirp) sequence . . . . . . . . . . . . . . . .33 fig 14. example of using the isp1507 to transmit and receive usb data . . . . . . . . . . . . . . . . . . . . . . . . .34 fig 15. high-speed transmit-to-transmit packet timing. . .35 fig 16. high-speed receive-to-transmit packet timing . . .36 fig 17. preamble sequence . . . . . . . . . . . . . . . . . . . . . . .37 fig 18. full-speed suspend and resume . . . . . . . . . . . . .38 fig 19. high-speed suspend and resume . . . . . . . . . . . .40 fig 20. remote wake-up from low-power mode . . . . . . .42 fig 21. transmitting usb packets without automatic sync and eop generation . . . . . . . . . . . . . . . . .43 fig 22. example of transmit followed by receive in 6-pin serial mode . . . . . . . . . . . . . . . . . . . . . . . . .45 fig 23. example of transmit followed by receive in 3-pin serial mode . . . . . . . . . . . . . . . . . . . . . . . . .45 fig 24. human body esd test model. . . . . . . . . . . . . . . .56 fig 25. charge pump supply current as a function of v bus output current . . . . . . . . . . . . . . . . . . . . . . .63 fig 26. v bus output voltage as a function of v bus output current . . . . . . . . . . . . . . . . . . . . . . .63 fig 27. v bus output voltage as a function of charge pump supply voltage . . . . . . . . . . . . . . . . . . . . . .63 fig 28. charge pump supply current as a function of temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 fig 29. rise time and fall time . . . . . . . . . . . . . . . . . . . . .67 fig 30. timing of tx_dat and tx_se0 to dp and dm . .67 fig 31. timing of tx_enable to dp and dm. . . . . . . . .67 fig 32. timing of dp and dm to rx_rcv, rx_dp and rx_dm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 fig 33. ulpi interface timing . . . . . . . . . . . . . . . . . . . . . .67 fig 34. using the isp1507 with an otg controller; internal charge pump is utilized and crystal is attached . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 fig 35. using the isp1507 with a standard usb host controller; external 5 v source with built-in fault and external square wave input on xtal1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 fig 36. using the isp1507 with a standard usb peripheral controller; external crystal. . . . . . . . . .71 fig 37. package outline sot617-1 (hvqfn32) . . . . . . . 72 fig 38. temperature pro?les for large and small components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
isp1507a_isp1507b_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 19 may 2008 80 of 81 continued >> nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver 26. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 7 7.1 ulpi interface controller . . . . . . . . . . . . . . . . . . 7 7.2 usb data serializer and deserializer. . . . . . . . . 7 7.3 hi-speed usb (usb 2.0) atx . . . . . . . . . . . . . 7 7.4 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . 8 7.5 crystal oscillator and pll. . . . . . . . . . . . . . . . . 8 7.6 otg module . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.6.1 id detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.6.2 v bus comparators. . . . . . . . . . . . . . . . . . . . . . . 9 7.6.2.1 v bus valid comparator . . . . . . . . . . . . . . . . . . . 9 7.6.2.2 session valid comparator . . . . . . . . . . . . . . . . . 9 7.6.2.3 session end comparator. . . . . . . . . . . . . . . . . . 9 7.6.3 srp charge and discharge resistors . . . . . . . . 9 7.6.4 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.7 band gap reference voltage . . . . . . . . . . . . . . 10 7.8 power-on reset (por) . . . . . . . . . . . . . . . . . 10 7.9 detailed description of pins . . . . . . . . . . . . . . 10 7.9.1 data[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.9.2 v cc(i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.9.3 rref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.9.4 dp and dm . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.9.5 fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.9.6 id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.9.7 cpgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.9.8 c_a and c_b . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.9.9 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.9.10 psw_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.9.11 v bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.9.12 reg3v3 and reg1v8 . . . . . . . . . . . . . . . . . . 13 7.9.13 xtal1 and xtal2. . . . . . . . . . . . . . . . . . . . . . 13 7.9.14 reset_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9.15 dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9.16 stp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.9.17 nxt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.9.18 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.9.19 chip_select_n. . . . . . . . . . . . . . . . . . . . . . 14 7.9.20 gnd (die pad). . . . . . . . . . . . . . . . . . . . . . . . . 14 8 modes of operation . . . . . . . . . . . . . . . . . . . . . 15 8.1 ulpi modes . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.1 synchronous mode . . . . . . . . . . . . . . . . . . . . 15 8.1.2 low-power mode . . . . . . . . . . . . . . . . . . . . . . 16 8.1.3 6-pin full-speed or low-speed serial mode . . . 17 8.1.4 3-pin full-speed or low-speed serial mode . . . 17 8.2 usb and otg state transitions . . . . . . . . . . . 18 9 protocol description . . . . . . . . . . . . . . . . . . . . 20 9.1 ulpi references . . . . . . . . . . . . . . . . . . . . . . . 20 9.2 power-on reset (por) . . . . . . . . . . . . . . . . . 20 9.3 power-up, reset and bus idle sequence . . . . . 20 9.3.1 interface protection. . . . . . . . . . . . . . . . . . . . . 22 9.3.2 interface behavior with respect to reset_n. 23 9.3.3 interface behavior with respect to chip_select_n . . . . . . . . . . . . . . . . . . . . . 23 9.4 v bus power and fault detection . . . . . . . . . . . 25 9.4.1 driving 5 v on v bus . . . . . . . . . . . . . . . . . . . . 25 9.4.2 fault detection . . . . . . . . . . . . . . . . . . . . . . . . 25 9.5 txcmd and rxcmd . . . . . . . . . . . . . . . . . . . 25 9.5.1 txcmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.5.2 rxcmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.5.2.1 linestate encoding . . . . . . . . . . . . . . . . . . . . . 27 9.5.2.2 v bus state encoding . . . . . . . . . . . . . . . . . . . . 28 9.5.2.3 using and selecting the v bus state encoding. 29 9.5.2.4 rxevent encoding . . . . . . . . . . . . . . . . . . . . . 30 9.6 register read and write operations . . . . . . . . 31 9.7 usb reset and high-speed detection handshake (chirp) . . . . . . . . . . . . . . . . . . . . . 31 9.8 usb packet transmit and receive . . . . . . . . . . 34 9.8.1 usb packet timing . . . . . . . . . . . . . . . . . . . . . 34 9.8.1.1 isp1507 pipeline delays. . . . . . . . . . . . . . . . . 34 9.8.1.2 allowed link decision time . . . . . . . . . . . . . . . 34 9.9 preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.10 usb suspend and resume . . . . . . . . . . . . . . . 37 9.10.1 full-speed or low-speed host-initiated suspend and resume . . . . . . . . . . . . . . . . . . . 37 9.10.2 high-speed suspend and resume . . . . . . . . . 38 9.10.3 remote wake-up . . . . . . . . . . . . . . . . . . . . . . 41 9.11 no automatic sync and eop generation (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.12 on-the-go operations . . . . . . . . . . . . . . . . . . 43 9.12.1 otg charge pump . . . . . . . . . . . . . . . . . . . . . 44 9.12.2 otg comparators. . . . . . . . . . . . . . . . . . . . . . 44 9.12.3 pull-up and pull-down resistors . . . . . . . . . . . 44 9.12.4 id detection . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.12.5 v bus charge and discharge resistors . . . . . . . 44 9.13 serial modes . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.14 aborting transfers. . . . . . . . . . . . . . . . . . . . . . 46 9.15 avoiding contention on the ulpi data bus . . . 46
nxp semiconductors isp1507a; isp1507b ulpi hs usb otg transceiver ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 19 may 2008 document identifier: isp1507a_isp1507b_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 10 register map . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 immediate register set . . . . . . . . . . . . . . . . . . 48 10.1.1 vendor id and product id registers . . . . . . . . 48 10.1.1.1 vendor_id_low register . . . . . . . . . . . . . . 48 10.1.1.2 vendor_id_high register. . . . . . . . . . . . . . 48 10.1.1.3 product_id_low register . . . . . . . . . . . . . 48 10.1.1.4 product_id_high register . . . . . . . . . . . . 48 10.1.2 func_ctrl register . . . . . . . . . . . . . . . . . . . 48 10.1.3 intf_ctrl register . . . . . . . . . . . . . . . . . . . . 49 10.1.4 otg_ctrl register . . . . . . . . . . . . . . . . . . . . 51 10.1.5 usb_intr_en_r_e register . . . . . . . . . . . . . 52 10.1.6 usb_intr_en_f_e register . . . . . . . . . . . . . 52 10.1.7 usb_intr_stat register. . . . . . . . . . . . . . . . 53 10.1.8 usb_intr_l register . . . . . . . . . . . . . . . . . . . 53 10.1.9 debug register . . . . . . . . . . . . . . . . . . . . . . . 54 10.1.10 scratch register . . . . . . . . . . . . . . . . . . . . . 54 10.1.11 reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.1.12 access extended register set . . . . . . . . . . . . . 55 10.1.13 vendor-speci?c registers . . . . . . . . . . . . . . . . 55 10.1.14 pwr_ctrl register . . . . . . . . . . . . . . . . . . . . 55 10.2 extended register set . . . . . . . . . . . . . . . . . . . 55 11 electrostatic discharge (esd) . . . . . . . . . . . . 56 11.1 esd protection . . . . . . . . . . . . . . . . . . . . . . . . 56 11.2 esd test conditions . . . . . . . . . . . . . . . . . . . . 56 12 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 57 13 recommended operating conditions. . . . . . . 57 14 static characteristics. . . . . . . . . . . . . . . . . . . . 58 15 dynamic characteristics . . . . . . . . . . . . . . . . . 64 15.1 ulpi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 16 application information. . . . . . . . . . . . . . . . . . 68 17 package outline . . . . . . . . . . . . . . . . . . . . . . . . 72 18 soldering of smd packages . . . . . . . . . . . . . . 73 18.1 introduction to soldering . . . . . . . . . . . . . . . . . 73 18.2 wave and re?ow soldering . . . . . . . . . . . . . . . 73 18.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 73 18.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 74 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 75 20 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 21 revision history . . . . . . . . . . . . . . . . . . . . . . . . 76 22 legal information. . . . . . . . . . . . . . . . . . . . . . . 77 22.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 77 22.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 22.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 22.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 23 contact information. . . . . . . . . . . . . . . . . . . . . 77 24 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 26 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

▲Up To Search▲

Price & Availability of ISP1507ABS

	To Download ISP1507ABS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .