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RT9627A ? ds9627a-00 november 2012 www.richtek.com 1 copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? features z z z z z dual-channel driver z z z z z each channel drives two n-mosfets z z z z z adaptive shoot-through protection z z z z z 0.5 on-resistance, 4a sink current capability z z z z z supports high switching frequency z z z z z tri-state pwm input for power stage shutdown z z z z z output disable function z z z z z integrated boost switch z z z z z low bias supply current z z z z z vcc por feature integrated z z z z z rohs compliant and halogen free applications z core voltage supplies for intel ? / amd ? mobile microprocessors z high frequency low profile dc/dc converters z high current low output voltage dc/dc converters z high input voltage dc/dc converters high voltage synchronous rectified dual-channel buck mosfet driver for notebook computer general description the RT9627A is a high frequency, dual-channel driver specifically designed to drive two power n-mosfets in each channel of a synchronous-rectified buck converter topology. it is especially suited for mobile computing applications that require high efficiency and excellent thermal performance. this driver, combined with richtek's series of multi-phase buck pwm controllers, provides a complete core voltage regulator solution for advanced microprocessors. the drivers are capable of driving a 3nf load with fast rising/falling time and fast propagation delay. this device implements bootstrapping on the upper gates with only a single external capacitor. this reduces implementation complexity and allows the use of higher performance, cost effective, n-mosfets. adaptive shoot through protection is integrated to prevent both mosfets from conducting simultaneously. simplified application circuit vcc pwm1 ugate1 phase1 lgate1 RT9627A q ug1 v cc pwm1 v core q lg1 en c1 c out r1 l2 v in c3 r5 pwm2 gnd boot2 ugate2 phase2 lgate2 q ug2 pwm2 q lg2 c15 r5 l3 c16 r8 v in c in boot1 c2 r2 enable
RT9627A 2 ds9627a-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1, 7 ugate1, ugate2 high side gate drive outputs. connect to the gates of high side power n-mosfets. 2, 6 boot1, boot2 bootstrap supply for high side gate drives. connect the bootstrap capacitors between these pins and the phasex pins. the bootstrap capacitors provide the charge to turn on the high side mosfets. 3, 4 pw m1, pw m2 control inputs for drivers. the pwm signal can enter three distinct states during operation. connect these pins to the pwm outputs of the controller. 5 en enable control input. when pulling low, both ugatex and lgatex are driven low and the normal operation is disabled. 8, 12 phase2, phase1 switch nodes. connect these pins to the sources of the high side mosfets and the drains of the low side mosfets. these pins provide return paths for the high side gate drivers. 9, 11 lgate2, lgate1 low side gate drive outputs. connect to the gates of the low side power n-mosfets. 10 vcc supply voltage input. connect this pin to a 5v bias supply. place a high quality bypass capacitor from this pin to gnd. 13 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. ordering information pin configurations (top view) wdfn-12l 3x3 ugate1 boot1 en pwm2 phase1 lgate1 vcc phase2 lgate2 pwm1 boot2 ugate2 11 10 9 1 2 3 4 5 12 67 8 gnd 13 marking information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. RT9627A package type qw : wdfn-12l 3x3 (w-type) lead plating system g : green (halogen free and pb free) 0h= : product code ymdnn : date code 0h=ym dnn
RT9627A 3 ds9627a-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram shoot-through protection boot1 ugate1 phase1 por vcc r r tri-state detect pwm1 en control logic lgate1 gnd vcc vcc shoot-through protection boot2 ugate2 phase2 r r tri-state detect pwm2 control logic lgate2 vcc vcc operation por (power on reset) por block detects the voltage at the vcc pin. when the vcc pin voltage is higher than por rising threshold, the por pin output voltage (por output) is high. por output is low when vcc is not higher than por rising threshold. when the por pin voltage is high, ugatex and lgatex can be controlled by pwmx input voltage. if the por pin voltage is low, both ugatex and lgatex will be pulled to low. tri-state detect when both por output and enx pin voltages are high, ugatex and lgatex can be controlled by pwmx input. there are three pwmx input modes which are high, low, and shutdown state. if pwmx input is within the shutdown window, both ugatex and lgatex outputs are low. when pwmx input is higher than its rising threshold, ugatex is high and lgatex is low. when pwmx input is lower than its falling threshold, ugatex is low and lgatex is high. control logic control logic block detects whether high side mosfet is turned off by monitoring (ugatex ? phasex) voltages below 1.1v or phase voltage below 2v. to prevent the overlap of the gate drives during the ugatex pull low and the lgatex pull high, low side mosfet can be turned on only after high side mosfet is effectively turned off. shoot-through protection shoot-through protection block implements the dead-time when both high side and low side mosfets are turned off. with shoot-through protection block, high side and low side mosfets are never turned on simultaneously. thus, shoot-through between high side and low side mosfets is prevented.
RT9627A 4 ds9627a-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics recommended operating conditions (note 4) z input voltage, vin --------------------------------------------------------------------------------------------------------- 4.5v to 26v z supply voltage, vcc ----------------------------------------------------------------------------------------------------- 4.5v to 5.5v z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c (v cc = 5v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit vcc supply current quiescent current i q pwm pin floating, v en = 3.3v -- 120 -- a shutdown current i shdn v en = 0v, pwm = 0v -- 0 5 a v porh vcc por rising -- 3.85 4.1 v v porl vcc por falling 3.4 3.65 -- v vcc power on reset (por) v porhys hysteresis -- 200 -- mv internal boot switch internal boot switch on resistance r boot vcc to boot, 10ma -- -- 80 absolute maximum ratings (note 1) z supply voltage, vcc ----------------------------------------------------------------------------------------------------- ? 0.3v to 6v z bootx to phasex ------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z phasex to gnd dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 32v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 8v to 38v z ugatex to phasex dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 5v to 7.5v z lgatex to gnd dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 2.5v to 7.5v z pwmx, en to gnd ------------------------------------------------------------------------------------------------------ ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wdfn-12l 3x3 ------------------------------------------------------------------------------------------------------------- 3.28w z package thermal resista nce (note 2) wdfn-12l 3x3, ja ------------------------------------------------------------------------------------------------------- 30.5 c/w wdfn-12l 3x3, jc ------------------------------------------------------------------------------------------------------- 7.5 c/w z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 se c.) ------------------------------------------------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------------- 2kv
RT9627A 5 ds9627a-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit pwmx input v pwm = 5v -- 174 -- input current i pwm v pwm = 0v -- ? 174 -- a pwmx tri-state rising threshold v pwmh 3.5 3.8 4.1 v pwmx tri-state falling threshold v pwml 0.7 1 1.3 v tri-state shutdown hold-off time t shd_tri 100 175 250 ns en input logic-high v enh 2 -- -- en input voltage logic-low v enl -- -- 0.5 v switching time ugatex rise time t ugater 3nf load -- 8 -- ns ugatex fall time t ugatef 3nf load -- 8 -- ns lgatex rise time t lgater 3nf load -- 8 -- ns lgatex fall time t lgatef 3nf load -- 4 -- ns ugatex turn-off propagation delay t pdlu outputs unloaded -- 35 -- ns lgatex turn-off propagation delay t pdll outputs unloaded -- 35 -- ns ugatex turn-on propagation delay t pdhu outputs unloaded -- 20 -- ns lgatex turn-on propagation delay t pdhl outputs unloaded -- 20 -- ns ugatex/lgatex tri-state propagation delay t pts outputs unloaded -- 35 -- ns output ugatex driver source resistance r ugatesr 100ma source current -- 1 -- ugatex driver source current i ugatesr v ugate ? v phase = 2.5v -- 2 -- a ugatex driver sink resistance r ugatesk 100ma sink current -- 1 -- ugatex driver sink current i ugatesk v ugate ? v phase = 2.5v -- 2 -- a lgatex driver source resistance r lgatesr 100ma source current -- 1 -- lgatex driver source current i lgatesr v lgate = 2.5v -- 2 -- a lgatex driver sink resistance r lgatesk 100ma sink current -- 0.5 -- lgatex driver sink current i lgatesk v lgate = 2.5v -- 4 -- a note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution recommended. the human body mode is a 100pf capacitor is charged through a 1.5k resistor into each pin. note 4. the device is not guaranteed to function outside its operating conditions.
RT9627A 6 ds9627a-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit vcc pwm1 boot1 ugate1 phase1 lgate1 RT9627A 1f q ug1 v cc 1f pwm1 1h 2.2h v core q lg1 en c1 c2 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 r1 r2 r3 r4 l1 l2 v in v bat 3.3nf c3 2.2 r5 enable pwm2 gnd boot2 ugate2 phase2 lgate2 1f q ug2 pwm2 1h q lg2 c15 r5 r6 r7 l3 3.3nf c16 2.2 r8 v in 10 5 3 4 13 (exposed pad) 9 8 6 7 11 12 1 2
RT9627A 7 ds9627a-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics driver enable ugate (50v/div) phase (20v/div) en (10v/div) lgate (10v/div) time (2 s/div) v in = 19v, no load driver disable ugate (50v/div) phase (20v/div) en (10v/div) lgate (10v/div) time (2 s/div) v in = 19v, no load dead time ugate phase lgate (5v/div) time (20ns/div) full load dead time ugate phase (5v/div) lgate time (20ns/div) full load pwm rising edge ugate (20v/div) phase (20v/div) pwm (10v/div) lgate (5v/div) time (20ns/div) pwm falling edge ugate (20v/div) phase (20v/div) pwm (10v/div) lgate (5v/div) time (20ns/div)
RT9627A 8 ds9627a-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dead time ugate phase lgate (5v/div) time (20ns/div) no load dead time ugate phase lgate (5v/div) time (20ns/div) no load short pulse ugate phase lgate (5v/div) time (20ns/div) no load ugate - phase
RT9627A 9 ds9627a-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information supply voltage and power on reset the RT9627A is designed to drive two sets of both high side and low side n-mosfets through two externally input pwmx control signals. connect 5v to vcc to power on the RT9627A. a minimum 1 f ceramic capacitor is recommended to bypass the supply voltage. place the bypassing capacitor physically near the ic. the power on reset (por) circuit monitors the supply voltage at the vcc pin. if vcc exceeds the por rising threshold voltage, the controller resets and prepares for operation. ugatex and lgatex are held low before vcc is above the por rising threshold. enable and disable the RT9627A includes an en pin for sequence control. when the en pin rises above the v enh trip point, the RT9627A begins a new initialization and follows the pwmx command to control the ugatex and lgatex. when the en pin falls below the v enl trip point, the RT9627A shuts down and keeps ugatex and lgatex low. three state pwm input after initialization, the pwmx signal takes over the control. the rising pwmx signal first forces the lgatex signal low and then allows the ugatex signal to go high right after a non-overlapping time to avoid shoot-through current. in contrast, the falling pwmx signal first forces ugatex to go low. when the ugatex or phasex signal reach a predetermined low level, lgatex signal is then allowed to go high. non-overlap control to prevent the overlap of the gate drives during the ugatex pull low and the lgatex pull high, the non-overlap circuit monitors the voltages at the phasex node and high side gate drive (ugatex ? phasex). when the pwmx input signal goes low, ugatex begins to pull low (after propagation delay). before lgatex can pull high, the non- overlap protection circuit ensures that the monitored (ugatex ? phasex) voltages have gone below 1.1v or phase voltage is below 2v. once the monitored voltages fall below the threshold, lgatex begins to turn high. by waiting for the voltages of the phasex pin and high side gate drive to fall below their threshold, the non-overlap protection circuit ensures that ugatex is low before lgatex pulls high. also to prevent the overlap of the gate drives during lgatex pull low and ugatex pull high, the non-overlap circuit monitors the lgatex voltage. when lgatex go below 1.1v, ugatex is allowed to go high. driving power mosfets the dc input impedance of the power mosfet is extremely high. the gate draws the current only for few nano-amperes. thus, once the gate has been driven up to ? on ? level, the current could be negligible. however, the capacitance at the gate to source terminal should be considered. it requires relatively large currents to drive the gate up and down rapidly. it is also required to switch drain current on and off with the required speed. the required gate drive currents are calculated as follows. figure1. equivalent circuit and associated waveforms l d 2 s 2 c gs2 g 2 i g2 i gd2 i gs2 c gd2 c gs1 c gd1 i gd1 i gs1 i g1 d 2 v out s 1 v in d 1 d 1 gnd g 1 phasex 5v t t v g2 v g1 v phasex +5v
RT9627A 10 ds9627a-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. in figure 1, the current i g1 and i g2 are required to move the gate up to 5v. the operation consists of charging c gd1 , c gd2 , c gs1 and c gs2 . c gs1 and c gs2 are the capacitors from gate to source of the high side and the low side power mosfets, respectively. in general data sheets, the c gs1 and c gs2 are referred as ? c iss ? which are the input capacitors. c gd1 and c gd2 are the capacitors from gate to drain of the high side and the low side power mosfets, respectively and referred to the data sheets as ? c rss ? the reverse transfer capacitance. for example, t r1 and t r2 are the rising time of the high side and the low side power mosfets respectively, the required current i gs1 and i gs2 , are shown as below : == == g1 gs1 gs1 gs1 r1 g2 gs1 gs2 gs1 r2 dv c x 5 ic dt t dv c x 5 ic dt t before driving the gate of the high side mosfet up to 5v, the low side mosfet has to be off; the high side mosfet is turned off before the low side is turned on. from figure 1, the body diode ? d 2 ? had been turned on before high side mosfets turned on. (1) (2) == gd1 gd1 gd1 r1 dv 5 ic c dt t (3) before the low side mosfet is turned on, the c gd2 have been charged to v in . thus, as c gd2 reverses its polarity and g 2 is charged up to 5v, the required current is : + == gd2 gd2 gd2 r2 dv vi 5 ic c dt t (4) it is helpful to calculate these currents in a typical case. assume a synchronous rectified buck converter, input voltage v in = 12v, v g1 = v g2 = 5v. the high side mosfet is phb83n03lt whose c iss = 1660pf, c rss = 380pf, and t r = 14ns. the low side mosfet is phb95n03lt whose c iss = 2200pf, c rss = 500pf and t r = 30ns, from the equation (1) and (2) we can obtain : == == -12 gs1 -9 -12 gs2 -9 1660 x 10 x 5 i 0.593 (a) 14 x 10 2200 x 10 x 5 i 0.367 (a) 30 x 10 (5) (6) from equation. (3) and (4) () == == -12 gd1 -9 -12 gd2 -9 380 x 10 x 5 i 0.136 (a) 14 x 10 500 x 10 x 12 + 5 i 0.283 (a) 30 x 10 (7) (8) the total current required from the gate driving source can be calculated as following equations : by a similar calculation, we can also get the sink current required from the turned off mosfet. select the bootstrap capacitor figure 2 shows part of the bootstrap circuit of the RT9627A. the v cb (the voltage difference between bootx and phasex on RT9627A) provides a voltage to the gate of the high side power mosfet. this supply needs to be ensured that the mosfet can be driven. for this, the capacitance c b has to be selected properly. it is determined by following constraints. () () =+= + = =+= + = g1 gs1 gd1 g2 gs2 gd2 i i i 0.593 0.136 0.729 (a) i i i 0.367 0.283 0.65 (a) (9) (10) figure 2. part of bootstrap circuit of RT9627A in practice, a low value capacitor c b will lead to the over charging that could damage the ic. therefore, to minimize the risk of overcharging and to reduce the ripple on v cb , the bootstrap capacitor should not be smaller than 0.1 f, and the larger the better. in general design, using 1 f can provide better performance. at least one low esr capacitor should be used to provide good local de-coupling. it is recommended to adopt a ceramic or tantalum capacitor. v in c b v cb + - bootx v cc ugatex phasex lgatex gnd
RT9627A 11 ds9627a-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 3. derating curve of maximum power dissipation figure 4. synchronous buck converter circuit when layout the pcb, it should be very careful. the power circuit section is the most critical one. if not configured properly, it will generate a large amount of emi. the junction of q ugx , q lgx , lx should be very close. next, the trace from ugatex, and lgatex should also be short to decrease the noise of the driver output signals. phasex signals from the junction of the power mosfet, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. the bypass capacitor c1 should be connected to gnd directly. furthermore, the bootstrap capacitors (c b ) should always be placed as close to the pins of the ic as possible. layout considerations figure 4 shows the schematic circuit of a synchronous buck converter to implement the RT9627A. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn-12l 3x3 package, the thermal resistance, ja , is 30.5 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (30.5 c/w) = 3.28w for wdfn-12l 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. bootx ugatex phasex lgatex vcc RT9627A gnd c b l1 c out v bat v core c in2 phb83n03lt phb95n03lt lx q lgx q ugx + + 5v pwmx pwm signal 5v c1 r1 en v in c in1 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT9627A 12 ds9627a-00 november 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.400 1.750 0.055 0.069 e 0.450 0.018 l 0.350 0.450 0.014 0.018 w-type 12l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options

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