View ML7105-002_7592633.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fedl7105-002-01 issue date: june. 10, 2013 ML7105-002 bluetooth ? low energy 1/30 overview ML7105-002 is a bluetooth? low energy (here in after le) lsi integrating rf, baseband, microproccessor core and each peripherals, which has bluetooth? le compliant 2.4ghz band radio communication capability. ML7105-002 (hereafter "ml7105") is suitable for applications such as wrist watch, remote controller or pc peripherals. features ? bluetooth? sig core spec v4.0 compliant ? ultra low power rf block ? cortex-m0 micro processor, it has interrupt controller and sys-tick timer ? 64kb rom (code_rom) for program, 16kb ram (data_ram) for data ? 12kb ram (code_ram) for user program ? bluetooth ? le single mode compliant baseband controller ? uart interface for bluetooth ? host controller interface (hci) ? spi (slave mode) interface for custom host controller interface ? i2c (master & slave) interface for eeprom or custom host controller interface ? gpio ports ? system clock timer and external low power clock timer ? low power operating mode ? single power supply 1.6v to 3.6v ? operating temperature -20 deg.c to 70 deg.c ? current consumptions deep sleep mode below 0.7ua (with external low power clock) below 2.9ua (with internal low power clock oscillator circuit) idle mode below 3.0ma tx mode below 9.0ma rx mode below 9.0ma ? package 32pins wqfn (p-wqfn32-0505-0.50-a63) pb free, rohs compliant
fedl7105-002-01 ML7105-002 2/30 block diagram 1chip overview bluetooth ? le controller
fedl7105-002-01 ML7105-002 3/30 pin assignment 32pins wqfn i2c_scl vddio uart_rxd uart_txd spiclk spixcs spidout spidin 24 23 22 21 20 19 18 17 i2c_sda 25 16 vddcore gpio0 26 15 efuse gpio1 27 14 xon gpio2 28 13 xop gndpkg gpio3 29 12 regc tmode 30 11 lpclkin resetb 31 10 lpclkbus a0 32 9 vddbat 1 2 345678 a1 vddrf swout swrx swtx vddvco plllpf regout top view note: centre of the chip at bottom side is gnd (symbol : package gnd)
fedl7105-002-01 ML7105-002 4/30 pin definitions no. pin name i/o ana/dig io type function 1 a1 in ana dirio general purpose analog input 2 vddrf --- pwr vcc power supply for rf block (1.2v) 3 swout inout ana dirio_rf rf signal rx/tx inout 4 swrx inout ana dirio_rf rx sw control signal 5 swtx inout ana dirio_rf tx sw control signal 6 vddvco --- pwr vcc power supply for rf-vco (1.2v) 7 plllpf out ana dirio pll loop filter 8 regout out ana dirio regulator output 9 vddbat --- pwr vcc power supply from battery (=vddio) (1.6v to 3.6v) 10 lpclkbus inout ana dirio low power clock output/ 11 lpclkin inout ana dirio low power clock/xtal input 12 regc out ana dirio decoupling capacitor pin for internal regulator 13 xop inout ana dirio positive inout pin for xtal oscillator block 14 xon inout ana dirio negative inout pin for xtal oscillator block 15 efuse --- dig dirio power supply for e-fuse (fixed to gnd in normal) 16 vddcore --- pwr vcc power supply for digital core (1.2v) 17 spidin in dig cmos, in spi slave data input 18 spidout inout dig cmos, bidir spi slave data output 19 spixcs in dig cmos, in spi slave chip select 20 spiclk in dig cmos, in spi slave clock 21 uart_txd out dig cmos, out uart txd output 22 uart_rxd in dig cmos, in uart rxd input 23 vddio --- pwr vcc power supply for digital io (1.6v to 3.6v) 24 i2c_scl inout dig cmos, bidir i2c_scl 25 i2c_sda inout dig cmos, bidir i2c_sda 26 gpio0 /rf_active inout dig cmos, bidir gpio inout/rf_active 27 gpio1 /wakeup inout dig cmos, bidir gpio inout/wakeup 28 gpio2 /irq inout dig cmos, bidir gpio inout/irq 29 gpio3 /ps_control inout dig cmos, bidir gpio inout/external control switch control 30 tmode in dig cmos, in testmode input 31 resetb in dig cmos, in reset input 32 a0 in ana dirio general purpose analog input g gndpkg --- gnd gnd package gnd
fedl7105-002-01 ML7105-002 5/30 pin definition i rf : rf input and output i : digital input i pd : digital input with pull-down resistor i a : analog input i ah : analog input support 3v i sh : low-power clock input x sh : x?tal pin for low-power clock x m : x?tal pin for master clock o 2 : digital output with 2ma load capability b 2 : digital inout with 2ma load capability o a : analog output i/o definitions o ah : analog output support 3v rf analog pins no pin name status in reset i/o active level function 3 swout hi-z i rf --- rf signal rx/tx inout 4 swrx hi-z i rf --- rx sw control signal 5 swtx hi-z i rf --- tx sw control signal 32 a0 hi-z i ah --- general purpose analog input 1 a1 hi-z i ah, --- general purpose analog input 7 plllpf hi-z o a --- pll loop filter xo, lpxo pins no pin name status in reset i/o active level function 13 xop hi-z x m --- positive inout pin for master clock oscillator block 14 xon hi-z x m --- negative inout pin for master clock oscillator block 10 lpclkbus 0v x sh --- low power clock xtal output 11 lpclkin i sh x sh , i sh --- low power clock/xtal input spi pins no pin name status in reset i/o active level function 17 spidin input i --- spi slave data input 18 spidout output b 2 --- spi slave data output 19 spixcs input i low spi slave chip select 20 spiclk input i --- spi slave clock
fedl7105-002-01 ML7105-002 6/30 uart pins no pin name status in reset i/o active level function 21 uart_txd high output o 2 --- uart txd output 22 uart_rxd input i pd --- uart rxd input i2c pins no pin name status in reset i/o active level function 24 i2c_scl input b 2 --- i2c_scl 25 i2c_sda input b 2 --- i2c_sda gpio pins no pin name status in reset i/o active level function 26 gpio0 /rf_active low output b 2 --- gpio inout/rf_active (default : rf_active) 27 gpio1 /wakeup input b 2 --- gpio inout/wakeup (default : wakeup) 28 gpio2 /irq high output b 2 --- gpio inout/irq (default : irq) 29 gpio3 /ps_control low output b 2 --- gpio inout/external switch control (default : ps_control) miscellaneous pins no pin name status in reset i/o active level function 31 resetb input i low reset input (low = reset) 15 efuse --- --- --- power supply for e-fuse (fixed to gnd in normal) 30 tmode input i --- testmode input (low = normal mode) regulator pins no pin name status in reset i/o active level function 8 regout hi-z o ah --- regulator output 12 regc 1.2v output o ah --- decoupling capacitor pin for internal regulator
fedl7105-002-01 ML7105-002 7/30 power supply pin no pin name status in reset i/o active level function 2 vddrf --- --- --- power supply for rf block (1.2v) 6 vddvco --- --- --- power supply for rf-vco (1.2v) 9 vddbat --- --- --- power supply from battery (=vddio) (1.6v to 3.6v) 16 vddcore --- --- --- power supply for digital core (1.2v) 23 vddio --- --- --- power supply for digital io (1.6v to 3.6v) g gndpkg --- --- --- package gnd unused pins followings are recommendation for pins are not used. no pin name recommendation 1 a1 open 10 lpclkbus open 15 efuse fix to gnd 17 spidin fix to vddio 18 spidout fix to vddio 19 spixcs fix to vddio 20 spiclk fix to vddio 21 uart_txd open 22 uart_rxd fix to gnd (see operating mode section) 24 i2c_scl fix to vddio 25 i2c_sda fix to gnd 26 gpio0 open 27 gpio1 fix to vddio or gnd (see operating mode section) 28 gpio2 open 29 gpio3 open 32 a0 open note leaving input pins open with hi-z status, current consumption will be increased. it is highly recommended that input or inout pins should not be left open.
fedl7105-002-01 ML7105-002 8/30 electrical characteristics absolute maximum rating (*1) vddbat, vddio pins (*2) vddrf, vddvco, vddcore, (*3) gnd: gnd pin (package gnd) (*4) io pins with i, i pd , b 2 symbol in pin definition (*5) io pins with o 2 ,b 2 symbol in pin definition (*6) io pins with i a , o a, x m symbol in pin definition (*7) io pins with i ah , o ah, i sh, x sh, symbol in pin definition recommended operating conditions item symbol condition min typ max unit power supply v ddio1 vddio pin vddbat Rvddio 1.6 3.3 3.6 v power supply v ddio2 vddbat pin vddbat Rvddio 1.6 3.3 3.6 v ambient temperature t a ? ?20 +25 +85 c rising time digital input pins t ir1 digital input/inout pins ? ? 20 ns falling time digital input pins t if1 digital input/inout pins ? ? 20 ns load capacitance digital c dl digital output/inout pins ? ? 20 pf master clock (26 mhz) crystal oscillator frequency f mck1 connect cristal oscillator between xop xon pins *1 , (*2) ?40 ppm 26 +40 ppm mhz low power clock (32.768 khz) crystal oscillator frequency f lpck1 lpclkin pin, lpclkbus pin (*2) ?250 ppm 32.768 +250 ppm khz low power clock input duty ratio d lpck1 external input from lpclkin, lpclkbus pin left open 30 50 70 % rf channel frequency (*2) f rf swout pin 2402 ? 2480 mhz rf input level p rfin -70 ? -10 dbm (*1) cristal oscillator is recommended (*2) the cristal should be used the one that meet the specification include peripheral circuit. (*3) frequency range f = 2402 + 2 x k [mhz] here k=0, 1,2,?,39. item symbol condition rating unit power supply 3.3v (*1) v ddio1 v ddio2 ?0.3 to +4.6 v power supply 1.2v (*2) v ddrf ?0.3 to +1.8 v digital input voltage (*4) v din ?0.3 to v ddio +0.3 v digital output voltage (*5) v do ta = ? 20 to +70 deg.c ?0.3 to v ddio +0.3 v analog io voltage (*6) v a gnd= 0 v (*3) ?0.3 to v ddrf +0.3 v analog hv io voltage (*7) v ah vddrf=vddvco ?0.3 to v ddio +0.3 v digital io load current i do =vddcore, ?10 to +10 ma analog io current (*6)(*7) i a vddbat=vddio, ?2 to +2 ma power dissipation p d 1.0 w storage temperature t stg ? ?55 to +125 deg.c
fedl7105-002-01 ML7105-002 9/30 current consumption (ta = ? 20 to +70 deg.c) item symbol condition min typ max unit i dd1 deep sleep state (external low power clock) ? 0.7 ? ua i dd2 deep sleep state (internal low power clock oscillation) ? 2.9 ? ua i dd3 idle state ? 3 ? ma i dd4 rf rx state 9 ? ma rf tx state (-6dbm) ? 9 ? ma current consumption (*1) i dd5 rf tx state (0dbm) ? 10.9 ? ma (*1) condition: ta = 25deg. vddhv = 3.3v dc characteristics (ta = ? 20 to +70 deg.c) item symbol condition min typ max unit h level voltage input v ih1 (*1) (*2) (*5) v ddio x0.7 ? v ddio v l level voltage input v il1 (*1) (*2) (*5) 0 ? v ddio x0.3 v lpclkin pin h level voltage input v ih2 (*3) 1 ? v ddio v lpclkin pin l level voltage input v il2 (*3) 0 ? 0.3 v i ih1 v ih = v ddio (*1) (*5) ?1 ? 1 ua i ih2 v ih = v ddio (*2) 5 ? 250 ua input leak current i il1 v il = 0 v (*1) (*2) (*5) ?-1 ? 1 ua i ozh v oh = v ddio (*4) (*5) ?1 ? 1 ua tri-state output leak current i ozl v ol = 0 v (*4) (*5) ?1 ? 1 ua h level voltage output v oh i oh = ? 2ma (*4) (*5) v ddio = v ddrf = 1.6v to 3.6v v ddio 0.75 ? v ddio v l level voltage output v ol i ol = 2ma (*4) (*5) 0 ? v ddio 0.25 v input pin capacitance c in f=1mhz (*1) (*2) (*4) (*5) ? 8 ? pf (*1) io pins with i symbol in pin definition (*2) io pins with i pd symbol in pin definition (*3) io pins with i sh symbol in pin definition (*4) io pins with o 2 symbol in pin definition (*5) io pins with b 2 symbol in pin definition
fedl7105-002-01 ML7105-002 10/30 rf characteristics (ta = ? 20 to +70 deg.c) item symbol condition min typ max unit tx tx power p out1 0dbm setting ?3 0 3 dbm p out2 -18dbm setting ? ?18 ? dbm centre frequency tolerance f cerr master clock tolerance < 40 ppm ?40 ? 40 ppm modulation data rate d rate ? ? 1 ? mbps modulation index f idx ? 0.45 0.50 0.55 ? bandwidth-bit rate products bt bt gfsk ? 0.5 ? ? f 1avg frequency deviation of 10101010 pattern 225 250 275 khz f rate frequency deviation ratio between 10101010 and 00001111 sequence 80 ? ? % modulation characteristics f delta minimum frequency deviation 185 ? ? khz p os1 2mhz apart from carrier frequency in a 1mhz bandwidth ? ? -20 dbm in-band spurious p os2 3mhz apart from carrier frequency in a 1mhz bandwidth ? ? -30 dbm rx receiver sensitivity p sens per = 30.8% (*1) ? -85 -70 dbm ci co co-channel interference c/i 21 ? ? db ci s1 adjacent (1mhz) interference c/i 15 ? ? db ci s2 adjacent (2mhz) interference c/i -17 ? ? db ci s3 adjacent (>=3mhz) interference c/i -27 ? ? db ci img image frequency interference (-4mhz) c/i -9 ? ? db interference performance per<30.8% wanted signal :-67dbm interfering signal : modulated signal (*2) ci imgs1 adjacent (1mhz) interference to image frequency (-3mhz,-5mhz)) c/i -15 ? ? db p blk1 30mhz to 2000mhz bw 10mhz -30 ? ? dbm p blk2 2003 to 2399mhz bw 3mhz -35 ? ? dbm p blk3 2484 to 2997mhz bw 3mhz -35 ? ? dbm out of band blocking per<30.8% wanted signal :-67dbm interfering signal:cw (*2) (*3) p blk4 3000mhz to 12.75ghz bw 25mhz -30 ? ? dbm
fedl7105-002-01 ML7105-002 11/30 intermodulation per<30.8% wanted signal :-64dbm (*2) p im cw interering signal +/-3mhz modulated interfering signal +/-6mhz or cw interfering signal +/-4mhz modulated interfering signal +/-8mhz or cw interfering signal +/-5mhz modulated interfering signal +/-10mhz -50 ? ? dbm maximum input level(*2) p rxmax per = 30.8% (*1) ? ? -10 dbm p rssima x upper -40 ? ? dbm rssi detection range (*2) p rssimin lower ? ? -80 dbm (*1) per=30.8% is corresponding to ber=0.1% (*2) condition: ta = 25deg. vddhv = 3.3v (*3) follow rcv-le/ca/04/c test spec of bluetooth sig
fedl7105-002-01 ML7105-002 12/30 spi interface (ta = ? 20 to +70 deg.c) item symbol condition min typ max unit spiclk clock frequency f sclk 16.384 32.768 1625 khz spixcs input setup time t cesu 1/fsclk ? ? ms spixcs input hold time t ceh 1/fsclk ? ? ms spiclk minimum high pulse width t wckh 250 ? ? ns spiclk minimum low pulse width t wckl 250 ? ? ns spidin input setup time t disu 5 ? ? ns spidin input hold time t dih 250 ? ? ns spiclk output delay time t ckod ? ? 250 ns spidout output hold time t doh 5 ? ? ns spixcs enable delay time t ceen 0 ? 300 ns spixcs disable delay time t cedis load capacitance cl=20pf 150 ? ? ns note: when using the width of the following spiclk edge from the data output trigger spiclk edge within 250 ns, there is possibility that the output timing of spidout becomes simultaneous with the following edge. consider the data input setup time of host and set pulse width. remarks: all timing specification is defined at v ddio x 20% and v ddio x 80% spixcs input setup/hold time have to be at least 1cycle of spiclk clock frequency measurement point measurement point 0.8v ddio 0.2v ddio 0.8v ddio 0.2v ddio spixcs spiclk spidout spidin msb in bits6-1 lsb in t ceen t wckh msb out bits6-1 lsb out t ceh t cedis t ckod t doh t wckl f sclk t ckod t disu t dih t cesu
fedl7105-002-01 ML7105-002 13/30 uart interface (ta = ? 20 to +70 deg.c) item symbol condition min typ max unit baud rate f baud load capacitance cl=20pf ? 57600 ? bps(h z)
fedl7105-002-01 ML7105-002 14/30 i2c interface (ta = ? 20 to +70 deg.c) item symbol condition min typ max unit scl clock frequency f scl ? ? 400 khz scl minimum high pulse width t wsckh 10 ? ? us scl minimum low pulse width t wsckl 10 ? ? us start condition hold time t dstah 5 ? ? us start condition setup time t dstas 5 ? ? us stop condition setup time t dstos 5 ? ? us sda output hold time t dsoh 5 ? ? us scl output delay time t dsos 5 ? ? us sda input setup time t dsis 80 ? ? ns sda input hold time t dsih load capacitance cl=20pf 0 ? ? ns note: scl clock frequency is fixed to 400khz start condition sda falling edge while scl= , stop condition sda rising edge while scl= tx/rx case scl f scl t wsckh t wsckl t dstas sda(output ) start condition stop condition t dstos t dstah scl sda(output) sda(input) t dsoh t dsos t dsis t dsih
fedl7105-002-01 ML7105-002 15/30 reset operation (ta = ? 20 to +70 deg.c) item symbol condition min typ max unit resetb propagation delay time power on t rdl start supplying power (vddbat,vddio) 20 ? ? ms resetb pulse width t rpls resetb pin 1 ? ? us power on reset function reset function from resetb pin it is possible to reset internal circuit by asserting resetb after power supply is on. it is possible to reset internal circuit by same way even if it is not power sequence. internal circuit will move to normal state after oscillation circuit become stable by clock stabilizing circuit after reset function. power on (ta = ? 20 to +70 deg.c) item symbol condition min typ max unit vdd pin rising time t pwon while power on vdd pins (vddbat,vddio) 0.2 1 5 ms time difference between vdd pin while power on state t pwondly while power on vdd pins (vddbat,vddio) 0 - - ms time difference between vdd pin while power off state t pwofdly while power off vdd pins (vddbat,vddio) 0 - - ms vddbat, vddio vdd level gnd level resetb t rdl t pwon 90% 10% vddbat, t pwon 90% 10% vddio
fedl7105-002-01 ML7105-002 16/30 operating mode following 4 operating modes are available to use baci mode: application mode using spi-slave interface hci mode: hci mode (bluetooth le standard compliant) using uart interface. ram mode: function extension mode downloading user program to internal memory debug mode: debugging mode to have access to i2c-eeprom write and read. operating mode configuration configuration of operating mode will be done by pin status shown in table below. the symbol ?x? is don?t care, it has to be used as normal function. when configure operating mode, reset has to be issued. ram mode and debug mode is distinguished by configuration parameter. pin confitions operating mode uart_rxd bli mode low hci mode 1 high ram mode x debug mode x (*) fix wakeup pin to low on hci mode. see anootations on section about power state transition
fedl7105-002-01 ML7105-002 17/30 boot sequence operating mode will be deciede by boot sequence shown below. no start (power on & hardware rese t uart_rx == high ? spi_slave (baci) initialization for loading i/f check external pins by gpio is not required yes check external pins by gpio not wakeup or config is ivalid wakeup or config is valid retention status register? uart0 (hci) initialization for loading i/f load config parameters (debug mode) reset handle r i2c_sda == high ? no no ?eeprom_is_not_connected? load config from eeprom is config valid? (== 0x5a) no ?eeprom_is_not_valid? yes ?eeprom_is_valid? ?eeprom_is_connected? yes check external pins by gpio
fedl7105-002-01 ML7105-002 18/30 rom or ram mode ? go to gatt & gap i/f (spi_slave) for application and test (baci mode) go to hci i/f (uart0) for application and test (hci mode) check parameter value ram mode rom mode yes check external pins by gpio no go to user application (ram mode) uart_rx == high? disable pull-down of uart_rxd pin download user application to code_ram restore remap call reset handler normal operation store & retention status = wakeup can shutdown? yes no wakeup pin == high ? yes no
fedl7105-002-01 ML7105-002 19/30 power management power mode following power modes are available. active mode idle mode deep sleep mode application sleep [active mode] active mode will be used during rf connection state. [idle mode] idle mode is low power consumption mode. it can be used between connection events with short time interval which is equal to or less than 40msec. [deep sleep mode] deep sleep mode will be used between connection evenrs or system function is suspended. oscillation block in rf block is suspeded, communication time interval will be counted by low power clock supplied from external pin. [application sleep] application sleep mode will suspend oscillation in rf block, and stand by with low power clock supplied from external pin. this is low power mode used in the case communications is unnecessary. sleep command issue by host cpu makes become this mode, and this mode is kept till wake up from external pin.
fedl7105-002-01 ML7105-002 20/30 power state transition power mode transition is described in fig.1 fig. 1 power state transition and operating mode [power on] assert hardware reset pin for a definite period when power supply is started.ml7105 will become oot state when hardware reset is released. [boot state] booting operation will be started when hardware reset is released. booting program will execute to initileze peripheral blocks and download of parameters. [connection state] communication setting and application processing will be performed in active mode. [short interval or application processing state] short period ( Q 40msec) between communications and simple application processing will be performed in sleep mode. [long interval state] deep sleep mode will be used during a long period of waiting for radio commutication or when no access is made by host for a certain time in a non-communication period. deep sleep mode is kept with 32.768khz low power clock from an external pin. (note) in this state, the communication interval is counted by the internal timer, enabling ml7105 to return from the deep sleep mode temporarily at the timer expiration (a t about 40-second interval). when you want to keep the deep sleep state, make a transition to the sleep state. active mode appli- cation sleep [boot state] initialization and parameter load from eeprom [connection state] [sleep state] active mode [power on] power supply on hardware reset deep sleep mode hardware control (wakeup factor) [long interval state] idle mode [short interval or application processing state] hci mode baci mode
fedl7105-002-01 ML7105-002 21/30 [sleep state] it is allowed to become shutdown state if all operations can be temporarily stopped, by baci command or hci vender command. sleep mode will suspend 26mhz cloc k in rf block, and be kept with 32.768khz low power clock from external pin till wakeup. (note) in the hci mode, the transition to the long interval state or sleep state is not performed. wakeup factor wakeup factor is necessary to return from deep sleep mode or application sleep. wakeup factor, low state of gpio1 pin or wakeup pin, will be detected, and rf block clock will start to oscillate. current profile following example shows current consumption and power state transition waking up from deep sleep mode, perform rx and tx and return to deep sleep mode. idsm istb y iidle itx, ir x txo-idle tboot trx tifs tt x t dwn curren t time tinit trfinit trash t dsm irash iboot irfinit iifs status definition tdsm deepsleep period depend on connection interval trash spike from voltage regulator wake-up txo_idle start up time for xtal oscillator block for systems clock 26mhz tboot system is in booting operation trfinit initialize rf register tinit pre-processing after deep sleep mode trx packet reception tifs time between rx to tx operation ttx packet transmission tdwn post processing before moving to deep sleep operation
fedl7105-002-01 ML7105-002 22/30 host interfaces overview there are two host interfaces available shown below. spi interface ? baci mode spi-slave intrerface will be used as host interface. hostsystem can send command or receive event information via through spi inrerface. uart interface ? hci mode & debug mode uart intrerface will be used as host interface. host system can send command or receive event information via through uart interface. connection with host system connection with host system consist of serial inte rface (uart or spi-slave) and 3pins of gpio. following example shows spi-slave used as host interface. 3pins of gpio have following functionality. rf_active: indicates bluetooth communication is active or trans from deep sleep to idle/(shows higher current load). when ml7105 wake-up from deepsleep by internal timer, rf_active indicates rush current . but when ml7105 wakes-up from deepsleep by wakeup pin, or wake-up from powerdown, rf_active indicates nothing. wakeup: control signal indicate request or ready status from host system to ml7105. it has to be asserted low before start spi communication (request). irq: irq indicates request or ready status from ml7105 to host system. once ml7105 receive request from host system and it become ready, ml7105 set irq signal to low. reporting request from ml7105 will be done by asserting irq signal to low. lapis u8
fedl7105-002-01 ML7105-002 23/30 behavior of each pins are described below. the normal state of the rf_active pin is low. the normal states of the wakeup, irq, and spixcs pins are high. the spi communication is performed in the following sequence: - communication request from host 1. host toggles the wakeup pin to low. 2. when ml7105 detects wakeup and goes to the ready state, ml7105 toggles the irq pin to low. 3. host starts the spi communication. during the co mmunication, host toggles the spixcs pin to low. 4. when the spi communication is completed, host toggles the wakeup pin to high. 5. when ml7105 detects that the wakeup pin turns to high, ml7105 toggles the irq pin to high. [note] when transmitting dummy data other than baci packet from host, be sure to transmit 0xff. - communication request from ml7105 (when transmitting one baci packet ) 1. ml7105 toggles the irq pin to low. 2. when host detects irq and goes to the ready state, host toggles the wakeup pin to low. 3. host starts the spi communication. during the co mmunication, host toggles the spixcs pin to low. ml7105 outputs the dummy data (0xff) and then starts the transmission of the baci packet. 4. ml7105 starts transmitting the baci packet. 5. when host completes receiving the baci packet, host must toggle the wakeup pin to high. 6. when ml7105 detects that the wakeup pin turns to high, ml7105 toggles the irq pin to high. - timing control when a communication request from host is made after toggling the irq signal to high, ml7105 transitions to the deep sleep mode if no communication request from host is made for a specified period (abou t 1 ms). during this transition to the deep sleep mode, no communication request from host is accepted. therefore, insert a wait of 3 ms or more after toggling the wakeup signal to high before toggling it to low, so that a communication request from host can be accepted. if there is no irq signal response to the communication request from host, perform the retry process (toggle the wakeup signal back to high and then toggle it to low again).
fedl7105-002-01 ML7105-002 24/30 wakeup irq spi default high default high spixcs default high ready request 1st data transfer (ml7105 host) ff ready request 2nd data transfer (ml7105 host) ff - communication request from ml7105 (when transmitting two baci packets continuously) 1. ml7105 toggles the irq pin to low. 2. when host detects irq and goes to the ready state, host toggles the wakeup pin to low. 3. host starts the spi communication. during the co mmunication, host toggles the spixcs pin to low. ml7105 outputs the dummy data (0xff) and then starts the transmission of the baci packet. 4. when host completes receiving the baci packet, host must toggle the wakeup pin to high. 5. if there are more baci packets to be transmitted continuously, ml7105 keeps irq in the low state. 6. when host detects that irq is in the low state, host must toggle the wakeup pin to low. 7. host starts the spi communication. during the co mmunication, host toggles the spixcs pin to low. ml7105 outputs the dummy data (0xff) and then starts the transmission of the second baci packet. 8. when host completes receiving the baci packet, host must toggle the wakeup pin to high. 9. when ml7105 detects that the wakeup pin turns to high, ml7105 toggles the irq pin to high.
fedl7105-002-01 ML7105-002 25/30 behavior of rf_active is shown below. the rf_active pin outputs high during the period of rf communication or calibration where an increased current is required. the rf_active pin outputs high also at return from deep sleep by the internal timer, since the current increases due to the rush current. the rf_active pin outputs high during the t_rf_act period before the current increases. the value of t_rf_act varies depending on the cause to be notified. when rf_active notifies the current increase due to rf communication, t_rf_act is 625 sec * 2 = about 1.2 msec or 625 sec *3 = about 1.8 msec. on the other hand, t_rf_act is about 1 msec at return from deep sleep. the rf_active pin is toggled to low when the rf communication is completed or at transition to deep sleep. while the rf communication continues, the rf_active pin always outputs high. at a return from power-down or at a return to idle from deep sleep by the wakeup pin, the current increases due to the rush current just like the case at the return from deep sleep by the internal timer. however, the rf_active pin does not output high in this case.
fedl7105-002-01 ML7105-002 26/30 spi interface description possible combination of parameters are described below when spi-slave block are used as host interface. table 1 spi_slave settings parameter spec bit rate typ. 32.768khz max. 1.625mhz spi mode motorola spi (mode 3) data size 8 bits chip select low active uart interface description possible combination of parameters are described be low when uart block are used as host interface. table 2 uart settings parameter spec baud rate 57600bps data size 8 bits parity bit no parity stop bit 1 stop bit flow control no
fedl7105-002-01 ML7105-002 27/30 package dimensions notes for mounting the surface mount type packages the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl7105-002-01 ML7105-002 28/30 application example the following circuit shows the typical application circuit. this circuit may vary depending on the shipment time or other factor. this circuit shows ml7105 application example and does not guarantee the characteristics. it is recommended that choosing and finalize the best component valuse by evaluationg on the target board. xo n (14) xo p (13) tmode (30) efuse (15) a1 (1) a0 (32) gpio0 (26) gpio1 (27) gpio2 (28) gndpkg (9) vddbat (23) vddio (8) regout (16) vddcore (6) vddvco (29) gpio3 gndpkg has to be connected gnd pattern of pcb
fedl7105-002-01 ML7105-002 29/30 revision history page document no. date previous edition current edition description fedl7105-002-01 june, 10, 2013 ? ? final 1 st edition
fedl7105-002-01 ML7105-002 30/30 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013 lapis semiconductor co., ltd.

▲Up To Search▲

Price & Availability of ML7105-002

	To Download ML7105-002 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .