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________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 1 / 1 4 u m 34 87e 15kv esd - protected, fail - safe, hot - swappable a uto polarity reversal rs - 485 transceiver s um3487e sop8 /dip8 general description the um3487e series are +3.3 v powered 15kv esd protected, fail - safe, hot - swap pable , auto p olarity reversal rs - 485 transceivers. t h e device include s fail - safe circuitry, which guarantees a logic - high receiver output when the receiver inputs are open, shorted or idle. this means that the receiver output will be logic high if all transmitters on a terminated bus are disab led (high impedance). the um3487e features reduced slew - rate driver that minimizes emi and reduces reflections caused by improperly terminated cables, allowing error - free data transmission up to 500kbps. all tr ansmitter outputs and receiver inputs are protected to 15kv using the human body model and iec 6 1000 - 4 - 2, air - gap discharge . the um3487e include s cable auto - invert functions that reverse the polarity of the rs485 bus pins in case the cable is misconnec te d . r eceiver s full fail - safe features are m aintained even when the r eceiver polarity has been revers ed. the transceivers typically draw 3 00a of supply current when unloaded, or when fully loaded with the drivers disabled. the device ha s a 1/8 - unit - load rec eiver input impedance that allows up to 256 tra nsceivers on the bus and is intended for half - duplex communications. applications features ? smart meters/automated meter reading systems ? industrial - control local area networks ? profibus? and other rs - 485 b ased field bus networks ? building lighting and environmental control systems ? high node count rs - 485 systems ? transceivers for emi - sensitive applications ? automatic polarity reversal rs - 485 transceivers ? i/o logic compatible with +5v, + 3.3v & +1.8v logic ? esd p rotection for rs - 485 i/o pins 15kv ? true fail - safe receiver ? enhanced slew - rate limiting ? C ? allows up to 256 transceivers on the bus ? thermal shutd own ? current - limiting for driver overload protection pin configurations top view o rdering information part number marking code operating temperature package type UM3487EESA UM3487EESA - 40 c to + 85 c sop8 um3487eepa um3487eepa - 40 c to + 85 c dip8 r o r e d e d i v c c l 1 l 2 g n d 1 2 3 4 5 6 7 8 x x x x x x x x x x x x
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 2 / 1 4 u m 34 87e absolute maximum ratings s ymbol p arameter v alue u nit v cc supply voltage + 7 v control input voltage ( / re, de) - 0.3v to 7v v driver input voltage (di) - 0.3v to 7v v driver output voltage ( l1 , l2 ) - 7.5 to +12.5 v receiver input voltage ( l1 , l2 ) - 7.5 to +12.5 v receiver output voltage (ro) - 0.3v to (v cc + 0.3v) v t a ambient temperature - 40 to +85 c t stg storage temperature range - 65 to + 1 6 0 c t l lead temperature for s oldering 10 seconds +300 c dc electrical characteristics (v cc = + 3.3 v 5% , t a = t min to t max , unless otherwise noted. typical values are at v cc = + 3.3 v and t a = +25c.) (note 1) p arameter s ymbol test c onditions m in t yp m ax u nit supply current supply current i cc no load, di = gnd or v cc de = v cc , /re =0v or v cc 0.35 ma de =0v, /re =0v 0.25 supply current in shutdown mode i shdn de = gnd, /re = v cc 0.1 1 a logic input high voltage v ih1 de, di, /re 1 . 5 v input low voltage v il1 de, di, /r e 0. 4 v di input hysteresis v hys 1 8 0 mv driver differential driver output v od1 no load , figure 2 3.2 3.3 v differential driver output v od2 figure 2, r = 54 1.5 v change - in - magnitude of differential output voltage v od figure 2, r = 54 ; (note 2) 0. 1 v driver common - mode output voltage v oc figure 2, r = 54 1.4 1.8 v change - in - magnitude of common - mode voltage v oc figure 2, r = 54 ; (note 2) 0. 1 v driver short - circuit output current (note 3) i osd v out = - 7v - 250 ma v out = 12v 250
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 3 / 1 4 u m 34 87e dc electrical characteristics ( continued ) (v cc = + 3.3 v 5%, t a = t min to t max , unless otherwise noted. typical values are at v cc = + 3.3 v and t a = +25c.) (note 1) parameter symbol test conditions min typ max unit receiver receiver diff erential threshold voltage v th - 7vv cm 12v - 200 - 50 mv receiver input hysteresis v th v cm =0v 5 0 mv receiver input resistance r in - 7vv cm 12v 96 k input current (l1 and l2) i in2 de = gnd, v cc = gnd or 5v v in = 12v 1.0 ma v in = - 7v - 0.8 receiver output high voltage v oh i o = - 1.5ma, v id = 200mv v cc - 0.2 v receiver output low voltage v ol i o = 2.5ma, v id = 200mv 0. 3 v three - state output current at receiver i ozr 0v v o v cc 1 a receiver output short circuit current i osr 0vv ro v cc 10 4 0 ma esd protection e sd protection for a, b human body model 15 kv iec61000 - 4 - 2 air discharge 15 iec61000 - 4 - 2 contact 8 note 1: all currents into the device are positive; all currents out of the device are negative. all voltages are referred to device ground unless otherwise noted. note 2: v od and v oc are the changes in v od and v oc , respectively, when the di input changes state. note 3 : maximum current level applies to peak current just prior to fold back current limiting; minimum current level applies during current limiting.
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 4 / 1 4 u m 34 87e switching characteristics (v cc = + 3.3 v 5%, t a = t min to t max , unless otherwise noted. typical values are at v cc = + 3.3 v and t a = +25c.) parameter symbol test conditions min typ max unit maximum data rate f max 500 k bps driver input - to - output t dpl h figures 3 and 7 , r diff = 54 , c l1 = c l2 = 100pf 50 100 2 00 ns t dphl 50 100 2 00 driver output skew | t dplh - t dphl | t dskew figures 3 and 7 , r diff = 54, c l1 = c l2 = 100pf 3 100 ns driver rise or fall time t dr , t df figures 3 and 7 , r diff = 54, c l1 = c l2 = 100pf 100 200 500 ns driver enable to output high t dzh figures 4 and 8 , c l = 100pf, s2 closed 100 2500 ns driver enable to output low t dzl figures 4 and 8 , c l = 100pf, s1 closed 100 2500 ns driver disable time from low t dlz figures 4 and 8 , c l = 15pf, s1 closed 50 100 ns driver disable time from high t dhz figures 4 and 8 , c l = 15pf, s2 closed 50 100 ns receiver input to output t rplh , t rphl | v id | 1 .0v; rise and fall time of v id 15ns 100 200 ns differential receiver skew | t rplh - t rphl | t rskd figures 6 and 9 ; | v id | 1 .0v; rise and fall time of v id 15ns 3 30 ns receiver enable to output low t rz l figures 5 and 10 , c l = 100pf, s1 closed 20 2 00 ns receiver enable to output high t rzh figures 5 and 10 , c l = 100pf, s2 closed 20 200 ns receiver disable time from low t rlz figures 5 and 10 , c l = 100pf, s1 closed 20 200 ns receiver disable time from high t rhz figures 5 and 10 , c l = 100pf, s2 closed 20 200 ns time to shutdown t shdn (note 4 ) 50 200 600 ns driver enable from shutdown to output high t dzh(shdn) figures 4 and 8 , c l = 15pf, s2 closed 4500 ns driver enable from shutdown to output low t dzl(shdn) figures 4 and 8 , c l = 15pf, s1 c losed 4500 ns receiver enable from shutdown to output high t rzh(shdn) figures 5 and 10 , c l = 100pf, s2 closed 3500 ns receiver enable from shutdown to output low t rzl(shdn) figures 5 and 10 , c l = 100pf, s1 closed 3500 ns note 4 : the device is put into shutdown by bringing /re high and de low. if the enable inputs are in this state for less than 50ns, the device is guaranteed not to enter shutdown. if the enable inputs are in this state for at least 600ns, the device is guaranteed to have entered s hutdown.
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 5 / 1 4 u m 34 87e non - polarity features t he polarities of driver and receiver is always kept the same status. when de= /re =logic 0 a nd ro is standing logic 0 for t s time, the polarities will be reversed automatically . parameter symbol test conditions min typ max u nit w ait ing t ime for i nverting t s de= /re =l, ro keep s l 150 2 00 2 50 ms pin description pin number symbol function 1 ro receiver output. 2 /re receiver enable. drive /re low to enable r eceiver, ro is high impedance when /re is high. drive /re high and de low to enter low - power shutdown mode. 3 de driver enable. drive de high to enable driver s . the outputs are high impedance when de is low. drive /re high and de low to enter low - power shutdown mode. 4 di driver input. 5 gnd ground 6 l2 a uto polarit y reversal receiver input and driver output pin. when power up, the bus pins have their normal polarity definition of l2 as non inverting and l1 as inverting; otherwise l2 become inverting and l1 become non inverting for reversal status . 7 l1 8 v cc pow er supply for rs - 485 transceiver rs - 485 communication function table table1. transmit t ing inputs outputs /re de di a b x h h/o h l x h l l h l l/o x z z h l/o x shutdown table2. receiving h: high, l: low, x: do not care, z: high impedance. in normal rs485 polarity status, l2=a and l1=b, o therwise l2=b and l1=a. inputs outputs /re de v id =v a - v b r o l x
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 6 / 1 4 u m 34 87e typical operating characteristics (v cc =3.3v, driver o utput and receiver output no load, unless otherwise noted.) r load =5 k r load =5 k r load =5 4
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 7 / 1 4 u m 34 87e r load =5 4 r load =5 4
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 8 / 1 4 u m 34 87e typical operating circuit figure 1 . typical half - duplex non - polarity rs - 485 network test circuit figure 2 . dr iver dc test load figure 3 . driver timing test circuit figure 4 . driver enable / disable timing test load figure 5 . receiver enable / disable timing test load l 1 l 2 r load / 2 r load / 2 v od v oc 1 k 1 k v cc s 1 s 2 + c rl 15 pf test point receive output l 1 l 2 di de 3 v v od 2 c l 2 c l 1 r diff + c l s 1 s 2 v cc driver output under test 500 ohm r d di de ro re r d di de ro re r d de ro re di b a l 1 l 2 l 1 l 2 r d de di ro re l 1 l 2 120 ohm 120 ohm 5 0 0 o h m 5 0 0 o h m + 5 v gnd l 1 l 2 master node slave node 1 slave node n terminal slave node all um 3487 e ' s l 1 l 2 pin can interchange each other ;
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 9 / 1 4 u m 34 87e figure 6 . receiver propagation delay test circuit figure 7 . driver propagation delays figure 8 . driver enable and disable times figure 9 . receiver propagation delays figure 10 . receiver enable and disable times di 3 v l 1 0 v l 2 v o 1 . 5 v 1 . 5 v t dplh t dphl 1 / 2 v o 1 / 2 v o - v o v o 0 v v diff 90 % 90 % 10 % 10 % t df t dr v diff = v l 1 - v l 2 t skew = | t dplh - t dphl | o u t p u t n o r m a l l y l o w o u t p u t n o r m a l l y h i g h d e 3 v l 1 0 v l 2 1 . 5 v 1 . 5 v v o l v o h v o l v o h 1 . 4 v 1 . 4 v t d l z t d z l ( s h d n ) , t d z l t d h z t d z h ( s h d n ) , t d z h v o l + 0 . 5 v v o h - 0 . 5 v v o h v o l r o 1 v - 1 v l 1 l 2 1 . 5 v 1 . 5 v o u t p u t i n p u t t r p l h t r p h l o u t p u t n o r m a l l y l o w o u t p u t n o r m a l l y h i g h r e 3 v 0 v r o 1 . 5 v v o h v o l 1 . 5 v 1 . 5 v t r l z t r z l ( s h d n ) , t r z l t r h z t r z h ( s h d n ) , t r z h v o l + 0 . 5 v v o h - 0 . 5 v 1 . 5 v ate v d r b a receiver output
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 10 / 1 4 u m 34 87e detail description polarity reversal function with large node count rs485 network, it is common for some cable data lines to be wired backwards during installation. when this happens, the node is unable to c ommunicate over, he must then rewire the connector, which is time consuming. the um3487e simplifies this task by including an automatic polarity reversal function inside. upon um3487e power up, when de=/re=logic low, and ro keeps logic low over a predefine d time t s (i.e t s =200ms in um3487e), the chip reverse its bus pins polarity, so b become non - inverting, and a become inverting. otherwise, the chip operates like any standard rs485 transceiver, and the bus pins have their normal polarity definition of a as non inverting and b as inverting. union semi s unique automatic polarity reversal function is superior to that found on competing devices, because the receiver s full fail safe function is maintained, even when the rx polarity is reversed. fail - safe and hot - swap the um3487e guarantees a logic high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. this is done by setting the receiver input threshold between - 50mv and - 200mv. if the differential receiver input voltage v id is greater than or equal to - 50mv, ro id logic high. if v id is less than or equal to - 200mv, ro is logic low. in the case of a terminated bus with all transmitters disabled, the receiver s di fferential input voltage is pulled to 0v by the termination. with the receiver threshold of um3487e, this results in logic high with a 50mv minimum noise margin, and this - 50mv to - 200mv threshold complies wi th the 200mv eia/tia - 485 standard. when circuit boards with rs485 transceiver are inserted into a hot or powered backplane, differential dist urbances to the data bus cab lead to data errors. upon initial circuit board insertion, the microprocessor undergoes its own power - up sequence. during this period , the processor/s logic output drivers are high impedance and unable to driver the de and /re inputs of these devices to a defined logic level. leakage currents up to 1 0 a from the high impedance state of processor s logic drivers could cause standard cmos enable inputs of a transceiver to drift to an incorrect logic level. additionally , parasitic circuit board capacitance could cause coupling of v cc or gnd to the enable inputs. without the hot - swap capability, these facts could improperly enable the transceiver s driver or receiver. when vcc rises, an internal pull down circuit holds de low and /re high. after the initial power up sequence, the pull down/pull up circuit becomes transparent, resetting the hot - swap tolerable input. this hot - swap input circuit enhance s um3487e s performance in harsh environment application. 15kv esd protection all pins on um3487e device include esd protection structures, and the family inc orporates advanced structures which allow the rs - 485 pins ( l1, l2 ) to survive esd events up to 15kv. the rs - 485 pins are particularly vulnerable to esd damage because they typically connect to an exposed port on the exterior of the finished product. the e sd structures withstand high esd in all states: normal operation, shutdown, and powered down. after an esd event, c ircuits keep working without latch up. the esd protection can be tested in various ways and with reference to the ground pin . t he l1 , l2 are characterized for protection to the following limits: 15kv using the human body model and iec 6 1000 - 4 - 2 , air - gap discharge , and 8kv contact discharge. t he logic pin s (ro, /re , de, di) are characterized for protection to the following limits: 2kv using th e human body model .
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 11 / 1 4 u m 34 87e applications information n on - polarity transceiver when establish ed the n on - polarity rs - 485 net, you should pay attention to two conditions. first, a pair of bias r esistance (pull - up to +5v for r s - 4 85 a bus, p ush - down to gnd for rs - 485 b bus) mu st be required, usually be buil t in the master node, or independently , 500 ? resistance is recommend ed . t he other node s don t need bias resistance anymore . second, the transce iver rat e must be higher than 100 bps or the maxim um transmitt ing time for low logic should be less than 100m s . 256 transceivers on the bus the standard rs - 485 receiver input impedance is 12k (one unit load), and the standard driver can drive up to 32 uni t loads. the union family of transceivers have a 1/8 unit load receiver input impedance (96k), allowing up to 256 transceivers to be connected in parallel on one communication line. any combination of these devices and/or other rs - 485 transceivers with a total of 32 unit loads or less can be connected to the line. low - power shutdown mode low - power shutdown mode is initiated by bringing both /re high and de low. in shutdown, the dev ice typically draw s only 10u a of supply current. /re and de may be driven simultaneously; the parts are guaranteed not to enter shutdown if /re is high and de is low for less than 50ns. if the inputs are in this state for at least 600ns, the parts are guaranteed to enter shutdown. enable times t zh and t zl in the switching charac teristics tables assume the part was not in a low - power shutdown state. enable times t zh(shdn) and t zl(shdn) assume the parts were shut down. it takes drivers and receivers longer to become enabled from low - power shutdown mode (t zh(shdn ), t z l (shdn) ) than f rom driver/receiver - disable mode (t zh , t zl ). driver output protection two mechanisms prevent excessive output current and power dissipation caused by faults or by bus contention. the first, a foldback current limit on the output stage, provides immediate protection against short circuits over the whole common - mode voltage range (see typical operating characteristics). the second, a thermal shutdown circuit, forces the driver outputs into a high - impedance state if the die temperature becomes excessive. lin e length vs. data rate the rs - 485/rs - 422 standard covers line lengths up to 4000 feet. for line lengths greater than 4000 feet, repeater is required. typical applications the um3487e transceivers are designed for bidirectional data communications on multi point bus transmission lines. to minimize reflections, the line should be terminated at both ends in its characteristic impedance, and stub lengths off the main line should be kept as short as possible.
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 12 / 1 4 u m 34 87e package information um3487e esa sop8 outline draw ing dimensions symbol millimeters inches min max min max a 1.350 1.750 0.053 0.069 a1 0.100 0.250 0.004 0.010 a2 1.350 1.550 0.053 0.061 b 0.33 0.51 0.013 0.020 c 0.170 0.250 0.006 0.010 d 4.700 5.100 0.185 0.200 e 3.800 4.000 0.150 0.157 e1 5.800 6.200 0.228 0.244 e 1.270 (bsc) 0.050 (bsc) l 0.400 1.270 0.016 0.050 0 8 0 8 land pattern notes: 1. compound dimension: 4.90 3.90 ; 2. unit: mm; 3. general tolerance 0 .0 5 mm unless otherwise specified; 4. the layout is just for reference. tape and reel orientation d e 1 e e 1 2 t o p v i e w l c e n d v i e w a 2 b a 1 a s i d e v i e w 4 . 9 5 1 . 3 0 1 . 2 7 0 . 5 0 u m 3 4 8 7 e e s a x x
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 13 / 1 4 u m 34 87e um3487eepa dip8 outline drawing dimensions symbol millimeters inches min max min max a - 5.08 - 0.200 a1 0.38 - 0.015 - a2 3.18 4.45 0.125 0.175 a3 1.40 2.03 0.055 0.080 b 0.41 0.56 0.016 0.022 b1 1.14 1.65 0.045 0.065 c 0.20 0.30 0.008 0.012 d (8 pin) 8.84 9.91 0.348 0.390 d1 0.13 2.03 0.005 0.080 e 7.62 8.26 0.300 0.325 e1 6.10 7.87 0.240 0.310 e 2.54 - 0.100 - ea 7.62 - 0.300 - eb - 10.16 - 0.400 l 2.92 3.81 0.115 0.150 d d 1 a 3 a 2 a 1 a l e b b 1 e 1 e e a e b c
________________________________________________________________________ http://www.union - ic.com rev.0 2 jan .20 1 4 14 / 1 4 u m 34 87e important notice the information in this document has been carefully reviewed and is believed to be accurate. nonetheless, this document is subject to c hange without notice. union assumes no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update or to keep current the contained information, or to notify a person or organization of any update. union re serves the right to make changes, at any time, in order to improve reliability, function or design and to attempt to supply the best product possible. union semiconductor, inc add : 2f, building 3 , lane 647, songtao road, shanghai 201203 tel: 021 - 51093966 fax: 021 - 51026018 website: www.union - ic.com

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