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publication number s71ws256/128/064j_cs revision a amendment 0 issue date october 27, 2004 advance datasheet distinctive characteristics mcp features ? power supply voltage of 1.7 to 1.95v ? speed: 66mhz ? packages ? 8 x 11.6mm, 84 ball fbga ? 7 x 9mm, 80-ball fbga ? operating temperature ??25c to +85c ??40c to +85c general description the s71ws series is a product line of stacked multi-chip product (mcp) packages and consists of: ? one or more flash memory die ? psram the products covered by this document are listed in the table below. for details about their specifications, please refer to the individual constituent datasheets for further details: flash memory density 256mb 128mb 64mb psram density 64mb s71ws256jc0 s71ws128jc0 32mb s71ws128jb0 s71ws064jb0 16mb s71ws128ja0 s71ws064ja0 s71wsxxxj based mcps stacked multi-chip product (mcp) 128/64 megabit (8m/4m x 16-bit) cmos 1.8 volt-only, simultaneous read/write, burst mode flash memory with cosmoram
2 s71wsxxxj based mcps s71ws256/128/064j_csa0 october 27, 2004 product selector guide device-model# flash density psram density flash speed (mhz) psram speed (mhz/ns) supplier package availability status s71ws064ja0-2y 64mb 16mb 66 66/70 cosmo ram tlc080 advanced s71ws064jb0-2y 32mb cosmo ram advanced s71ws128ja0-ay 128mb cosmo ram tla084 preliminary s71ws128jb0-ay cosmo ram preliminary s71ws128jc0-ay 64mb cosmo ram preliminary s71ws256jc0-ty 256mb cosmo ram fta084 advanced
october 27, 2004 s71ws256/128/064j_csa0 3 advance information s71wsxxxj based mcps distinctive characteristics . . . . . . . . . . . . . . . . . . . 1 mcp features ........................................................................................................ 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 1 product selector guide . . . . . . . . . . . . . . . . . . . . . .2 connection diagram (cosmoram type-based) . .7 special handling instructions for fbga package ...................................8 connection diagram (cosmoram type-based) . .9 special handling instructions for fbga package ................................. 10 lookahead connection diagram . . . . . . . . . . . . . 11 input/output descriptions . . . . . . . . . . . . . . . . . . . 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . 13 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . 16 tla084?84-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package ........................................................................................... 16 fta084?84-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package ............................................................................................17 tlc080?80-ball fine-pitch ball grid array (fbga) 7 x 9 mm package ............................................................................... 18 s29ws128/064j general description . . . . . . . . . . . . . . . . . . . . . . . . 22 product selector guide . . . . . . . . . . . . . . . . . . . . .24 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 block diagram of simultaneous operation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 25 input/output descriptions . . . . . . . . . . . . . . . . . . .26 device bus operations . . . . . . . . . . . . . . . . . . . . . . 27 table 1. device bus operations .......................................... 27 versatileio? (v io ) control .............................................................................27 requirements for asynchronous read operation (non-burst) ..........27 requirements for synchronous (burst) read operation ...................... 28 8-, 16-, and 32-word linear burst with wrap around ..................... 29 table 2. burst address groups ............................................ 29 configuration register ..................................................................................... 29 handshaking ......................................................................................................... 29 simultaneous read/write operations with zero latency ................... 30 writing commands/command sequences ................................................ 30 accelerated program operation .................................................................. 30 autoselect mode ..................................................................................................31 table 3. autoselect codes (high voltage method) ................. 32 sector/sector block protection and unprotection ..................................32 table 4. s29ws128/064j_mcp boot sector/sector block addresses for protection/unprotection ................................................. 32 table 5. s29ws064j boot sector/sector block addresses for protection/unprotection ..................................................... 34 sector protection ...........................................................................................36 persistent sector protection ...........................................................................36 persistent protection bit (ppb) ..................................................................37 persistent protection bit lock (ppb lock) .............................................37 dynamic protection bit (dyb) ...................................................................37 table 6. sector protection schemes ..................................... 38 persistent sector protection mode locking bit ........................................39 password protection mode .............................................................................39 password and password mode locking bit ................................................39 64-bit password .................................................................................................. 40 persistent protection bit lock ....................................................................... 40 standby mode ...................................................................................................... 40 automatic sleep mode ...................................................................................... 41 reset#: hardware reset input ................................................................. 41 output disable mode ................................................................................... 42 figure 1. temporary sector unprotect operation ................... 42 figure 2. in-system sector protection/sector unprotection algorithms........................................................................ 43 table 7. secsi? sector addresses ...................................... 44 secsi? sector protection bit ...................................................................... 45 hardware data protection ......................................................................... 45 write protect (wp#) ....................................................................................... 45 low v cc write inhibit ................................................................................. 46 write pulse ?glitch? protection ............................................................... 46 logical inhibit ................................................................................................... 46 power-up write inhibit ............................................................................... 46 common flash memory interface (cfi) . . . . . . . 47 table 8. cfi query identification string ................................ 47 table 9. system interface string ......................................... 48 table 10. device geometry definition................................... 48 table 11. primary vendor-specific extended query ................ 49 table 12. ws128j sector address table ............................... 50 table 13. ws064j sector address table ............................... 58 command definitions . . . . . . . . . . . . . . . . . . . . . . 64 reading array data ........................................................................................... 64 set configuration register command sequence ..................................... 64 figure 3. synchronous/asynchronous state diagram.............. 65 read mode setting ......................................................................................... 65 programmable wait state configuration ............................................... 65 table 14. programmable wait state settings ......................... 66 standard wait-state handshaking option ............................................... 66 table 15. wait states for standard wait-state handshaking .... 66 read mode configuration ........................................................................... 66 table 16. read mode settings ............................................. 67 burst active clock edge configuration .................................................. 67 rdy configuration ........................................................................................ 67 table 17. configuration register .......................................... 68 reset command .................................................................................................68 autoselect command sequence ....................................................................68 enter secsi? sector/exit secsi? sector command sequence ............. 69 program command sequence ........................................................................ 70 unlock bypass command sequence ........................................................ 70 figure 4. program operation ............................................... 71 chip erase command sequence .................................................................... 71 sector erase command sequence ................................................................ 72 erase suspend/erase resume commands .................................................. 73 figure 5. erase operation ................................................... 74 password program command ....................................................................... 74 password verify command ............................................................................. 74 password protection mode locking bit program command .............. 75 persistent sector protection mode locking bit program command 75 secsi? sector protection bit program command ................................... 75 ppb lock bit set command ............................................................................ 75 dpb write/erase/status command ............................................................. 76 password unlock command .......................................................................... 76 ppb program command .................................................................................. 76 all ppb erase command .................................................................................. 77 ppb status command ....................................................................................... 77 ppb lock bit status command ...................................................................... 77 command definitions ....................................................................................... 78 table 18. command definitions .......................................... 78 write operation status . . . . . . . . . . . . . . . . . . . . . 81 dq7: data# polling .............................................................................................81 figure 6. data# polling algorithm ........................................ 82
4 s71ws256/128/064j_csa0 october 27, 2004 advance information dq6: toggle bit i ................................................................................................83 figure 7. toggle bit algorithm.............................................. 84 dq2: toggle bit ii .............................................................................................. 84 table 19. dq6 and dq2 indications ..................................... 85 reading toggle bits dq6/dq2 ..................................................................... 85 dq5: exceeded timing limits ....................................................................... 86 dq3: sector erase timer ................................................................................ 86 table 20. write operation status ......................................... 87 absolute maximum ratings . . . . . . . . . . . . . . . . . .88 figure 8. maximum negative overshoot waveform ................. 88 figure 9. maximum positive overshoot waveform .................. 88 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 89 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . .90 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 10. test setup ......................................................... 91 table 21. test specifications ............................................... 91 key to switching waveforms . . . . . . . . . . . . . . . 91 switching waveforms . . . . . . . . . . . . . . . . . . . . . 91 figure 11. input waveforms and measurement levels............. 91 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . .92 v cc power-up ..................................................................................................... 92 figure 12. v cc power-up diagram ........................................ 92 clk characterization ....................................................................................... 92 figure 13. clk characterization ........................................... 92 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 93 synchronous/burst read @ v io = 1.8 v ......................................................93 figure 14. clk synchronous burst mode read (rising active clk).............................................................. 94 figure 15. clk synchronous burst mode read (falling active clock) .......................................................... 94 figure 16. synchronous burst mode read.............................. 95 figure 17. 8-word linear burst with wrap around................... 95 figure 18. linear burst with rdy set one cycle before data .... 96 asynchronous mode read @ v io = 1.8 v ..................................................97 figure 19. asynchronous mode read with latched addresses ... 98 figure 20. asynchronous mode read..................................... 98 figure 21. reset timings..................................................... 99 erase/program operations @ v io = 1.8 v ................................................100 figure 22. asynchronous program operation timings: avd# latched addresses ........................................................... 101 figure 23. asynchronous program operation timings: we# latched addresses ........................................................... 102 figure 24. synchronous program operation timings: we# latched addresses ....................................................................... 103 figure 25. synchronous program operation timings: clk latched addresses ....................................................................... 104 figure 26. chip/sector erase command sequence................ 105 figure 27. accelerated unlock bypass programming timing ... 106 figure 28. data# polling timings (during embedded algorithm)............................................ 107 figure 29. toggle bit timings (during embedded algorithm).. 107 figure 30. synchronous data polling timings/toggle bit timings................................................ 108 figure 31. dq2 vs. dq6 .................................................... 108 temporary sector unprotect .......................................................................109 figure 32. temporary sector unprotect timing diagram........ 109 figure 33. sector/sector block protect and unprotect timing diagram.......................................................................... 110 figure 34. latency with boundary crossing.......................... 111 figure 35. latency with boundary crossing into program/erase bank .............................................................................. 112 figure 36. example of wait states insertion ........................ 113 figure 37. back-to-back read/write cycle timings ............... 114 cosmoram features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 pin description (32m) . . . . . . . . . . . . . . . . . . . . . . .117 functional description . . . . . . . . . . . . . . . . . . . . . 118 asynchronous operation (page mode) .......................................................118 functional description . . . . . . . . . . . . . . . . . . . . . 119 synchronous operation (burst mode) ........................................................119 state diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 120 initial/standby state ...........................................................................................120 figure 38. initial standby state diagram ............................ 120 asynchronous operation state ....................................................................120 figure 39. asynchronous operation state diagram............... 120 synchronous operation state ........................................................................121 figure 40. synchronous operation diagram ........................ 121 functional description . . . . . . . . . . . . . . . . . . . . . 121 power-up ...............................................................................................................121 configuration register ......................................................................................121 cr set sequence ................................................................................................121 power down .......................................................................................................124 burst read/write operation .........................................................................124 figure 41. burst read operation........................................ 125 figure 42. burst write operation ....................................... 125 clk input function ..........................................................................................125 adv# input function .......................................................................................126 wait# output function ................................................................................126 figure 43. read latency diagram ...................................... 127 address latch by adv# .................................................................................128 burst length ........................................................................................................128 single write .........................................................................................................128 write control ....................................................................................................129 figure 44. write controls.................................................. 129 burst read suspend ..........................................................................................129 figure 45. burst read suspend diagram............................. 130 burst write suspend ........................................................................................130 figure 46. burst write suspend diagram ............................ 130 burst read termination ..................................................................................130 figure 47. burst read termination diagram ........................ 131 burst write termination ................................................................................. 131 figure 48. burst write termination diagram........................ 131 absolute maximum ratings . . . . . . . . . . . . . . . . 132 recommended operating conditions (see warning below) . . . . . . . . . . . . . . . . . . . . . . . . . . 132 package pin capacitance . . . . . . . . . . . . . . . . . . . 132 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 133 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 134 read operation .................................................................................................134 write operation ............................................................................................... 136 synchronous operation - clock input (burst mode) ............................ 137 synchronous operation - address latch (burst mode) ....................... 137 synchronous read operation (burst mode) ............................................138 synchronous write operation (burst mode) ..........................................139 power down parameters ...............................................................................140 other timing parameters ...............................................................................140 ac test conditions .........................................................................................140 ac measurement output load circuit ......................................................141 figure 49. output load circuit........................................... 141 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 50. asynchronous read timing #1-1 (basic timing) ... 142 figure 51. asynchronous read timing #1-2 (basic timing) ... 142
october 27, 2004 s71ws256/128/064j_csa0 5 advance information figure 52. asynchronous read timing #2 (oe# & address access) ................................................... 143 figure 53. asynchronous read timing #3 (lb# / ub# byte access) .................................................. 143 figure 54. asynchronous read timing #4 (page address access after ce1# control access)................................................ 144 figure 55. asynchronous read timing #5 (random and page address access) ............................................................... 144 figure 56. asynchronous write timing #1-1 (basic timing) ... 145 figure 57. asynchronous write timing #1-2 (basic timing) ... 145 figure 58. asynchronous write timing #2 (we# control) ...... 146 figure 59. asynchronous write timing #3-1 (we# / lb# / ub# byte write control) .......................................................... 146 figure 60. asynchronous write timing #3-2 (we# / lb# / ub# byte write control) .......................................................... 147 figure 61. asynchronous write timing #3-3 (we# / lb# / ub# byte write control) .......................................................... 147 figure 62. asynchronous write timing #3-4 (we# / lb# / ub# byte write control) .......................................................... 148 figure 63. asynchronous read / write timing #1-1 (ce1# control) ................................................................ 148 figure 64. asynchronous read / write timing #1-2 (ce1# / we# / oe# control) ................................................................... 149 figure 65. asynchronous read / write timing #2 (oe#, we# control) .......................................................................... 149 figure 66. asynchronous read / write timing #3 (oe,# we#, lb#, ub# control) ................................................................... 150 figure 67. clock input timing ............................................ 150 figure 68. address latch timing (synchronous mode)........... 151 figure 69. 32m synchronous read timing #1 (oe# control).. 152 figure 70. 32m synchronous read timing #2 (ce1# control) 153 figure 71. 32m synchronous read timing #3 (adv# control) 154 figure 72. synchronous read - wait# output timing (continuous read)............................................................................. 155 figure 73. 64m synchronous read timing #1 (oe# control) . 156 figure 74. 64m synchronous read timing #2 (ce1# control) 157 figure 75. 64m synchronous read timing #3 (adv# control) 158 figure 76. synchronous write timing #1 (we# level control) 159 figure 77. synchronous write timing #2 (we# single clock pulse control) ......................................................................... 160 figure 78. synchronous write timing #3 (adv# control) ..... 161 figure 79. synchronous write timing #4 (we# level control, single write)................................................................... 162 figure 80. 32m synchronous read to write timing #1(ce1# control) ......................................................................... 163 figure 81. 32m synchronous read to write timing #2(adv# control) ......................................................................... 164 figure 82. 64m synchronous read to write timing #1(ce1# control) ......................................................................... 165 figure 83. 64m synchronous read to write timing #2(adv# control) ......................................................................... 166 figure 84. synchronous write to read timing #1 (ce1# control) ............................................................... 167 figure 85. synchronous write to read timing #2 (adv# control) ............................................................... 168 figure 86. power-up timing #1 ......................................... 169 figure 87. power-up timing #2 ........................................ 169 figure 88. power down entry and exit timing ..................... 169 figure 89. standby entry timing after read or write ............ 170 figure 90. configuration register set timing #1 (asynchronous operation) ...................................................................... 170 figure 91. configuration register set timing #2 (synchronous operation) ...................................................................... 171 revision summary
october 27, 2004 s71ws256/128/064j_csa0 6 advance information mcp block diagram notes: 1. r-cre is only present in cellularram-compatible psram. 2. r-ce2 is only present in cosmoram-compatible psram. 3. for 1 flash = psram, f1-ce# = ce#. for 2 flash + psra m, ce# = f1-ce# and f2-ce# is the chip-enable pin for the second flash. 4. only needed for s71ws256jc0, and s70ws256j00. 5. clk and avd# not applicable for 16mb psram. v id v cc rdy psram flash 1 dq15 to dq0 flash-only address shared address (note 3) f1-ce# f-acc r-ub# (note 1) r-ce2 (note 2) r-cre r-v cc v cc v ccq f-vcc a22 clk clk f-wp# oe# we# f-rst# avd# ce# acc wp# oe# we# reset# avd# rdy v ss v ssq dq15 to dq0 16 i/o15 to i/o0 16 r-ce1# ce# we# oe# ub# r-lb# lb# a22 (note 3) f2-ce# clk avd# flash 2 (note 4) (note 5) (note 5) wait#
7 s71ws256/128/064j_csa0 october 27, 2004 advance information connection diagram (cosmoram type-based) notes: 1. in mcp?s based on a single s29wsxxxj (s71wsxxxj), ball b5 is rfu. in mcp?s based on two s29wsxxxj (s71ws256j), ball b5 is ce#f2 or f2-ce#. 2. addresses are shared btween flash and ra m depending on the density of the psram. mcp flash-only addresses shared addresses s71ws064ja0 a21-a20 a19-a0 s71ws064jb0 a21 a20-a0 s71ws128ja0 a22-a20 a19-a0 s71ws128jb0 a22-a21 a19-a0 s71ws128jc0 a22 a21-a0 s71ws256jc0 a22 a21-a0 e4 ub#s f4 a18 g4 a17 h4 dq1 j4 dq9 dq10 d4 e6 ce2s a20 j6 dq4 vccs d6 e7 a19 f7 a9 g7 a10 h7 dq6 j7 dq13 dq12 d7 e5 reset# rdy j5 dq3 vccf d5 e8 a12 f8 a13 g8 a14 h8 rfu j8 dq15 dq7 d9 e9 f9 a21 g9 a22 a16 j9 rfu vss e3 a6 f3 a5 g3 a4 h3 vss j3 oe# dq0 ce1#s d3 e2 f2 a2 g2 a1 h2 a0 j2 ce1#f h6 h5 1st flash only legend reserved for future use a3 d2 a15 d10 a1 nc a10 nc m1 m10 nc nc c4 lb#s we# c7 a8 acc c8 a11 c9 rfu c3 a7 c2 wp# c6 b4 clk rfu b7 rfu f2-ce# b8 rfu b9 rfu b3 rfu b2 avd# b6 b5 l4 rfu rfu l7 rfu vccf l8 rfu l9 rfu l3 rfu l2 rfu l6 k4 dq2 rfu k7 dq5 dq11 k8 dq14 k9 rfu k3 dq8 k2 rfu k6 k5 rfu rfu g6 g5 a23 rfu f6 f5 c5 h9 l5 1st ram only shared 2nd flash only 84-ball fine-pitch ball grid array cosmoram-based pinout (top view, balls facing down)
october 27, 2004 s71ws256/128/064j_csa0 8 advance information special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultra- sonic cleaning methods. the package and/ or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged peri- ods of time.
9 s71ws256/128/064j_csa0 october 27, 2004 advance information connection diagram (cosmoram type-based) notes: 1. in mcp?s based on a single s29wsxxxj (s71wsxxxj), ball b5 is rfu. in mcp?s based on two s29wsxxxj (s71ws256j), ball b5 is ce#f2 or f2-ce#. 2. addresses are shared btween flash and ra m depending on the density of the psram. 3. the 80-ball pinout is applicable only to those mcps wi th flash density of 64mb or 32mb. for all the other mcps included in this datasheet, please use the 84-ball pinout for design. mcp flash-only addresses shared addresses s71ws064ja0 a21-a20 a19-a0 s71ws064jb0 a21 a20-a0 s71ws128ja0 a22-a20 a19-a0 s71ws128jb0 a22-a21 a19-a0 s71ws128jc0 a22 a21-a0 s71ws256jc0 a22 a21-a0 d3 ub#s e3 a18 f3 a17 g3 dq1 h3 dq9 dq10 c3 d5 ce2s a20 h5 dq4 vccs c5 d6 a19 e6 a9 f6 a10 g6 dq6 h6 dq13 dq12 c6 d4 reset# rdy h4 dq3 vccf c4 d7 a12 e7 a13 f7 a14 g7 rfu h7 dq15 dq7 c7 d8 e8 a21 f8 a22 a16 h8 rfu vss d2 a6 e2 a5 f2 a4 g2 vss h2 oe# dq0 ce1#s c2 d1 e1 a2 f1 a1 g1 a0 h1 ce1#f g5 g4 1st flash only legend reserved for future use a3 c1 a15 c8 b3 lb#s we# b6 a8 acc b7 a11 b8 rfu b2 a7 b1 wp# b5 a3 clk rfu a6 rfu f2-ce# a7 rfu a8 rfu a2 rfu a1 avd# a5 a4 k3 rfu rfu k6 rfu vccf k7 rfu k8 rfu k2 rfu k1 rfu k5 j3 dq2 rfu j6 dq5 dq11 j7 dq14 j8 rfu j2 dq8 j1 rfu j5 j4 rfu rfu f5 f4 a23 rfu e5 e4 b4 g8 k4 1st ram only shared 2nd flash only 80-ball fine-pitch ball grid array cosmoram-based pinout (top view, balls facing down)
october 27, 2004 s71ws256/128/064j_csa0 10 advance information special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultra- sonic cleaning methods. the package and/ or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged peri- ods of time.
11 s71ws256/128/064j_csa0 october 27, 2004 advance information lookahead connection diagram notes: 1. f1 and f2 denote xip/code flash, while f3 and f4 denote data/companion flash. 2. in addition to being defined as f2-ce#, ball c5 can also be assigned as f1-ce2# for code flash that has two chip enable signals. 3. for mcps requiring 3.0v vcc and 1.8v vio, use the 1.8v look-ahead pinout in order to accommodate extra avd, mrs and clk pins for the psram (if needed). 4. refer to application note on pinout subsets to match the package size offerings. 5. ball b5 is shared between flash rdy and ram wait# signals. j4 j5 j6 j7 j8 j2 h7 h8 h9 g7 g8 g9 f7 f8 f9 e7 e8 e9 k2 k3 d6 d7 f1-ce# j3 oe# r1-ce1# dq0 d2 d3 c2 c3 avd# vss f-wp# a7 a8 we# r-lb# c4 c5 c 5 c6 c7 d8 d9 f3-ce# a11 c8 c9 f2-oe# r-oe# f-clk f-vcc f2-ce# clk a15 a12 a19 a21 a13 a9 a22 a14 a10 a16 a24 dq6 h6 h 6 g6 f6 r1-ce2 a20 a23 r2-ce2 h4 h5 h 5 g4 g5 g 5 f4 f5 e5 f-rst# r-ub# rdy a18 r2-ce1 a17 r2-vcc dq1 dnu dq15 dq13 dq4 dq3 dq9 k4 k5 k 5 k7 k8 k9 dq7 r1-vcc f-vcc dq10 h2 h3 g2 g3 f2 f3 e2 e3 a6 a3 a5 a2 a4 a1 vss a0 l4 l5 l6 l7 l8 l9 l2 l 2 l3 m2 m3 r-vcc dq8 a27 a26 vss dq12 wp#/acc dq14 dq5 a25 dq11 dq2 m4 m5 m6 m8 m9 f-vccq r-vccq f4-ce# f-vcc vss r-clk n10 f-dqs-1 n1 f-dqs0 legend: mirrorbit data-storage only shared or dnu (do not use) flash/data shared only 1st flash only flash only k5 k6 b2 dnu a2 dnu b1 a1 dnu dnu b9 dnu a9 dnu b10 dnu a10 dnu p9 dnu n9 dnu p10 dnu n2 dnu p1 dnu p2 dnu j2 j 2 e6 1st ram only 2nd ram only xram shared only wp#/acc l2 m7 d5 d 5 d4 e4
october 27, 2004 s71ws256/128/064j_csa0 12 advance information input/output descriptions a22-a0 = address inputs dq15-dq0 = data input/output oe# = output enable input. asynchronous relative to clk for the burst mode. we# = write enable input. v ss = ground nc = no connect; not connected internally rdy = ready output. indicates the status of the burst read (shared with wait# pin of ram). clk = clock input. in burst mode, after the initial word is output, subsequent active edges of clk increment the internal address counter. should be at v il or v ih while in asynchronous mode avd# = address valid input. indicates to device that the valid address is present on the address inputs. low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. high = device ignores address inputs f-rst# = hardware reset input. low = device resets and returns to reading array data f-wp# = hardware write protect input. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. f-acc = accelerated input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. r-ce1# = chip-enable input for psram. f1-ce# = chip-enable input for fl ash 1. asynchronous relative to clk for burst mode. r-cre = control register enable (only for mcps with cellularram psram). f-v cc = flash 1.8 volt-only single power supply. r-v cc = psram power supply. r-ub# = upper byte control (psram). r-lb# = lower byte control (psram). f2-ce# = chip-enable input for fl ash 2. asynchronous relative to clk for burst mode (needed only for s71ws256j). dnu = do not use. reserved for future spansion products. r-ce2 = chip-enable input for psram
13 s71ws256/128/064j_csa0 october 27, 2004 advance information ordering information the order number is formed by a valid combinations of the following: s71ws 256 j c0 ba w a k 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel model number y = cosmoram 1, 66mhz package modifier a = 8 x 11.6 mm, 1.2 mm height, 84 balls, fbga (128) t = 8 x 11.6 mm, 1.4 mm height, 84 balls, fbga 2 = 7 x 9 mm, 1.2 mm height, 80 balls, fbga temperature range w = wireless (-25 c to +85 c) i=industrial (-40 c to +85 c) package type ba = very-thin fine-pitch bga lead (pb)-free compliant package bf = very-thin fine-pitch bga lead (pb)-free package psram density c0 = 64 mb psram b0 = 32 mb psram a0 = 16 mb psram process technology j = 110 nm, floating gate technology flash density 256 = 256mb 128 = 128mb 064 = 64mb product family s71ws multi-chip product (mcp) 1.8-volt simultaneous read/write, burst mode flash memory and pram s71ws064jb0 valid combinations (ws064j flash + 16mb psram) material set supplier base ordering part number package marking temperature range burst speed s71ws064ja0baw2y 71ws064ja0baw2y -25c to +85c 66 mhz pb-free compliant cosmoram s71ws064ja0bai2y 71ws064ja0bai2y 40c to +85c s71ws064ja0bfw2y 71ws064ja0bfw2y -25c to +85c pb-free s71ws064ja0bfi2y 71ws064ja0bfi2y 40c to +85c notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
october 27, 2004 s71ws256/128/064j_csa0 14 advance information s71ws064jb0 valid combinations (ws064j flash + 32mb psram) material set supplier base ordering part number package marking temperature range burst speed s71ws064jb0baw2y 71ws064jb0baw2y -25c to +85c 66 mhz pb-free compliant cosmoram s71ws064jb0bai2y 71ws064jb0bai2y 40c to +85c s71ws064jb0bfw2y 71ws064jb0bfw2y -25c to +85c pb-free s71ws064jb0bfi2y 71ws064jb0bfi2y 40c to +85c s71ws128jb0 valid combinations (ws128j flash + 16mb psram) material set supplier base ordering part number package marking temperature range burst speed s71ws128ja0baway 71ws128ja0baway -25c to +85c 66 mhz pb-free compliant cosmoram s71ws128ja0baiay 71ws128ja0baiay -40c to +85c s71ws128ja0bfway 71ws128ja0bfway -25c to +85c pb-free s71ws128ja0bfiay 71ws128ja0bfiay -40c to +85c s71ws128jb0 valid combinations (ws128j flash + 32mb psram) material set supplier base ordering part number package marking temperature range burst speed s71ws128jb0baway 71ws128jb0baway -25c to +85c 66 mhz pb-free compliant cosmoram s71ws128jb0baiay 71ws128jb0baiay -40c to +85c s71ws128jb0bfway 71ws128jb0bfway -25c to +85c pb-free s71ws128jb0bfiay 71ws128jb0bfiay -40c to +85c s71ws128jc0 valid combinations (ws128j flash + 64mb psram) material set supplier base ordering part number package marking temperature range burst speed s71ws128jc0baway 71ws128jc0baway -25c to +85c 66 mhz pb-free compliant cosmoram s71ws128jc0baiay 71ws128jc0baiay -40c to +85c s71ws128jc0bfway 71ws128jc0bfway -25c to +85c pb-free s71ws128jc0bfiay 71ws128jc0bfiay -40c to +85c notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations. notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations. notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations. notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
15 s71ws256/128/064j_csa0 october 27, 2004 advance information s71ws256jc0 valid combinations (2 x ws128j flash + 64mb psram) material set supplier base ordering part number package marking temperature range burst speed s71ws256jc0bawty 71ws256jc0bawty -25c to +85c 66 mhz pb-free compliant cosmoram s71ws256jc0baity 71ws256jc0baity -40c to +85c s71ws256jc0bfwty 71ws256jc0bfwty -25c to +85c pb-free s71ws256jc0bfity 71ws256jc0bfity -40c to +85c notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
october 27, 2004 s71ws256/128/064j_csa0 16 advance information physical dimensions tla084?84-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package 3372-2 \ 16-038.22a package tla 084 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10, e1,e10,f1,f10,g1,g10, h1,h10,j1,j10,k1,k10,l1,l10, m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 c a b m c m 0.08 pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view
17 s71ws256/128/064j_csa0 october 27, 2004 advance information fta084?84-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package 3388 \ 16-038.21a package fta 084 jedec n/a d x e 11.60 mm x 8.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.17 --- --- ball height a2 1.02 --- 1.17 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10,e1,e10 f1,f10,g1,g10,h1,h10 j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. (2x) c 0.08 0.20 c c 6 b side view 84x a1 a2 a 0.15 m c mc ab 0.08 bottom view ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd a e b c 0.15 d c 0.15 (2x) index mark 10 top view corner pin a1
october 27, 2004 s71ws256/128/064j_csa0 18 advance information tlc080?80-ball fine-pitch ball grid array (fbga) 7 x 9 mm package 3430 \ 16-038.22 \ 10.15.04 package tlc 080 jedec n/a d x e 9.00 mm x 7.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 7.20 bsc. matrix footprint e1 5.60 bsc. matrix footprint md 10 matrix size d direction me 8 matrix size e direction n 80 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 6 b top view side view corner 80x a1 a2 a 0.15 m c mc ab 0.08 pin a1 j k e1 7 se a d1 ed dc e f g h 8 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view 10
this document contains information on a product under development at fasl, llc. the information is intended to help you evaluat e this product. do not design in this product without contacting the factory. fasl reserves the right to change or discontinue work on this proposed product without notice. publication number s29ws128_064j_mcp_00 revision a amendment 0 issue date may 5, 2004 advance information s29ws128/064j flash family for multi-chip products (mcp) 128/64 megabit (8/4 m x 16-bit) cmos 1.8 volt-only simultaneous read/write, burst mode flash memory distinctive characteristics architectural advantages ? single 1.8 volt read, program and erase (1.65 to 1.95 volt) ? manufactured on 0.11 m process technology ? versatileio? (v io ) feature ? device generates data output voltages and tolerates data input voltages as determined by the voltage on the v io pin ? 1.8v compatible i/o signals (1.65-1.95 v) ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in other bank ? zero latency between read and write operations ? four bank architecture: ws128j: 16mb/48mb/48mb/ 16mb, ws064j: 8mb/24mb/24mb/8mb ? programable burst interface ? 2 modes of burst read operation ? linear burst: 8, 16, and 32 words with wrap-around ? continuous sequential burst ? secsi? (secured silicon) sector region ? 128 words accessible through a command sequence, 64words for the factory secsi? sector and 64words for the customer secsi? sector. ? sector architecture 4 kword x 16 boot sectors, eight at the top of the address range, and eight at the bottom of the address range ? ws128j: 4 kword x 16, 32 kword x 254 sectors bank a: 4 kword x 8, 32 kword x 31 sectors bank b: 32 kword x 96 sectors bank c: 32 kword x 96 sectors bank d: 4 kword x 8, 32 kword x 31 sectors ? ws064j: 4 kword x 16, 32 kword x 126 sectors. bank a: 4 kword x 8, 32 kword x 15 sectors bank b: 32 kword x 48 sectors bank c: 32 kword x 48 sectors bank d: 4 kword x 8, 32 kword x 15 sectors ? cycling endurance: 100,000 cycles per sector typical ? data retention: 20-years typical performance characteristics ? read access times at 80/66 mhz ? burst access times of 9.1/11.2 ns @ 30 pf at industrial temperature range ? synchronous latency of 46/56 ns (at 30 pf) ? asynchronous random access times of 45/55 ns (at 30 pf) ? power dissipation (typical values, c l = 30 pf) ? burst mode read: 10 ma @ 80mhz ? simultaneous operation: 25 ma @ 80mhz ? program/erase: 15 ma ? standby mode: 0.2 a hardware features ? handshaking feature available ? provides host system with minimum possible latency by monitoring rdy ? hardware reset input (reset#) ? hardware method to reset the device for reading array data ? wp# input ? write protect (wp#) function allows protection of four outermost boot sectors, regardless of sector protect status ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level ? password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ? acc input: acceleration function reduces programming time; all sectors locked when acc = v il ? cmos compatible inputs, cmos compatible outputs ? low v cc write inhibit software features ? supports common flash memory interface (cfi) ? software command set compatible with jedec 42.4 standards ? backwards compatible with amd am29bds, amd am29bdd, amd am29bl, and fujitsu mbm29bs families ? data# polling and toggle bits ? provides a software method of detecting program and erase operation completion
21 s29ws128/064j may 5, 2004 ? erase suspend/resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences
may 5, 2004 s29ws128/064j 22 general description the s29ws128/064j_mcp/s29ws064j is a 128/64 mbit, 1.8 volt-only, simultaneous read/write, burst mode flash memory device, organized as 8,388,608/4,194,304 words of 16 bits each. this device uses a single v cc of 1.65 to 1.95 v to read, program, and erase the memory array. a 12.0-volt v hh on acc may be used for faster program perfor - mance if desired. the device can also be programmed in standard eprom programmers. at 80 mhz, the device provides a burst access of 9.1 ns at 30 pf with a latency of 46 ns at 30 pf. at 66 mhz, the device provides a burst access of 11.2 ns at 30 pf with a latency of 56 ns at 30 pf. the device operates within the industrial temperature range of -40c to +85c and the wireless temperature range of -25c to +85c. the device is offered in various fbga packages. the simultaneous read/write architecture provides simultaneous operation by divid - ing the memory space into four banks. th e device can improve overall system perfor - mance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. this releases the system from waiting for the completion of program or erase operations. the device is divided as shown in the following table: the versatileio? (v io ) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the v io pin. the device uses chip enable (ce#), write enable (we#), address valid (avd#) and out - put enable (oe#) to control asynchronous read and write operations. for burst opera - tions, the device additionally requires ready (rdy), and clock (clk). this implementation allows easy interface with minimal glue logic to a wide range of micropro - cessors/microcontrollers for high performance read operations. the burst read mode feature gives system designers flexibility in the interface to the de - vice. the user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. the clock polarity feature provides system designers a choice of active clock edges, either rising or falling. the active clock edge init iates burst accesses and determines when data will be output. the device is entirely command set compatible with the jedec 42.4 single-power- supply flash standard . commands are written to the command register using standard microprocessor write timing. register contents serve as inputs to an internal state-ma - chine that controls the erase and programming ci rcuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. the erase suspend/erase resume feature enables the user to put erase or program on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secsi? sector area (one time program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. program sus - pend is also offered. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset cir - cuitry. a system reset would thus also rese t the device, enabling th e system microproces - sor to read boot-up firmware from the flash memory device. bank quantity size 128mb 64 mb a 8 8 4 kwords 31 15 32 kwords b 96 48 32 kwords c 96 48 32 kwords d 31 15 32 kwords 8 8 4 kwords
23 s29ws128/064j may 5, 2004 the host system can detect whether a program or erase operation is complete by using the device status bit dq7 (data# polling) an d dq6/dq2 (toggle bits). after a program or erase cycle has been completed, the device automatically returns to reading array data. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically in - hibits write operations during power transitions. the device also offers two types of data protection at the sector level. when at v il , wp# locks the four outermost boot sectors. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both modes. spansion? flash memory products combine years of flash memory manufacturing expe - rience to produce the highest levels of quality, reliability and cost effectiveness. the de - vice electrically erases all bits within a sector simultaneously via fowler-nordheim tunnelling. the data is programmed using hot electron injection.
may 5, 2004 s29ws128/064j 24 product selector guide block diagram part number s29ws128/064j_mcp/s29ws064j synchronous/burst asynchronous speed option 66 mhz 80* 2 mhz speed option 66 mhz 80* 2 mhz v io = 1.65 ? 1.95 v max latency, ns (t iacc ) 56 46 max access time, ns (t acc ) 55 45 max burst access time, ns (t bacc ) 11.2 9.1 max ce# access, ns (t ce ) 55 45 max oe# access, ns (t oe ) 11.2 9.1 max oe# access, ns (t oe ) 11.2 9.1 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v ssio v io we# reset# wp# acc ce# oe# dq15 ? dq0 data latch y-gating cell matrix address latch amax?a0 rdy buffer rdy burst state control burst address counter avd# clk amax: ws064j (a21), ws128j (a22)
25 s29ws128/064j may 5, 2004 block diagram of simultaneous operation circuit amax: ws064j (a21), ws128j (a22) v ss v cc v io v ssio bank b address reset# acc we# ce# avd# rdy dq15?dq0 wp# state control & command register bank b x-decoder y-decoder latches and control logic bank a x-decoder y-decoder latches and control logic dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 bank c y-decoder x-decoder latches and control logic bank d y-decoder x-decoder latches and control logic oe# status control amax?a0 amax?a0 amax?a0 amax?a0 amax?a0 bank c address bank d address bank a address
may 5, 2004 s29ws128/064j 26 input/output descriptions amax-a0 = address inputs dq15-dq0 = data input/output ce# = chip enable input. asynchronous relative to clk for the burst mode. oe# = output enable input. asynchronous relative to clk for the burst mode. we# = write enable input. v cc = device power supply (1.65 ? 1.95 v). v io = input & output buffer power supply (1.65 ? 1.95 v). v ss = ground nc = no connect; not connected internally rdy = ready output; in synchronous mode, indicates the status of the burst read. low = data not valid at expected time. high = data valid. in asynchronous mode, indicates the status of the internal program and erase function. low = program/erase in progress. high impedance = program/erase completed. clk = clk is not required in asynchronous mode. in burst mode, after the initial word is output, subsequent active edges of clk increment the internal address counter. avd# = address valid input. indicates to device that the valid address is present on the address inputs (amax-a0). low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. high = device ignores address inputs reset# = hardware reset input. low = device resets and returns to reading array data wp# = hardware write protect input. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. acc = at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il , locks all sectors. should be at v ih for all other conditions. note: 1. amax = a22 (ws128j), a21 (ws064j)
27 s29ws128/064j may 5, 2004 device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is com - posed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machin e. the state machine outputs dictate the function of the device. ta b l e 1 lists the device bus operations, the inputs and con - trol levels they require, and the resu lting output. the following subsections describe each of these operations in further detail. ta b l e 1 . device bus operations legend: l = logic 0, h = logic 1, x = don?t care note: default active edge of clk is the rising edge. ve rs a ti l e i o ? ( v io ) control the versatileio (v io ) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data in - puts to the same voltage level that is asserted on the v io pin. requirements for asynchronous read operation (non-burst) to read data from the memory array, the system must first assert a valid address on amax?a0(a22-a0 for ws128j and a21-a0 for ws064j), while driving avd# and ce# to v il . we# should remain at v ih . the rising edge of avd# latches the address. the data will appear on dq15 ?dq0. since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad - operation ce# oe# we# a22?0 dq15?0 reset# clk (see note) avd# asynchronous read - addresses latched l l h addr in i/o h x asynchronous read - addresses steady state l l h addr in i/o h x l asynchronous write l h l addr in i/o h x l synchronous write l h l addr in i/o h standby (ce#) h x x high z high z h x x hardware reset x x x high z high z l x x burst read operations load starting burst address l x h addr in x h advance burst to next address with appropriate data presen ted on the data bus l l h high z burst data out h h terminate current burst read cycle h x h high z high z h x terminate current burst read cycle via reset# x x h high z high z l x x terminate current burst read cycle and start new burst read cycle l x h high z i/o h
may 5, 2004 s29ws128/064j 28 dresses and stable ce# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output. the internal state machine is set for re ading array data in asynchronous mode upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. requirements for synchronous (burst) read operation the device is capable of continuous sequential burst operation and linear burst operation of a preset length. when the device first powers up, it is enabled for asynchronous read operation. prior to entering burst mode, the system should determine how many wait states are desired for the initial word (t iacc ) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the rdy signal will transition with valid data. the system would then write the configuration register command sequence. see ?set configuration register command sequence? section on page 64 and ?command definitions? section on page 64 for further details. once the system has written the ?set configuration register? command se - quence, the device is enabled for synchronous reads only. the initial word is output t iacc after the active edge of the first clk cycle. sub - sequent words are output t bacc after the active edge of each successive clock cycle, which automatically increments the internal address counter. note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003fh. during the time the device is outputting data at this fixed internal address bound - ary (address 00003fh, 00007fh, 0000bfh, etc.), a two cycle latency occurs before data appears for the next address (address 000040h, 000080h, 0000c0h, etc.). additionally, when the device is read from an odd address, 1 wait state is inserted when the address pointer crosses the first boundary that occurs every 16 words. for instance, if the device is read from 00001ah (odd), 1 wait state is inserted before the data of 000020h is output. this wait states is inserted at only the first 16 words boundary. then, if the device is read from the odd address within the last 16 words of 64 word boundary (address 000031h, 000033h,..., 00003eh), a three cycle latency occurs before data appears for the next address (address 000040h). the rdy output indicates this condition to the system by pulsing deactive (low). see figure 34, ?latency with boundary crossing,? on page 111 . the device will continue to output sequen tial burst data, wrapping around to ad - dress 000000h after it reaches the highest addressable memory location, until the system drives ce# high, reset# low, or avd# low in conjunction with a new address. see tab le 1, ?device bus operations,? on page 27 . if the host system crosses the bank boundary while reading in burst mode, and the device is not programming or erasing, a two-cycle latency will occur as de - scribed above in the subsequent bank. if the host system crosses the bank boundary while the device is programming or erasing, the device will provide read status information. the clock will be ignored. after the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and avd# pulse.
29 s29ws128/064j may 5, 2004 8-, 16-, and 32-word linear burst with wrap around the remaining three burst read modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. in each of these modes, the burst addresses read ar e determined by the group within which the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see ta b l e 2 .) ta b l e 2 . burst address groups as an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3fh, and the burst sequence would be 39-3a-3b- 3c-3d-3e-3f-38h-etc. the burst sequence begins with the starting address writ - ten to the device, but wraps back to the first address in the selected group. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. note that in these three burst read modes the address pointer does not cross the boundary that occurs every 128 or 64 words; thus, no wait states are inserted (except during the initial access). the rdy pin indicates when data is valid on the bus. configuration register the device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, rdy configuration, and synchronous mode active. handshaking the device is equipped with a handshaking feature that allows the host system to simply monitor the rdy signal from th e device to determine when the initial word of burst data is ready to be read. the host system should use the program - mable wait state configuration to set the number of wait states for optimal burst mode operation. the initial word of burst data is indicated by the active edge of rdy after oe# goes low. for optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on clock frequency. see ?set configuration register command sequence? section on page 64 for more information. mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h,... 16-word 16 words 0-fh, 10-1fh, 20-2fh,... 32-word 32 words 00-1fh, 20-3fh, 40-5fh,...
may 5, 2004 s29ws128/064j 30 simultaneous read/write oper ations with zero latency this device is capable of reading data from one bank of memory while program - ming or erasing in another bank of memory. an erase operation may also be suspended to read from or program to another location within the same bank (ex - cept the sector being erased). figure 37, ?back-to-back read/write cycle timings,? on page 114 shows how read and write cycles may be initiated for si - multaneous operation with zero latency. refer to the dc characteristics table for read-while-program and read-while-erase current specifications. writing commands/command sequences the device has the capability of performing an asynchronous or synchronous write operation. while the device is configured in asynchronous read mode, it is able to perform asynchronous write oper ations only. clk is ignored in the asyn - chronous programming mode. when in the synchronous read mode configuration, the device is able to pe rform both asynchronous and synchronous write operations. clk and we# address latch is supported in the synchronous programming mode. during a synchronous write operation, to write a command or command sequence (which includes programming data to the device and eras - ing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih . when writing commands or data. during an asynchronous write operation, the system must drive ce# and we# to v il and oe# to v ih when pro - viding an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. the asynchronous and synchronous programing operation is independent of the set device read mode bit in the configuration register (see ta b l e 17, ?configu - ration register,? on page 68 ). the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypa ss mode, only two write cycles are re - quired to program a word, instead of four. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e 12, ?ws128j sector address table,? on page 50 and ta b l e 13, ?ws064j sector address table,? on page 58 indicate the address space that each sector oc - cupies. the device address space is divided into four banks. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits required to uniquely select a sector. i cc2 in the ?dc characteristics? section on page 90 represents the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. acc is primarily intended to allow faster ma nufacturing throughput at the factory. if the system asserts v hh on this input, the device automatically enters the afore - mentioned unlock bypass mode and uses the higher voltage on the input to reduce the time required for program operations. the system would use a two- cycle program command sequence as required by the unlock bypass mode. re - moving v hh from the acc input returns the device to normal operation. note that sectors must be unlocked prior to raising acc to v hh . note that the acc pin must not be at v hh for operations other than accele rated programming, or device dam - age may result. in addition, the acc pin must not be left floating or unconnected; inconsistent behavior of the device may result . when at v il , acc locks all sectors. acc should be at v ih for all other conditions.
31 s29ws128/064j may 5, 2004 autoselect mode the autoselect mode provides manufacturer and device identification, and sec - tor protection verification, through identifier codes output from the internal register (which is separate from the memory array) on dq15?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on ad - dress pin a9. address pins must be as shown in tab l e 3, ?autoselect codes (high voltage method),? on page 32 . in addition, when verify ing sector protection, the sector address must appear on the appr opriate highest order address bits (see ta b l e 4, ?s29ws128/064j_mcp boot sector/sector block addresses for protec - tion/unprotection,? on page 32 and ta b l e 5, ?s29ws064j boot sector/sector block addresses for protection/unprotection,? on page 34 ). ta b l e 3 shows the remaining address bits that are don?t ca re. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15?dq0. however, the autoselect codes can also be ac - cessed in-system through the command reg ister, for instances when the device is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in ta b l e 18, ?command definitions,? on page 78 . note that if a bank address (ba) on address bits a22, a21, and a20 for the ws128j (a21:a19 for the ws064j) is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. to access the autoselect codes in-system, the host system can issue the autose - lect command via the command register, as shown in ta b l e 18, ?command definitions,? on page 78 . this method does not require v id . autoselect mode may only be entered and used when in the asynchronous read mode. refer to the ?autoselect command sequence? section on page 68 for more information.
may 5, 2004 s29ws128/064j 32 ta b l e 3 . autoselect codes (high voltage method) legend: l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sector address, x = don?t care. notes: 1. the autoselect codes may also be accessed in-system via command sequences. 2. ppb protection status is shown on the data bus sector/sector block protection and unprotection the hardware sector protection feature disables both programming and erase op - erations in any sector. the hardware sect or unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection/ unprotection can be implemented via two methods. (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see tab l e 4, ?s29ws128/064j_mcp boot sector/sector block addresses for protection/unprotection,? on page 32 and ta b l e 5, ?s29ws064j boot sector/sector block addresses for protection/unpro - tection,? on page 34 ).) ta b l e 4 . s29ws128/064j_mcp boot sector/sector block addresses for protection/unprotection description ce# oe# we # reset# ama x to a12 a11 to a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id : fasl l l h h x x v id x x l x l l l l 0001h device id read cycle 1 l l h h x x v id x l l l l l l h 227eh read cycle 2 h h h l 2218h (ws128j) 221eh (ws064j) read cycle 3 h h h h 2200h (ws128j) 2201h (ws064j) sector protection verification l l h h sa x v id x l l l l l h l 0001h (protected), 0000h (unprotected) indicator bits l l h h x x v id x x l x l l h h dq15 - dq8 = 0 dq7 - factory lock bit 1 = locked, 0 = not locked dq6 -customer lock bit 1 = locked, 0 = not locked dq5 = handshake bit 1 = reserved, 0 = standard handshake dq4 & dq3 - boot code dq2 - dq0 = 001 hardware sector group protection l l h h sa x v id x x x l l l h l 0001h (protected), 0000h (unprotected) sector a22?a12 sector/ sector block size sa0 00000000000 4 kwords sa1 00000000001 4 kwords sa2 00000000010 4 kwords sa3 00000000011 4 kwords sa4 00000000100 4 kwords sa5 00000000101 4 kwords sa6 00000000110 4 kwords sa7 00000000111 4 kwords
33 s29ws128/064j may 5, 2004 sa8 00000001xxx, 32 kwords sa9 00000010xxx, 32 kwords sa10 00000011xxx, 32 kwords sa11?sa14 000001xxxxx 128 (4x32) kwords sa15?sa18 000010xxxxx 128 (4x32) kwords sa19?sa22 000011xxxxx 128 (4x32) kwords sa23-sa26 000100xxxxx 128 (4x32) kwords sa27-sa30 000101xxxxx 128 (4x32) kwords sa31-sa34 000110xxxxx 128 (4x32) kwords sa35-sa38 000111xxxxx 128 (4x32) kwords sa39-sa42 001000xxxxx 128 (4x32) kwords sa43-sa46 001001xxxxx 128 (4x32) kwords sa47-sa50 001010xxxxx 128 (4x32) kwords sa51?sa54 001011xxxxx 128 (4x32) kwords sa55?sa58 001100xxxxx 128 (4x32) kwords sa59?sa62 001101xxxxx 128 (4x32) kwords sa63?sa66 001110xxxxx 128 (4x32) kwords sa67?sa70 001111xxxxx 128 (4x32) kwords sa71?sa74 010000xxxxx 128 (4x32) kwords sa75?sa78 010001xxxxx 128 (4x32) kwords sa79?sa82 010010xxxxx 128 (4x32) kwords sa83?sa86 010011xxxxx 128 (4x32) kwords sa87?sa90 010100xxxxx 128 (4x32) kwords sa91?sa94 010101xxxxx 128 (4x32) kwords sa95?sa98 010110xxxxx 128 (4x32) kwords sa99?sa102 010111xxxxx 128 (4x32) kwords sa103?sa106 011000xxxxx 128 (4x32) kwords sa107?sa110 011001xxxxx 128 (4x32) kwords sa111?sa114 011010xxxxx 128 (4x32) kwords sa115?sa118 011011xxxxx 128 (4x32) kwords sa119?sa122 011100xxxxx 128 (4x32) kwords sa123?sa126 011101xxxxx 128 (4x32) kwords sa127?sa130 011110xxxxx 128 (4x32) kwords sa131-sa134 011111xxxxx 128 (4x32) kwords sa135-sa138 100000xxxxx 128 (4x32) kwords sa139-sa142 100001xxxxx 128 (4x32) kwords sa143-sa146 100010xxxxx 128 (4x32) kwords sa147-sa150 100011xxxxx 128 (4x32) kwords sa151?sa154 100100xxxxx 128 (4x32) kwords sa155?sa158 100101xxxxx 128 (4x32) kwords sa159?sa162 100110xxxxx 128 (4x32) kwords sa163?sa166 100111xxxxx 128 (4x32) kwords sa167?sa170 101000xxxxx 128 (4x32) kwords sa171?sa174 101001xxxxx 128 (4x32) kwords sa175?sa178 101010xxxxx 128 (4x32) kwords sa179?sa182 101011xxxxx 128 (4x32) kwords sa183?sa186 101100xxxxx 128 (4x32) kwords sa187?sa190 101101xxxxx 128 (4x32) kwords sector a22?a12 sector/ sector block size
may 5, 2004 s29ws128/064j 34 ta b l e 5 . s29ws064j boot sector/sector block addresses for protection/unprotection sa191?sa194 101110xxxxx 128 (4x32) kwords sa195?sa198 101111xxxxx 128 (4x32) kwords sa199?sa202 110000xxxxx 128 (4x32) kwords sa203?sa206 110001xxxxx 128 (4x32) kwords sa207?sa210 110010xxxxx 128 (4x32) kwords sa211?sa214 110011xxxxx 128 (4x32) kwords sa215?sa218 110100xxxxx 128 (4x32) kwords sa219?sa222 110101xxxxx 128 (4x32) kwords sa223?sa226 110110xxxxx 128 (4x32) kwords sa227?sa230 110111xxxxx 128 (4x32) kwords sa231?sa234 111000xxxxx 128 (4x32) kwords sa235?sa238 111001xxxxx 128 (4x32) kwords sa239?sa242 111010xxxxx 128 (4x32) kwords sa243?sa246 111011xxxxx 128 (4x32) kwords sa247?sa250 111100xxxxx 128 (4x32) kwords sa251?sa254 111101xxxxx 128 (4x32) kwords sa255?sa258 111110xxxxx 128 (4x32) kwords sa259 11111100xxx 32 kwords sa260 11111101xxx 32 kwords sa261 11111110xxx 32 kwords sa262 11111111000 4 kwords sa263 11111111001 4 kwords sa264 11111111010 4 kwords sa265 11111111011 4 kwords sa266 11111111100 4 kwords sa267 11111111101 4 kwords sa268 11111111110 4 kwords sa269 11111111111 4 kwords sector a21?a12 sector/ sector block size sa0 0000000000 4 kwords sa1 0000000001 4 kwords sa2 0000000010 4 kwords sa3 0000000011 4 kwords sa4 0000000100 4 kwords sa5 0000000101 4 kwords sa6 0000000110 4 kwords sa7 0000000111 4 kwords sa8 0000001xxx 32 kwords sa9 0000010xxx 32 kwords sa10 0000011xxx 32 kwords sa11?sa14 00001xxxxx 128 (4x32) kwords sa15?sa18 00010xxxxx 128 (4x32) kwords sa19?sa22 00011xxxxx 128 (4x32) kwords sa23-sa26 00100xxxxx 128 (4x32) kwords sa27-sa30 00101xxxxx 128 (4x32) kwords sector a22?a12 sector/ sector block size
35 s29ws128/064j may 5, 2004 sa31-sa34 00110xxxxx 128 (4x32) kwords sa35-sa38 00111xxxxx 128 (4x32) kwords sa39-sa42 01000xxxxx 128 (4x32) kwords sa43-sa46 01001xxxxx 128 (4x32) kwords sa47-sa50 01010xxxxx 128 (4x32) kwords sa51?sa54 01011xxxxx 128 (4x32) kwords sa55?sa58 01100xxxxx 128 (4x32) kwords sa59?sa62 01101xxxxx 128 (4x32) kwords sa63?sa66 01110xxxxx 128 (4x32) kwords sa67?sa70 01111xxxxx 128 (4x32) kwords sa71?sa74 10000xxxxx 128 (4x32) kwords sa75?sa78 10001xxxxx 128 (4x32) kwords sa79?sa82 10010xxxxx 128 (4x32) kwords sa83?sa86 10011xxxxx 128 (4x32) kwords sa87?sa90 10100xxxxx 128 (4x32) kwords sa91?sa94 10101xxxxx 128 (4x32) kwords sa95?sa98 10110xxxxx 128 (4x32) kwords sa99?sa102 10111xxxxx 128 (4x32) kwords sa103?sa106 11000xxxxx 128 (4x32) kwords sa107?sa110 11001xxxxx 128 (4x32) kwords sa111?sa114 11010xxxxx 128 (4x32) kwords sa115?sa118 11011xxxxx 128 (4x32) kwords sa119?sa122 11100xxxxx 128 (4x32) kwords sa123?sa126 11101xxxxx 128 (4x32) kwords sa127?sa130 11110xxxxx 128 (4x32) kwords sa131 1111100xxx 32 kwords sa132 1111101xxx 32 kwords sa133 1111110xxx 32 kwords sa134 1111111000 4 kwords sa135 1111111001 4 kwords sa136 1111111010 4 kwords sa137 1111111011 4 kwords sa138 1111111100 4 kwords sa139 1111111101 4 kwords sa140 1111111110 4 kwords sa141 1111111111 4 kwords sector a21?a12 sector/ sector block size
may 5, 2004 s29ws128/064j 36 sector protection the device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: persistent sector protection a command sector protection method that replaces the old 12 v controlled pro - tection method. password sector protection a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted wp# hardware protection a write protect pin that can prevent program or erase operations in the outer - most sectors. all parts default to operate in the persistent sector protection mode. the cus - tomer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method will be used. if the customer decides to continue using the persistent sector protection method, they must set the persistent sector protection mode locking bit . this will permanently set the part to op - erate only using persistent sector protecti on. if the customer decides to use the password method, they must set the password mode locking bit . this will permanently set the part to operate only using password sector protection. it is important to remember that setting either the persistent sector protec - tion mode locking bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two meth - ods once a locking bit has been set. it is important that one mode is explicitly selected when the device is first programmed, rather than re - lying on the default mode alone. this is so that it is not possible for a system program or virus to later set the passwor d mode locking bit, which would cause an unexpected shift from the default persistent sector protection mode into the password protection mode. the wp# hardware protection feature is always available, independent of the software managed protection method chosen. the device is shipped with all sectors unprotected. optional spansion ? pro - gramming services enable programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a sector is protected or unprotected. see ?autoselect command sequence? section on page 68 for details. persistent sector protection the persistent sector protection method replaces the old 12 v controlled protec - tion method while at the same time enhancing flexibility by providing three different sector protection states: ? persistently locked ?a sector is protected and cannot be changed. ? dynamically locked ?the sector is protected and can be changed by a sim - ple command ? unlocked ?the sector is unprotected and can be changed by a simple com - mand in order to achieve these states, three types of ?bits? are going to be used:
37 s29ws128/064j may 5, 2004 persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to a maximum of four sectors ( ?s29ws128/064j_mcp boot sector/sector block addresses for protec - tion/unprotection? section on page 32 , ?s29ws064j boot sector/sector block addresses for protection/unprotection? section on page 34 ). all 4 kbyte boot- block sectors have individual sector persistent protection bits (ppbs) for greater flexibility. each ppb is individually modifiable through the ppb program command . note: if a ppb requires erasure, all of the sector ppbs must first be prepro - grammed prior to ppb erasing. all ppbs erase in parallel, unlike programming where individual ppbs are programmable. it is the responsibility of the user to perform the preprogramming operation. otherwise, an already erased sector ppbs has the potential of being over-erased. there is no hardware mechanism to prevent sector ppbs over-erasure. persistent protection bit lock (ppb lock) a global volatile bit. when set to ?1?, the ppbs cannot be changed. when cleared (?0?), the ppbs are changeable. there is only one ppb lock bit per device. the ppb lock is cleared after power-up or hardware reset. there is no command se - quence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dybs is ?0?. each dyb is individually modifiable through the dpb write command. when the parts are first shipped, the ppbs are cleared (?0?). the dpbs and ppb lock are defaulted to power up in th e cleared state ? meaning the ppbs are changeable. when the device is first powered on, the dybs power up in the cleared state (sectors not protected). the protection state for each sector is determined by the logical or of the ppb and the dpb related to that sector. for the sectors that have the ppbs cleared, the dpbs control whether or not the sector is protected or unprotected. by issuing the dpb write command sequences, the dpbs will be set or cleared, thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. this allows software to easily protect sec - tors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. the dpbs maybe set or cleared as often as needed. the ppbs allow for a more static, and diffic ult to change, level of protection. the ppbs retain their state across power cycles because they are non-volatile. indi - vidual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are also lim - ited to 100 erase cycles. the pbb lock bit adds an additional level of protection. once all ppbs are pro - grammed to the desired settings, the ppb lock may be set to ?1?. setting the ppb lock disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can deter - mine if any changes to the ppb are needed e.g. to allow new system code to be downloaded. if no changes are needed th en the boot code can set the ppb lock to disable any further changes to the ppbs during system operation.
may 5, 2004 s29ws128/064j 38 the wp# write protect pin adds a final level of hardware protection to the four outermost 4 kbytes sectors (sa0 - sa3 for a bottom boot, ws128j: sa266 - sa269, ws064j: sa138 - sa141, or sa0 - sa3 & ws128j: sa266 - sa269, ws064j: sa138 - sa141 for a dual boot). when this pin is low it is not possible to change the contents of these four sectors. these sectors generally hold sys - tem boot code. so, the wp# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during sys - tem initialization. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all un - protected. if there is a need to protect some of them, a simple dpb write command sequence is all that is necess ary. the dpb write command for the dy - namic sectors switch the dpbs to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the device operates normally again. note: to achieve the best protection, it?s recommended to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp# = v il . ta b l e 6 . sector protection schemes ta b l e 6 contains all possible combinations of the dpb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the ppb lock. if the ppb is cleared, the sector can be dynamically locked or unlocked. the dpb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. an erase command to a protected sector enables status polling for approximately dpb ppb ppb lock sector state 0 0 0 unprotected?ppb and dpb are changeable 1 0 0 protected?ppb and dpb are changeable 0 1 0 protected?ppb and dpb are changeable 1 1 0 protected?ppb and dpb are changeable 0 0 1 unprotected?ppb not changeable, dpb is changeable 1 0 1 protected?ppb not changeable, dpb is changeable 0 1 1 protected?ppb not changeable, dpb is changeable 1 1 1 protected?ppb not changeable, dpb is changeable
39 s29ws128/064j may 5, 2004 50 s after which the device returns to read mode without having erased the protected sector. the programming of the dpb, ppb, and ppb lock for a given sector can be veri - fied by writing a dpb/ppb/ppb lock verify command to the device. persistent sector protec tion mode locking bit like the password mode locking bit, a pers istent sector protection mode locking bit exists to guarantee that the device remain in software sector protection. once set, the persistent sector protection locking bit prevents programming of the password protection mode locking bit. this guarantees that a hacker could not place the device in password protection mode. password protection mode the password sector protection mode meth od allows an even higher level of se - curity than the persistent sector protection mode. there are two main differences between the persistent sector protection and the password sector protection mode: ? when the device is first powered on, or comes out of a reset cycle, the ppb lock bit is set to the locked state , rather than cleared to the unlocked state. ? the only means to clear the ppb lock bit is by writing a unique 64-bit pass - word to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. the password is stored in a the secsi? (secured silicon) region of the flash memory. once the password mode locking bit is set, the password is perma - nently set with no means to read, progra m, or erase it. the password is used to clear the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally compares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each ?password check.? this delay is intended to thwart any efforts to run a program that tries all possible combina - tions in order to crack the password. password and password mode locking bit in order to select the password sector protection scheme, the customer must first program the password. fasl recommends that the password be somehow corre - lated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password verify operations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: 1. it permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. 2. it also disables all further commands to the password region. all program, and read operations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the password mode locking bit. more impor - tantly, the user must be sure that the password is correct when the password
may 5, 2004 s29ws128/064j 40 mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after setting the password mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persis - tent sector protection locking bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and verify commands (see ?password program command? section on page 74 and ?password verify command? sec - tion on page 74 ). the password function works in conjunction with the password mode locking bit, which when set, prevents the password verify command from reading the contents of the password on the pins of the device. persistent protection bit lock the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode locking bit after power-up reset. if the password mode lock bit is also set, after a hardware rese t (reset# asserted) or a power-up reset the only means for clearing the ppb lock bi t in password protection mode is to issue the password unlock command. successful execution of the password un - lock command clears the ppb lock bit, allowing for sector ppbs modifications. asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a ?1?. if the password mode locking bit is not set, including persistent protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is setable by issuing the ppb lo ck bit set command. once set the only means for clearing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is igno red in persistent protection mode. high voltage sector protection sector protection and unprotection may also be implemented using programming equipment. the procedure requires high voltage (vid) to be placed on the re - set# pin. refer to figure 2, ?in-system sector protection/sector unprotection algorithms,? on page 43 for details on this procedure. note that for sector unpro - tect, all unprotected sectors must be first protected prior to the first sector write cycle. once the password mode locking bit or persistent protection locking bit are set, the high voltage sector protect/unprotect capability is disabled. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws ac - tive current until the operation is completed.
41 s29ws128/064j may 5, 2004 i cc3 in the ?dc characteristics? section on page 90 represents the standby cur - rent specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. while in asynchronous mode, the device automatica lly enables this mode when addresses remain stable for t acc + 60 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. based on the implementation by design, the auto power down feature is disabled in synchronous mode and enabled in asynchronous mode. as a result, in synchronous mode, the device can be in auto power down mode only by deselecting the ce#. note that a new burst operation is required to provide new data. i cc6 in the ?dc characteristics? section on page 90 represents the automatic sleep mode current specification. reset#: hardware reset input the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device im - mediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the de - vice is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current will be greater. reset# may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase operation, the device requires a time of t ready (during embedded algorithms) before the device is ready to read data again. if reset# is asserted when a program or erase operation is not ex - ecuting, the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after reset# returns to v ih . refer to the ?ac characteristics? section on page 99 for reset# parameters and to figure 21, ?reset timings,? on page 99 for the timing diagram.
may 5, 2004 s29ws128/064j 42 output disable mode when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. figure 1. temporary sector unprotect operation start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected (if wp# = v il , outermost boot sectors will remain protected). 2. all previously protected sect ors are protected once again.
43 s29ws128/064j may 5, 2004 figure 2. in-system sector protection/sector unprotection algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a7:a0 = 00000010 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a7:a0 = 01000010 set up first sector address wait 1.5 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
may 5, 2004 s29ws128/064j 44 secsi? (secured silicon) sector flash memory region the secsi? (secured silicon) sector fe ature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi? sector is 128 words in length and located at addresses 000000h-000007h. the factory indicator bit (dq7) is used to indicate whether or not the factory secsi? sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secsi? sector is locked when shipped from the factory. these bits are perma - nently set at the factory and cannot be ch anged, in order to prevent cloning of a factory locked part. this ensures the security of the esn and customer code once the product is shipped to the field. fasl? offers the device with a 64 word factory secsi? sector that is locked when the part is shipped and a 64 words cu stomer secsi? sector that is either locked or is lockable. the factory secsi? sector is always protected when shipped from the factory, and has the factory indicator bit (dq7) permanently set to a ?1?. the customer secsi? sector is shipped unprotected with the cus - tomer indicator bit (dq6) set to ?0?, allowi ng customers to utilize that sector in any manner they choose. once the customer secsi? sector area is protected, the customer indicator bit will be permanently set to ?1.? the system accesses the secsi? sector through a command sequence (see ?enter secsi? sector/exit secsi? sector command sequence? ). after the sys - tem has written the enter secsi? sector command sequence, it may read the secsi? sector by using the addresses normally occupied by the memory array. this mode of operation continues until th e system issues the exit secsi? sector command sequence, or until power is removed from the device. while secsi? sector access is enabled, memory array read access, program operations, and erase operations to all sectors other than sa0 are also available. on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. factory locked: factor secsi? sector programmed and protected at the factory in a factory sector locked device, the factory secsi? sector is protected when the device is shipped from the factory wh ether or not the area was programmed at the factory. the factory secsi? sector cannot be modified in any way. op - tional spansion? programming service can preprogram a random esn, a customer-defined code, or any combination of the two. the factory secsi? sec - tor is located at addresses 000000h?00003fh. the device is available preprogrammed with one of the following: ? a random, secure esn only within the factor secsi? sector ? customer code within the customer secsi? sector through the spansion programming service ? both a random, secure esn and customer code through the spansion pro - gramming service. ta b l e 7 . secsi? sector addresses customers may opt to have their code programmed by fasl through the span - sion programming service. fasl programs the customer?s code, with or without the random esn. the devices are then shipped from fasl?s factory with the fac - sector sector size address range customer 64 words 000040h-00007fh factory 64 words 000000h-00003fh
45 s29ws128/064j may 5, 2004 tory secsi? sector and customer secsi? sector permanently locked. contact the local sales office for details on using spansion programming services. customer secsi? sector the customer lockable area is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. secu - rity feature is not required, the customer secsi? sector can be treated as an additional flash memory space. the cust omer secsi? sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock bypass functions are not available when programming the customer secsi? sector, but reading in banks a, b, and c is available. the customer secsi? sector is located at addresses 000040h? 00007fh. the customer secsi? sector area can be protected using one of the following procedures: ? write the three-cycle enter secsi? sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ?in- system sector protection/sector unprotection algorithms,? on page 43 ex - cept that reset# may be at either v ih or v id . this allows in-system protec - tion of the customer secsi? sector region without raising any device pin to a high voltage. note that this method is only applicable to the secsi? sector. ? write the secsi? sector protection bit lock command sequence. once the customer secsi? sector is lock ed and verified, the system must write the exit secsi? sector region command sequence to return to reading and writing the remainder of the array. the customer secsi? sector lock must be used with caution since, once locked, there is no procedure available for unlock ing the customer secsi? sector area and none of the bits in the customer secsi? sector memory space can be mod - ified in any way. secsi? sector protection bit the customer secsi? sector protection bit prevents programming of the cus - tomer secsi? sector memory area. once set, the customer secsi? sector memory area contents are non-modifiable. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to ta b l e 18, ?command definitions,? on page 78 for command definitions). the device offers two types of data protection at the sector level: ? the ppb and dpb associated command sequences disables or re-enables both program and erase operations in any sector or sector group. ? when wp# is at v il , the four outermost sectors are locked. ? when acc is at v il , all sectors are locked. the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. write protect (wp#) the write protect feature provides a hard ware method of protecting the four outermost sectors. this function is provided by the wp# pin and overrides the previously discussed sector protection/unprotection method.
may 5, 2004 s29ws128/064j 46 if the system asserts v il on the wp# pin, the device disables program and erase functions in the four ?outermost? 4 kword boot sectors. the four outermost 4 kword boot sectors are the four sectors containing the lowest addresses (sa0 - sa3), or the four sectors containing the highest addresses (ws128j: sa266 - sa269, ws064j: sa138 - sa141) or both the lower four (sa0 - sa3) and upper four sectors (ws128j: sa266 - sa269, ws064j: sa138 - sa141) in a dual-boot- configured device. if the system asserts v ih on the wp# pin, the device reverts to whether the upper and/or lower four sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in ?ppb pro - gram command? section on page 76 . note that the wp# pin must not be left floating or unconnected; inconsistent be - havior of the device may result. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro - tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the sys - tem must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up.
47 s29ws128/064j may 5, 2004 common flash memory interface (cfi) the common flash interface (cfi) specificati on outlines device and host system software interrogation handshake, which allows specific vendor-specified soft - ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back - ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 8 - 11 . to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au - toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 8 - 11 . the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specification and cfi publication 100, available via the fasl site at the following url: http://www.amd.com/us-en/flashmemory/technicalresources/ 0,,37_1693_1780_1834^1955,00.html . alternatively, contact an fasl represen - tative for copies of these documents. ta b l e 8 . cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
may 5, 2004 s29ws128/064j 48 ta b l e 9 . system interface string ta b l e 1 0 . device geometry definition addresses data description 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0003h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses data description 27h 0018h (ws128j) 0017h (ws064j) device size = 2 n byte 28h 29h 0001h 0000h flash device interface descriptio n (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 00fdh (ws128j) 007dh (ws064j) erase block region 2 information 32h 33h 34h 0000h 0000h 0001h 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information
49 s29ws128/064j may 5, 2004 ta b l e 1 1 . primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 000ch address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon technology (bits 5-2) 0011 = 0.13 m 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0007h sector protect/unprotect scheme 07 = advanced sector protection 4ah 00e7h (ws128j) 0077h (ws064j) simultaneous operation number of sectors in all banks except boot block 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page, 04 = 16 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 01h = dual boot device, 02h = bottom boot device, 03h = top boot device 50h 0000h program suspend. 00h = not supported 57h 0004h bank organization: x = number of banks 58h 0027h (ws128j) 0017h (ws064j) bank a region information. x = number of sectors in bank 59h 0060h (ws128j) 0030h (ws064j) bank b region information. x = number of sectors in bank 5ah 0060h (ws128j) 0030h (ws064j) bank c region information. x = number of sectors in bank 5bh 0027h (ws128j) 0017h (ws064j) bank d region information. x = number of sectors in bank
may 5, 2004 s29ws128/064j 50 ta b l e 1 2 . ws128j sector address table bank sector sector size (x16) address range bank d sa0 4 kwords 000000h-000fffh sa1 4 kwords 001000h-001fffh sa2 4 kwords 002000h-002fffh sa3 4 kwords 003000h-003fffh sa4 4 kwords 004000h-004fffh sa5 4 kwords 005000h-005fffh sa6 4 kwords 006000h-006fffh sa7 4 kwords 007000h-007fffh sa8 32 kwords 008000h-00ffffh sa9 32 kwords 010000h-017fffh sa10 32 kwords 018000h-01ffffh sa11 32 kwords 020000h-027fffh sa12 32 kwords 028000h-02ffffh sa13 32 kwords 030000h-037fffh sa14 32 kwords 038000h-03ffffh sa15 32 kwords 040000h-047fffh sa16 32 kwords 048000h-04ffffh sa17 32 kwords 050000h-057fffh sa18 32 kwords 058000h-05ffffh sa19 32 kwords 060000h-067fffh sa20 32 kwords 068000h-06ffffh sa21 32 kwords 070000h-077fffh sa22 32 kwords 078000h-07ffffh sa23 32 kwords 080000h-087fffh sa24 32 kwords 088000h-08ffffh sa25 32 kwords 090000h-097fffh sa26 32 kwords 098000h-09ffffh sa27 32 kwords 0a0000h-0a7fffh sa28 32 kwords 0a8000h-0affffh sa29 32 kwords 0b0000h-0b7fffh sa30 32 kwords 0b8000h-0bffffh sa31 32 kwords 0c0000h-0c7fffh sa32 32 kwords 0c8000h-0cffffh sa33 32 kwords 0d0000h-0d7fffh sa34 32 kwords 0d8000h-0dffffh sa35 32 kwords 0e0000h-0e7fffh sa36 32 kwords 0e8000h-0effffh sa37 32 kwords 0f0000h-0f7fffh sa38 32 kwords 0f8000h-0fffffh
51 s29ws128/064j may 5, 2004 bank c sa39 32 kwords 100000h-107fffh sa40 32 kwords 108000h-10ffffh sa41 32 kwords 110000h-117fffh sa42 32 kwords 118000h-11ffffh sa43 32 kwords 120000h-127fffh sa44 32 kwords 128000h-12ffffh sa45 32 kwords 130000h-137fffh sa46 32 kwords 138000h-13ffffh sa47 32 kwords 140000h-147fffh sa48 32 kwords 148000h-14ffffh sa49 32 kwords 150000h-157fffh sa50 32 kwords 158000h-15ffffh sa51 32 kwords 160000h-167fffh sa52 32 kwords 168000h-16ffffh sa53 32 kwords 170000h-177fffh sa54 32 kwords 178000h-17ffffh sa55 32 kwords 180000h-187fffh sa56 32 kwords 188000h-18ffffh sa57 32 kwords 190000h-197fffh sa58 32 kwords 198000h-19ffffh sa59 32 kwords 1a0000h-1a7fffh sa60 32 kwords 1a8000h-1affffh sa61 32 kwords 1b0000h-1b7fffh sa62 32 kwords 1b8000h-1bffffh sa63 32 kwords 1c0000h-1c7fffh sa64 32 kwords 1c8000h-1cffffh sa65 32 kwords 1d0000h-1d7fffh sa66 32 kwords 1d8000h-1dffffh sa67 32 kwords 1e0000h-1e7fffh sa68 32 kwords 1e8000h-1effffh sa69 32 kwords 1f0000h-1f7fffh sa70 32 kwords 1f8000h-1fffffh table 12. ws128j sector address table (continued) bank sector sector size (x16) address range
may 5, 2004 s29ws128/064j 52 bank c sa71 32 kwords 200000h-207fffh sa72 32 kwords 208000h-20ffffh sa73 32 kwords 210000h-217fffh sa74 32 kwords 218000h-21ffffh sa75 32 kwords 220000h-227fffh sa76 32 kwords 228000h-22ffffh sa77 32 kwords 230000h-237fffh sa78 32 kwords 238000h-23ffffh sa79 32 kwords 240000h-247fffh sa80 32 kwords 248000h-24ffffh sa81 32 kwords 250000h-257fffh sa82 32 kwords 258000h-25ffffh sa83 32 kwords 260000h-267fffh sa84 32 kwords 268000h-26ffffh sa85 32 kwords 270000h-277fffh sa86 32 kwords 278000h-27ffffh sa87 32 kwords 280000h-287fffh sa88 32 kwords 288000h-28ffffh sa89 32 kwords 290000h-297fffh sa90 32 kwords 298000h-29ffffh sa91 32 kwords 2a0000h-2a7fffh sa92 32 kwords 2a8000h-2affffh sa93 32 kwords 2b0000h-2b7fffh sa94 32 kwords 2b8000h-2bffffh sa95 32 kwords 2c0000h-2c7fffh sa96 32 kwords 2c8000h-2cffffh sa97 32 kwords 2d0000h-2d7fffh sa98 32 kwords 2d8000h-2dffffh sa99 32 kwords 2e0000h-2e7fffh sa100 32 kwords 2e8000h-2effffh sa101 32 kwords 2f0000h-2f7fffh sa102 32 kwords 2f8000h-2fffffh table 12. ws128j sector address table (continued) bank sector sector size (x16) address range
53 s29ws128/064j may 5, 2004 bank c sa103 32 kwords 300000h-307fffh sa104 32 kwords 308000h-30ffffh sa105 32 kwords 310000h-317fffh sa106 32 kwords 318000h-31ffffh sa107 32 kwords 320000h-327fffh sa108 32 kwords 328000h-32ffffh sa109 32 kwords 330000h-337fffh sa110 32 kwords 338000h-33ffffh sa111 32 kwords 340000h-347fffh sa112 32 kwords 348000h-34ffffh sa113 32 kwords 350000h-357fffh sa114 32 kwords 358000h-35ffffh sa115 32 kwords 360000h-367fffh sa116 32 kwords 368000h-36ffffh sa117 32 kwords 370000h-377fffh sa118 32 kwords 378000h-37ffffh sa119 32 kwords 380000h-387fffh sa120 32 kwords 388000h-38ffffh sa121 32 kwords 390000h-397fffh sa122 32 kwords 398000h-39ffffh sa123 32 kwords 3a0000h-3a7fffh sa124 32 kwords 3a8000h-3affffh sa125 32 kwords 3b0000h-3b7fffh sa126 32 kwords 3b8000h-3bffffh sa127 32 kwords 3c0000h-3c7fffh sa128 32 kwords 3c8000h-3cffffh sa129 32 kwords 3d0000h-3d7fffh sa130 32 kwords 3d8000h-3dffffh sa131 32 kwords 3e0000h-3e7fffh sa132 32 kwords 3e8000h-3effffh sa133 32 kwords 3f0000h-3f7fffh sa134 32 kwords 3f8000h-3fffffh table 12. ws128j sector address table (continued) bank sector sector size (x16) address range
may 5, 2004 s29ws128/064j 54 bank b sa135 32 kwords 400000h-407fffh sa136 32 kwords 408000h-40ffffh sa137 32 kwords 410000h-417fffh sa138 32 kwords 418000h-41ffffh sa139 32 kwords 420000h-427fffh sa140 32 kwords 428000h-42ffffh sa141 32 kwords 430000h-437fffh sa142 32 kwords 438000h-43ffffh sa143 32 kwords 440000h-447fffh sa144 32 kwords 448000h-44ffffh sa145 32 kwords 450000h-457fffh sa146 32 kwords 458000h-45ffffh sa147 32 kwords 460000h-467fffh sa148 32 kwords 468000h-46ffffh sa149 32 kwords 470000h-477fffh sa150 32 kwords 478000h-47ffffh sa151 32 kwords 480000h-487fffh sa152 32 kwords 488000h-48ffffh sa153 32 kwords 490000h-497fffh sa154 32 kwords 498000h-49ffffh sa155 32 kwords 4a0000h-4a7fffh sa156 32 kwords 4a8000h-4affffh sa157 32 kwords 4b0000h-4b7fffh sa158 32 kwords 4b8000h-4bffffh sa159 32 kwords 4c0000h-4c7fffh sa160 32 kwords 4c8000h-4cffffh sa161 32 kwords 4d0000h-4d7fffh sa162 32 kwords 4d8000h-4dffffh sa163 32 kwords 4e0000h-4e7fffh sa164 32 kwords 4e8000h-4effffh sa165 32 kwords 4f0000h-4f7fffh sa166 32 kwords 4f8000h-4fffffh table 12. ws128j sector address table (continued) bank sector sector size (x16) address range
55 s29ws128/064j may 5, 2004 bank b sa167 32 kwords 500000h-507fffh sa168 32 kwords 508000h-50ffffh sa169 32 kwords 510000h-517fffh sa170 32 kwords 518000h-51ffffh sa171 32 kwords 520000h-527fffh sa172 32 kwords 528000h-52ffffh sa173 32 kwords 530000h-537fffh sa174 32 kwords 538000h-53ffffh sa175 32 kwords 540000h-547fffh sa176 32 kwords 548000h-54ffffh sa177 32 kwords 550000h-557fffh sa178 32 kwords 558000h-55ffffh sa179 32 kwords 560000h-567fffh sa180 32 kwords 568000h-56ffffh sa181 32 kwords 570000h-577fffh sa182 32 kwords 578000h-57ffffh sa183 32 kwords 580000h-587fffh sa184 32 kwords 588000h-58ffffh sa185 32 kwords 590000h-597fffh sa186 32 kwords 598000h-59ffffh sa187 32 kwords 5a0000h-5a7fffh sa188 32 kwords 5a8000h-5affffh sa189 32 kwords 5b0000h-5b7fffh sa190 32 kwords 5b8000h-5bffffh sa191 32 kwords 5c0000h-5c7fffh sa192 32 kwords 5c8000h-5cffffh sa193 32 kwords 5d0000h-5d7fffh sa194 32 kwords 5d8000h-5dffffh sa195 32 kwords 5e0000h-5e7fffh sa196 32 kwords 5e8000h-5effffh sa197 32 kwords 5f0000h-5f7fffh sa198 32 kwords 5f8000h-5fffffh table 12. ws128j sector address table (continued) bank sector sector size (x16) address range
may 5, 2004 s29ws128/064j 56 bank b sa199 32 kwords 600000h-607fffh sa200 32 kwords 608000h-60ffffh sa201 32 kwords 610000h-617fffh sa202 32 kwords 618000h-61ffffh sa203 32 kwords 620000h-627fffh sa204 32 kwords 628000h-62ffffh sa205 32 kwords 630000h-637fffh sa206 32 kwords 638000h-63ffffh sa207 32 kwords 640000h-647fffh sa208 32 kwords 648000h-64ffffh sa209 32 kwords 650000h-657fffh sa210 32 kwords 658000h-65ffffh sa211 32 kwords 660000h-667fffh sa212 32 kwords 668000h-66ffffh sa213 32 kwords 670000h-677fffh sa214 32 kwords 678000h-67ffffh sa215 32 kwords 680000h-687fffh sa216 32 kwords 688000h-68ffffh sa217 32 kwords 690000h-697fffh sa218 32 kwords 698000h-69ffffh sa219 32 kwords 6a0000h-6a7fffh sa220 32 kwords 6a8000h-6affffh sa221 32 kwords 6b0000h-6b7fffh sa222 32 kwords 6b8000h-6bffffh sa223 32 kwords 6c0000h-6c7fffh sa224 32 kwords 6c8000h-6cffffh sa225 32 kwords 6d0000h-6d7fffh sa226 32 kwords 6d8000h-6dffffh sa227 32 kwords 6e0000h-6e7fffh sa228 32 kwords 6e8000h-6effffh sa229 32 kwords 6f0000h-6f7fffh sa230 32 kwords 6f8000h-6fffffh table 12. ws128j sector address table (continued) bank sector sector size (x16) address range
57 s29ws128/064j may 5, 2004 bank a sa231 32 kwords 700000h-707fffh sa232 32 kwords 708000h-70ffffh sa233 32 kwords 710000h-717fffh sa234 32 kwords 718000h-71ffffh sa235 32 kwords 720000h-727fffh sa236 32 kwords 728000h-72ffffh sa237 32 kwords 730000h-737fffh sa238 32 kwords 738000h-73ffffh sa239 32 kwords 740000h-747fffh sa240 32 kwords 748000h-74ffffh sa241 32 kwords 750000h-757fffh sa242 32 kwords 758000h-75ffffh sa243 32 kwords 760000h-767fffh sa244 32 kwords 768000h-76ffffh sa245 32 kwords 770000h-777fffh sa246 32 kwords 778000h-77ffffh sa247 32 kwords 780000h-787fffh sa248 32 kwords 788000h-78ffffh sa249 32 kwords 790000h-797fffh sa250 32 kwords 798000h-79ffffh sa251 32 kwords 7a0000h-7a7fffh sa252 32 kwords 7a8000h-7affffh sa253 32 kwords 7b0000h-7b7fffh sa254 32 kwords 7b8000h-7bffffh sa255 32 kwords 7c0000h-7c7fffh sa256 32 kwords 7c8000h-7cffffh sa257 32 kwords 7d0000h-7d7fffh sa258 32 kwords 7d8000h-7dffffh sa259 32 kwords 7e0000h-7e7fffh sa260 32 kwords 7e8000h-7effffh sa261 32 kwords 7f0000h-7f7fffh sa262 4 kwords 7f8000h-7f8fffh sa263 4 kwords 7f9000h-7f9fffh sa264 4 kwords 7fa000h-7fafffh sa265 4 kwords 7fb000h-7fbfffh sa266 4 kwords 7fc000h-7fcfffh sa267 4 kwords 7fd000h-7fdfffh sa268 4 kwords 7fe000h-7fefffh sa269 4 kwords 7ff000h-7fffffh table 12. ws128j sector address table (continued) bank sector sector size (x16) address range
may 5, 2004 s29ws128/064j 58 ta b l e 1 3 . ws064j sector address table bank sector sector size (x16) address range bank d sa0 4 kwords 000000h-000fffh sa1 4 kwords 001000h-001fffh sa2 4 kwords 002000h-002fffh sa3 4 kwords 003000h-003fffh sa4 4 kwords 004000h-004fffh sa5 4 kwords 005000h-005fffh sa6 4 kwords 006000h-006fffh sa7 4 kwords 007000h-007fffh sa8 32 kwords 008000h-00ffffh sa9 32 kwords 010000h-017fffh sa10 32 kwords 018000h-01ffffh sa11 32 kwords 020000h-027fffh sa12 32 kwords 028000h-02ffffh sa13 32 kwords 030000h-037fffh sa14 32 kwords 038000h-03ffffh sa15 32 kwords 040000h-047fffh sa16 32 kwords 048000h-04ffffh sa17 32 kwords 050000h-057fffh sa18 32 kwords 058000h-05ffffh sa19 32 kwords 060000h-067fffh sa20 32 kwords 068000h-06ffffh sa21 32 kwords 070000h-077fffh sa22 32 kwords 078000h-07ffffh
59 s29ws128/064j may 5, 2004 bank c sa23 32 kwords 080000h-087fffh sa24 32 kwords 088000h-08ffffh sa25 32 kwords 090000h-097fffh sa26 32 kwords 098000h-09ffffh sa27 32 kwords 0a0000h-0a7fffh sa28 32 kwords 0a8000h-0affffh sa29 32 kwords 0b0000h-0b7fffh sa30 32 kwords 0b8000h-0bffffh sa31 32 kwords 0c0000h-0c7fffh sa32 32 kwords 0c8000h-0cffffh sa33 32 kwords 0d0000h-0d7fffh sa34 32 kwords 0d8000h-0dffffh sa35 32 kwords 0e0000h-0e7fffh sa36 32 kwords 0e8000h-0effffh sa37 32 kwords 0f0000h-0f7fffh sa38 32 kwords 0f8000h-0fffffh sa39 32 kwords 100000h-107fffh sa40 32 kwords 108000h-10ffffh sa41 32 kwords 110000h-117fffh sa42 32 kwords 118000h-11ffffh sa43 32 kwords 120000h-127fffh sa44 32 kwords 128000h-12ffffh sa45 32 kwords 130000h-137fffh sa46 32 kwords 138000h-13ffffh table 13. ws064j sector address table (continued) bank sector sector size (x16) address range
may 5, 2004 s29ws128/064j 60 bank c sa47 32 kwords 140000h-147fffh sa48 32 kwords 148000h-14ffffh sa49 32 kwords 150000h-157fffh sa50 32 kwords 158000h-15ffffh sa51 32 kwords 160000h-167fffh sa52 32 kwords 168000h-16ffffh sa53 32 kwords 170000h-177fffh sa54 32 kwords 178000h-17ffffh sa55 32 kwords 180000h-187fffh sa56 32 kwords 188000h-18ffffh sa57 32 kwords 190000h-197fffh sa58 32 kwords 198000h-19ffffh sa59 32 kwords 1a0000h-1a7fffh sa60 32 kwords 1a8000h-1affffh sa61 32 kwords 1b0000h-1b7fffh sa62 32 kwords 1b8000h-1bffffh sa63 32 kwords 1c0000h-1c7fffh sa64 32 kwords 1c8000h-1cffffh sa65 32 kwords 1d0000h-1d7fffh sa66 32 kwords 1d8000h-1dffffh sa67 32 kwords 1e0000h-1e7fffh sa68 32 kwords 1e8000h-1effffh sa69 32 kwords 1f0000h-1f7fffh sa70 32 kwords 1f8000h-1fffffh table 13. ws064j sector address table (continued) bank sector sector size (x16) address range
61 s29ws128/064j may 5, 2004 bank b sa71 32 kwords 200000h-207fffh sa72 32 kwords 208000h-20ffffh sa73 32 kwords 210000h-217fffh sa74 32 kwords 218000h-21ffffh sa75 32 kwords 220000h-227fffh sa76 32 kwords 228000h-22ffffh sa77 32 kwords 230000h-237fffh sa78 32 kwords 238000h-23ffffh sa79 32 kwords 240000h-247fffh sa80 32 kwords 248000h-24ffffh sa81 32 kwords 250000h-257fffh sa82 32 kwords 258000h-25ffffh sa83 32 kwords 260000h-267fffh sa84 32 kwords 268000h-26ffffh sa85 32 kwords 270000h-277fffh sa86 32 kwords 278000h-27ffffh sa87 32 kwords 280000h-287fffh sa88 32 kwords 288000h-28ffffh sa89 32 kwords 290000h-297fffh sa90 32 kwords 298000h-29ffffh sa91 32 kwords 2a0000h-2a7fffh sa92 32 kwords 2a8000h-2affffh sa93 32 kwords 2b0000h-2b7fffh sa94 32 kwords 2b8000h-2bffffh table 13. ws064j sector address table (continued) bank sector sector size (x16) address range
may 5, 2004 s29ws128/064j 62 bank b sa95 32 kwords 2c0000h-2c7fffh sa96 32 kwords 2c8000h-2cffffh sa97 32 kwords 2d0000h-2d7fffh sa98 32 kwords 2d8000h-2dffffh sa99 32 kwords 2e0000h-2e7fffh sa100 32 kwords 2e8000h-2effffh sa101 32 kwords 2f0000h-2f7fffh sa102 32 kwords 2f8000h-2fffffh sa103 32 kwords 300000h-307fffh sa104 32 kwords 308000h-30ffffh sa105 32 kwords 310000h-317fffh sa106 32 kwords 318000h-31ffffh sa107 32 kwords 320000h-327fffh sa108 32 kwords 328000h-32ffffh sa109 32 kwords 330000h-337fffh sa110 32 kwords 338000h-33ffffh sa111 32 kwords 340000h-347fffh sa112 32 kwords 348000h-34ffffh sa113 32 kwords 350000h-357fffh sa114 32 kwords 358000h-35ffffh sa115 32 kwords 360000h-367fffh sa116 32 kwords 368000h-36ffffh sa117 32 kwords 370000h-377fffh sa118 32 kwords 378000h-37ffffh table 13. ws064j sector address table (continued) bank sector sector size (x16) address range
63 s29ws128/064j may 5, 2004 bank a sa119 32 kwords 380000h-387fffh sa120 32 kwords 388000h-38ffffh sa121 32 kwords 390000h-397fffh sa122 32 kwords 398000h-39ffffh sa123 32 kwords 3a0000h-3a7fffh sa124 32 kwords 3a8000h-3affffh sa125 32 kwords 3b0000h-3b7fffh sa126 32 kwords 3b8000h-3bffffh sa127 32 kwords 3c0000h-3c7fffh sa128 32 kwords 3c8000h-3cffffh sa129 32 kwords 3d0000h-3d7fffh sa130 32 kwords 3d8000h-3dffffh sa131 32 kwords 3e0000h-3e7fffh sa132 32 kwords 3e8000h-3effffh sa133 32 kwords 3f0000h-3f7fffh sa134 4 kwords 3f8000h-3f8fffh sa135 4 kwords 3f9000h-3f9fffh sa136 4 kwords 3fa000h-3fafffh sa137 4 kwords 3fb000h-3fbfffh sa138 4 kwords 3fc000h-3fcfffh sa139 4 kwords 3fd000h-3fdfffh sa140 4 kwords 3fe000h-3fefffh sa141 4 kwords 3ff000h-3fffffh table 13. ws064j sector address table (continued) bank sector sector size (x16) address range
may 5, 2004 s29ws128/064j 64 command definitions writing specific address and data commands or sequences into the command register initiates device operations. ta b l e 18, ?command definitions,? on page 78 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write th e reset command to return the device to reading array data. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data in asynchronous mode. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. after completing a pro - gramming operation in the erase suspend mode, the system may once again read array data from any non-erase-suspended sector within the same bank. see the ?erase suspend/erase resume commands? section on page 73 for more information. the system must issue the reset command to return a bank to the read (or erase- suspend-read) mode if dq5 goes high during an active program or erase opera - tion, or if the bank is in the autoselect mode. see the ?reset command? section on page 68 for more information. see also ?requirements for asynchronous read operation (non-burst)? section on page 27 and ?requirements for synchronous (b urst) read operation? section on page 28 for more information. the asynchronous read and synchronous/ burst read tables provide the read parameters, and figure 14, ?clk synchronous burst mode read (rising active clk),? on page 94 , figure 16, ?synchronous burst mode read,? on page 95 , and figure 19, ?asynchronous mode read with latched addresses,? on page 98 show the timings. set configuration register command sequence the device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, rdy configuration, and synchronous mode active. the configur ation register must be set before the device will enter burst mode. the configuration register is loaded with a three-cycle command sequence. the first two cycles are standard unlock sequences. on the third cycle, the data should be c0h, address bits a11?a0 should be 555h, and address bits a19?a12 set the code to be latched. the device will power up or after a hardware reset with the default setting, which is in asyn chronous mode. the register must be set before the device can enter synchronou s mode. the configuration register can not be changed during device operatio ns (program, erase, or sector lock).
65 s29ws128/064j may 5, 2004 figure 3. synchronous/asynchronous state diagram read mode setting on power-up or hardware reset, the device is set to be in asynchronous read mode. this setting allows the system to en able or disable burst mode during sys - tem operations. address a19 determines th is setting: ?1? for asynchronous mode, ?0? for synchronous mode. programmable wait state configuration the programmable wait state feature informs the device of the number of clock cycles that must elapse after avd# is driven active before data will be available. this value is determined by the input frequency of the device. address bits a14? a12 determine the setting (see tab le 14, ?programmable wait state settings,? on page 66 ). the wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. the number of wait states that should be programmed into the device is directly related to the clock frequency. power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (d15 = 0) set burst mode configuration register command for asynchronous mode (d15 = 1)
may 5, 2004 s29ws128/064j 66 ta b l e 1 4 . programmable wait state settings notes: 1. upon power-up or hardware reset, the default setting is seven wait states. 2. rdy will default to being active with data when the wait state setting is set to a total initial access cycle of 2. it is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. a hardware reset will set the wait state to the default setting. standard wait-state handshaking option the host system must set the appropriate number of wait states in the flash de - vice depending upon the clock frequency. the host system should set address bits a14?a12 to 010 for a clock frequency of 66/80 mhz. ta b l e 1 5 describes the typical number of clock cycles (wait states) for various conditions. ta b l e 1 5 . wait states for standard wait-state handshaking * in the 8-, 16- and 32-word burst read modes, the addr ess pointer does not cross 64-word boundaries (addresses which are multiples of 3fh). the host system must set the appropriate number of wait states in the flash de - vice depending upon the clock frequency. the autoselect function allows the host system to determine whether the flash de vice is enabled for handshaking. see the ?autoselect command sequence? section on page 68 for more information. read mode configuration the device supports four different read modes: continuous mode, and 8, 16, and 32 word linear wrap around modes. a contin uous sequence begins at the starting address and advances the address pointer until the burst operation is complete. if the highest address in the device is reached during the continuous burst read mode, the address pointer wraps ar ound to the lowest address. for example, an eight-word linear read wi th wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. the address pointer then returns to the 1st word after the previous eight word a14 a13 a12 total initial access cycles 0 0 0 2 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 7 (default) 1 1 0 reserved 1 1 1 reserved burst mode conditions typical no. of clock cycles after avd# low 66/80 mhz 8-word or 16-word or continuous v io = 1.8 v 4 32-word v io = 1.8 v 5
67 s29ws128/064j may 5, 2004 boundary, wrapping through the starting location. the sixteen- and thirty-two lin - ear wrap around modes operate in a fashion similar to the eight-word mode. ta b l e 1 6 shows the address bits and settings for the four read modes. ta b l e 1 6 . read mode settings note: upon power-up or hardware reset the default setting is continuous. burst active clock edge configuration by default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. subsequent outputs will also be on the following rising edges, barring any delays. the device can be set so that the falling clock edge is active for all synchronous accesses. address bit a17 determines this set - ting; ?1? for rising active, ?0? for falling active. rdy configuration by default, the device is set so that the rdy pin will output v oh whenever there is valid data on the outputs. the device can be set so that rdy goes active one data cycle before active data. address bit a18 determines this setting; ?1? for rdy active with data, ?0? for rdy active one clock cycle before valid data. in asynchronous mode, rdy is an open-drain output. configuration register ta b l e 1 7 shows the address bits that determine the configuration register settings for various device functions. burst modes address bits a16 a15 continuous 0 0 8-word linear wrap around 0 1 16-word linear wrap around 1 0 32-word linear wrap around 1 1
may 5, 2004 s29ws128/064j 68 ta b l e 1 7 . configuration register note: device will be in the default state upon power-up or hardware reset. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys - tem was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). this re - sets the bank to which the system was wr iting to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writ - ing the reset command returns that bank to the erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the op - eration is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autosele ct mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manu - facturer and device codes, and determine whether or not a sector is protected. ta b l e 18, ?command definitions,? on page 78 shows the address and data re - address bit function settings (binary) a19 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous mode (default) a18 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) a17 clock 0 = burst starts and data is output on the falling edge of clk 1 = burst starts and data is output on the rising edge of clk (default) a16 read mode synchronous mode 00 = continuous (default) 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around a15 a14 programmable wait state 000 = data is valid on the 2nd active clk edge after avd# transition to v ih 001 = data is valid on the 3rd active clk edge after avd# transition to v ih 010 = data is valid on the 4th active clk edge after avd# transition to v ih 011 = data is valid on the 5th active clk edge after avd# transition to v ih 100 = data is valid on the 6th active clk edge after avd# transition to v ih 101 = data is valid on the 7th active clk edge after avd# transition to v ih (default) 110 = reserved 111 = reserved a13 a12
69 s29ws128/064j may 5, 2004 quirements. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autose - lect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle th at contains the bank address and the au - toselect command. the bank then enters the autoselect mode. no subsequent data will be made available if the autoselect data is read in synchronous mode. the system may read at any address within the same bank any number of times without initiating another autoselect command sequence. read commands to other banks will return data from the array. the following table describes the ad - dress requirements for the various autose lect functions, and the resulting data. ba represents the bank address, and sa represents the sector address. the de - vice id is read in three cycles. the system must write the reset command to return to the read mode (or erase- suspend-read mode if the bank wa s previously in erase suspend). enter secsi? sector/exit secsi? sector command sequence the secsi? sector region provides a secured data area containing a random, eight word electronic serial number (esn). the system can access the secsi? sector region by issuing the three-cycle enter secsi? sector command se - quence. the device continues to access the secsi? sector region until the system issues the four-cycle exit secsi? sector command sequence. the exit secsi? sector command sequence returns the device to normal operation. the secsi? sector is not accessible when th e device is executing an embedded pro - gram or embedded erase algorithm. ta b l e 18, ?command definitions,? on description address read data manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 227eh device id, word 2 (ba) + 0eh 2218h (ws128j) 221eh (ws064j) device id, word 3 (ba) + 0fh 2200h (ws128j) 2201h (ws064j) sector protection verification (sa) + 02h 0001 (locked), 0000 (unlocked) indicator bits (ba) + 03h dq15 - dq8 = 0 dq7 - factory lock bit 1 = locked, 0 = not locked dq6 -customer lock bit 1 = locked, 0 = not locked dq5 - handshake bit 1 = reserved, 0 = standard handshake dq4 & dq3 - boot code 00 = dual boot sector, 01 = top boot sector, 10 = bottom boot sector dq2 - dq0 = 001
may 5, 2004 s29ws128/064j 70 page 78 shows the address and data re quirements for both command sequences. the following commands are not allo wed when the secsi? is accessible. ?cfi ? unlock bypass entry ? unlock bypass program ? unlock bypass reset ? erase suspend/resume ?chip erase program command sequence programming is a four-bus-cycle operat ion. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com - mand. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further con - trols or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. ta b l e 18, ?command defini - tions,? on page 78 shows the address and data requirements for the program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by monitoring dq7 or dq6/dq2. refer to the ?write operation status? section on page 81 for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program op - eration. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit can - not be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bit to indicate the oper - ation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to primarily program to a array faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program com - mand sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program - ming time. the host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. the erase command sequences are four cycles in length instead of six cycles. ta b l e 18, ?command definitions,? on page 78 shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program, unlock bypass sector erase, unlock bypass chip erase, and unlock bypass reset com - mands are valid. to exit the unlock bypass mode, the system must issue the two- cycle unlock bypass reset command sequence. the first cycle must contain the
71 s29ws128/064j may 5, 2004 bank address and the data 90h. the second cycle need only contain the data 00h. the array then returns to the read mode. the device offers accelerated program operations through the acc input. when the system asserts v hh on this input, the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the acc input to ac - celerate the operation. figure 4, ?program operation,? on page 71 illustrates the algorithm for the pro - gram operation. refer to the erase/program operations table in the ac characteristics section for parameters, and figure 22, ?asynchronous program operation timings: avd# latched addresses,? on page 101 and figure 24, ?syn - chronous program operation timings: we# latched addresses,? on page 103 for timing diagrams. figure 4. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini - tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto - matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is no t required to provide any controls or tim - ings during these operations. tab l e 18, ?command definitions,? on page 78 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latche d. the system can determine the status start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 18 for program command sequence.
may 5, 2004 s29ws128/064j 72 of the erase operation by using dq7 or dq6/dq2. refer to the ?write operation status? section on page 81 for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. the command sequence is two cycles in length instead of six cycles. see tab le 18, ?command definitions,? on page 78 for details on the unlock bypass command sequences. figure 5, ?erase operation,? on page 74 illustrates the algorithm for the erase op - eration. refer to the erase/program operations table in the ac characteristics section for parameters and timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi - tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. tab le 18, ?command defi - nitions,? on page 78 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em - bedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electr ical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than 50 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise era - sure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor inter - rupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system must rewrite the command se - quence and any additional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see ?dq3: sector erase timer? section on page 86 .) the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading dq7 or dq6/dq2 in the erasing bank. refer to the ?write operation status? sec - tion on page 81 for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im - mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
73 s29ws128/064j may 5, 2004 the host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. the command sequence is four cycles cycles in length instead of six cycles. figure 5, ?erase operation,? on page 74 illustrates the algorithm for the erase op - eration. refer to the erase/program operations table in the figure , ?ac characteristics,? on page 100 for parameters and timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this com - mand is valid only during the sector erase operation, including the minimum 50 s time-out period during the sector erase command sequence. the erase sus - pend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. how - ever, when the erase suspend command is written during the sector erase time- out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the erase-sus - pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta - tus information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the figure , ?write operation status,? on page 81 for information on these sta - tus bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bi ts, just as in the standard program op - eration. refer to the ?write operation status? section on page 81 for more information. in the erase-suspend-read mode, the syst em can also issue the autoselect com - mand sequence. refer to the ?autoselect mode? section on page 31 and ?autoselect command sequence? section on page 68 for details.
may 5, 2004 s29ws128/064j 74 to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writ - ing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. figure 5. erase operation password program command the password program command permits programming the password that is used as part of the hardwa re protection scheme. the actual password is 64-bits long. 4 password program commands are required to program the password. the user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. there are no provisions for entering the 2-cycle unlock cycle, the password pro - gram command, and all the password data. there is no special addressing order required for programming the password. also, when the password is undergoing programming, simultaneous operation is disabled. read operations to any memory location will return the programming status except dq7. once pro - gramming is complete, the user must issue a secsi? exit command to return the device to normal operation. once the password is written and verified, the password mode locking bit must be set in order to prevent verification. the password program command is only capable of programming ?0?s. program - ming a ?1? after a cell is programmed as a ?0? results in a time-out by the embedded program algorithm? with the cell remaining as a ?0?. the password is all f?s when shipped from the factory. all 64-bit password combinations are valid as a password. password verify command the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 18 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
75 s29ws128/064j may 5, 2004 password mode locking bit is programmed and the user attempts to verify the password, the device will always drive all f?s onto the dq data bus. also, the device will not operate in simultaneous operation when the password verify command is executed. only the password is returned regardless of the bank address. the lower two address bits (a1?a0) are valid during the password verify. writing the secsi? exit command returns the device back to normal operation. password protection mode locking bit program command the password protection mode locking bit program command programs the password protection mode locking bit, which prevents further verifies or up - dates to the password. once programmed, the password protection mode locking bit cannot be erased and the persistent protection mode locking bit pro - gram circuitry is disabled, thereby forcing the device to remain in the password protection mode. after issuing ?pl/68h? at the fourth bus cycle, the device re - quires a time out period of approximately 150 s for programming the password protection mode locking bit. then by writing ?pl/48h? at the fifth bus cycle, the device outputs verify data at dq0. if dq0 = 1, then the password protection mode locking bit is programmed. if not, the system must repeat this program sequence from the fourth cycle of ?pl/68h?. exiting the password protection mode locking bit program command is acco mplished by writing the secsi sector command. persistent sector protection mode locking bit program command the persistent sector protection mode locking bit program command programs the persistent sector protection mode locking bit, which prevents the password mode locking bit from ever being prog rammed. by disabling the program cir - cuitry of the password mode locking bit, the device is forced to remain in the persistent sector protection mode of operat ion, once this bit is set. after issuing ?smpl/68h? at the fourth bus cycle, the device requires a time out period of ap - proximately 150 s for programming the persistent protect ion mode locking bit. then by writing ?smpl/48h? at the fifth bus cycle, the device outputs verify data at dq0. if dq0 = 1, then the persistent protection mode locking bit is pro - grammed. if not, the system must repeat this program sequence from the fourth cycle of ?pl/68h?. exiting the persistent protection mode locking bit pro - gram command is accomplished by writ ing the secsi sector exit command. secsi? sector protection bit program command to protect the secsi sector, write the secsi sector protect command sequence while in the secsi sector mode. after issu ing ?opbp/48h? at the fourth bus cycle, the device requires a time out period of approximately 150 s to protect the secsi sector. then, by writing ?opbp/48? at the fifth bus cycle, the device outputs verify data at dq0. if dq0 = 1, then the secsi sector is protected. if not, then the sys - tem must repeat this program sequence from the fourth cycle of ?opbp/48h?. ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit if it is cleared ei - ther at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear command. on ce the ppb lock bit is set, it cannot be cleared unless the device is taken through a power-on clear or the password unlock command is executed. upon se tting the ppb lock bit, the ppbs are latched into the dpbs. if the password mode locking bit is set, the ppb lock bit status is reflected as set, even after a power-on reset cycle. exiting the ppb lock
may 5, 2004 s29ws128/064j 76 bit set command is accomplished by writing the secsi? exit command, only while in the persistent sector protection mode. dpb write/erase/status command the dpb write command is used to set or clear a dpb for a given sector. the high order address bits (amax?a11) are issued at the same time as the code 01h or 00h on dq7-dq0. all other dq data bus pins are ignored during the data write cycle. the dpbs are modifiable at any time, regardless of the state of the ppb or ppb lock bit. if the ppb is set, the sector is protected regardless of the value of the dpb. if the ppb is cleared, setting the dpb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device will clear the dpbs. the programming of the dpb for a given sector can be verified by writing a dpb status command to the device. exiting the dpb write/erase command is accomplished by writing the read/reset command. ex - iting the dpb status command is accomplished by writing the secsi? sector exit command password unlock command the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modification, thereby allowing the ppbs to become ac - cessible for modification. the exact pass word must be entered in order for the unlocking function to occur. this command cannot be issued any faster than 2 s at a time to prevent a hacker from runn ing through the all 64-bit combinations in an attempt to correctly match a password. if the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. the password unlock function is accompl ished by writing password unlock com - mand and data to the device to perform the clearing of the ppb lock bit. the password is 64 bits long, so the user mu st write the password unlock command 4 times. a1 and a0 are used for matching. writing the password unlock com - mand is not address order specific. the lower address a1?a0= 00, the next password unlock command is to a1?a0= 01, then to a1?a0= 10, and finally to a1?a0= 11. once the password unlock command is entered for all four words, the rdy pin goes low indicating that the device is busy. also, reading the bank d results in the dq6 pin toggling, indicating that the password unlock function is in progress. reading the other bank returns actual array data. approximately 1s is required for each portion of the unlock. once the first portion of the password unlock completes (rdy is not driven and dq6 does not toggle when read), the password unlock command is issued again, only this time with the next part of the password. four password unlock commands are required to successfully clear the ppb lock bit. as with the first password unlock command, the rdy sig - nal goes low and reading the device results in the dq6 pin toggling on successive read operations until complete. it is the responsibility of the micro - processor to keep track of the number of password unlock commands, the order, and when to read the ppb lock bit to confirm successful password unlock. in order to re lock the device into the password mode, the ppb lock bit set com - mand can be re-issued. ppb program command the ppb program command is used to program, or set, a given ppb. each ppb is individually programmed (but is bulk erased with the other ppbs). the specific sector address (amax?a12) are written at the same time as the program com - mand 60h with a6 = 0. if the ppb lock bit is set and the corresponding ppb is set
77 s29ws128/064j may 5, 2004 for the sector, the ppb program command will not execute and the command will time-out without programming the ppb. after programming a ppb, two additional cycles are needed to determine whether the ppb has been programmed with margin. after 4th cycle, the device requires approximately 150 s time out period for programming the ppb. and then after 5th cycle, the device outputs verify data at dq0. the ppb program command does not follow the embedded program algorithm. writing the secsi? sector exit command returns the device back to normal operation. all ppb erase command the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually erasing a specific ppb. unlike the ppb program, no specific sector address is required. however, when the ppb erase command is written (60h) and a6 = 1, all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command will not execute and the command will time-out with - out erasing the ppbs. after erasing the ppbs, two additional cycles are needed to determine whether the ppb has been erased with margin. after 4th cycle, the device requires ap - proximately 1.5 ms time out period for erasing the ppb. and then after 5th cycle, the device outputs verify data at dq0. it is the responsibility of the user to preprogram all ppbs prior to issuing the all ppb erase command. if the user attempts to erase a cleared ppb, over-erasure may occur making it difficult to program the ppb at a later time. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. writing the secsi? sector exit command returns the device back to normal operation. ppb status command the programming of the ppb for a given sector can be verified by writing a ppb status verify command to the device. ppb lock bit status command the programming of the ppb lock bit for a given sector can be verified by writ - ing a ppb lock bit status verify command to the device.
may 5, 2004 s29ws128/064j 78 command definitions ta b l e 1 8 . command definitions command sequence (note 1) cycles bus cycles (notes 1?6) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data asynchronous read (note 7) 1 ra rd reset (note 8) 1 xxx f0 autoselect (note 9) manufacturer id 4 555 aa 2aa 55 (ba) 555 90 (ba) x00 0001 device id (note 10) 6 555 aa 2aa 55 (ba) 555 90 (ba) x01 227e (ba)x 0e (note 10) (ba) x0f (not e 10) sector lock verify (note 11) 4 555 aa 2aa 55 (sa) 555 90 (sa) x02 0000/ 0001 indicator bits 4 555 aa 2aa 55 (ba) 555 90 (ba) x03 (note 12) program 4 555 aa 2aa 55 555 a0 pa data chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 15) 1 ba b0 erase resume (note 16) 1 ba 30 set configuration register (note 17) 3 555 aa 2aa 55 (cr) 555 c0 cfi query (note 18) 1 55 98 unlock bypass mode unlock bypass entry 3 555 aa 2aa 55 555 20 unlock bypass program (notes 13 , 14 ) 2 xx a0 pa pd unlock bypass sector erase (notes 13 , 14 ) 2 xx 80 sa 30 unlock bypass erase (notes 13 , 14 ) 2 xx 80 xxx 10 unlock bypass reset (notes 13 , 14 ) 2 xx 90 xxx 00 sector protection command definitions secsi? sector secsi? sector entry 3 555 aa 2aa 55 555 88 secsi? sector exit 4 555 aa 2aa 55 555 90 xx 00 secsi? protection bit program (notes 19 , 20 , 22 ) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd (0) password protection password program (notes 19 , 24 ) 4 555 aa 2aa 55 555 38 xx0 pd0 xx1 pd1 xx2 pd2 xx3 pd3 password verify 4 555 aa 2aa 55 555 c8 xx0 pd0 xx1 pd1 xx2 pd2 xx3 pd3 password unlock (note 24 ) 7 555 aa 2aa 55 555 28 xx0 pd0 xx1 pd1 xx2 pd2 xx3 pd3
79 s29ws128/064j may 5, 2004 legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the rising edge of the avd# pulse or active edge of clk which ever comes first. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits amax?a12 uniquely select any sector. ba = address of the bank (ws128j: a22, a21, a20, ws064j: a21, a20, a19) that is being switched to autoselect mode, is in bypass mode, or is being erased. sla = address of the sector to be locked. set sector address (sa) and either a6 = 1 for unlocked or a6 = 0 for locked. cr = configuration register address bits a19?a12. ow = address (a7?a0) is (00011010). pd3?pd0 = password data. pd3?pd0 present four 16 bi t combinations that represent the 64-bit password pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. pl = address (a7-a0) is (00001010) rd(0) = dq0 protection indicator bit. if protected, dq0 = 1, if unprotected, dq0 = 0. rd(1) = dq1 protection indicator bit. if protected, dq1 = 1, if unprotected, dq1 = 0. sl = address (a7-a0) is (00010010) wd= write data. see ?configuration register? definition for specific write data wp = address (a7-a0) is (00000010) notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at rd(0) and rd(1). 4. data bits dq15?dq8 are don?t care in command sequences, except for rd, pd, wd, pwd, and pd3-pd0. 5. unless otherwise noted, address bits amax?a12 are don?t cares. ppb commands ppb program (notes 19 , 20 , 22 ) 6 555 aa 2aa 55 555 60 (sa) + wp 68 (sa) + wp 48 xx rd (0) all ppb erase (notes 19 , 20 , 23 , 25 ) 6 555 aa 2aa 55 555 60 wp 60 (sa) wp 40 xx rd (0) ppb status (note 26 ) 4 555 aa 2aa 55 (sa) 555 90 (sa) x02 rd (0) ppb lock bit ppb lock bit set 3 555 aa 2aa 55 555 78 ppb lock bit status (note 20 ) 4 555 aa 2aa 55 (ba) 555 58 ba rd (1) dpb dpb write 4 555 aa 2aa 55 555 48 sa x1 dpb erase 4 555 aa 2aa 55 555 48 sa x0 dpb status 4 555 aa 2aa 55 (ba) 555 58 sa rd (0) password protection mode locking bit program (notes 19 , 20 , 22 ) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd (0) persistent protection mode locking bit program (notes 19 , 20 , 22 ) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd (0) command sequence (note 1) cycles bus cycles (notes 1?6) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
may 5, 2004 s29ws128/064j 80 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. the fourth cycle of the autoselect command sequence is a re ad cycle. the system must provide the bank address. see the autoselect command sequence section for more information. 10. (ba)x0fh = 2200h (ws128j), (ba)x0eh = 2218h (ws128j), (ba)x0fh = 221eh (ws064j), (ba)x0eh = 2201h (ws064j) 11. the data is 0000h for an unlocked sector and 0001h for a locked sector 12. dq15 - dq8 = 0, dq7 - factory lock bit (1 = locked, 0 = not locked), dq6 -customer lock bit (1 = locked, 0 = not locked), dq5 = handshake bit (1 = reserved, 0 = standard handshake)8, dq4 & dq3 - boot code (00= dual boot sector, 01= top boot sector, 10= bottom boot sector, 11=no boot sector), dq2 - dq0 = 001 13. the unlock bypass command sequence is required prior to this command sequence. 14. the unlock bypass reset command is required to return to reading array data. 15. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sect or erase operation, and requires the bank address. 16. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 17. see ?set configuration register command sequence? for details. 18. command is valid when device is ready to read array data or when device is in autoselect mode. 19. the reset command returns the device to reading the array. 20. regardless of clk and avd# interaction or control register bit 15 setting, command mode verifies are always asynchronous read operations. 21. acc must be at v hh during the entire operation of this command 22. the fourth cycle programs the addressed locking bit. the fifth and sixth cycles are used to validate whether the bit has bee n fully programmed. if dq0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 23. the fourth cycle erases all ppbs. the fifth and sixth cycles ar e used to validate whether the bits have been fully erased. i f dq0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 24. the entire four bus-cycle sequence must be entered for each portion of the password. 25. before issuing the erase command, all ppbs should be programmed in order to prevent over-erasure of ppbs. 26. in the fourth cycle, 01h indicates ppb set; 00h indicates ppb not set.
81 s29ws128/064j may 5, 2004 write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. ta b l e 20, ?write operation status,? on page 87 and the following subsections describe the function of these bits. dq7 and dq6 each offers a method for determining whether a program or erase op - eration is complete or in progress. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the com - plement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro - gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1 ? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status in - formation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the bank returns to the read mode. if not al l selected sectors are protected, the em - bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if th e system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq6?dq0 while output enable (oe#) is as - serted low. that is, the device may chan ge from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6-dq0 may be still invalid. valid data on dq7-d00 will appear on successive read cycles. ta b l e 20, ?write operation status,? on page 87 shows the outputs for data# poll - ing on dq7. figure 6, ?data# polling algorithm,? on page 82 shows the data# polling algorithm. figure 28, ?data# polling timings (during embedded algorithm),? on page 107 in the ac characteristics section shows the data# polling timing diagram.
may 5, 2004 s29ws128/064j 82 notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a va lid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 6. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
83 s29ws128/064j may 5, 2004 rdy: ready the rdy is a dedicated output that, when the device is configured in the synchro - nous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. the rdy pin is only controlled by ce#. using the rdy configuration command sequ ence, rdy can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. the following conditions caus e the rdy output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3fh. when the device is configured in asynch ronous mode, the rdy is an open-drain output pin which indicates whether an embedded algorithm is in progress or completed. the rdy status is valid after the rising edge of the final we# pulse in the command sequence. if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is in high im - pedance (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. ta b l e 20, ?write operation status,? on page 87 shows the outputs for rdy. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy - cles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo - rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac - tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en - ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter - natively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a pr otected sector, dq6 toggles for approxi - mately 1 ms after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for a dditional information: figure 7, ?toggle bit algorithm,? on page 84 , ?dq6: toggle bit i? on page 83 , figure 29, ?toggle bit timings (during embedded algorithm),? on page 107 (toggle bit timing diagram), and ta b l e 19, ?dq6 and dq2 indications,? on page 85 . toggle bit i on dq6 requires either oe# or ce# to be deasserteed and reasserted to show the change in state.
may 5, 2004 s29ws128/064j 84 figure 7. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is ac - tively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte (dq0-dq7) address = va dq6 = toggle? read byte twice (dq 0-dq7) adrdess = va read byte (dq0-dq7) address = va fail pass note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
85 s29ws128/064j may 5, 2004 mode information. refer to tab l e 19, ?dq6 and dq2 indications,? on page 85 to compare outputs for dq2 and dq6. see the following for a dditional information: figure 7, ?toggle bit algorithm,? on page 84 , ?dq6: toggle bit i? on page 83 , figure 29, ?toggle bit timings (during embedded algorithm),? on page 107 , and ta b l e 19, ?dq6 and dq2 indi - cations,? on page 85 . ta b l e 1 9 . dq6 and dq2 indications reading toggle bits dq6/dq2 refer to figure 7, ?toggle bit algorithm,? on page 84 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7? dq0 at least twice in a row to determine whether a toggle bit is toggling. typi - cally, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the tog - gle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc - cessfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system in itially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de - scribed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo - rithm when it returns to determine the status of the operation ( figure 7, ?toggle bit algorithm,? on page 84 ). if device is and the system reads then dq6 and dq2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable.
may 5, 2004 s29ws128/064j 86 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified inter - nal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspen d-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de - termine whether or not erasure has beg un. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be as - sumed to be less than 50 s, the system need not monitor dq3. see also ?sector erase command sequence? on page 72 . after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further comman ds (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept addi - tional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each sub - sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 2 0 shows the status of dq3 relative to the other status bits.
87 s29ws128/064j may 5, 2004 ta b l e 2 0 . write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs arra y data if the system addresses a non-busy bank. 4. the system may read either asynchronously or synchronously (burst) while in erase suspend. 5. the rdy pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. this is available in the asynchronous mode only. 6. when the device is set to asynchronous mode, these status flags should be read by ce# toggle. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) rdy (note 5) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle (note 6) 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read (note 4) erase suspended sector 1 no toggle (note 6) 0 n/a toggle high impedance non-erase suspended sector data data data data data high impedance erase-suspend-program dq7# toggle 0 n/a n/a 0
may 5, 2004 s29ws128/064j 88 absolute maximum ratings storage temperature, plastic packages ................................. ?65c to +150c ambient temperature with power applied .............................. ?65c to +125c voltage with respect to ground: all inputs and i/os except as noted below (note 1) ................ ?0.5 v to v io + 0.5 v v cc (note 1) ................................................................. ?0.5 v to +2.5 v v io ............................................................................. ?0.5 v to +2.5 v a9, reset#, acc (note 1) ............................................. ?0.5 v to +12.5 v output short circuit current (note 3) ................................... 100 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ? 2.0 v for periods of up to 20 ns. see figure 8 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 9 . 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 3. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v
89 s29ws128/064j may 5, 2004 operating ranges commercial (c) devices ambient temperature (t a )0c to +70c industrial (i) devices ambient temperature (t a )................................................... ?40c to +85c supply voltages v cc supply voltages ........................................................... +1.65 v to +1.95 v v io supply voltages: .......................................................... +1.65 v to +1.95 v v cc >= v io - 100mv operating ranges define those limits between which the functionality of the device is guaranteed.
may 5, 2004 s29ws128/064j 90 dc characteristics cmos compatible notes: 1. maximum i cc specifications are tested with v cc = v cc max. 2. v cc = v io 3. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 4. i cc active while embedded erase or embedded program is in progress. 5. device enters automatic sleep mode when addresses are stable for t acc + 60 ns. typical sleep mode current is equal to i cc3 . 6. total current during accelerated programming is the sum of v acc and v cc currents. parameter description test conditions notes: 1 & 2 min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v ih , we# = v ih , burst length = 8 66 mhz 15 30 ma 80 mhz 18 36 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 16 66 mhz 15 30 ma 80 mhz 18 36 ma ce# = v il , oe# = v ih , we# = v ih , burst length = continuous 66 mhz 15 30 ma 80 mhz 18 36 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 8 50 200 a i io1 v io non-active output oe# = v ih 0.2 10 a i cc1 v cc active asynchronous read current (note 3) ce# = v il , oe# = v ih , we# = v ih 10 mhz 20 30 ma 5 mhz 12 16 ma 1 mhz 3.5 5 ma i cc2 v cc active write current (note 4) ce# = v il , oe# = v ih , acc = v ih 15 40 ma i cc3 v cc standby current (note 5) ce# = reset# = v cc 0.2 v 0.2 50 a i cc4 v cc reset current reset# = v il, clk = v il 0.2 50 a i cc5 v cc active current (read while write) ce# = v il , oe# = v ih 66 mhz 22 54 ma 80 mhz 25 60 ma i cc6 v cc sleep current ce# = v il , oe# = v ih 0.2 50 a i acc accelerated program current (note 6) ce# = v il , oe# = v ih, v acc = 12.0 0.5 v v acc 7 15 ma v cc 5 10 ma v il input low voltage v io = 1.8 v ?0.5 0.4 v v ih input high voltage v io = 1.8 v v io ? 0.4 v io + 0.4 v ol output low voltage i ol = 100 a, v cc = v cc min = v io 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min = v io v io ? 0.1 v v id voltage for autoselect and temporary sector unprotect v cc = 1.8 v 11.5 12.5 v v hh voltage for accelerated program 11.5 12.5 v v lko low v cc lock-out voltage 1.0 1.4 v
91 s29ws128/064j may 5, 2004 test conditions ta b l e 2 1 . test specifications key to switching waveforms switching waveforms test condition all speed options unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 2.5 - 3 ns input pulse levels 0.0?v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v c l device under te s t figure 10. test setup waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) figure 11. input waveforms and measurement levels v io 0.0 v output measurement level input v io /2 v io /2 all inputs and outputs
may 5, 2004 s29ws128/064j 92 ac characteristics v cc power-up notes: 1. v cc >= v io - 100mv and v cc ramp rate is > 1v / 100s 2. v cc ramp rate <1v / 100s, a hardware reset will be required. figure 12. v cc power-up diagram clk characterization figure 13. clk characterization parameter description test setup speed unit t vcs v cc setup time min 50 s t vios v io setup time min 50 s t rsth reset# low hold time min 50 s parameter description 66 mhz 80 mhz unit f clk clk frequency max 66 80 mhz t clk clk period min 15 12.5 ns t ckh clk high time min 7.0 5 ns t ckl clk low time t cr clk rise time max 3 2.5 ns t cf clk fall time v cc v io reset# t vcs t vios t clk t cl t ch t cr t cf clk
93 s29ws128/064j may 5, 2004 ac characteristics synchronous/burst read @ v io = 1.8 v note: 1. addresses are latched on the first of either the active edge of clk or the rising edge of avd#. parameter description 66 mhz 80 mhz unit jedec standard t iacc latency (standard wait-state handshake mode) for 8-word and 16-word burst max 56 46 ns t iacc latency (standard wait-state handshake mode) for 32- word and continuous burst max 71 58.5 ns t bacc burst access time valid clock to output delay max 11.2 9.1 ns t acs address setup time to clk (note 1) min 4 ns t ach address hold time from clk (note 1) min 5.5 ns t bdh data hold time from next clock cycle min 2 ns t cr chip enable to rdy valid max 11.2 9.1 ns t oe output enable to output valid max 11.2 9.1 ns t cez chip enable to high z max 8 ns t oez output enable to high z max 8 ns t ces ce# setup time to clk min 4 ns t rdys rdy setup time to clk min 4 ns t racc ready access time from clk max 11.2 9.1 ns t aas address setup time to avd# (note 1) min 4 ns t aah address hold time to avd# (note 1) min 5.5 ns t cas ce# setup time to avd# min 0 ns t avc avd# low to clk min 4 ns t avd avd# pulse min 10 ns t acc access time max 55 45 ns t cka clk to access resume max 11.2 9.1 ns t ckz clk to high z max 8 ns t oes output enable setup time min 4 ns
may 5, 2004 s29ws128/064j 94 ac characteristics notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at a 64-word boundary, two a dditional clock cycle are inserted, and is indicated by rdy. 3. the device is in synchronous mode. figure 14. clk synchronous burst mode read (rising active clk) notes: 1. figure shows total number of wait states set to four cycl es. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active falling edge. 2. if any burst address occurs at a 64-word boundary, two a dditional clock cycle are inserted, and is indicated by rdy. 3. the device is in synchronous mode. figure 15. clk synchronous burst mode read (falling active clock) da da + 1 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t acc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1 2 34 56 7 t rdys t bacc t cr da da + 1 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t oez t cez t iacc t acc t bdh 4 cycles for initial access shown. t racc hi-z hi-z hi-z 12345 t rdys t bacc t cr
95 s29ws128/064j may 5, 2004 ac characteristics notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at a 64-word boundary, two a dditional clock cycle are inserted, and is indicated by rdy. 3. the device is in synchronous mode. figure 16. synchronous burst mode read notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at a 64-word boundary, two a dditional clock cycle are inserted, and is indicated by rdy. 3. the device is in synchronous mode with wrap around. 4. d0-d7 in data waveform indicates the order the data with in a given 8-word address range, from lowest to highest. starting address in figure is the 4th address in range (ac) figure 17. 8-word linear burst with wrap around da da + 1 da + n oe# data addresses aa avd# rdy clk ce# t cas t aas t avc t avd t aah t oe t racc t oez t cez t iacc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1234567 t rdys t bacc t acc t cr dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df db 7 cycles for initial access shown. hi-z t racc 1 234567 t rdys t bacc t cr d8 t racc
may 5, 2004 s29ws128/064j 96 ac characteristics notes: 1. figure assumes 6 wait states for initial access and synchronous read. 2. the set configuration register command sequence has been written with a18=0; device will output rdy one cycle before valid data. figure 18. linear burst with rdy set one cycle before data da+1 da da+2 da+3 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 6 wait cycles for initial access shown. hi-z hi-z hi-z 1 23456 t rdys t bacc t cr
97 s29ws128/064j may 5, 2004 ac characteristics asynchronous mode read @ v io = 1.8 v notes: 1. asynchronous access time is from the last of either stable addresses or the falling edge of avd#. 2. not 100% tested. parameter description 66 mhz 80 mhz unit jedec standard t ce access time from ce# low max 55 45 ns t acc asynchronous access time (note 1) max 55 45 ns t avdp avd# low time min 10 ns t aavds address setup time to rising edge of avd min 4 ns t aavdh address hold time from rising edge of avd min 5.5 ns t oe output enable to output valid max 11.2 9.1 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 8 ns t oez output enable to high z (note 2) max 8 ns t cas ce# setup time to avd# min 0 ns
may 5, 2004 s29ws128/064j 98 ac characteristics note: ra = read address, rd = read data. figure 19. asynchronous mode read with latched addresses note: ra = read address, rd = read data. figure 20. asynchronous mode read t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez t aavdh t avdp t aavds avd# ra t cas t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez avd# ra
99 s29ws128/064j may 5, 2004 ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 35 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 200 ns t rpd reset# low to standby mode min 20 s reset# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp figure 21. reset timings
may 5, 2004 s29ws128/064j 100 ac characteristics erase/program operations @ v io = 1.8 v notes: 1. not 100% tested. 2. asynchronous mode allows both asynchronous and synchronous program operation. synchronous mode allows both asynchronous and synchronous program operation. 3. in asynchronous program operation timing, addresses are latc hed on the falling edge of we# or rising edge of avd#. in synchronous program operation timing, addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 4. see the ?erase and programming performance? section for more information. 5. does not include the preprogramming time. parameter description 66 mhz 80 mhz unit jedec standard t avav t wc write cycle time (note 1) min 45 ns t avwl t as address setup time (notes 2 , 3 ) synchronous min 4 ns asynchronous 0 t wlax t ah address hold time (notes 2 , 3 ) synchronous min 5.5 ns asynchronous 15 t avdp avd# low time min 10 ns t dvwh t ds data setup time min 20 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 20 ns t whwl t wph write pulse width high min 20 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 4) typ <7 s t whwh1 t whwh1 accelerated programming operation (note 4) typ <4 s t whwh2 t whwh2 sector erase operation (notes 4 , 5 ) typ <0.2 sec chip erase operation (notes 4 , 5 ) <104 t vid v acc rise and fall time min 500 ns t vids v acc setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s t elwl t cs ce# setup time to we# min 0 ns t avsw avd# setup time to we# min 4 ns t avhw avd# hold time to we# min 4 ns t avhc avd# hold time to clk min 4 ns t csw clock setup time to we# min 5 ns
101 s29ws128/064j may 5, 2004 ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a22?a12 are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is independent of the set device read mode bit in the configuration reg - ister. figure 22. asynchronous program operation timings: avd# latched addresses oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph pa t vcs t cs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h 555h pd
may 5, 2004 s29ws128/064j 102 ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a22?a12 are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is independent of the set device read mode bit in the configuration reg - ister. figure 23. asynchronous program operation timings: we# latched addresses oe# ce# data addresses avd# we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t acs t cas t ah t csw t avsw
103 s29ws128/064j may 5, 2004 ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a22?a12 are don?t care during command sequence unlock cycles. 4. addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 5. either ce# or avd# is required to go from low to high in between programming command sequences. 6. the synchronous programming operation is dependent of the set device read mode bit in the configuration register. the configuration register must be set to the synchronous read mode. figure 24. synchronous program operation timings: we# latched addresses oe# ce# data addresses avd# we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t acs t cas t ah t avch t csw t avsw
may 5, 2004 s29ws128/064j 104 ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a22?a12 are don?t care during command sequence unlock cycles. 4. addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 5. either ce# or avd# is required to go from low to high in between programming command sequences. 6. the synchronous programming operation is dependent of the set device read mode bit in the configuration register. the configuration register must be set to the synchronous read mode. figure 25. synchronous program operation timings: clk latched addresses oe# ce# data addresses avd# we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avch t csw t avsc
105 s29ws128/064j may 5, 2004 ac characteristics figure 26. chip/sector erase command sequence notes: 1. sa is the sector address for sector erase. 2. address bits a22?a12 are don?t cares during unlock cycles in the command sequence. oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h
may 5, 2004 s29ws128/064j 106 ac characteristics note: use setup and hold times from conventional program operation. figure 27. accelerated unlock bypass programming timing ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id 1 s v il or v ih t vid t vids
107 s29ws128/064j may 5, 2004 ac characteristics notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data# polling will output true data. 3. while in asynchronous mode, rdy will be low while the device is in embedded erase or programming mode. figure 28. data# polling timings (during embedded algorithm) notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. while in asynchronous mode, rdy will be low while the device is in embedded erase or programming mode. figure 29. toggle bit timings (during embedded algorithm) we# ce# oe# t oe addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data we# ce# oe# t oe addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data
may 5, 2004 s29ws128/064j 108 ac characteristics notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. rdy is active with data (a18 = 0 in the configuration register). when a18 = 1 in the configuration register, rdy is active one clock cycle before data. figure 30. synchronous data polling timings/toggle bit timings ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 31. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
109 s29ws128/064j may 5, 2004 ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from rdy high for temporary sector unprotect min 4 s reset# t vidr v id v il or v ih v id v il or v ih ce# we# rdy t vidr t rsp program or erase command sequence t rrb figure 32. temporary sector unprotect timing diagram
may 5, 2004 s29ws128/064j 110 ac characteristics sector protect: 150 s sector unprot ect: 1.5 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. figure 33. sector/sector block protect and unprotect timing diagram
111 s29ws128/064j may 5, 2004 ac characteristics notes: 1. rdy active with data (a18 = 0 in the configuration register). 2. rdy active one clock cycle before data (a18 = 1 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. figure shows the device not crossing a bank in the process of performing an erase or program. 4. if the starting address latched in is either 3eh or 3fh (or some 64 multiple of either), there is no additional 2 cycle latency at the boundary crossing. figure 34. latency with boundary crossing clk address (hex) c60 c61 c62 c63 c63 c63 c64 c65 c66 c67 d60 d61 d62 d63 d64 d65 d66 d67 (stays high) avd# rdy data address boundary occurs every 64 words, beginning at address 00003fh: 00007fh, 0000bfh, etc. address 000000h is also a boundary crossing. 3c 3d 3e 3f 3f 3f 40 41 42 43 latency rdy latency t racc (note 1) (note 2) t racc t racc t racc
may 5, 2004 s29ws128/064j 112 ac characteristics notes: 1. rdy active with data (a18 = 0 in the configuration register). 2. rdy active one clock cycle before data (a18 = 1 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. figure shows the device crossing a bank in the process of performing an erase or program. figure 35. latency with boundary crossing into program/erase bank clk address (hex) c60 c61 c62 c63 c63 c63 c64 d60 d61 d62 d63 read status (stays high) avd# rdy data oe#, ce# (stays low) address boundary occurs every 64 words, beginning at address 00003fh: 00007fh, 0000bfh, etc. address 000000h is also a boundary crossing. 3c 3d 3e 3f 3f 3f 40 latency rdy latency t racc (note 1) (note 2) t racc t racc t racc invalid
113 s29ws128/064j may 5, 2004 ac characteristics wait state decoding addresses: a14, a13, a12 = ?111? ? reserved a14, a13, a12 = ?110? ? reserved a14, a13, a12 = ?101? ? 5 programmed, 7 total a14, a13, a12 = ?100? ? 4 programmed, 6 total a14, a13, a12 = ?011? ? 3 programmed, 5 total a14, a13, a12 = ?010? ? 2 programmed, 4 total a14, a13, a12 = ?001? ? 1 programmed, 3 total a14, a13, a12 = ?000? ? 0 programmed, 2 total note: figure assumes address d0 is not at an address boundary, active clock edge is rising, and wait state is set to ?101?. figure 36. example of wait states insertion data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles p ro g rammed 45
may 5, 2004 s29ws128/064j 114 ac characteristics note: breakpoints in waveforms indicate that system may alternately read array data from the ?non-busy bank? while checking the status of the program or erase operation in the ?busy? bank. th e system should read status twice to ensure valid information. figure 37. back-to-back read/w rite cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph
115 s29ws128/064j may 5, 2004 erase and programming performance notes: 1. typical program and erase times as sume the following conditions: 25 c, 1.8 v v cc , 100,000 cycles. additionally, programming typicals assumes a checkerboard pattern. 2. under worst case conditions of 90c, v cc = 1.65 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 18, ?command definitions,? on page 78 for further information on command definitions. 6. the device has a minimum cycling endurance of 100,000 cycles per sector. parameter typ (note 1) max (note 2) unit comments sector erase time 32 kword <0.4 <2 s excludes 00h programming prior to erasure (note 4) 4 kword <0.2 <2 chip erase time 128j <103 s 064j <53 word programming time <6 <100 s excludes system level overhead (note 5) accelerated word programming time <4 <67 s chip programming time (note 3) 128j <50.4 s excludes system level overhead (note 5) 064j <25.2 accelerated chip programming time 128j <33 s 064j <17
october 5, 2004 cosmoram_00_a0 cosmoram 116 preliminary cosmoram 32mbit (2m word x 16-bit) 64mbit (4m word x 16-bit) features ? asynchronous sram interface ? fast access time ?t ce = t aa = 70ns max ? 8 words page access capability ?t paa = 20ns max ? low voltage operating condition ?v dd = +1.65v to +1.95v (32m) ? +1.70v to +1.95v (64m) ? wide operating temperature ? ta = -30c to +85c ? byte control by lb# and ub# ? low power consumption ?i dda1 = 30ma max (32m), tbdma max (64m) ?i dds1 = 80ma max (32m), tbdma max (64m) ? various power down mode ? sleep, 4m-bit partial or 8m-bit partial (32m) ? sleep, 8m-bit partial or 16m-bit partial (64m)
117 cosmoram cosmoram_00_a0 october 5, 2004 preliminary pin description (32m) pin name description a 21 to a 0 address input: a 20 to a 0 for 32m, a 21 to a 0 for 64m ce1# chip enable (low active) ce2 chip enable (high active) we# write enable (low active) oe# output enable (low active) ub# upper byte control (low active) lb# lower byte control (low active) clk clock input adv# address valid input (low active) wait# wait signal output dq 16 - 9 upper byte data input/output dq 8 - 1 lower byte data input/output v dd power supply v ss ground
october 5, 2004 cosmoram_00_a0 cosmoram 118 preliminary functional description asynchronous operation (page mode) legend: l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance. notes: 1. should not be kept at this logic condition longer than 1s. 2. power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of partial size. refer to the " power down " section in the functional description for details. 3. ?l? for address pass through and ?h? for address latch on the rising edge of adv#. 4. oe# can be v il during write operation if the following conditions are satisfied: (1) write pulse is initiated by ce1# (refer to ce1# controlled write timing), or cycle time of the previous operation cycle is satisfied. (2) oe# stays v il during write cycle 5. can be either v il or v ih but must be valid before read or write. 6. output is either valid or high-z depending on the level of ub# and lb# input. mode ce2 ce1# clk adv# we# oe# lb# ub# a 21-0 dq 8-1 dq 16-9 wait# standby (deselect) h h x x x x x x x high-z high-z high-z output disable (note 1) hl x (note 3) h h x x note 5 high-z high-z high-z output disable (no read) x hl h h valid high-z high-z high-z read (upper byte) x h l valid high-z output valid high-z read (lower byte) x l h valid output valid high-z high-z read (word) x l l valid output valid output valid high-z page read x l/h l/h valid note 6 note 6 high-z no write x l h (note 4) h h valid invalid invalid high-z write (upper byte) x h l valid invalid input valid high-z write (lower byte) x l h valid input valid invalid high-z write (word) x l l valid input valid input valid high-z power down (note 2) l x x x x x x x x high-z high-z high-z
119 cosmoram cosmoram_00_a0 october 5, 2004 preliminary functional description synchronous operation (burst mode) legend: l = v il , h = v ih , x can be either v il or v ih , ve = valid edge, pelp = positive edge of low pulse, high- z = high impedance. notes: 1. should not be kept this logic condition longer than the specified time of 8s for 32m and 4s for 64m. 2. power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of partial size. refer to the " power down " section for details.f 3. valid clock edge shall be set on either positive or negative edge through cr set. clk must be started and stable prior to memory access. 4. can be either v il or v ih except for the case the both of oe# and we# are v il . it is prohibited to bring the both of oe# and we# to v il . 5. when device is operating in ?we# single clock pulse control? mode, we# is don?t care once write operation is determined by we# low pulse at the beginning of write access together with address latching. write suspend feature is not supported in ?we# single clock pulse control? mode. 6. can be either v il or v ih but must be valid before read or write is determined. and once ub# and lb# inputs are determined, they must not be changed until the end of burst. 7. once valid address is determined, input address must not be changed during adv#=l. 8. if oe#=l, output is either invalid or high-z depending on the level of ub# and lb# input. if we#=l, input is invalid. if oe#=we#=h, output is high-z. 9. output is either valid or high-z depending on the level of ub# and lb# input. 10. input is either valid or invalid depending on the level of ub# and lb# input. 11. output is either high-z or invalid depending on the level of oe# and we# input. 12. keep the level from previous cycle except for suspending on last data. refer to ?wait# output function? for details. 13. wait# output is driven in high level during write operation. mode ce2 ce1# clk adv# we# oe# lb# ub# a 21-0 dq 8-1 dq 16-9 wait# standby (deselect) h h x x x x x x x high-z high-z high-z start address latch (note 1) l ve (note 3) pelp x (note 4) x (note 4) x (note 6) x (note 6) valid (note 7) high-z (note 8) high-z (note 8) high-z (note 11) advance burst read to next address (note 1) ve (note 3) h h l x output valid (note 9) output valid (note 9) output valid burst read suspend (note 1) ve (note 3) h high-z high-z high (note 12) advance burst write to next address (note 1) ve (note 3) l (note 5) h input valid (note 10) input valid (note 10) high (note 13) burst write suspend (note 1) ve (note 3) h (note 5) iput invalid iput invalid high (note 12) terminate burst read ve x h x high-z high-z high-z terminate burst write ve x x h high-z high-z high-z power down (note 2) l x x x x x x x x high-z high-z high-z
october 5, 2004 cosmoram_00_a0 cosmoram 120 preliminary state diagrams initial/standby state asynchronous operation state figure 38. initial standby state diagram figure 39. asynchronous operation state diagram asynchronous operation (page mode) synchronous operation (burst mode) common state cr set power down standby standby power up pause time ce2=h ce2=l power down ce2=h @rp=1 ce2=l @m=0 @m=1 ce2=h @rp=0 (64m only) standby output disable write read ce2=ce1# = h ce1# = h address change or byte control byte control byte control @oe# = l ce1# = h ce1# = h ce1# = l we# = h we# = l oe# = h oe# = l ce1# = l & oe# = l ce1# = l & we# = l
121 cosmoram cosmoram_00_a0 october 5, 2004 preliminary synchronous operation state notes: 1. assumes all the parameters specified in the " ac characteristics " section are satisfied. refer to the " functional description " section, " ac characteristics " section, and the " timing diagrams " section for details. rp (reset to page) mode is available only for 64m. functional description this device supports asynchronous page read & normal write operation and syn - chronous burst read & burst write operation for faster memory access and features three kinds of power down modes for power saving as a user config - urable option. power-up it is required to follow the power-up timing to start executing proper device op - eration. refer to power-up timing. after power-up, the device defaults to asynchronous page read & normal write operation mode with sleep power down feature. configuration register the configuration register (cr) is used to configure the type of device function among optional features. each selection of features is set through cr set se - quence after power-up. if cr set sequence is not performed after power-up, the device is configured for asynchronous operation with sleep power down feature as default configuration. cr set sequence the cr set requires total 6 read/write operations with unique address. between each read/write operation requires the device to be in standby mode. the follow - ing table shows the detail sequence. figure 40. synchronous operation diagram cycle # operation address data 1st read 3fffffh (msb) read data (rda) 2nd write 3fffffh rda standby write read read suspend write suspend ce2 = ce1# = h ce1# = h ce1# = h we# = h we# = l a dv# low pulse adv# low pulse (@bl = 8 or 16, and after burst operation is completed) ce1# = l adv# low pulse & we# = l ce1# = l adv# low pulse & oe# = l adv# low pulse oe# = l oe# = h ce1# = h ce1# = h
october 5, 2004 cosmoram_00_a0 cosmoram 122 preliminary the first cycle is to read from most significant address (msb). the second and third cycle are to write to msb. if the second or third cycle is writ - ten into the different address, the cr set is cancelled and the data written by the second or third cycle is valid as a normal write operation. it is recommended to write back the data (rda) read by first cycle to msb in order to secure the data. the forth and fifth cycle is to write to msb. the data of forth and fifth cycle is don?t-care. if the forth or fifth cycle is written into different address, the cr set is also cancelled but write data may not be written as normal write operation. the last cycle is to read from specific address key for mode selection. and read data (rdb) is invalid. once this cr set sequence is performed from an initial cr set to the other new cr set, the written data stored in memory cell array may be lost. so, cr set se - quence should be performed prior to regu lar read/write operation if necessary to change from default configuration. 3rd write 3fffffh rda 4th write 3fffffh x 5th write 3fffffh x 6th read address key read data (rdb) cycle # operation address data
123 cosmoram cosmoram_00_a0 october 5, 2004 preliminary address key the address key has the following format. notes: 1. a21 and a6 to a0 must be all ?1? in any case. 2. it is prohibited to apply this key. 3. if m=0, all the registers must be set with appropriate key input at the same time. 4. if m=1, ps must be set with appropriate key input at the same time. except for ps, all the other key inputs must be ?1?. 5. burst read & single write is not supported at we# single clock pulse control. 6. effective only when ps=11. rp (reset to page) mode is available only for 64m. address pin register name function key description note 32m 64m a21 ? ? 1 ? unused bits muse be 1 1 a20-a19 ps partial size 00 8m partial 16m partial 01 4m partial 8m partial 10 reserved for future use 2 11 sleep [default] a18-a16 bl burst length 000 to 001 reserved for future use 2 010 8 words 011 16 words 100 to 110 reserved for future use 2 111 continuous a15 m mode 0 synchronous mode (burst read / write) 3 1 asynchronous mode [default] (page read / normal write) 4 a14-a12 rl read latency 000 reserved for future use 2 001 3 clocks 010 4 clocks 011 5 clocks 100 reserved for future use 6 clocks 101 to 111 reserved for future use 2 a11 bs burst sequence 0 reserved for future use 2 1 sequential a10 sw single write 0burst read & burst write 1 burst read & single write 5 a9 ve valid clock edge 0 falling clock edge 1 rising clock edge a8 rp reset to page 0 unused bits must be 1 reset to page mode 6 1 remain the previous mode a7 wc write control 0 we# single clock pulse control without write suspend function 5 1 we# level control with write suspend function a6-a0 ? ? 1 unused bits muse be 1 1
october 5, 2004 cosmoram_00_a0 cosmoram 124 preliminary power down the power down is low power idle state controlled by ce2. ce2 low drives the device in power down mode and maintains low power idle state as long as ce2 is kept low. ce2 high resumes the device from power down mode. these devices have three power down mode. these can be programmed by series of read/write operations. each mode has following features. the default state is sleep and it is the lowest power consumption but all data will be lost once ce2 is brought to low for power down. it is not required to program to sleep mode after power-up. 64m supports reset to page (rp) mode. when rp=0, power down comprehends a function to reset the device to defaul t configuration (asynchronous mode). after resuming from power down mode, the dev ice is back in default configurations. this is effective only when ps is set on sleep mode. when partial mode is se - lected, rp=0 is not effective. burst read/write operation synchronous burst read/write operation pr ovides faster memory access that syn - chronized to microcontroller or system bus frequency. configuration register set is required to perform burst read & write operation after power-up. once cr set sequence is performed to select synchronous burst mode, the device is config - ured to synchronous burst read/write op eration mode with corresponding rl and bl that is set through cr set sequence together with operation mode. in order to perform synchronous burst read & write operation, it is required to control new signals, clk, adv# and wait# that low power srams don?t have. 32m 64m mode data retention size retention address mode data retention size retention address sleep (default) no n/a sleep (default) no n/a 4m partial 4m bit 000000h to 03ffffh 8m partial 8m bit 000000h to 07ffffh 8m partial 8m bit 000000h to 07ffffh 16m partial 16m bit 000000h to 0fffffh
125 cosmoram cosmoram_00_a0 october 5, 2004 preliminary clk input function the clk is input signal to synchronize memory to micr ocontroller or system bus frequency during synchronous burst read & write operation. the clk input incre - ments device internal address counter and the valid edge of clk is referred for latency counts from address latch, burst write data latch, and burst read data out. during synchronous operation mode, clk input must be supplied except for standby state and power down state. clk is don?t care during asynchronous operation. figure 41. burst read operation figure 42. burst write operation a ddress adv# clk dq valid ce1# oe# wait# high-z high-z rl bl q 2 q bl q 1 we# high a ddress adv# clk dq valid ce1# oe# wait# high-z high-z rl-1 bl d 2 d bl d 1 we# high
october 5, 2004 cosmoram_00_a0 cosmoram 126 preliminary adv# input function the adv# is input signal to indicate valid address presence on address inputs. it is applicable to synchronous operation as well as asynchronous operation. adv# input is active during ce1#=l and ce1#=h disables adv# input. all addresses are determined on the positive edge of adv#. during synchronous burst read/write operation, adv#=h disables all address in - puts. once adv# is brought to high after valid address latch, it is inhibited to bring adv# low until the end of burst or until burst operation is terminated. adv# low pulse is mandatory for synchronous burst read/write operation mode to latch the valid address input. during asynchronous operation, adv#=h also disables all address inputs. adv# can be tied to low during asynchronous operation and it is not necessary to con - trol adv# to high. wait# output function the wait# is output signal to indicate data bus status when the device is oper - ating in synchronous burst mode. during burst read operation, wait# output is enabled after specified time dura - tion from oe#=l or ce1#=l whichever occurs last. wait# output low indicates data out at next clock cycle is invalid, and wait# output becomes high one clock cycle prior to valid data out. during oe# read suspend, wait# output doesn?t indicate data bus status but carries the same level from previous clock cycle (kept high) except for read suspend on the final data output. if final read data out is suspended, wait# output become high impedance after specified time duration from oe#=h. in case of continuous burst read operation of 32m, an additional output delay may occur when a burst sequence crosses it?s device-row boundary. the wait# out - put indicates this delay. refer to the " burst length " section for the additional delay cycles in details. during burst write operation, wait# output is enabled to high level after speci - fied time duration from we#=l or ce1#=l whichever occurs last and kept high for entire write cycles including we# write suspend. the actual write data latch - ing starts on the appropriate clock edge with respect to valid clock edge, read latency and burst length. during we# write suspend, wait# output doesn?t in - dicate data bus status but carries the same level from previous clock cycle (kept high) except for write suspend on the final data input. if final write data in is sus - pended, wait# output become high impedance after specified time duration from we#=h. the burst write operation of 32m and the both burst read/write operation of 64m are always started after fixed latency with respect to read latency set in cr. when the device is operating in asynch ronous mode, wait# output is always in high impedance.
127 cosmoram cosmoram_00_a0 october 5, 2004 preliminary latency read latency (rl) is the number of clock cycles between the address being latched and first read data becoming av ailable during synchronous burst read op - eration. it is set through cr set sequence after power-up. once specific rl is set through cr set sequence, write latency, that is the number of clock cycles be - tween address being latched and first write data being latched, is automatically set to rl-1.the burst operation is always started after fixed latency with respect to read latency set in cr. rl=6 is available only for 64m. figure 43. read latency diagram address adv# clk valid q1 q2 q3 d1 d2 d3 d4 0 12 345 rl=3 q4 d5 dq [out] dq [in] ce1# oe# or we# wait# wait# 6 q5 d5 q1 q2 d1 d2 d3 rl=4 q3 d4 dq [out] dq [in] wait# wait# q4 d5 q1 d1 d2 rl=5 q2 d3 dq [out] dq [in] wait# wait# q3 d4 high-z high-z high-z high-z high-z high-z d1 rl=6 q1 d2 dq [out] dq [in] wait# wait# q2 d3 high-z high-z
october 5, 2004 cosmoram_00_a0 cosmoram 128 preliminary address latch by adv# the adv# indicates valid address presence on address inputs. during synchro - nous burst read/write operation mode, all the address are determined on the positive edge of adv# when ce1#=l. the specified minimum value of adv#=l setup time and hold time against valid ed ge of clock where rl count begin must be satisfied for appropriate rl counts. valid address must be determined with specified setup time against either the negative edge of adv# or negative edge of ce1# whichever comes late. and the determined valid address must not be changed during adv#=l period. burst length burst length is the number of word to be read or write during synchronous burst read/write operation as the result of a single address latch cycle. it can be set on 8, 16 words boundary or continuous for entire address through cr set sequence. the burst type is sequential that is incremental decoding scheme within a bound - ary address. starting from initial address being latched, device internal address counter assign +1 to the previous address until reaching the end of boundary ad - dress and then wrap round to least significant address (=0). after completing read data out or write data latch for the set burst length, operation automatically ended except for continuous burst length. when continuous burst length is set, read/write is endless unless it is terminated by the positive edge of ce1#. during continuous burst read of 32m, an additional output delay may occur when a burst sequence cross it?s device-row boundary. this is the case when a0 to a6 of starting address is either 7dh, 7eh, or 7fh as shown in the following table. the wait# signal indicates this delay. the 64m device has no additional output delay. note: read address in hexadecimal. single write single write is synchronous write operation with burst length =1. the device can be configured either to ?burst read & single write? or to ?burst read & burst write? through cr set sequence. once the device is configured to ?burst read & single write? mode, the burst length for synchronous write operation is always fixed 1 regardless of bl values set in cr, while burst length for read is in accor - dance with bl values set in cr. start address (a6-a0) read address sequence bl = 8 bl = 16 continuous 00h 00-01-02-...-06-07 00-01-02-...-0e-0f 00-01-02-03-04-... 01h 01-02-03-...-07-00 01-02-03-...-0f-00 01-02-03-04-05-... 02h 02-03-...-07-00-01 02-03-...-0f-00-01 02-03-04-05-06-... 03h 03-...-07-00-01-02 03-...-0f-00-01-02 03-04-05-06-07-... ... ... ... ... 7ch 7c-...-7f-78-...-7b 7c-...-7f-70-...-7b 7c-7d-7e-7f-80-81-... 7dh 7d-7e-7f-78-...-7c 7d-7e-7f-70-...-7c 7d-7e-7f- wait -80-81-... 7eh 7e-7f-78-79-...-7d 7e-7f-70-71-...-7d 7e-7f- wait - wait -80-81-... 7fh 7f-78-79-7a-...-7e 7f-70-71-72-...-7e 7f- wait - wait - wait -80-81
129 cosmoram cosmoram_00_a0 october 5, 2004 preliminary write control the device has two types of we# signal control method, ?we# level control? and ?we# single clock pulse control?, for synchronous write operation. it is config - ured through cr set sequence. burst read suspend burst read operation can be suspended by oe# high pulse. during burst read op - eration, oe# brought to high suspends burst read operation. once oe# is brought to high with the specified set up time against clock where the data being suspended, the device internal counter is suspended, and the data output be - come high impedance after specified time duration. it is inhibited to suspend the first data out at the beginning of burst read. oe# brought to low resumes burst read operation. once oe# is brought to low, data output become valid after specified time duration, and internal address counter is reactivated. the last data out being suspended as the result of oe#=h and first data out as the result of oe#=l are from the same address. in order to guarantee to output last data before suspension and first data after resumption, the specified minimum value of oe#=l hold time and setup time against clock edge must be satisfied respectively. figure 44. write controls address adv# clk valid 0 12 345 ce1# we# 6 d1 d2 rl=5 d3 dq [in] wait# d4 we# d1 d2 d3 dq [in] wait# d4 high-z t wld high-z t wsck t ckwh t wlth t clth we# level control we# single clock pulse control t wlth
october 5, 2004 cosmoram_00_a0 cosmoram 130 preliminary burst write suspend burst write operation can be suspended by we# high pulse. during burst write operation, we# brought to high suspends burst write operation. once we# is brought to high with the specified set up time against clock where the data being suspended, device internal counter is susp ended, data input is ignored. it is in - hibited to suspend the first data input at the beginning of burst write. we# brought to low resumes burst write operation. once we# is brought to low, data input become valid after specifie d time duration, and internal address counter is reactivated. the write address of the cycle where data being sus - pended and the first write address as the result of we#=l are the same address. in order to guarantee to latch the last data input before suspension and first data input after resumption, the specified minimum value of we#=l hold time and setup time against clock edge must be satisfied respectively. burst write suspend function is available when the device is operating in we# level controlled burst write only. burst read termination burst read operation can be terminated by ce1# brought to high. if bl is set on continuous, burst read operation is continued endless unless terminated by figure 45. burst read suspend diagram figure 46. burst write suspend diagram q 2 dq oe# clk q 1 t ac t ckqx t olz t ac q 2 t ckqx t ac q 3 t ckqx t ac t ckoh t osck t ckoh t osck t ohz wait# t cktv q 4 dq we# d 1 t dhck t dsck t dsck d 2 t dhck t dsck t dsck d 3 t dhck t dsck t dsck t ckwh t wsck t ckwh t wsck d 2 d 4 wait# high clk
131 cosmoram cosmoram_00_a0 october 5, 2004 preliminary ce1#=h. it is inhibited to terminate burst read before first data out is completed. in order to guarantee last data output, the specified minimum value of ce1#=l hold time from clock edge must be satisfied. after termination, the specified min - imum recovery time is required to start new access. burst write termination burst write operation can be terminated by ce1# brought to high. if bl is set on continuous, burst write operation is continued endless unless terminated by ce1#=h. it is inhibited to terminate burst write before first data in is completed. in order to guarantee last write data being latched, the specified minimum values of ce1#=l hold time from clock edge must be satisfied. after termination, the specified minimum recovery time is required to start new access. figure 47. burst read termination diagram figure 48. burst write termination diagram a ddress adv# dq oe# clk valid ce1# wait# q 1 q 2 t ac t ckqx t ckclh t trb t ckoh t chz high-z t chtz t ohz a ddress adv# dq we# clk valid ce1# wait# t ckclh t trb t ckwh t chtz high-z d 2 d 1 t dhck t dhck t dsck t dsck t chck
october 5, 2004 cosmoram_00_a0 cosmoram 132 preliminary absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating cond itions (see warning below) notes: 1. maximum dc voltage on input and i/o pins are v dd +0.2v. during voltage transitions, inputs may positive overshoot to v dd +1.0v for periods of up to 5 ns. 2. minimum dc voltage on input or i/o pins are -0.3v. during voltage transitions, inputs may negative overshoot v ss to -1.0v for periods of up to 5ns. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the de - vice?s electrical characteristics are warra nted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating cond itions, or combinations not represented on the data sheet. package pin capacitance test conditions: t a = 25c, f = 1.0 mhz item symbol value unit voltage of v dd supply relative to v ss v dd -0.5 to +3.6 v voltage at any pin relative to v ss v in , v out -0.5 to +3.6 v short circuit output current i out 50 ma storage temperature t stg -55 to +125 c parameter symbol 32m 64m unit min max min max supply voltage v dd 1.65 1.95 1.7 1.95 v v ss 0 0 0 0 v high level input voltage (note 1) v ih v dd x 0.8 v dd +0.2 v dd x 0.8 v dd +0.2 v high level input voltage (note 2) v il -0.3 v dd x 0.2 -0.3 v dd x 0.2 v ambient temperature t a -30 85 -30 85 c symbol description te s t s e t u p ty p max unit c in1 address input capacitance v in = 0v ? 5 pf c in2 control input capacitance v in = 0v ? 5 pf c io data input/output capacitance v io = 0v ? 8 pf
133 cosmoram cosmoram_00_a0 october 5, 2004 preliminary dc characteristics (under recommended conditions unless otherwise noted) notes: 1. all voltages are referenced to v ss . 2. dc characteristics are measured after following power-up timing. 3. i out depends on the output load conditions. parameter symbol test conditions 32m 64m unit min. max. min. max. input leakage current i li v in = v ss to v dd -1.0 +1.0 -1.0 +1.0 a output leakage current i lo v out = v ss to v dd , output disable -1.0 +1.0 -1.0 +1.0 a output high voltage level v oh v dd = v dd (min), i oh = ?0.5ma 2.4 ? 2.4 ? v output low voltage level v ol i ol = 1ma ? 0.4 ? 0.4 v v dd power down current i ddps v dd = v dd max., v in = v ih or v il , ce2 0.2v sleep ? 10 ? tbd a i ddp4 4m partial ? 40 n/a a i ddp8 8m partial ? 50 ? tbd a i ddp16 16m partial n/a ? tbd v dd standby current i dds v dd = v dd max., v in (including clk)= v ih or v il , ce1# = ce2 = v ih ?1.5?tbdma i dds1 v dd = v dd max., v in (including clk) 0.2v or v in (including clk) v dd ? 0.2v, ce1# = ce2 v dd ? 0.2v ta +85c ? 80 ? tbd a ta +40c ? 80 ? tbd a v dd = v dd max., t ck =min. v in 0.2v or v in v dd ? 0.2v, ce1# = ce2 v dd ? 0.2v ? 200 ? tbd a v dd active current i dda1 v dd = v dd max., v in = v ih or v il , ce1# = v il and ce2= v ih , i out =0ma t rc / t wc = minimum ?30?35ma i dda2 t rc / t wc = 1 s ?3?5ma v dd page read current i dda3 v dd = v dd max., v in = v ih or v il , ce1# = v il and ce2= v ih , i out =0ma, t prc = min. ?10?tbdma v dd burst access current i dda4 v dd = v dd max., v in = v ih or v il , ce1# = v il and ce2= v ih , t ck = t ck min., bl = continuous, i out =0ma ?15?tbdma
october 5, 2004 cosmoram_00_a0 cosmoram 134 preliminary ac characteristics (under recommended operating conditions unless otherwise noted) read operation notes: 1. maximum value is applicable if ce#1 is kept at low without change of address input of a3 to a21. 2. address should not be changed within minimum t rc . 3. the output load 50pf with 50ohm termination to v dd *0.5 v. parameter symbol 32m 64m unit notes min. max. min. max. read cycle time t rc 70 1000 70 1000 ns 1, 2 ce1# access time t ce ? 70 ? 70 ns 3 oe# access time t oe ? 40 ? 40 ns 3 address access time t aa ? 70 ? 70 ns 3, 5 adv# access time t av 70 70 ns 3 lb# / ub# access time t ba ? 30 ? 30 ns 3 page address access time t paa ? 20 ? 20 ns 3,6 page read cycle time t prc 20 1000 20 1000 ns 1, 6, 7 output data hold time t oh 5 ? 5 ? ns 3 ce1# low to output low-z t clz 5 ? 5 ? ns 4 oe# low to output low-z t olz 10 ? 0 ? ns 4 lb# / ub# low to output low-z t blz 0 ? 0 ? ns 4 ce1# high to output high-z t chz ? 20 ? 20 ns 3 oe# high to output high-z t ohz ? 20 ? 20 ns 3 lb# / ub# high to output high-z t bhz ? 20 ? 20 ns 3 address setup time to ce1# low t asc ?5 ? ?5 ? ns address setup time to oe# low t aso 10 ? 10 ? ns adv# low pulse width t vpl 10 ? 10 ? ns 8 adv# high pulse width t vph 15 ? 15 ? ns 8 address setup time to adv high t asv 5 ? 5 ? ns address hold time from adv# high t ahv 10 ? 5 ? ns address invalid time t ax ? 10 ? 10 ns 5, 9 address hold time from ce1# high t chah ?5 ? ?5 ? ns 10 address hold time from oe# high t ohah ?5 ? ?5 ? ns 10 we# high to oe# low time for read t whol 15 1000 25 1000 ns 11 ce1# high pulse width t cp 15 ? 15 ? ns
135 cosmoram cosmoram_00_a0 october 5, 2004 preliminary 4. the output load 5pf without any other load. 5. applicable to a3 to a21 when ce1# is kept at low. 6. applicable only to a0, a1 and a2 when ce1# is kept at low for the page address access. 7. in case page read cycle is continued with keeping ce1# stays low, ce1# must be brought to high within 4s. in other words, page read cycle must be closed within 4s. 8. t vpl is specified from the negative edge of either ce1# or adv# whichever comes late. the sum of t vpl and t vph must be equal or greater than trc for each access. 9. applicable to address access when at least two of address inputs are switched from previous state. 10. t rc (min) and t prc (min) must be satisfied. 11. if actual value of t whol is shorter than specified minimum values, the actual t aa of following read may become longer by the amount of subtracting actual value from specified minimum value.
october 5, 2004 cosmoram_00_a0 cosmoram 136 preliminary write operation notes: 1. maximum value is applicable if ce1# is kept at low without any address change. 2. minimum value must be equal or greater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wr ). 3. write pulse is defined from high to low transition of ce1#, we#, or lb# / ub#, whichever occurs last. 4. t vpl is specified from the negative edge of either ce#1 or adv# whichever comes late. the sum of t vpl and t vph must be equal or greater than t wc for each access. 5. applicable for byte mask only. byte mask setup time is defined to the high to low transition of ce1# or we# whichever occurs last. 6. applicable for byte mask only. byte mask hold time is defined from the low to high transition of ce1# or we# whichever occurs first. 7. write recovery is defined from low to high transition of ce1#, we#, or lb# / ub#, whichever occurs first. 8. if oe# is low after minimum t ohcl , read cycle is initiated. in other words, oe# must be brought to high within 5ns after ce1# is brought to low. once read cycle is initiated, new write pulse should be input after minimum t rc is met. 9. if oe# is low after new address input, read cycle is initiated. in other word, oe# must be brought to high at the same time or before new address valid. once read cycle is init iated, new write pulse should be input after minimum t rc is met and data bus is in high-z. parameter symbol 32m 64m unit notes min. max. min. max. write cycle time t wc 70 1000 70 1000 ns 1, 2 address setup time t as 0 ? 0 ? ns 3 adv# low pulse width t vpl 10 ? 10 ? ns 4 adv# high pulse width t vph 15 ? 15 ? ns address setup time to adv# high t asv 5 ? 5 ? ns address hold time from adv# high t ahv 10 ? 5 ? ns ce1# write pulse width t cw 45 ? 45 ? ns 3 we# write pulse width t wp 45 ? 45 ? ns 3 lb# / ub# write pulse width t bw 45 ? 45 ? ns 3 lb# / ub# byte mask setup time t bs -5 ? -5 ? ns 5 lb# / ub# byte mask hold time t bh -5 ? -5 ? ns 6 ce1# write recovery time t wrc 15 ? 15 ? ns 7 write recovery time t wr 15 1000 15 1000 ns 7 ce1# high pulse width t cp 15 ? 15 ? ns we# high pulse width t whp 15 1000 15 1000 ns lb# / ub# high pulse width t bhp 15 1000 15 1000 ns data setup time t ds 15 ? 15 ? ns data hold time t dh 0 ? 0 ? ns oe# high to ce1# low setup time for write t ohcl -5 ? -5 ? ns 8 oe# high to address setup time for write t oes 0 ? 0 ? ns 9 lb# / ub# write pulse overlap t bwo 30 ? 30 ? ns
137 cosmoram cosmoram_00_a0 october 5, 2004 preliminary synchronous operation - clock input (burst mode) notes: 1. clock period is defined between valid clock edges. 2. clock rise/fall time is defined between v ih min. and v il max. synchronous operation - address latch (burst mode) notes: 1. t ascl is applicable if ce1# is brought to low after adv# is brought to low. 2. t asvl is applicable if adv# is brought to low after ce1# is brought to low. 3. t vpl is specified from the negative edge of either ce1# or adv# whichever comes late. 4. applicable to the 1st valid clock edge. parameter symbol 32m 64m unit notes min. max. min. max. clock period rl = 6 t ck n/a 13 ? ns 1 rl = 5 15 ? 15 ? ns rl = 4 20 ? 18 ? ns rl = 3 30 ? 30 ns clock high time t ckh 5 ? 4 ? ns clock low time t ckl 5 ? 4 ? ns clock rise/fall time t ckt ? 3 ? 3 ns 2 parameter symbol 32m 64m unit notes min. max. min. max. address setup time to adv# low t asvl -5 ? -5 ? ns 1 address setup time to ce1# low t ascl -5 ? -5 ? ns 2 address hold time from adv# high t ahv 10 ? 5 ? ns adv# low pulse width t vpl 10 ? 10 ? ns 3 adv# low setup time to clk rl = 6, 5 t vsck 7 ? 5 ? ns 4 rl = 4, 3 ? 7 ? ns 4 ce1 low setup time to clk rl = 6, 5 t clck 7 ? 5 ? ns 4 rl = 4, 3 ? 7 ? ns 4 adv# low hold time from clk t ckvh 1 ? 1 ? ns 4 burst end adv# high hold time from clk t vhvl 15 ? 13 ? ns
october 5, 2004 cosmoram_00_a0 cosmoram 138 preliminary synchronous read operation (burst mode) notes: 1. the output load 50pf with 50ohm termination to v dd *0.5 v. 2. wait# drives high at the beginning depending on oe# falling edge timing. 3. t cktv is guaranteed after t oltl (max) from oe# falling edge and t osck must be satisfied. 4. the output load is 5pf without any other load. 5. once they are determined, they must not be changed until the end of burst. 6. defined from the low to high transition of ce1# to the high to low transition of either adv# or ce1# whichever occurs late. parameter symbol 32m 64m unit notes min. max. min. max. burst read cycle time t rcb ? 8000 ? 4000 ns clk access time rl = 6, 5 t ac ? 12 ? 10 ns 1 rl = 4, 3 ? 12 ns 1 output hold time from clk t ckqx 3 ? 3 ? ns 1 ce1# low to wait# low t cltl 5 20 5 20 ns 1 oe# low to wait# low t oltl 0 20 0 20 ns 1, 2 adv# low to wait# low t vltl n/a 0 20 ns 1 clk to wait# valid time t cktv ? 12 ? 10 ns 1, 3 wait# valid hold time from clk t cktx 3 ? 3 ? ns 1 ce1# low to output low-z t clz 5 ? 5 ? ns 4 oe# low to output low-z t olz 10 ? 10 ? ns 4 lb#, ub# low to output low-z t blz 0 ? 0 ? ns 4 ce1# high to output high-z t chz ? 14 ? 20 ns 1 oe# high to output high-z t ohz ? 14 ? 20 ns 1 lb#, ub# high to output high-z t bhz ? 14 ? 20 ns 1 ce1# high to wait high-z t chtz ? 20 ? 20 ns 1 oe# high to wait high-z t ohtz ? 20 ? 20 ns 1 oe# low setup time to 1st data-out t olq 30 ? 30 ? ns ub#, lb# setup time to 1st data-out t blq 30 ? 26 ? ns 5 oe# setup time to clk t osck 5 ? 5 ? ns oe# hold time from clk t ckoh 5 ? 5 ? ns burst end ce1# low hold time from clk t ckclh 5 ? 5 ? ns burst end ub#, lb# hold time from clk t ckbh 5 ? 5 ? ns burst terminate recovery time bl=8, 16 t trb 30 ? 26 ? ns 6 bl=continuous 70 ? 70 ? ns 6
139 cosmoram cosmoram_00_a0 october 5, 2004 preliminary synchronous write operation (burst mode) notes: 1. defined from the valid input edge to the high to low transition of either adv#, ce1#, or we#, whichever occurs last. and once they are determined, they must not be changed until the end of burst. 2. the output load 50pf with 50ohm termination to v dd *0.5 v. 3. defined from the valid clock edge where last data-in being latched at the end of burst write to the high to low transition of either adv# or ce1# whichever occurs late for the next access. 4. defined from the low to high transition of ce1# to the high to low transition of either adv# or ce1# whichever occurs late for the next access. parameter symbol 32m 64m unit notes min. max. min. max. burst write cycle time t wcb ? 8000 ? 4000 ns data setup time to clock t dsck 7 ? 5 ? ns data hold time from clk t dhck 3 ? 3 ? ns we# low setup time to 1st data in t wld 30 ? 30 ? ns ub#, lb# setup time for write t bs -5 ? -5 ? ns 1 we# setup time to clk t wsck 5 ? 5 ? ns we# hold time from clk t ckwh 5 ? 5 ? ns ce1# low to wait# high t clth 5 20 5 20 ns 2 we# low to wait# high t wlth 0 20 0 20 ns 2 ce1# high to wait# high-z t chtz ? 20 ? 20 ns 2 we# high to wait# high-z t whtz ? 20 ? 20 ns 2 burst end ce1# low hold time from clk t ckclh 5 ? 5 ? ns burst end ce1# high setup time to next clk t chck 5 ? 5 ? ns burst end ub#, lb# hold time from clk t ckbh 5 ? 5 ? ns burst write recovery time t wrb 30 26 ns burst terminate recovery time bl=8, 16 t trb 30 ? 26 ? ns 3 bl=continuous t trb 70 ? 70 ? ns 4
october 5, 2004 cosmoram_00_a0 cosmoram 140 preliminary power down parameters notes: 1. applicable when rp=0 (reset to page mode). rp (reset to page) mode is available only for 64m. 2. applicable also to power-up. 3. applicable when partial mode is set. other timing parameters notes: 1. some data might be written into any address location if t chwx (min) is not satisfied. 2. except for clock input transition time. 3. the input transition time (t t ) at ac testing is 5ns for asynchronous operation and 3ns for synchronous operation respectively. if actual t t is longer than 5ns or 3ns specified as ac test condition, it may violate ac specification of some timing parameters. see the " ac test conditions " section ac test conditions parameter symbol 32m 64m unit notes min. max. min. max. ce2 low setup time for power down entry t csp 20 ? 10 ? ns ce2 low hold time after power down entry t c2lp 70 ? 70 ? ns ce2 low hold time for reset to asynchronous mode t c2lpr n/a 50 ? s 1 ce1# high hold time following ce2 high after power down exit [sleep mode only] t chh 300 ? 300 ? s 2 ce1# high hold time following ce2 high after power down exit [not in sleep mode] t chhp 70 ? 70 ? s 3 ce1# high setup time following ce2 high after power down exit t chs 0 ? 0 ? ns 2 parameter symbol 32m 64m unit notes min. max. min. max. ce1 high to oe invalid time for standby entry t chox 10 ? 10 ? ns ce1 high to we invalid time for standby entry t chwx 10 ? 10 ? ns 1 ce2 low hold time after power-up t c2lh 50 ? 50 ? s ce1 high hold time following ce2 high after power-up t chh 300 ? 300 ? s input transition time t t 1 25 1 25 ns 2 symbol description te s t s e t u p value unit note v ih input high level v dd * 0.8 v v il input low level v dd * 0.2 v v ref input timing measurement level v dd * 0.5 v t t input transition time async. between v il and v ih 5 ns sync. 3 ns
141 cosmoram cosmoram_00_a0 october 5, 2004 preliminary ac measurement output load circuit figure 49. output load circuit device under test v dd v dd *0.5v v ss out 0.1 f 50pf 50ohm
october 5, 2004 cosmoram_00_a0 cosmoram 142 preliminary timing diagrams note: this timing diagram assumes ce2=h and we#=h. note: this timing diagram assumes ce2=h and we#=h. figure 50. asynchronous read timing #1-1 (basic timing) figure 51. asynchronous read timing #1-2 (basic timing) t ce valid data output address ce1# dq (output) oe# t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz t oe t ba t blz adv# low lb# / ub# t ce valid data output address ce1# dq (output) oe# t chz t rc t olz t cp t asc t asc t ohz t oh t bhz t oe t ba t blz adv# address valid t ahv t vpl t av lb# / ub#
143 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assume s ce2=h, adv#=l and we#=h. note: this timing diagram assume s ce2=h, adv#=l and we#=h. figure 52. asynchronous read timing #2 (oe# & address access) figure 53. asynchronous read timing #3 (lb# / ub# byte access) t aa valid data output address ce1# dq (output) t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe# t ax low t aa t ohah t aso lb# / ub# t aa valid data output address dq1-8 (output) ub# t bhz t ba t rc t blz address valid valid data output t bhz t oh lb# t ax low t ba t ax dq9-16 (output) t blz t ba t blz t oh t bhz t oh valid data output ce1#, oe#
october 5, 2004 cosmoram_00_a0 cosmoram 144 preliminary note: this timing diagram assumes ce2=h and we#=h. notes: 1. this timing diagram assumes ce2=h, adv#=l and we#=h. 2. either or both lb# and ub# must be low when both ce1# and oe# are low. figure 54. asynchronous read timing #4 (page ad dress access after ce1# control access) figure 55. asynchronous read timing #5 (random and page address access) valid data output (normal access) address (a2-a0) ce1# dq (output) oe# t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t paa address (a21-a3) address valid t paa t oh t prc t paa t prc t oh address valid address valid t rc adv# t asc lb# / ub# valid data output (normal access) address (a2-a0) ce1# dq (output) oe# t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa address (a21-a3) address valid t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso lb# / ub#
145 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assumes ce2=h and adv#=l. note: this timing diagram assumes ce2=h. figure 56. asynchronous write timing #1-1 (basic timing) figure 57. asynchronous write timing #1-2 (basic timing) t as valid data input address ce1# dq (input) we# t dh t ds t wc t wrc t wp t cw t as t bw address valid t as t as t br oe# t ohcl t as t as t wr adv# low lb#, ub# t as valid data input a ddress ce1# dq (input) we# t dh t ds t wc t wrc t wp t cw t as t bw address valid t as t as t br oe# t ohcl t as t as t wr adv# t vpl t ahv lb#, ub#
october 5, 2004 cosmoram_00_a0 cosmoram 146 preliminary note: this timing diagram assumes ce2=h and adv#=l. note: this timing diagram assume s ce2=h, adv#=l and oe#=h. figure 58. asynchronous write timing #2 (we# control) figure 59. asynchronous write timing #3-1 (we# / lb# / ub# byte write control) t as address we# ce1# t wc t wr t wp address valid t as t wr t wp valid data input dq (input) t dh t ds oe# t oes t ohz t wc valid data input t dh t ds low address valid t ohah ub#, lb# t as a ddress we# ce1# t wc t br t wp lb# address valid t as t br t wp valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh
147 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assume s ce2=h, adv#=l and oe#=h. note: this timing diagram assume s ce2=h, adv#=l and oe#=h. figure 60. asynchronous write timing #3-2 (we# / lb# / ub# byte write control) figure 61. asynchronous write timing #3-3 (we# / lb# / ub# byte write control) t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t as a ddress we# ce1# t wc t br t bw lb# address valid t as t br t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh
october 5, 2004 cosmoram_00_a0 cosmoram 148 preliminary note: this timing diagram assume s ce2=h, adv#=l and oe#=h. notes: 1. this timing diagram assumes ce2=h and adv#=l. 2. write address is valid from either ce1# or we# of last falling edge. figure 62. asynchronous write timing #3-4 (we# / lb# / ub# byte write control) figure 63. asynchronous read / write timing #1-1 (ce1# control) t as a ddress we# ce1# t wc t br t bw lb# address valid t as t br t bw dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t dh t ds t as t br t bw t as t br t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo read data output address ce1# dq we# t wc t cw oe# t ohcl t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wrc t chah t dh t clz t oh ub#, lb#
149 cosmoram cosmoram_00_a0 october 5, 2004 preliminary notes: 1. this timing diagram assumes ce2=h and adv#=l. 2. oe# can be fixed low during write operation if it is ce1# controlled write at read-write-read sequence. notes: 1. this timing diagram assumes ce2=h and adv#=l. 2. ce1# can be tied to low for we# and oe# controlled operation. figure 64. asynchronous read / write timing #1-2 (ce1# / we# / oe# control) figure 65. asynchronous read / write timing #2 (oe#, we# control) read data output address ce1# dq we# t wc t wp oe t ohcl t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output ub#, lb# read data output address ce1# dq we# t wc t wp oe# t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah ub#, lb#
october 5, 2004 cosmoram_00_a0 cosmoram 150 preliminary notes: 1. this timing diagram assumes ce2=h and adv#=l. 2. ce1# can be tied to low for we# and oe# controlled operation. notes: 1. stable clock input must be required during ce1#=l. 2. t ck is defined between valid clock edges. 3. t ckt is defined between v ih min. and v il max figure 66. asynchronous read / write timing #3 (oe,# we#, lb#, ub# control) figure 67. clock input timing read data output a ddress ce1# dq we# t wc t bw oe# t ba write address t as t rc write data input t ds t bhz t oh t aa read address t br t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes ub#, lb# clk t ck t ckh t ckl t ckt t ckt t ck
151 cosmoram cosmoram_00_a0 october 5, 2004 preliminary notes: 1. case #1 is the timing when ce1# is brought to low after adv# is brought to low. case #2 is the timing when adv# is brought to low after ce1# is brought to low. 2. t vpl is specified from the negative edge of either ce1# or adv# whichever comes late. at least one valid clock edge must be input during adv#=l. 3. t vsck and t clck are applied to the 1st valid clock edge during adv#=l. figure 68. address latch timing (synchronous mode) clk adv# a ddress ce 1# t ahv t vpl t asvl valid case #1 case #2 t vsck t ahv t vpl t vlcl valid t vsck t clck t ascl low t ckvh t ckvh
october 5, 2004 cosmoram_00_a0 cosmoram 152 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 69. 32m synchronous read timing #1 (oe# control) adv# dq we# oe# valid t asvl t ahv t vpl t clck t ascl wait# q 1 t olq t ac t ckqx t oltl t ac t cktv high q bl high-z rl=5 t vsck t ohtz t olz t ac t ckqx t ohz t rcb t ckoh t cktv valid t vsck t clck t cp t vpl t vhvl high-z t blq t ckbh t ascl t asvl t cktx t cktx t ckvh t ckvh ce1# lb#, ub# address clk
153 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 70. 32m synchronous read timing #2 (ce1# control) addr e ss adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl t clck t ascl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t vsck t clck t cp t vpl t vhvl t cltl high t clz t ckclh t ascl t ahv q bl t chtz t clz t ckqx t chz t cktv t cltl t ckbh t asvl t cktx t cktx t ckvh t ckvh
october 5, 2004 cosmoram_00_a0 cosmoram 154 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 71. 32m synchronous read timing #3 (adv# control) address adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t asvl t vsck t vpl t vhvl high t ahv q bl t ckqx t cktv low low t cktx t cktx t ckvh t ckvh
155 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 72. synchronous read - wait# output timing (continuous read) xxx7fh t asvl t ahv t vpl t clck t ascl q 1 t olq t ac t ckqx t oltl t ac t cktv high high-z rl=5 t vsck t olz t cktv high-z q 2 t ckqx q 3 t ckqx t ac t ac t cktv t ac t blq t cktx t cktx t cktx t ckvh clk address adv# ce1# oe# we# lb#, ub# wait# dq
october 5, 2004 cosmoram_00_a0 cosmoram 156 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 73. 64m synchronous read timing #1 (oe# control) t ahv address adv# dq we# oe# clk valid ce1# t asvl t vpl t clck t ascl wait# q 1 t olq t ac t ckqx t oltl t ac t cktv high q bl high-z rl=5 t vsck t ohtz t olz t ac t ckqx t ohz t rcb t ckoh valid t vsck t clck t cp t vpl t vhvl high-z t blq t ckbh t ascl t asvl t cktx t ckvh t ckvh lb#, ub#
157 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 74. 64m synchronous read timing #2 (ce1# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t vsck t clck t cp t vpl t vhvl t cltl high t clz t ckclh t ascl t ahv q bl t chtz t clz t ckqx t chz t cltl t ckbh t asvl t cktx t ckvh t ckvh lb#, ub#
october 5, 2004 cosmoram_00_a0 cosmoram 158 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 75. 64m synchronous read timing #3 (adv# control) addr es s adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t asvl t vsck t vpl t vhvl high t ahv q bl t ckqx low low t cktx t vltl t vltl t ckvh t ckvh
159 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 76. synchronous write timing #1 (we# level control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckwh t wld valid t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t ckvh t ckvh t asvl lb#, ub#
october 5, 2004 cosmoram_00_a0 cosmoram 160 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 77. synchronous write timing #2 (we# single clock pulse control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckclh valid t asvl t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t chtz t wlth t wsck t ckwh t ckwh t wsck t ckvh t ckvh lb#, ub#
161 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 78. synchronous write timing #3 (adv# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl wait# high rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb valid t asvl t ahv t vpl t vsck t bs t wrb t vsck t vhvl t ckbh high t ckvh t ckvh lb#, ub#
october 5, 2004 cosmoram_00_a0 cosmoram 162 preliminary notes: 1. this timing diagram assumes ce2=h, the valid clock edge on rising edge and single write operation. 2. write data is latched on the valid clock edge. figure 79. synchronous write timing #4 (we# level control, single write) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 t dhck t dsck t wcb t ckwh t wld valid t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t wlth t ckvh t ckvh t asvl lb#, ub#
163 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 80. 32m synchronous read to write timing #1(ce1# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# t vsck t bs t cp rl=5 d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t chtz t ac t ckqx t chz t ckqx t ckclh t ckclh t cktv t vhvl t ckbh t ckbh t cktx t wcb t ckvh t clth lb#, ub#
october 5, 2004 cosmoram_00_a0 cosmoram 164 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 81. 32m synchronous read to write timing #2(adv# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl wait# t vsck t bs rl=5 t ckwh d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t ohtz t ac t ckqx t ohz t ckqx t wld t ckoh t cktv t vhvl t ckbh t ckbh t cktx t ckvh t wlth lb#, ub#
165 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 82. 64m synchronous read to write timing #1(ce1# control) addr ess adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl t clck t ascl wait# t vsck t bs t cp rl=5 d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t chtz t ac t ckqx t chz t ckqx t ckclh t ckclh t vhvl t ckbh t ckbh t wcb t clth t ckvh
october 5, 2004 cosmoram_00_a0 cosmoram 166 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 83. 64m synchronous read to write timing #2(adv# control) addr es s adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl wait# t bs rl=5 t ckwh d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t ohtz t ac t ckqx t ohz t ckqx t wld t ckoh t vhvl t ckbh t ckbh t wlth t ckvh t vsck
167 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 84. synchronous write to read timing #1 (ce1# control) d bl address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t ckt t clck t ascl wait# t vsck t cp rl=5 t ckclh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t cltl t clz t wrb t ckbh t cktx t ckvh t chtz high-z lb#, ub#
october 5, 2004 cosmoram_00_a0 cosmoram 168 preliminary note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 85. synchronous write to read timing #2 (adv# control) d bl address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t ckt wait# low t vsck rl=5 t ckwh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t oltl t olz t olq t wrb t blq t ckbh t cktx t ckvh t whtz high-z lb#, ub#
169 cosmoram cosmoram_00_a0 october 5, 2004 preliminary note: the t c2lh specifies after v dd reaches specified minimum level. note: the t chh specifies after v dd reaches specified minimum level and applicable to both ce1# and ce2. note: this power down mode can be also used as a reset timi ng if the power-up timing above could not be satisfied and power-down program was not performed prior to this reset. figure 86. power-up timing #1 figure 87. power-up timing #2 figure 88. power down entry and exit timing t c2lh ce1# v dd v dd min 0v ce2 t chh t chs ce1# v dd v dd min 0v ce2 t chh t csp ce1# power down entry ce2 t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z
october 5, 2004 cosmoram_00_a0 cosmoram 170 preliminary note: both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce1# low to high transition. notes: 1. the all address inputs must be high from cycle #1 to #5. 2. the address key must confirm the format specified in the " functional description " section. if not, the operation and data are not guaranteed. 3. after t cp or t rc following cycle #6, the configuration register set is completed and returned to the normal operation. t cp and t rc are applicable to returning to asynchronous mode and to synchronous mode respectively. 4. byte read or write is available in addition to word read or write. at least one byte control signal (lb# or ub#) need to be low. figure 89. standby entry timing after read or write figure 90. configuration register set timing #1 (asynchronous operation) t chox ce1# oe# we# active (read) standby active (write) standby t chwx address ce1# dq* 3 we# t rc oe# rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb t cp * 3 (t rc ) lb#, ub#
171 cosmoram cosmoram_00_a0 october 5, 2004 preliminary notes: 1. the all address inputs must be high from cycle #1 to #5. 2. the address key must confirm the format specified in the " functional description " section. if not, the operation and data are not guaranteed. 3. after t trb following cycle #6, the configuration register set is completed and returned to the normal operation. 4. byte read or write is available in addition to word read or write. at least one byte control signal (lb# or ub#) need to be low. figure 91. configuration register set timing #2 (synchronous operation) address adv# dq we# oe# clk ce1# wait# rda msb rda msb rda msb x msb x msb rdb key t rcb t wcb t wcb t wcb t wcb t rcb t trb t trb t trb t trb t trb cycle#1 cycle#2 cycle#3 cycle#4 cycle#5 cycle#6 t trb rl rl-1 rl-1 rl-1 rl-1 rl lb#, ub#
october 27, 2004 s71ws256/128/064j_csa0 revision summary 172 advance information colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above-men- tioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au- thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion llc. spansion llc reserves the right to change or di scontinue work on any product without notice. the information in this document is provided as is? without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose , merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damage s of any kind arising out of the use of the information in this document. copyright ? 2004 spansion llc. all rights reserved. spansion, the spansion logo, mirrorbit, combinations thereof, and expressfl ash are trademarks of span- sion llc. other company and product names used in this publication are for identification purposes only and may be trademarks o f their respective compa- nies. revision summary revision a (october 27, 2004) initial release.

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