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w19b160bt/b data sheet publication release date:apr. /20/2009 - 1 - revision a9 -table of contents- 1. general des cription ......................................................................................................... 4 2. features ....................................................................................................................... .......... 4 3. pin configura tions ............................................................................................................ 6 4. block di agram .................................................................................................................. .... 7 5. pin descri ption................................................................................................................ ..... 8 6. functional des cription ................................................................................................... 9 6.1 device bus o peration............................................................................................ 9 6.1.1 word/byte conf iguratio n ..................................................................................................9 6.1.2 reading arra y data ..........................................................................................................9 6.1.3 writing commands/c ommand s equences .......................................................................9 6.1.4 program and erase o peration st atus...............................................................................9 6.1.5 standby m ode ..................................................................................................................9 6.1.6 automatic sl eep mode ...................................................................................................10 6.1.7 #reset: hardware reset pi n........................................................................................10 6.1.8 output disabl e mode ......................................................................................................10 6.1.9 auto-selec t mode ............................................................................................................10 6.1.10 sector protection and un-protect ion.............................................................................11 6.1.11 temporary sector unprot ect ........................................................................................11 6.1.12 hardware data protecti on ............................................................................................11 6.1.13 write pulse ?glitch ? protec tion .....................................................................................11 6.1.14 logical inhi bit ...............................................................................................................1 1 6.1.15 power-up write inhibi t..................................................................................................11 6.2 command defini tions ........................................................................................... 12 6.2.1 reading arra y data ........................................................................................................12 6.2.2 reset co mmand .............................................................................................................12 6.2.3 auto-select co mmand sequenc e ...................................................................................12 6.2.4 byte/word program command s equence ......................................................................13 6.2.5 chip erase co mmand sequenc e ...................................................................................13 6.2.6 sector erase co mmand sequenc e ................................................................................13 6.2.7 unlock bypass co mmand sequenc e .............................................................................14 6.3 write operatio n stat us..................................................................................... 14 6.3.1 dq7: #data polling .........................................................................................................14 6.3.2 ry/#by: ready /#busy ...................................................................................................15 6.3.3 dq6: toggl e bit ..............................................................................................................15
w19b160bt/b data sheet - 2 - 6.3.4 reading toggle bits dq6/dq 2 ......................................................................................15 6.3.5 dq3: sector er ase time r ...............................................................................................16 6.3.6 dq5 : exceeded ti ming limi ts .......................................................................................16 7. special charact eristic .................................................................................................. 16 8. table of operat ion mode s ............................................................................................ 17 8.1 device bus o perati ons ................................................................................................. 17 8.2 sector address table (top boot block) ....................................................................... 18 8.3 sector address table (b ottom boot block) .................................................................. 19 8.4 cfi query identific ation st ring...................................................................................... 20 8.5 system interf ace stri ng ................................................................................................ 20 8.6 device geometry defini tion .......................................................................................... 21 8.7 primary vendor-specific extended q uery.................................................................... 22 8.8 command defi nitions ................................................................................................... 23 8.9 write operati on status ................................................................................................. 24 8.10 temporary sector u nprotect al gorithm ........................................................................ 25 8.11 in-system sector protec t/unprotect al gorithms ........................................................... 26 8.12 program al gorithm ........................................................................................................ 27 8.13 erase algorithm (polli ng) .............................................................................................. 27 8.14 erase algorithm (toggl e).............................................................................................. 28 8.15 data polling algorithm .................................................................................................. 29 8.16 toggle bit al gorithm ..................................................................................................... 30 9. electrical chara cteristi cs......................................................................................... 31 9.1 absolute maxi mum rati ngs .......................................................................................... 31 9.2 operating ranges ......................................................................................................... 31 9.3 dc character istics.............................................................................................. 32 9.4 ac character istics.............................................................................................. 33 9.4.1 test condi tion ................................................................................................................3 3 9.4.2 ac test load and wavefo rms .......................................................................................33 9.4.3 read-only o perati ons....................................................................................................34 9.4.4 read-only o perati ons....................................................................................................34 9.4.5 hardware rese t (#reset ) ............................................................................................35 9.4.6 word/byte configur ation (# byte) ..................................................................................35 9.4.7 erase and program operatio n........................................................................................36 9.4.8 temporary sector unprot ect ..........................................................................................36 9.4.9 alternate #ce controlled eras e and program o peratio n ...............................................37 10. timing w aveforms ............................................................................................................. 38 10.1 ac read wa veform ...................................................................................................... 38
w19b160bt/b data sheet publication release date apr,20, 2009 - 3 - revision a9 10.2 reset wave form ........................................................................................................... 38 10.3 #byte waveform for read operat ion ......................................................................... 39 10.4 #byte waveform for write oper ation ......................................................................... 39 10.5 programming wa veform............................................................................................... 40 10.6 chip/sector eras e wavefo rm ....................................................................................... 40 10.7 #data polling waveform (d uring embedded al gorithm s) ............................................ 41 10.8 toggle bit waveform (dur ing embedded algor ithms) ................................................. 41 10.9 temporary sector unpr otect timing diagram .............................................................. 42 10.10 sector protect and unpr otect timing diagram ........................................................ 42 10.11 alternate #ce controlled write (era se/program) oper ation ti ming ....................... 43 11. latchup charact eristics .............................................................................................. 44 12. capacit ance.................................................................................................................... ..... 44 13. ordering info rmation .................................................................................................... 45 device number/description 7 : 70 ~ 79ns 9 : 90 ~ 99ns speedoption t = top sector b = bottom sector boot code sector architecture t = 48 - pin tsop package, 12 x 20mm package type : h: extended ( - m:industrial ( 40 ~85 )with green package quality grade & green ~85 )with green package -20 w19b160b 16 megabit (2m x 8 - bit/ 1 m x 16 - bit) cmos flash memory package dime nsio ns ............................................................................................................. ........ 45 package dime nsio ns ............................................................................................................. ........ 46 14. version hi story ................................................................................................................ .47
w19b160bt/b data sheet - 4 - 1. general description the w19b160b is a 16mbit, 2.7~3.6 volt cmos flash memory organized as 2m 8 or 1m 16 bits. for flexible erase capability, the 16mbits of data are divided into one 16kbyte, two 8kbyte, one 32kbyte, and thirty-one 64kbyte sectors. the word-wide ( 16) data appears on dq15-dq0, and byte-wide ( 8) data appears on dq7 ? dq0. the device can be programmed and erased in-system with a standard 2.7~3.6v power supply. a 12-volt v pp is not required. the unique cell architecture of the w19b160b results in fast program/erase operati ons with extremely low current consumption. the device can also be programmed and erased by using standard eprom programmers. 2. features performance ? 2.7~3.6-volt write (progr am and erase) operations ? fast write operation ? sector erase time: 0.7s (typical) ? chip erases time: 25 s (typical) ? byte/word programming time: 5/7 s (typical) ? read access time: 70 ns ? typical program/erase cycles: ? 100k ? twenty-year data retention ? ultra low power consumption ? active current (read): 9ma (typical) ? active current (program/erase): 20ma (typical) ? standby current: 0.2 a (typical) architecture ? sector erases architecture ? one 16kbyte, two 8kbyte, one 32kby te, and thirty-one 64kbyte sectors ? top or bottom boot block configurations available ? supports full chip erase ? jedec standard byte-wide and word-w ide pin-outs ttl compatible i/o ? manufactured on winstack-s 0.13m process technology ? available packages: 48-pin tsop software features ? compatible with common flash memo ry interface (cfi) specification ? flash device parameters st ored directly on the device ? allows software driver to identify and use a vari ety of different current and future flash products ? end of program detection
w19b160bt/b data sheet publication release date apr,20, 2009 - 5 - revision a9 ? software method: toggle bit/data polling ? unlock bypass program command ? allows the system to program bytes or word s to device faster than standard program command. hardware features ? ready/#busy output (ry/#by) ? detect program or erase cycle completion ? hardware reset pin (#reset) ? reset the internal state machine to the read mode ? sector protection ? sectors can be locked in-system or via programmer ? temporary sector unprotect allows c hanging data in protected sectors in-system temperature range ? extended temperature range (-20 to 85 ) ? industrial devices ambient temperature(-40 to +85 )
w19b160bt/b data sheet - 6 - 3. pin configurations
w19b160bt/b data sheet publication release date apr,20, 2009 - 7 - revision a9 4. block diagram
w19b160bt/b data sheet - 8 - 5. pin description symbol pin name a0 ? a19 address inputs dq0 ? dq14 data inputs/outputs word mode dq15 is data inputs/outputs dq15/a-1 byte mode a-1 is address input #ce chip enable #oe output enable #we write enable #byte byte enable input #reset hardware reset ry/#by ready/busy status v dd power supply v ss ground nc no connection
w19b160bt/b data sheet publication release date apr,20, 2009 - 9 - revision a9 6. functional description 6.1 device bus operation 6.1.1 word/byte configuration the #byte pin controls the device data i/o pins operat e whether in the byte or word configuration. when the #byte pin is ?1?, the device is in word configuration; dq15-dq0 are active and controlled by #ce and #oe. when the #byte pin is ?0?, the device is in byte configuration, and only data i/o pins dq7-dq0 are active and controlled by #ce and #oe. the data i/o pins dq8-dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. 6.1.2 reading array data to read array data from the outputs, the #ce and #oe pins must be set to v il . #ce is the power control and used to select the device. #oe is the output control gates a rray data to the output pins. #we should stay at v ih . the #byte pin determines the device outputs a rray data whether in words or bytes. the internal state machine is set for reading a rray data when device power-up, or after hardware reset. this ensures that no excess modification of the memory content occurs during the power transition. in this mode there is no command nece ssary to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are changed. 6.1.3 writing commands/command sequences in writhing a command or command sequence (which includes programming data to the device and erasing sectors of memory), t he system must drive #we and #ce to v il , and #oe to v ih . for program operations, the #byte pin determines the device accepts program data whether in bytes or in words. refer to ?word/byte conf iguration? for more information. the erase operation can erase a sector, multiple se ctors, even the entire devic e. the ?sector address? is the address bits required to solely select a sector. 6.1.4 program and erase operation status during an erase or program operati on, the system may check the st atus of the operation by reading the status bits on dq7 ? dq0. refer to ?write o peration status? and ?ac char acteristics? for more information. 6.1.5 standby mode when the system is not reading or writing to the device, the device will be in a standby mode. in this mode, current consumption is greatly reduced, and the outputs are in the high impedance state, independent from the #oe input. when the #ce and #reset pins are both held at v dd
w19b160bt/b data sheet - 10 - held at v ih , but not within v dd 0.3v, the device will be in the st andby mode, but t he standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, bef ore it is ready to read data. when the device is deselected during erasing or progr amming, the device initiates active current until the operation is completed. 6.1.6 automatic sleep mode the automatic sleep mode minimizes device's energy consumption. when addresses remain stable for t acc +30 ns, the device will enable this mode aut omatically. the automatic sleep mode is independent from the #ce , #we , and #oe control signals. standard addre ss access timings provide new data when addresses are changed. in sleep mode, output data is latched and always available to the system. 6.1.7 #reset: hardware reset pin the #reset pin provides a hardware method to re set the device to reading array data. when the #reset pin is set to low for at least a period of t rp , the device will immediately terminate every operations in progress, tri-states all output pins , and ignores all read/write commands for the duration of the #reset pulse. the device also resets the internal state machine to reading array data mode. to ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to accept another command sequence. current is reduced for the duration of t he #reset pulse. when #reset is held at vss 0.3v, the device initiates the cm os standby current (i cc4 ). if #reset is held at v il but not within vss 0.3v, the standby current will be greater. the #reset pin may be tied to the system-reset circuitry. thus the system reset would also reset the device, enabling the system to read t he boot-up firmware from the device. if #reset is asserted during the progr am or erase operation, the ry/#by pin will be at ?0? (busy) until the internal reset operation is complete. if #reset is asserted when a program or erase operation is not processing (ry/#by pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). after the #reset pin returns to v ih , the system can read data t rh. 6.1.8 output disable mode when the #oe input is at v ih , output from the device is disabled. the output pins are set in the high impedance state. 6.1.9 auto-select mode the auto select mode offers manufacturer and device identification, as well as sector protection verification, through identifier codes output on dq7-dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the auto select codes can also be accessed in-system through the command register. when using programming equipment, the auto select mode requires v id (8.5 v to 11.5 v) on address pins a9. address pins a6, a1, and a0 must be as shown in auto select table. in addition, when verifying sector protection, t he sector address must appear on the appropriate highest order address bits. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7-dq0.
w19b160bt/b data sheet publication release date apr,20, 2009 - 11 - revision a9 to access the auto select codes in-system, t he host system can issue the auto select command through the command register. this method does not require v id . also refer to the auto select command sequence section for more information. 6.1.10 sector protection and un-protection the sector protection feature will disable both pr ogram and erase operations in any sectors. the sector un-protection feature will re-enables both progr am and erase operations in previously protected sectors. sector protection / un-protec tion can be implemented through two methods. the primary method requires v id on the #reset pin, and can be implemented either in-system or through programming equipment. this method uses standard microprocessor bus cycle timing. the alternate method intended only for programming equipment requires v id on address pin a9 and #oe it is possible to determine whether a sector is protected or unprotect ed. see the auto select mode section for details. 6.1.11 temporary sector unprotect this feature allows temporary un- protection of previously protect ed sectors to change data in-system. when the #reset pin is set to v id , the sector unprotect mode is activated. during this mode, formerly protected sectors can be programmed or er ased by selecting the sect or addresses. what if v id is removed from the #reset pin, all the prev iously protected sector s are protected again. 6.1.12 hardware data protection the command sequence requirements of unlock cycles for programming or erasing provides data protection against negligent writes. in addition, the following hardware data protection measures prevent inadvertent erasure or pr ogramming, which might be caused by spurious system level signals during v dd power-up and power-down transiti ons, or from system noise. 6.1.13 write pulse ?glitch? protection noise pulses, which is less than 5ns (typical) on #o e, #ce or #we, do not initiate a write cycle. 6.1.14 logical inhibit write cycles are inhibited by holding any one of #oe = v il , #ce = v ih or #we = v ih . #ce and #we must be a logical zero while #oe is a logical one to initiate a write cycle. 6.1.15 power-up write inhibit during power up, if #we = #ce = v il and #oe = v ih , the device does not accept commands on the rising edge of #we. the internal state machine is automatically reset to the read mode on power-up.
w19b160bt/b data sheet - 12 - 6.2 command definitions the device operation can be initiated by writi ng specific address and data commands or sequences into the command register. the device will be rese t to reading array data when writing incorrect address and data values or writing them in the improper sequence. the addresses will be latched on the falling edge of #we or #ce, whichever happens later; while the data will be latched on the rising edge of #we or #ce, whichever happens first. please refer to timing waveforms. 6.2.1 reading array data after device power-up, it is automatically set to reading array data. there is no commands are required to retrieve data. after completing an embedded program or embedded erase algorithm, the device is ready to read array data. the system must initiate the reset command to return the device to read mode if dq5 goes high during an active program or erase operation; otherwi se, the device is in the auto select mode. see reset command section and requirements for reading array data in the device bus operations section for more information. 6.2.2 reset command the device will be to the read when writing the re set command. for this command, the address bits are don?t care. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to whic h the system was writing to the read mode. once erasure begins, however, the device ignores re set commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device, to which the system was wr iting to the read mode. the reset command may be written between the sequence cycles in an auto select command sequence. when in the auto select mode, the reset command must be written to return to the read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode. 6.2.3 auto-select command sequence the auto select command sequence provides the hos t system to access the manufacturer and device codes, and determine whether a sector is protected or not. this is an alternative method, which is intended for prom programmers and requires v id on address pin a9. the auto select command sequence may be written to an address within the devic e that is in the read mode. when the device is actively programming or erasing, the auto select command may not be written. the first writing two unlock cycles initiate the auto select command sequence. this is followed by a third write cycle that contains the auto select command. the device then enters into the auto select mode. the system may read at any address without initiating another auto select command sequence: ? a read cycle at address xx00h re turns the manufacturer code. ? a read cycle at address xx01h in word mode (or xx02h in byte mode) returns the device code. ? a read cycle to an address containing a sector address (sa), and the address 02h on a7-a0 in word mode (or the address 04h in byte mode) returns 01h if the sector is protec ted, or 00h if it is unprotected.
w19b160bt/b data sheet publication release date apr,20, 2009 - 13 - revision a9 to return to read mode and exit the auto select mode, the system must write the reset command. 6.2.4 byte/word program command sequence the device can be programmed either by word or byte, which depending on the state of the #byte pin. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by t he program setup command. the program address and data are written next, which in turn initiate t he embedded program algorithm. the device automatically provides internally generated program pulses and verifies the programmed cell margin. once the embedded program algorithm is complete , the device then returns to the read mode and addresses are no longer latched. the system can det ermine the status of t he program operation by using dq7, dq6, or ry/#by. please refer to the write operation status section for bits' information. any commands written to the device duri ng the embedded program algorithm are ignored. please note that a hardware reset will immediately stop the program operation. the program command sequence should be reinitiated when the device has re turned to the read mode, in order to ensure data integrity. programming is allowed in any sequence and acro ss sector boundaries. a bit cannot be programmed from ?0? back to ?1.? if trying to do so may cause that device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate that the operation is successful. howeve r, a succeeding read will show that the data is still ?0.? only erase operations can change ?0? to ?1.? 6.2.5 chip erase command sequence chip erase is a six-bus cycle operation. writing tw o unlock cycles initiates the chip erase command sequence, which is followed by a set-up command. after chip erase command, two additional unlock write cycles are then followed, which in turn invokes the embedded erase algorithm. the system preprogram is not required prior to erase. befo re electrical erase, the embedded erase algorithm automatically preprograms and verifies the entire memo ry for an all zero data pattern. any controls or timings during these operations is not required in system. as the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase oper ation by using dq7, dq6, or ry/#by. please refer to the write operati on status section for info rmation on these status bits. any commands written during the chip erase operat ion will be ignored. however, a hardware reset shall terminate the erase operation immediately. if this happens, to ensure data integrity, the chip erase command sequence should be reinitiated when t he device has returned to reading array data. 6.2.6 sector erase command sequence sector erase is a six-bus cycle operation. writi ng two unlock cycles initiates the sector erase command sequence, which is followed by a set- up command. two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. the device does not require the system to preprogram before erase. before electrical erase, the embedded erase algorithm automatically programs and ve rifies the entire memory for an all zero data pattern. any controls or timings during t hese operations is not required in system.
w19b160bt/b data sheet - 14 - as the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. please refer to the wri te operation status section for information on these status bits. however, a hardware reset shall terminate the eras e operation immediately. if this occurs, to ensure data integrity, the sector erase command sequence should be reinitiated once the device has returned to reading array data. 6.2.7 unlock bypass command sequence the unlock bypass feature allows t he system to program bytes or words to the device faster than using the standard program command sequence. t he unlock bypass command sequence is initiated by first writing two unlock cycles. this is follow ed by a third write cycle containing the unlock bypass command, 20h. the device enters the unlock by pass command mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program co mmand, a0h; the second cycle contains the program address and data. additional data is progra mmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. command defini tions shows the requirements for the command sequence. during the unlock bypass mode, only the unlo ck bypass program and unlock by-pass reset commands are valid. to exit the unlock bypass mode, the system must iss ue the two-cycle unlock bypass reset command sequence. the first cycle mu st contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycles . the device then returns to reading array data. program/erase operation refer program al gorithm and erase algorithm illustration. 6.3 write operation status the device provides several bits to determine the st atus of a program or er ase operation: dq5, dq6, and dq7. each of dq7 and dq6 provides a met hod for determining whether a program or erase operation is complete or in progress. the device also offers a hardware-based output signal, ry/#by, to determine whether an embedded program or er ase operation is in progress or has been completed. 6.3.1 dq7: #data polling the #data polling bit, dq7, indicates whether an embedded program or erase algorithm is in progress or completed. data polling is valid after the rising edge of the final #we pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 and the complement of the data programmed to dq7. when the embedded program al gorithm is complete, the device outputs the data programmed to dq7. the system must prov ide the program address to read valid status information on dq7. if a program address falls with in a protected sector, #data polling on dq7 is active for about 1 s, and then the device returns to the read mode. during the embedded erase algorithm, #data po lling produces ?0? on dq7.once the embedded erase algorithm has completed, #data polling produc es ?1? on dq7. an address within any of the sectors selected for erasure must be provided to read valid status information on dq7.
w19b160bt/b data sheet publication release date apr,20, 2009 - 15 - revision a9 after an erase command sequence is written, if all se ctors selected for erasi ng are protected, #data polling on dq7 is active for about 100 s, and then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if t he system reads dq7 at an address within a protected sector, the status may not be valid. just before the completion of an embedded pr ogram or erase operation, dq7 may change asynchronously with dq0-dq6 while output enable (#oe) is set to low. that is, the device may change from providing status information to va lid data on dq7. depending on when it samples the dq7 output, the system may read the status or va lid data. even if the dev ice has completed the program or erase operation and dq7 has valid data, the data outputs on dq0-dq6 may be still invalid. valid data on dq7-dq0 will appear on successive read cycles. 6.3.2 ry/#by: ready/#busy the ry/#by is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/#by status is valid after the rising edge of the final #we pulse in the command sequence. since ry/#by is an open-drain output, several ry/#by pins can be tied together in parallel with a pull-up resistor to v dd . when the output is low (busy), the device is active ly erasing or programming. when the output is high (ready), the device is in the read mode. 6.3.3 dq6: toggle bit toggle bit on dq6 indicates whether an embedded progr am or erase algorithm is in progress or complete. toggle bit may be read at any address, and is valid after the rising edge of the final #we pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operat ion, successive read cycles to any address cause dq6 to toggle. the system may use either #oe or #ce to control the read cycles. once the operation has completed, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for about 100 s, and then returns to reading array dat a. if not all selected sectors are protected, the embedded erase algorithm erases t he unprotected sectors, and ignores the selected sectors which are protected. if a program address falls within a protected sector, dq6 toggles for about 1 s after the program command sequence is written, and then returns to reading array data. 6.3.4 reading toggle bits dq6/dq2 whenever the system initially starts to read toggle bit status, it must read dq0 ? dq7 at least twice in a row to determine whether a toggle bit is toggling or not. typically, the system would note and store the value of the toggle bit after the first read. while after the second read, the system would compare the new value of the toggle bit with the first one. if the toggle bit is not toggling, the device has completed the program or erase operation. t he system can read array data on dq0 ? dq7 on the following read cycle. however, if after the initial two read cycles, the sy stem finds that the toggle bit is still toggling, the system also should note whether t he value of dq5 is high or not(see the section on dq5). if dq5 is
w19b160bt/b data sheet - 16 - high, the system should then determi ne again whether the toggle bit is toggling or not, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase oper ation. if it is still togg ling, the device did not complete the operation, and the syst em must write the reset command to return to reading array data. then the system initially determi nes that the toggle bit is togg ling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, and determines the status as described in the previous paragraph. alter natively, the system may choose to perform other system tasks. in this case, the system must start at t he beginning of the algorithm while it returns to determine the status of the operation. 6.3.5 dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether erasure has begun or not. (the sector erase timer does not apply to the chip erase command.) the entire time-out applies after each additional sector erase command if additional sectors are selected for erasure. once the timeout period has completed, dq3 switches from ?0? to ?1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor, dq3 does not need to be m onitored. please also refer to sector erase command sequence section. after the sector erase command is written, the system should read t he status of dq7 (#data polling) or dq6 (toggle bit i) to ensure that the dev ice has accepted the command sequence, and then read dq3. if dq3 is?1,? the embedded erase algorithm has begun; all further commands are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. the system software should check the status of dq3 before and following each subsequent sector erase command to ensure the command has been acc epted. if dq3 is high on the second status check, the last command mi ght not have been accepted. 6.3.6 dq5 : exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. dq5 produces ?1? under these conditions which indica tes that the program or erase cycle was not successfully completed. the device may output ?1? on dq5 if t he system tries to program ?1? to a location that was previously programmed to ?0.? only the erase operation can change ?0? back to ?1.? under this condition, the device stops the operation, and while the timi ng limit has been exceeded, dq5 produces ?1.? 7. special characteristic the w19b160b provides a good performance in the wireless products. it is concerned with access speed. if the access speed is quick to meet the demand of specification (70ns), the system?s application is widely and performance is better than other low speed products.
w19b160bt/b data sheet publication release date apr,20, 2009 - 17 - revision a9 8. table of operation modes 8.1 device bus operations dq8-dq15 mode #ce #oe #we #reset address (1) dq0- dq7 byte =vih byte =vil read l l h h ain dout dout write l h l h ain din din dq8- dq14=high-z dq15=a-1 standby vdd 0.3v x x vdd legend l = logic low = v il , h = logic high = v ih , v id = 8.5-11.5v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes 1. addresses are a19:a0 in word mode (#byte = v ih ), a19:a-1 in byte mode (#byte = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the? sector protection and unprotect ion? se ction.auto-select codes (high voltage method) description #ce #oe #we a19 to a12 a11 to a10 a9 a 8 to a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id: winbond 0 0 1 x x v id x 0 x 0 0 x dah device id: w19b160bt (top boot block) 0 0 1 x x v id x 0 x 0 1 22h (word ) c4h device id: w19b160bb (bottom boot block) 0 0 1 x x v id x 0 x 0 1 22h (word ) 49h sector protection verification 0 0 1 sa x v id x 0 x 1 0 x 01h (protected) 00h (unprotected ) legend : sa= sector address, x= don't care , v id = 8.5-11.5v , l = logic 0 = v il , h = logic 1 = v ih .
w19b160bt/b data sheet - 18 - 8.2 sector address table (top boot block) sector sector address a19-a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 00000xxx 64/32 000000h-00ffffh 00000h-07fffh sa1 00001xxx 64/32 010000h-01ffffh 08000h-0ffffh sa2 00010xxx 64/32 020000h-02ffffh 10000h-17fffh sa3 00011xxx 64/32 030000h-03ffffh 18000h-1ffffh sa4 00100xxx 64/32 040000h-04ffffh 20000h-27fffh sa5 00101xxx 64/32 050000h-05ffffh 28000h-2ffffh sa6 00110xxx 64/32 060000h-06ffffh 30000h-37fffh sa7 00111xxx 64/32 070000h-07ffffh 38000h-3ffffh sa8 01000xxx 64/32 080000h-08ffffh 40000h-47fffh sa9 01001xxx 64/32 090000h-09ffffh 48000h-4ffffh sa10 01010xxx 64/32 0a0000h-0affffh 50000h-57fffh sa11 01011xxx 64/32 0b0000h-0bffffh 58000h-5ffffh sa12 01100xxx 64/32 0c0000h-0cffffh 60000h-67fffh sa13 01101xxx 64/32 0d0000h-0dffffh 68000h-6ffffh sa14 01110xxx 64/32 0e0000h-0effffh 70000h-77fffh sa15 01111xxx 64/32 0f0000h-0fffffh 78000h-7ffffh sa16 10000xxx 64/32 100000h-10ffffh 80000h-87fffh sa17 10001xxx 64/32 110000h-11ffffh 88000h-8ffffh sa18 10010xxx 64/32 120000h-12ffffh 90000h-97fffh sa19 10011xxx 64/32 130000h-13ffffh 98000h-9ffffh sa20 10100xxx 64/32 140000h-14ffffh a0000h-a7fffh sa21 10101xxx 64/32 150000h-15ffffh a8000h-affffh sa22 10110xxx 64/32 160000h-16ffffh b0000h-b7fffh sa23 10111xxx 64/32 170000h-17ffffh b8000h-bffffh sa24 11000xxx 64/32 180000h-18ffffh c0000h-c7fffh sa25 11001xxx 64/32 190000h-19ffffh c8000h-cffffh sa26 11010xxx 64/32 1a0000h-1affffh d0000h-d7fffh sa27 11011xxx 64/32 1b0000h-1bffffh d8000h-dffffh sa28 11100xxx 64/32 1c0000h-1cffffh e0000h-e7fffh sa29 11101xxx 64/32 1d0000h-1dffffh e8000h-effffh sa30 11110xxx 64/32 1e0000h-1effffh f0000h-f7fffh sa31 111110xx 32/16 1f0000h-1f7fffh f8000h-fbfffh sa32 11111100 8/4 1f8000h-1f9fffh fc000h-fcfffh sa33 11111101 8/4 1fa000h-1fbfffh fd000h-fdfffh sa34 1111111x 16/8 1fc000h-1fffffh fe000h-fffffh note : the address range is [a19: a-1] in byte mode (#byte =vil) or [a19:a0] in word mode (#byte =vih ).
w19b160bt/b data sheet publication release date apr,20, 2009 - 19 - revision a9 8.3 sector address table (bottom boot block) sector sector address a19-a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 0000000x 16/8 000000h-003fffh 00000h-01fffh sa1 00000010 8/4 004000h-005fffh 02000h-02fffh sa2 00000011 8/4 006000h-007fffh 03000h-03fffh sa3 000001xx 32/16 008000h-00ffffh 04000h-07fffh sa4 00001xxx 64/32 010000h-01ffffh 08000h-0ffffh sa5 00010xxx 64/32 020000h-02ffffh 10000h-17fffh sa6 00011xxx 64/32 030000h-03ffffh 18000h-1ffffh sa7 00100xxx 64/32 040000h-04ffffh 20000h-27fffh sa8 00101xxx 64/32 050000h-05ffffh 28000h-2ffffh sa9 00110xxx 64/32 060000h-06ffffh 30000h-37fffh sa10 00111xxx 64/32 070000h-07ffffh 38000h-3ffffh sa11 01000xxx 64/32 080000h-08ffffh 40000h-47fffh sa12 01001xxx 64/32 090000h-09ffffh 48000h-4ffffh sa13 01010xxx 64/32 0a0000h-0affffh 50000h-57fffh sa14 01011xxx 64/32 0b0000h-0bffffh 58000h-5ffffh sa15 01100xxx 64/32 0c0000h-0cffffh 60000h-67fffh sa16 01101xxx 64/32 0d0000h-0dffffh 68000h-6ffffh sa17 01110xxx 64/32 0e0000h-0effffh 70000h-77fffh sa18 01111xxx 64/32 0f0000h-0fffffh 78000h-7ffffh sa19 10000xxx 64/32 100000h-10ffffh 80000h-87fffh sa20 10001xxx 64/32 110000h-11ffffh 88000h-8ffffh sa21 10010xxx 64/32 120000h-12ffffh 90000h-97fffh sa22 10011xxx 64/32 130000h-13ffffh 98000h-9ffffh sa23 10100xxx 64/32 140000h-14ffffh a0000h-a7fffh sa24 10101xxx 64/32 150000h-15ffffh a8000h-affffh sa25 10110xxx 64/32 160000h-16ffffh b0000h-b7fffh sa26 10111xxx 64/32 170000h-17ffffh b8000h-bffffh sa27 11000xxx 64/32 180000h-18ffffh c0000h-c7fffh sa28 11001xxx 64/32 190000h-19ffffh c8000h-cffffh sa29 11010xxx 64/32 1a0000h-1affffh d0000h-d7fffh sa30 11011xxx 64/32 1b0000h-1bffffh d8000h-dffffh sa31 11100xxx 64/32 1c0000h-1cffffh e0000h-e7fffh sa32 11101xxx 64/32 1d0000h-1dffffh e8000h-effffh sa33 11110xxx 64/32 1e0000h-1effffh f0000h-f7fffh sa34 11111xxx 64/32 1f0000h-1fffffh f8000h-fffffh note: the address range is [a19:a-1] in byte mode (#byte =vil) or [a19:a0] in word mode (#byte =vih ).
w19b160bt/b data sheet - 20 - 8.4 cfi query identification string description address (word mode) data address (byte mode) query-unique ascii string "qry" 10h 11h 12h 0051h 0052h 0059h 20h 22h 24h primary oem command set 13h 14h 0002h 0000h 26h 28h address for primary extended table 15h 16h 0040h 0000h 2ah 2ch alternate oem command set (00h=none exists) 17h 18h 0000h 0000h 2eh 30h address for alternate oem extended table (00h=none exists) 19h 1ah 0000h 0000h 32h 34h 8.5 system interface string description address (word mode) data address (byte mode) v dd min. (write/erase) d7-d4: volt , d3-d0: 100 mv 1bh 0027h 36h v dd max. (write/erase) d7-d4: volt , d3-d0: 100 mv 1ch 0036h 38h v pp min. voltage (00h=no vpp pin present) 1dh 0000h 3ah v pp max. voltage (00h=no vpp pin present) 1eh 0000h 3ch typical timeout per single byte/word write 2 n s 1fh 0004h 3eh typical timeout for min. size buffer write 2 n s (00h=not supported) 20h 0000h 40h typical timeout per individual block erase 2 n ms 21h 000ah 42h typical timeout for full chip erase 2 n ms (00h=not supported) 22h 0000h 44h max. timeout for byte/word write 2 n times typical 23h 0005h 46h max. timeout for buffer write 2 n times typical 24h 0000h 48h max. timeout per individual block erase 2 n times typical 25h 0004h 4ah max. timeout full chip erase 2 n times typical ( 00h = not supported) 26h 0000h 4ch
w19b160bt/b data sheet publication release date apr,20, 2009 - 21 - revision a9 8.6 device geometry definition description address (word mode) data address (byte mode) device size =2 n bytes 27h 0015h 4eh flash device interface description (refer to cfi publication 100) 28h 29h 0002h 0000h 50h 52h max. number of bytes in multi-byte write=2 n (00h=not supported) 2ah 2bh 0000h 0000h 54h 56h number of erase block regions within devices 2ch 0004h 58h erase block region 1 information (refer to the cfi specification or cfi publication 100 ) 2dh 2eh 2fh 30h 0000h 0000h 0040h 0000h 5ah 5ch 5eh 60h erase block region 2 information 31h 32h 33h 34h 0001h 0000h 0020h 0000h 62h 64h 66h 68h erase block region 3 information 35h 36h 37h 38h 0000h 0000h 0080h 0000h 6ah 6ch 6eh 70h erase block region 4 information 39h 3ah 3bh 3ch 001eh 0000h 0000h 0001h 72h 74h 76h 78h
w19b160bt/b data sheet - 22 - 8.7 primary vendor-specific extended query description address (word mode) data address ( byte mode) query-unique ascii string "pri" 40h 41h 42h 0050h 0052h 0049h 80h 82h 84h major version number, ascii 43h 0031h 86h minor version number, ascii 44h 0030h 88h address sensitive unlock 0 = required, 1 = not required 45h 0000h 8ah erase suspend 00 = not supported, 01=supported 46h 0000h 8ch sector protect 0 = not supported, x=number of sectors in per group 47h 0001h 8eh sector temporary unprotect 00 = not supported, 01=supported 48h 0001h 90h sector protect/unprotect scheme 00 = not supported, 01=supported 49h 0001h 92h simultaneous operation 00 = not supported, 01=supported 4ah 0000h 94h burst mode type 00 = not supported, 01=supported 4bh 0000h 96h page mode type 00 = not supported, 01=4 word page, 02=8 word page 4ch 0000h 98h
w19b160bt/b data sheet publication release date apr,20, 2009 - 23 - revision a9 8.8 command definitions bus cycles (2-5) first second third fourth fifth sixth command sequence (1) cycle addr data addr data addr data addr data addr data a ddr dat a read (note 6) 1 ra rd reset (note 7) 1 xxx f0 word 555 2aa 555 normal program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 word 555 2aa 555 unlock pass byte 3 aaa aa 555 55 aaa 20 unlock bypass program 2 xxx a0 pa pd unlock bypass reset 2 xxx 90 xxx 00 word 555 2aa 555 manufacturer code byte 4 aaa aa 555 55 aaa 90 x00 da word 555 2aa 555 x01 device code byte 4 aaa aa 555 55 aaa 90 x02 (note11 ) xx00 word 555 2aa 555 (sa) x02 xx01 00 autoselect(note8) sector protect verify (note 9) byte 4 aaa aa 555 55 aaa 90 (sa) x04 01 word 55 common flash interface (cfi) query (note 10) byte 1 aa 98 legend: x = don?t care ra = address of the memory location to be read. pa = address of the memory location to be programmed. a ddresses latch on the falling edge of the #we or #ce pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of #we or #c e pulse, whichever happens first. rd = data read from location ra during read operation. sa = address of the sector to be verified (in auto select mode) or erased. address bits a19-a12 uniquely select any sector. notes: 1. see bus operations table for details. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the aut o select command sequence, all bus cycles are write cycles. 4. data bits dq15-dq8 are don?t care for unlock and command cycle. 5. unless otherwise noted, address bits a19-a 11 are don?t cares for unlock and command cycles. 6. no unlock or command cycles required when reading array data. 7. when device is in the auto select mode, the reset command is required to return to reading array data, or if dq5 goes high (while the device is providing status data). 8. the fourth cycle of the auto select command sequence is a read cycle.
w19b160bt/b data sheet - 24 - 9. the data is 00h for an unprotected sector and 01h for a protected sector. 10. command is valid when device is r eady to read array data or when device is in auto select mode. 11. see auto-select codes table for device id information. 8.9 write operation status status dq7 (note 2) dq6 dq5 (note1) dq3 dq2 (note 2) ry/#by embedded program algorithm #dq7 toggle 0 n/a no toggle 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle 0 notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has ex ceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 requires a valid address when reading status information. please refe r to related sections for details.
w19b160bt/b data sheet publication release date apr,20, 2009 - 25 - revision a9 8.10 temporary sector unprotect algorithm start #reset = v id perform erase or program operations #reset = v ih temporary sector unprotect completed (note 2) (note 1) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again
w19b160bt/b data sheet - 26 - 8.11 in-system sector protect/unprotect algorithms start plscnt=1 #reset=v id wait 1 s first write cycle=60h? wait 150 s verity sector protect:write 40h to sector address with a6=0, a1=1,a0=0 set up sector address yes sector protect: write 60h to sector address with a6=0,a1=1,a0=0 read from sector address with a6=0, a1=1,a0=0 remove v from #reset id write reset command sector protect complete protect another sector? data=01h? temporary sector unprotect mode increment plscnt plscnt =25? no no device failed yes yes no reset plscnt=1 start plscnt=1 #reset=v id wait 1 s first write cycle=60h? yes all sector protected? yes wait 15 ms verity sector unprotect: write 40h to sector address with a6=1, a1=1,a0=0 sector unrotect: write 60h to sector address with a6=1,a1=1,a0=0 read from sector address with a6=1, a1=1,a0=0 remove v from #reset id write reset command last sector verified? data=00h? no yes no set up first sector address protect all sectors the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address temporary sector unprotect mode no no increment plscnt plscnt =1000? device failed yes sector unprotectt complete set up next sector address yes sector protect algorithm sector unprotect algorithm no yes no
w19b160bt/b data sheet publication release date apr,20, 2009 - 27 - revision a9 8.12 program algorithm start write program command sequence data poll from system verify data? increment address yes last address? yes programming completed embedded program algorithm in progress no no 8.13 erase algorithm (polling) start w rite erase com mand sequence data poll from system data=ffh? erase completed no yes embedded erase algorithm in progress
w19b160bt/b data sheet - 28 - 8.14 erase algorithm (toggle) stop erase command 100us delay dq6 toggle? yes no start embedded erase algorithm in progress
w19b160bt/b data sheet publication release date apr,20, 2009 - 29 - revision a9 8.15 data polling algorithm start read dq7-dq0 addr=va dq7=data? no dq5=1? yes no dq7=data? read dq7-dq0 addr=va fail pass yes yes no notes: 1. va = valid address for programming. during a sector erase operation; a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
w19b160bt/b data sheet - 30 - 8.16 toggle bit algorithm start read dq7-dq0 toggle bit no dq5=1? yes no toggle bit read dq7-dq0 twice yes yes no read dq7-dq0 =toggle? =toggle? program/erase operation not complete,write reset command program/erase complete (note 1) (notes 1, 2) notes: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may st op toggling as dq5 changes to ?1.?
w19b160bt/b data sheet publication release date apr,20, 2009 - 31 - revision a9 9. electrical characteristics 9.1 absolute maximum ratings parameter rating unit storage temperature plastic packages -65 to +150 c ambient temperature with power applied -65 to +125 c voltage with respect to ground , v dd (note1) -0.5 to +4.0 v a9, #oe, and #reset (note 2) -0.5 to v dd (max.) v all other pins (note 1) -0.5 to v dd +0.5 v output short circuit current (note 3) 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. duri ng voltage transitions, input or i/o pins may overshoot v ss to - 2.0 v for periods of up to 20 ns. maximu m dc voltage on input or i/o pins is v dd +0.5 v. during voltage transitions, input or i/o pins may overshoot to v dd +2.0 v for periods up to 20 ns. 2. minimum dc input voltage on pins a9, #oe, and #reset is -0.5 v. during voltage transitions, a9, #oe, and #reset may overshoot v ss to -2.0 v for periods of up to 20 ns. maximum dc input voltage on pin a9 is v dd (max.) which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time . duration of the short circ uit should not be greater than one second. stresses above those listed under ?abs olute maximum ratings? may caus e permanent damage to the device. this is a stress rating only; functional operation of t he device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. expos ure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 9.2 operating ranges parameter rating unit industrial (i) devices ambient temperature (ta ) -40 to +85 c commercial devices ambient temperature (ta ) 0 to +70 c vdd supply voltages vdd for standard voltage range 2.7 to 3.6 v operating ranges define those limits between whic h the functionality of the device is guaranteed.
w19b160bt/b data sheet - 32 - 9.3 dc characteristics limits parameter sym. test conditions min. typ. max. unit input load current ili vin = vss to vdd, vdd = vdd (max.) - - 1.0 a a9 input load current ilit vdd = vdd (max.), a9 = vid (max.) - - 35 a output leakage current ilo vout = vss to vdd , vdd = vdd (max.) - - 1.0 a 10 mhz 15 25 ma 5 mhz - 9 16 ma #ce = vil , #oe = vih byte mode 1 mhz 2 4 ma 10 mhz 18 25 ma 5 mhz 9 16 ma vdd active read current (note 1,2) icc1 #ce = vil , #oe = vih word mode 1 mhz 2 4 ma vdd active current (note 2,3,4) icc2 #ce = vil , #oe = vih - 20 30 ma vdd standby current (note 2,5) icc3 #reset , #ce = vdd 0.3v - 0.2 5 a vdd reset current (note 2,5) icc4 #reset = vss 0.3v - 0.2 5 a automatic sleep mode current (note 2,4,5,6) icc5 vih = vdd 0.3v, vil = vss 0.3v - 0.2 5 a input low voltage vil -0.5 - 0.8 v input high voltage vih 0.7 x vdd - vdd+0.3 v voltage for auto-select and temporary sector unprotected vid vdd =3.0v 10% 8.5 - 11.5 v output low voltage vol iol = 4.0 ma, vdd = vdd (min.) - - 0.45 v voh1 iol = -2.0 ma, vdd = vdd (min.) 2.4 - - v output high voltage voh2 ioh = -100 a, vdd = vdd (min.) vdd -0.4 - - v notes: 1. the i cc current is typically less than 2 ma/mhz, with #oe at v ih . typical v dd is 3.0v. 2. maximum i cc specifications are tested with v dd = v dd max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 5. for temperature >70 degree c, vih( max.)=vdd+0.1v and vil(min)=vss-0.1v. 6. not 100% tested
w19b160bt/b data sheet publication release date apr,20, 2009 - 33 - revision a9 9.4 ac characteristics 9.4.1 test condition test condition 70ns 90ns unit output load 1 ttl gate output load capacitance, cl (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0 - 3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v 9.4.2 ac test load and waveforms dut r2= 1.6k ohm r1= 6.2k ohm c= 0.1uf vcc v=3.3v cl= 30pf d=in3064 or equivalent note: 1. cl=30pf/70ns, cl=100pf/90ns 2. tr/tf=5ns 3. in/out reference levels=1.5v 4. output load: 1 ttl gate
w19b160bt/b data sheet - 34 - 9.4.3 read-only operations 70ns 90ns parameter sym. test setup min. max. min. max. unit read cycle time t rc 70 - 90 - ns address to output delay t acc #ce = v il , #oe = v il - 70 - 90 ns chip enable to output delay t ce #oe = v il - 70 - 90 ns output enable access time t oe - 30 - 35 ns chip enable to output high z t df - 25 - 30 ns output enable to output high z t df - 25 - 30 ns output hold time from address. #oe or #ce whichever occurs first t oh 0 - 0 - ns read 0 - 0 - ns output enable hold time toggle and #data polling t oeh 10 - 10 - ns note : not 100 % tested 9.4.4 read-only operations test condition 70ns 90ns unit output load 1 ttl gate output load capacitance, cl (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0 - 3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v note : not 100 % tested
w19b160bt/b data sheet publication release date apr,20, 2009 - 35 - revision a9 9.4.5 hardware reset (#reset) parameter sym. min. max. unit #reset pin low (during embedded algorithms) to read or write t ready - 20 us #reset pin low (not during embedded algorithms) to read or write t ready - 500 ns #reset pulse width t rp 500 - ns #reset high time before read t rh 50 - ns #reset low to standby mode t rpd 20 - us ry/#by recovery time t rb 0 - ns note: not 100 % tested 9.4.6 word/byte configuration (#byte) test condition 70ns 90ns unit output load 1 ttl gate output load capacitance, cl (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0 - 3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v
w19b160bt/b data sheet - 36 - 9.4.7 erase and program operation 70ns 90ns parameter sym. min. typ. max. min. typ. max. unit write cycle timing t wc 70 - - 90 - - ns address setup time t as 0 - - 0 - - ns address hold time t ah 45 - - 45 - - ns data setup time t ds 35 - - 45 - - ns data hold time t dh 0 - - 0 - - ns output enable setup time t oes 0 - - 0 - - ns read recovery time before write (#oe high to #we low) t ghwl 0 - - 0 - - ns #ce setup time t cs 0 - - 0 - - ns #ce hold time t ch 0 - - 0 - - ns write pulse width t wp 35 - - 35 - - ns write pulse width high t wph 30 - - 30 - - ns byte t pb - 5 150 - 5 150 us programming time word t pw - 7 210 - 7 210 us sector erase time t se - 0.7 10 - 0.7 10 sec vdd setup time (note 1) t vcs 50 - - 50 - - us write recovery time from ry/#by t rb 0 - - 0 - - ns program/erase valid to ry/#by delay t busy 30 - 90 - - 90 ns notes: not 100 % tested 9.4.8 temporary sector unprotect parameter sym. min. max. unit vid rise and fall time (see note) t vidr 500 - ns #reset setup time for temporary sector unprotect t rsp 4 - us #reset hold time from ry/#by high for temporary sector unprotect t rrb 4 - s note: not 100 % tested
w19b160bt/b data sheet publication release date apr,20, 2009 - 37 - revision a9 9.4.9 alternate #ce controlled erase and program operation 70ns 90ns parameter sym. min typ (note 3) max (note 4) min typ (note 3) max (note 4) unit write cycle time (note 1) t wc 70 - - 90 - - ns address setup time t as 0 - - 0 - - ns address hold time t ah 45 - - 45 - - ns data setup time t ds 35 - - 45 - - ns data hold time t dh 0 - - 0 - - ns output enable setup time t oes 0 - - 0 - - ns read recover time before write (#oe high to #we low) t ghel 0 - - 0 - - ns #we setup time t ws 0 - - 0 - - ns #we hold time t wh 0 - - 0 - - ns #ce pulse width t cp 35 - - 35 - - ns #ce pulse width high t cph 30 - - 30 - - ns byte t pb - 5 - - 5 - programming time (note 6) word t pw - 7 - - 7 - us sector erase time (note 2) t se - 0.7 - - 0.7 - sec chip erase time (note 2) t ce - 25 - - 25 - sec byte t cpb - 11 - - 11 - chip program time (note 5) word t cpw - 7.2 - - 7.2 - sec notes : 1. not 100 % tested. 2. in the pre-programming step of the embedded erase algor ithm, all bytes are programmed to 00h before erasure. 3. typical program and erase time assume the following conditions :25 ,3.0 v v dd , 10,000 cycles .additionally, programming typicals assume checkerboard pattern. 4. under worst case conditions of 90 , v dd =2.7v, 10,000 cycles. 5. the typical chip programming time is considerably less than the maximun chip programming time listed,since most bytes program faster than maximun program times listed. 6. system-level overhead is the time r equired to execute the two- or four-bus -cycle sequence for the program command. 7. the device has a minimum erase and program cycle endurance of 10,000 cycles.
w19b160bt/b data sheet - 38 - 10. timing waveforms 10.1 ac read waveform address outputs high-z #ce #oe #we t rc t oe t acc t oh t df high-z addresses stable t oeh t ce 0v #reset ry/#by output vaild 10.2 reset waveform rp t t rh t ready reset timing not during embedded algorithms #reset ry/#by #oe,#ce t ready t rp t rb reset timings during embedded algorithms #reset ry/#by #oe,#ce
w19b160bt/b data sheet publication release date apr,20, 2009 - 39 - revision a9 10.3 #byte waveform for read operation dq0-dq14 dq15/a-1 data output (dq0-dq14) dq15 output (dq0-dq7) data output address inp ut dq0-dq14 dq15 output address inp ut dq15/a-1 data output (dq0-dq14) (dq0-dq7) data output t elfl t flqz t elfh t fhqv #oe #ce #byte #byte switching from word to byte mode #byte switching from byte to word mode #byte 10.4 #byte waveform for write operation t set t hold as (t ) (t ah ) note: refer to the erase /program operations table for tas and tah specifications. #ce #byte #we the falling edge of the last #we signal
w19b160bt/b data sheet - 40 - 10.5 programming waveform 555h pa pa pa address t wc t as t ch t ah t wp t pw program command sequence (last two cycles) read status data (last two cycles) status d out pd a0h t cs t dh t wph t busy t rb t vcs data vdd ry/#by #we #oe #ce ds t notes : 1. pa=program address ,pd=program data,d out is the true data at the program address 2. illustration shows device in word mode 10.6 chip/sector erase waveform 2aah sa va va t wc t as t ch t ah t wp t cs t ds t dh t wph t se erase command sequence (last two cycles) read status data 30h 55h t busy t rb t vcs progress in complete 10 for chip erase 555h for chip erase address data vdd ry/#by #we #oe #ce notes : 1. sa= sector address (for sector er ase), va= valid address for reading stat us data (see ?write operation status?). 2. these waveforms are for the word mode
w19b160bt/b data sheet publication release date apr,20, 2009 - 41 - revision a9 10.7 #data polling waveform (during embedded algorithms) t rc valid data va t ce t acc t oe t oeh t busy t oh t ch t df addresses dq0-dq6 va va valid data high z high z dq7 status data complement true status data complement true ry/#by #we #oe #ce note : va= valid address. illustration shows first status cycl e after command sequence, last status read cycle, and array data read cycle. 10.8 toggle bit waveform (during embedded algorithms) addresses dq6 t df t oeh t ch t ce t rc t acc ry/#by #we #oe #ce t busy (stop toggling) (second read) (first read) valid status valid status valid status valid status va va va t oh high z va t oe note : va= valid address;not requires for dq6. illustration shows status cycle after command sequence, last status read cycle, and array data read cycle.
w19b160bt/b data sheet - 42 - 10.9 temporary sector unprotect timing diagram t rsp t vidr t vidr program or erase command sequence #reset #ce #we ry/#by 0 or 3v 12v 10.10 sector protect and unprotect timing diagram data valid* a1,a0 sa,a6, #reset sector protect:150 s, sector unprotect:15ms 1 s sector protect or unprotect v id v ih 60h 60h valid* valid* 40h verify status #ce #we #oe note: for sector protect, a6=0, a1=1, a0=0. for sector unprotect, a6=1, a1=1, a0=0.
w19b160bt/b data sheet publication release date apr,20, 2009 - 43 - revision a9 10.11 alternate #ce controlled write (erase/program) operation timing . . d out #dq7 #reset data address 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase #data polling pa t wc t as t ah t wh t ghel t cp t ws t ds t dh a0 for program 55 for erase pd for program 30 for sector erase 10 for chip erase t busy t rh #we #oe #ce ry/#by t pw, pb, or se tt t cph notes : 1. firgure indicates last two bus cycl es of a program or erase operation. 2. pa= program address, sa= sect or address, pd= program data. 3. #dq7 is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode.
w19b160bt/b data sheet - 44 - 11. latchup characteristics parameter min max input voltage with respect to vss on a ll pins except i/o pins (including a9, #oe, and #reset) -1.0 v 11.5 v input voltage with respect to vss on all i/o pins -1.0 v v dd +1.0 v v dd current -100 ma +100 ma note : includes all pins except vdd. test conditions: vdd = 3.0 v, one pin at a time. 12. capacitance parameter sym. test setup typ max unit input capacitance v in v in = 0 6 7.5 pf output capacitance v out v out = 0 8.5 12 pf control pin capacitance v in2 v in = 0 7.5 9 pf notes : 1. sampled, not 100 % tested. 2. test condition ta = 25 , f = 1.0 mhz.
w19b160bt/b data sheet publication release date apr,20, 2009 - 45 - revision a9 13. ordering information device number/description 7 : 70 ~ 79ns 9 : 90 ~ 99ns speedoption t = top sector b = bottom sector boot code sector architecture t = 48 - pin tsop package, 12 x 20mm package type : h: extended ( - m:industrial ( 40 ~85 )with green package quality grade & green ~85 )with green package -20 w19b160b 16 megabit (2m x 8 - bit/ 1 m x 16 - bit) cmos flash memory
w19b160bt/b data sheet - 46 - package dimensions 48-pin standard thin small outline package (measured in millimeters) e 1 48 b e d y a1 a a2 l1 l c h d 0.020 0.004 0.007 0.037 0.002 min. 0.60 y l l1 c 0.50 0.10 0.70 0.21 millimeter a a2 b a1 0.95 0.17 0.05 symbol min. 1.20 0.27 1.05 1.00 0.22 max. nom. 0.028 0.008 0.024 0.011 0.041 0.047 0.009 0.039 nom. inch max. e h d 0 5 0 5 e d 18.3 18.4 18.5 19.8 20.0 20.2 11.9 12.0 12.1 0.720 0.724 0.728 0.780 0.787 0.795 0.468 0.472 0.476 0.10 0.80 0.031 0.004 0.020 0.50
w19b160bt/b data sheet publication release date apr,20, 2009 - 47 - revision a9 14. version history version date page description a1 april/12/2007 all initial issued a2 july/17/2007 all 48-pin standard thin small outline package/vid spec to 11.5volt a3 oct./01/2007 34-38 1. reduced t busy form 90ns to 30ns 2. reduced i cc1 form 30/35ma to 25ma 3. removed max of t cpb/ t cpw 4. removed max of t pw a4 oct./17/2007 26,46 updated frame setting and package material as green a5 dec./20/2007 32,36-41 39 1. added note of icc3-5, 90ns/read only spec, and max. of tpw/tpb 2. modify ac test load a6 july/21/2008 45 updated frame setting a7 nov./04/2008 4,45 remo ved tfbga package type a8 dec./30/2008 removed erase suspend/resume feature a9 apr./20/2009 29 24 add erase algorithm (toggle) unlock bypass reset: 2nd command f0 00 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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