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| ws1102 3 x 3fpowerfampliferfmodulefforfcdma/ampsf(824C849fmhz) data sheet description the ws1102 is a cdma (code division multiple access) and amps (advanced mobile phone service) power amplifer module designed for handsets operating in the 824C849 mhz bandwidth. the ws1102 features coolpam circuit technology that ofers state-of-the-art reliability, temperature stability and ruggedness. the ws1102 meets stringent cdma linearity requirements to and beyond 28 dbm output power. the 3 mm x 3 mm form factor 8-pin surface mount package is self contained, incorporating 50 ohm input and output matching networks. features ? good linearity ? excellent efciency: 40% at pout = 28 dbm; 19% at pout = 16 dbm (without a dc/dc converter) ? 8-pin surface mounting package (3 mm x 3 mm x 1.1 mm) ? internal 50 matching networks for both rf input and output ? cdma 95a/b, cdma2000-1x/evdo applications ? digital cellular (cdma) ? analog cellular (amps) functional block diagram input match inter stage match output match bias circuit & control logic da pa v cc2(8) v ref ( 4 ) vc on t ( 3 ) v cc1(1) rf input (2) rf output (7) mmi c module
table 1. absolute maximum ratings [1] parameter symbol min. nominal max. unit rffinputfpower f p in f Cf Cf 10.0f dbm dcfsupplyfvoltage f v cc f Cf 3.4f 5.0f v dcfreferencefvoltage f v ref f Cf 2.85f 3.3f v storageftemperature f t stg f -55f Cf +125f c table 2. recommended operating conditions parameter symbol min. nominal max. unit dcfsupplyfvoltage f v cc f 3.2f 3.4f 4.2f v dcfreferencefvoltage f v ref f 2.75f 2.85f 2.95f v modefcontrolfvoltage f Cfhighfpowerfmode f v cont f Cf 0f Cf v f Cflowfpowerfmode f v cont f Cf 2.85f Cf v operatingffrequency f f o f 824f Cf 849f mhz ambientftemperature f t a f -30f 25f 85f c table 3. power range truth table power mode symbol vref vcont [2] range highfpowerfmode [3] f pr2 f 2.85f low f ~28fdbm lowfpowerfmode [3] f pr1f 2.85f highf ~16fdbm shutfdownfmode [4] f Cf 0.00f Cf C notes: 1. no damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. 2. high (1.5v C 3.0v), low (0.0v C 0.5v). 3. to change between high power mode and low power mode, switch vcont accordingly. 4. in order to shut down the module, turn of v ref accordingly. table 4-1. electrical characteristics for cdma mode (vcc=3.4v, vref=2.85v, t=25c) characteristics symbol condition min. typ. max. unit gain f f gain_hi f poutf=f28.0fdbm f 25.5f 28.5 f f db ff f gain_low f poutf=f16.0fdbm f 15.5f 18.5 f f db powerfaddedfefciency f f pae_hi f poutf=f28.0fdbm f 37f 40 f f % ff f pae_low f poutf=f16.0fdbm f 16f 19 f f % totalfsupplyfcurrent f f icc_hi f poutf=f28.0fdbm f f 460f 500f ma ff f icc_low f poutf=f16.0fdbm f f 60f 80f ma quiescentfcurrent f f iq_hi f highfpowerfmode f 60f 85f 110f ma ff f iq_low f lowfpowerfmode f 8f 14f 22f ma referencefcurrent f f iref_hi f poutf=f28.0fdbm f f 3f 7f ma ff f iref_low f poutf=f16.0fdbm f f 4f 8f ma controlfcurrent [1] f f icont f poutf=f16.0fdbm f f 0.2f 1f ma totalfcurrentfinfpower-downfmode f ipdf vreff=f0.0v f f 0.2f 5f a acprfinfhighfpowerfmode f 0.90fmhzfofset f acpr1_hi f poutf=f28.0fdbm f f -50f -47f dbc f ff 1.98fmhzfofset f acpr2_hi f poutf=f28.0fdbm f f -60f -57f dbc acprfinflowfpowerfmode f 0.90fmhzfofset f acpr1_low f poutf=f16.0fdbm f f -52f -47f dbc f ff 1.98fmhzfofset f acpr2_low f poutf=f16.0fdbm f f -62f -57f dbc harmonicfsuppressionf f secondf f 2f0f poutf=f28.0fdbm f f -33f -30f dbc f ff third f 3f0f poutf=f28.0fdbm f f -55f -40f dbc inputfvswr f f vswr f f f 2:1f 2.5:1f vswr stabilityf(spuriousfoutput) f f sf vswrf6:1,fallfphase f f f -60f dbc noisefpowerfinfrxfbandf f f rxbnf poutf=f28.0fdbm f f -136f -132f dbm/hz ruggednessf f ruf poutf evaluation board description figure 6. evaluation board schematic. figure 7. evaluation board assembly diagram. 1 vcc1 2 rf in 3 vcont 4 vref vcc2 8 rf out 7 gnd 6 gnd 5 rf out vcc1 rf in c5 2.2 f c1 560 pf vcont r1 6.2 kohm c3 100 pf vref c4 100 pf c2 82 pf c6 2.2 f vcc2 figure 8. package dimensional drawing and pin descriptions. package dimensions and pin descriptions notes: 1. all dimensions are in millimeters. 2. dimensions without tolerance: .xx ? 0.05mm. supply voltage vcc2 8 rf output rf out 7 ground gnd 6 ground gnd 5 reference voltage vref 4 control voltage vcont 3 rf input rf in 2 supply voltage vcc1 1 description name pin # top view 1.1 0.1 0.60 side view 3 0.1 2 3 4 5 8 7 6 3 0.1 pin 1 mark 1 bottom view pin descriptions 0.70 0.25 0.25 0.40 0.40 0.40 1.20 1.40 1.40 figure 9. marking specifcations. package dimensions and pin descriptions , fcontinued w s 1 1 0 2 p y y w w manufacturing part number a a a a a pin #1 mark lot number p manufacturing site yy manufacturing year ww work week aaaaa assembly lot numbe r vcc1 vcc2 in out vcont gnd vref gnd duplexer rf saw msm pa_r 0 pa_on rf out output matching circuit rf in ws1102 vdd r1 c3 v batt +2.85v c5 c4 c1 c8 c7 c6 l1 c2 peripheral circuit in handset figure 10. peripheral circuit. notes: 1. recommended voltage for vref is 2.85v. 2. place c1 near to vref pin. 3. place c3 and c4 close to pin 1 (vcc1) and pin 8 (vcc2). these capacitors can afect the rf performance. 4. use 50 transmission line between pam and duplexer and make it as short as possible to reduce conduction loss. 5. -type circuit topology is good to use for matching circuit between pa and duplexer. 6. pull-up resistor (r1) should be used to limit current drain. 6.2 k is recommended for ws1102. calibration calibration procedure is shown in figure 11. two calibration tables, high mode and low mode respectively, are required for coolpam, which is due to gain diference in each mode. for continuous output power at the mode change points, the input power should be adjusted according to gain step during the mode change. ofset value (diference between rising point and falling point) ofset value, which is the diference between the rising point (output power where pa mode changes from low mode to high mode) and falling point (output power where pa mode changes from high mode to low mode), should be adopted to prevent system oscillation. 3 to 5 db is recommended for hysteresis. average current and talk time probability distribution function implies that what is important for longer talk time is the efciency of low or medium power range rather than the efciency at full power. ws1102 idle current is 14 ma and operating current at 16 dbm is 60 ma at nominal condition. average current calculated with cdma pdf is 33 ma in urban area and 54 ma in suburban area. this pa with low current consumption prolongs talk time by no less than 30 minutes compared to other pas. average current = (pdf x current)dp pout min pwr max pwr high mode tx agc low mode rising falling rising falling high mode low mode pout gain figure 11. calibration procedure. figure 12. setting of ofset between rising and falling power. figure 13. cdma power distribution function. 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 -50 -40 -30 -20 -10 0 1 0 2 0 3 0 pa out (dbm) cdg urban cdg suburban conv pam digitally controlled pam cool pam 0 100 200 300 500 400 600 700 pdf current (ma) 10 pcb design guidelines the recommended ws1102 pcb land pattern is shown in figure 14 and figure 15. the substrate is coated with solder mask between the i/o and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. stencil design guidelines a properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the pcb pads. the recommended stencil layout is shown in figure 16. reducing the stencil opening can potentially generate more voids. on the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the i/o pads or conductive paddle to adjacent i/o pads. considering the fact that solder paste thickness will directly afect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100 mm (4 mils) or 0.127 mm (5mils) thick stainless steel which is capable of producing the required fne stencil outline. 0.25 0.8 0.4 0.65 0.5 ? 0.3mm on 0.5mm pitch 1.4 0.8 0.5 0.75 0.55 1.325 1.1 0.8 0.4 0.65 0.5 1.05 figure 14. metallization. figure 15. solder mask opening. figure 16. solder paste stencil aperture. 11 figure 17. tape and reel format C 3mm x 3mm. tape and reel information 8.00 0.10 p1 0.30 0.05 t 4.00 0.10 p0 12.00 0.30 w 1.60 0.10 d1 5.50 0.05 f 1.55 0.05 d0 1.75 0.10 e 1.70 0.10 k0 40.00 0.20 p10 3.40 0.10 b0 2.00 0.05 p2 3.40 0.10 a0 milimeter annote milimeter annote dimension list ordering information part number number of devices container f ws1102-blkf 100f bulk WS1102-TR1 f 2500f 13"ftapefandfreel 1 figure 18. plastic reel format 13"/14". tape and reel information ,f continued allfdimensionsfarefinfmillimeters 1 handling and storage esd (electrostatic discharge) electrostatic discharge occurs naturally in the environment. with the increase in voltage potential, the outlet of neutralization or discharge will be sought. if the acquired discharge route is through a semiconductor device, destructive damage will result. esd countermeasure methods should be developed and used to control potential esd damage during handling in a factory environment at each manufacturing site. msl (moisture sensitivity level) plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. avago technologies follows jedec standard j-std 020b. each component and package type is classifed for moisture sensitivity by soaking a known dry package at various temperatures and relative humidity, and times. after soak, the components are subjected to three consecutive simulated refows. table 5. esd classifcation pin# name description hbm mm classifcation 1f vcc1 f supplyfvoltage f f2000vf f200vf classf2 2f rffinf rffinputf f2000vf f200vf classf2 3f vcont f controlfvoltage f f2000vf f200vf classf2 4f vref f referencefvoltage f f2000vf f200vf classf2 5f gndf ground f f2000vf f200vf classf2 6f gndf ground f f2000vf f200vf classf2 7f rffout f rffoutput f f2000vf f200vf classf2 8f vcc2 f supplyfvoltage f f2000vf f200vf classf2 note: 1. module products should be considered extremely esd sensitive. the out of bag exposure time maximum limits are determined by the classifcation test described above which corresponds to a msl classifcation level 6 to 1 according to the jedec standard ipc/jedec j - std-020b and j-std-033. ws1102 is msl3. thus, according to the j-std-033 p.11 the maximum manufacturers exposure time (met) for this part is 168 hours. after this time period, the part would need to be removed from the reel, de-taped and then re-baked. msl classifcation refow temperature for the ws1102 is targeted at 250c +0/-5c. figure 19 and table 7 show typical smt profle for maximum temperature of 250c +0/-5c. table 6. moisture classifcation level and floor life msl level floor life (out of bag) at factory ambient 30c/60% rh or as stated 1f unlimitedfatfff30 o c/85%frh 2f 1fyear 2af 4fweeks 3f 168fhours 4f 72fhours 5f 48fhours 5af 24fhours 6f mandatoryfbakefbeforefuse.fafterfbake,fmustfbefrefowedfwithinftheftimeflimitfspecifedfonftheflabel note: 1. the msl level is marked on the msl label on each shipping bag. 1 figure 19. typical smt refow profle for maximum temperature = 250+0/-5c. table 7. typical smt refow profle for maximum temperature = 250+0/-5c profle feature sn-pb solder pb-free solder averageframp-upfratef(t l ftoft p )f 3c/secfmaxf 3c/secfmax preheat f ff -ftemperaturefminf(tsmin) f 100cf 150c f ff -ftemperaturefmaxf(tsmax) f 150cf 200c f ff -ftimef(minftofmax)f(ts) f 60C120fsec f 60C180fsec tsmaxftoft lf f ff -framp-upfrate f f 3c/secfmax timefmaintainedfabove: f ff -ftemperaturef(t l )f 183cf 217c f ff -ftimef(t l )f 60C150fsecf 60C150fsec peakftemperaturef(t p )f 240f+0/-5cf 250f+0/-5c timefwithinf5cfoffactualfpeakftemperaturef(tp) f 10C30fsecf 20C40fsec ramp-downfrate f 6c/secfmaxf 6c/secfmax timef25cftofpeakftemperature f 6fminfmax.f 8fminfmax. handling and storage ,f continued 1 handling and storage ,f continued storage conditions packages described in this document must be stored in sealed moisture barrier, anti-static bags. shelf life in a sealed moisture barrier bag is 12 months at <40 o c and 90% relative humidity (rh) j-std-033 p.7. out-of-bag time duration after unpacking the device must be soldered to the pcb within 168 hours as listed in the j -std - 020b p.11 with factory conditions <30 o c and 60% rh. baking it is not necessary to re-bake the part if both conditions (storage conditions and out-of-bag conditions) have been satisfed. baking must be done if at least one of the conditions above have not been satisfed. the baking conditions are 125 o c for 12 hours j-std-033 p.8. caution : tape and reel materials typically cannot be baked at the temperature described above. if out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (see moisture sensitive warning label on each shipping bag for information of baking). board rework component removal, rework and remount if a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200c. this method will minimize moisture related component damage. if any component temperature exceeds 200c, the board must be baked dry per baking of populated boards below prior to rework and/or component removal. component temperatures shall be measured at the top center of the package body. any smd packages that have not exceeded their foor life can be exposed to a maximum body temperature as high as their specifed maximum refow temperature. removal for failure analysis not following the requirements may cause moisture/ refow damage that could hinder or completely prevent the determination of the original failure mechanism. baking of populated boards some smd packages and board materials are not able to withstand long duration bakes at 125c. examples of this are some fr-4 materials, which cannot withstand a 24 hr bake at 125c. batteries and electrolytic capacitors are also temperature sensitive. with component and board temperature restrictions in mind, choose a bake temperature from table 4-1 in j - std 033; then determine the appropriate bake duration based on the component to be removed. for additional considerations see ipc- 7711 and ipc-7721. derating due to factory environmental conditions factory foor life exposures for smd packages removed from the dry bags will be a function of the ambient environmental conditions. a safe, yet conservative, handling approach is to expose the smd packages only up to the maximum time limits for each moisture sensitivity level as shown in table 6. this approach, however, does not work if the factory humidity or temperature are greater than the testing conditions of 30c/60% rh. a solution for addressing this problem is to derate the exposure times based on the knowledge of moisture difusion in the component packaging materials (ref. jesd22-a120). recommended equivalent total foor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. table 8 lists equivalent derated foor lives for humidities ranging from 20-90% rh for three temperatures, 20c, 25c, and 30c. this table is applicable to smds molded with novolac, biphenyl or multifunctional epoxy mold compounds. the following assumptions were used in calculating table 8: 1. activation energy for difusion = 0.35ev (smallest known value). 2. for 60% rh, use difusivity = 0.121exp (- 0.35ev/kt) mm2/s (this uses smallest known difusivity @ 30c). 3. for >60% rh, use difusivity = 1.320exp (- 0.35ev/kt) mm2/s (this uses largest known difusivity @ 30c). table 8. recommended equivalent total floor life (days) @ 20c, 25c & 30c for ics with novolac, biphenyl and multifunctional epoxies (refow at same temperature at which the component was classifed) handling and storage ,f continued forfproductfinformationfandfafcompleteflistfoffdistributors,fpleasefgoftofourfwebfsite:fffffffff www.avagotech.com avago,favagoftechnologies,fandfthefaflogofareftrademarksfoffavagoftechnologies,flimitedfinfthefunitedfstatesfandfotherfcountries. datafsubjectftofchange.ffcopyrightf?f2008favagoftechnologies,flimited.ffallfrightsfreserved. ffobsoletesf5989-4648enfff av02-0144enf-fjunef10,f2008 |
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