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| si4420 pin assignment rev c and later this document refers to si4420-ic rev d1. see www.silabs.com /integration for any applicable errata . see back page for ordering information. si4420 universal ism band fsk transceiver description silicon labs? si4420 is a single ch ip, low power, multi-channel fsk t ransceiver designed for use in applications requiring fcc or etsi conformance for unlicensed use in the 315, 433, 868 and 915 mhz bands. the si4420 transceiver is a part of silicon labs? ezradio tm product line, which produces a flexible, low cost, and highly integrated solution that does not require production alignments. the chip is a complete analog rf and baseband transceiver including a multi-band pll synthesizer with pa, lna, i/q down converter mixers, baseband filters and amplifiers, and an i/q demodulator. all required rf functions are integrated. only an external crystal and bypass filtering are needed for operation. the si4420 features a completely integr ated pll for easy rf design, and its rapid settling time allows for fast frequency-hopping, bypassin g multipath fading and interference to achieve robust wireless links. the pll?s high resolution allows the usage of multiple channels in any of the bands. the receiver baseband ba ndwidth (bw) is programmable to accommodate various deviation, da ta rate and crystal tolerance requirements. the transceiver employs the zero-if approach with i/q demodulation. consequently, no external components (except crystal and decoupling) are needed in most applications. the si4420 dramatically redu ces the load on the mi crocontroller with the integrated digital data processing features: data filtering, clock recovery, data pattern recognition, integrated fifo and tx data register. the automatic frequency contro l (afc) feature allows the use of a low accuracy (low cost) crystal. to mini mize the system cost, the si4420 can provide a clock signal for the microcontroller, avoiding the need for two crystals. for low power applicatio ns, the si4420 supports lo w duty cycle operation based on the internal wake-up timer. functional block diagram 1 si4420-ds rev 1.7r 0308 www.silabs.com rf parts low power parts data processing unit s bb amp/filt./limiter amp oc amp oc lna mix i q mix data filt clk rec data clk dqd comp rssi afc pll & i/q vco with cal. controller xosc self cal. lbd wtm with cal. clk div bias 13 rf1 rf2 12 8 9 clk xtl / ref 10 15 nint / vdi arssi 2 3 4 5 11 sck nsel sdo nirq 14 1 vss vdd sdi 7 6 dclk / cfil / ffit / fsk / data / nffs fifo 16 nres pa i/q demod features ? fully integrated (low bom, easy design-in) ? no alignment required in production ? fast-settling, programmable, high-resolution pll synthesizer ? fast frequency-hopping capability ? high bit rate (up to 115.2 kbps in digital mode and 256 kbps in analog mode) ? direct differential antenna input/output ? integrated power amplifier ? programmable tx frequency deviation (15 to 240 khz) ? programmable rx baseband bandwidth (67 to 400 khz) ? analog and digital rssi outputs ? automatic frequency control (afc) ? data quality detection (dqd) ? internal data filtering and clock recovery ? rx synchron pattern recognition ? spi compatible serial control interface ? clock and reset signals for microcontroller ? 16 bit rx data fifo ? two 8 bit tx data registers ? low power duty cycle mode ? standard 10 mhz crystal reference ? wake-up timer ? 2.2 to 5.4 v supply voltage ? low power consumption ? low standby current (0.3 ? a) ? compact 16 pin tssop package typical applications ? remote control ? home security and alarm ? wireless keyboard/mouse and other pc peripherals ? toy controls ? remote keyless entry ? tire pressure monitoring ? telemetry ? remote automatic meter reading
si4420 2 detailed feature-level description t he si4420 fsk transceiver is designed to cover the unlicensed frequency bands at 315, 433, 868 and 915 mhz. the devices facilitate complian ce with fcc and etsi requirements. the receiver block employs the zero-if approach with i/q demodulation, allowing the use of a minimal number of external components in a typical application. the si4420 incorporates a fully integrated multi-band pll synthesizer, pa with antenna tuning, an lna with switchable gain, i/q down converter mixers, baseband filters and amplifie rs, and an i/q demodulator followed by a data filter. pll the programmable pll synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. the pll?s high resolution allows the usage of multiple channels in any of the bands. the rf vco in the pll performs automatic calibration, which requires only a few microseconds. calibration always occurs when the synthesizer starts. if temperature or supply voltage changes significantly or operational band has changed, vco recalibration is recommended.. recalibration can be initiated at any time by switching the synthesizer off and back on again. rf power amplifier (pa) the power amplifier has an open-collector differential output and can directly drive a loop antenna with a programmable output power level. an automatic antenna tuning circuit is built in to avoid costly trimming procedures and the so-called ?hand effect.? lna the lna has 250 ohm input impedance, which functions well with the proposed antennas (see: application notes available from www.silabs.com/integration ) if the rf input of the chip is connected to 50 ohm devices, an external matching circuit is required to provide the correct matching and to minimize the noise figure of the receiver. the lna gain can be selected (0, ?6, ?14, ?20 db relative to the highest gain) according to rf signal strength. it can be useful in an environment with strong interferers. baseband filters the receiver bandwidth is selectable by programming the bandwidth (bw) of the baseband fi lters. this allows setting up the receiver according to the characteristics of the signal to be received. an appropriate bandwidth can be chosen to accommodate various fsk deviation, data rate and crystal tolerance requirements. the filter structure is 7th order butterworth low- pass with 40 db suppression at 2*bw frequency. offset cancellation is done by using a high-pass filter with a cut-off frequency below 7 khz. data filtering and clock recovery output data filtering can be completed by an external capacitor or by using digital filtering according to the final application. analog operation: the filter is an rc type low-pass filter followed by a schmitt-trigger (st). the resistor (10 kohm) and the st are integrated on the chip. an (external) capacitor can be chosen according to the actual bit rate. in this mode, the receiver can handle up to 256 kbps data rate. the fifo can not be used in this mode and clock is not prov ided for the demodulated data. digital operation: a digital filter is used with a clock frequency at 29 times the bit rate. in this mode there is a clock recovery circuit (cr), which can provide synchronized clock to the data. using this clock the received data can fill a fifo. the cr has three operation modes: fast, slow, and automatic. in slow mode, its noise immunity is very high, but it has slower settling time and requires more accurate data timing than in fast mode. in automatic mode the cr automatically changes between fast and slow mode. the cr starts in fast mode, then after locking it automatically switches to slow mode. (only the digital data filter and the clock recovery use the bit rate clock. for analog operation, there is no need for setting the correct bit rate.) si4420 3 when the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the configuration setting command, the chip provides a fixed number (196) of further clock pulses (?clock tail?) for the mic rocontroller to let it go to idle or sleep mode. data validity blocks rssi a digital rssi output is provided to monitor the input signal level. it goes high if the received signal strength exceeds a given preprogrammed level. an analog rssi signal is also available. the rssi settling time depends on the external filter capacitor. pin 15 is used as analog rssi output. the digital rssi can be can be monitored by reading the status register. low battery voltage detector the low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below a programmable threshold level. the detector circuit has 50 mv hysteresis. analog rssi voltage vs. rf input power wake-up timer the wake -up timer has very low current consumption (1.5 a typical) and can be programmed from 1 ms to several days with an accuracy of 5%. it calibrates itself to the crystal oscillator at every startup. when the crystal oscillator is switched off, the calibration circuit switches it on only long enough for a quick calibration (a few milliseconds) to facilitate accurate wake-up timing. event handling in order to minimize current consumption, the transceiver supports different power saving modes. active mode can be initiated by several wake-up events (negative logical pulse on nint input, wake-up timer timeout, low supply voltage detection, on-chip fifo filled up or receiving a request through the serial interface). p1 -65 dbm 1300 mv p2 -65 dbm 1000 mv p3 -100 dbm 600 mv p4 -100 dbm 300 mv if a ny wake-up event occurs, the wake-up logic generates an interrupt signal, which can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. the source of the interrupt can be read out from the transceiver by the microcontroller through the sdo pin. dqd the da ta quality detector is based on counting the spikes on the unfiltered received data. for correct operation, the ?dqd threshold? parameter must be filled in by using the data filter command. interface and controller afc an spi co mpatible serial interface lets the user select the frequency band, center frequency of the synthesizer, and the bandwidth of the baseband signal path. division ratio for the microcontroller clock, wake-up timer period, and low supply voltage detector threshold are also programmable. any of these auxiliary functions can be disabled when not needed. all parameters are set to default after power-on; the programmed values are retained during sleep mode. the interface supports the read-out of a status register, providing detailed information about the status of the transceiver and the received data. by using an integrated automatic frequency control (afc) feat ure, the receiver can minimize the tx/rx offset in discrete steps, allowing the use of: x inexpensive, low accuracy crystals x narrower receiver bandwidth (i.e. increased sensitivity) x higher data rate crystal oscillator the si4420 has a single-pin crysta l oscillator circuit, which provides a 10 mhz reference signal for the pll. to reduce external parts and simplify design, the crystal load capacitor is internal and programmable. guidelines for selecting the appropriate crystal can be found later in this datasheet. the tr ansmitter block is equipped with an 8 bit wide tx data register. it is possible to write 8 bits into the register in burst mode and the internal bit rate generator transmits the bits out with the predefined rate. it is also possible to store the received data bits into a fifo register and read them out in a buffered mode. the tr ansceiver can supply the clock signal for the microcontroller; so accurate timing is possible without the need for a second crystal. si4420 4 package pin definitions pin type key: d=digital, a=analog, s=supply, i=input, o=output, io=input/output pin name type function 1 sdi di data input of the serial control interface 2 sck di clock input of the serial control interface 3 nsel di chip select input of the serial control interface (active low) 4 sdo do serial data output with bus hold (tri-state) 5 nirq do interrupt request output (active low) fsk di transmit fsk data input data do received data output (fifo not used) 6 nffs di fifo select input (active low) in fifo mode, when bit ef is set in configuration setting command dlck do received data clock output (digital filter used, fifo not used) cfil aio external data filter capac itor connection (analog filter used) 7 ffit do fifo interrupt (active high) number of the bits in the rx fifo that reach the preprogrammed limit in fifo mode, when bit ef is set in configuration setting command 8 clk do microcontroller clock output xtl aio crystal connection (the other terminal of crystal to vss) or external reference input 9 ref aio external reference input. us e 33 pf series coupling capacitor 10 nres dio open drain reset output with internal pull-up and input buffer (active low) 11 vss s ground reference voltage 12 rf2 aio rf differential signal input/output 13 rf1 aio rf differential signal input/output 14 vdd s positive supply voltage 15 arssi ao analog rssi output nint di interrupt input (active low) 16 vdi do valid data indicator output note: the actual mode of the multipurpose pins (pin 6 and 7) is determined by the tx/rx data i/o settings of the transceiver. si4420 5 typical application typical application with fifo usage c2 100p c3 10p x1 10mhz c1 1u si4420 1 3 4 2 5 7 6 8 9 10 11 12 13 14 15 16 vcc sck sdo nirq p4 p3 p1 p2 sdi clkin nsel nffs ffit nres pcb antenna microcontroller p5 p6 p7 nres c4 2.2n p0 clk (optional) tp (optional) (optional) (optional) (optional) (optional) vdi pin 6 pin 7 transmit mode el=0 in configuration setting command tx data input - transmit mode el=1 in configuration setting command connect to logic high - receive mode ef=0 in configuration setting command rx data output rx data clock output receive mode ef=1 in configuration setting command nffs input ffit output si4420 6 general device specifications all voltages are referenced to v ss , the potential on the ground reference pin vss. absolute maximum ratings (non-operating) symbol parameter min max units v dd positive supply voltage -0.5 6 v v in voltage on any pin (except rf1 and rf2) -0.5 v dd +0.5 v v oc voltage on open collector outputs (rf1, rf2) -0.5 v dd +1.5 (note 1) v i in input current into any pin except vdd and vss -25 25 ma esd electrostatic discharge with human body model 1000 v t st storage temperature -55 125 o c t ld lead temperature (soldering, max 10 s) 260 o c recommended operating range symbol parameter min max units v dd positive supply voltage 2.2 5.4 v v ocdc dc voltage on open collector outputs (rf1, rf2) v dd +1.5 (note 2) v v ocac ac peak voltage on open collector outputs (rf1, rf2) v dd -1.5 (note 1) vdd+1.5 v t op ambient operating temperature -40 85 o c note 1: at maximum, v dd +1.5 v cannot be higher th an 7 v. at minimum, v dd - 1.5 v cannot be lower than 1.2 v. note 2: at maximum, v dd +1.5 v cannot be higher than 5.5 v. si4420 7 electrical specification (min/max values are valid over the whole recommended operating range, typ conditions: t op = 27 o c; v dd = v oc = 2.7 v) dc characteristics symbol parameter conditions/notes min typ max units 315/433 mhz bands 13 14 868 mhz band 16 18 i dd_tx_0 supply current (tx mode, p out = 0 dbm) 915 mhz band 17 19 ma 315/433 mhz bands 21 22 868 mhz band 23 25 i dd_tx_pmax supply current (tx mode, p out = p max ) 915 mhz band 24 26 ma 315/433 mhz bands 11 13 868 mhz band 12 14 i dd_rx supply current (rx mode) 915 mhz band 13 15 ma i pd standby current (sleep mode) all blocks disabled 0.3 a i lb low battery voltage detector current consumption 0.5 a i wt wake-up timer current consumption 1.5 a i x idle current crystal oscillator and baseband parts are on 3 3.5 ma v lb low battery detect threshold programmable in 0.1 v steps 2.25 5.35 v v lba low battery detection accuracy +/-3 % v il digital input low level voltage 0.3*v dd v v ih digital input high level voltage 0.7*v dd v i il digital input current v il = 0 v -1 1 a i ih digital input current v ih = v dd , v dd = 5.4 v -1 1 a v ol digital output low level i ol = 2 ma 0.4 v v oh digital output high level i oh = -2 ma v dd -0.4 v si4420 8 ac characteristics (pll parameters) symbol parameter conditions/notes min typ max units f ref pll reference frequency (note 1) 8 10 12 mhz 315 mhz band, 2.5 khz resolution 310.24 319.75 433 mhz band, 2.5 khz resolution 430.24 439.75 868 mhz band, 5.0 khz resolution 860.48 879.51 f o receiver lo/transmitter carrier frequency 915 mhz band, 7.5 khz resolution 900.72 929.27 mhz frequency error < 1khz t lock pll lock time after 10 mhz step 20 s t st, p pll startup time with a running crystal oscillator 250 s ac characteristics (receiver) symbol parameter conditions/notes min typ max units mode 0 60 67 75 mode 1 120 134 150 mode 2 180 200 225 mode 3 240 270 300 mode 4 300 350 375 bw receiver bandwidth mode 5 360 400 450 khz br fsk bit rate with internal digital filters 0.6 115.2 kbps bra fsk bit rate with analog filter 256 kbps p min receiver sensitivity ber 10 -3 , bw=67 khz, br=1.2 kbps (note 2) -109 -100 dbm afc range afc locking range df fsk : fsk deviation in the received signal 0.8*df fsk iip3 inh input ip3 in band interferers in high bands (868, 915 mhz) -21 dbm iip3 outh input ip3 out of band interferers l f-f o l > 4 mhz -18 dbm iip3 inl iip3 (lna ?6 db gain) in band interferers in low bands (315, 433 mhz) -15 dbm iip3 outl iip3 (lna ?6 db gain) out of band interferers l f-f o l > 4 mhz -12 dbm p max maximum input power lna: high gain 0 dbm cin rf input capacitance 1 pf rs a rssi accuracy +/-5 db rs r rssi range 46 db c arssi filter capacitor for arssi 1 nf rs step rssi programmable level steps 6 db rs resp drssi response time until the rssi signal goes high after the input signal exceeds the preprogrammed limit c arrsi = 5 nf 500 s all notes for tables ab ove are on page 10. si4420 9 ac characteristics (transmitter) symbol parameter conditions/notes min typ max units i out open collector output dc current programmable 0.5 6 ma in low bands 8 p max available output power with optimal antenna impedance (note 3, 4) in high bands 4 dbm p out typical output power selectable in 2.5 db steps (note 5) p max -21 p max dbm p sp spurious emission at max power with loop antenna (note 6) -50 dbc in low bands 2 2.6 3.2 c o output capacitance (set by the automatic antenna tuning circuit) in high bands 2.1 2.7 3.3 pf in low bands 13 15 17 q o quality factor of the output capacitance in high bands 8 10 12 100 khz from carrier -75 l out output phase noise 1 mhz from carrier -85 dbc/hz br fsk bit rate 256 kbps df fsk fsk frequency deviation programmable in 15 khz steps 15 240 khz ac characteristics (turn-on/turnaround timings) symbol parameter conditions/notes min typ max units t sx crystal oscillator startup time cr ystal esr < 100 (note 8) 1 5 ms t tx_rx_xtal_on transmitter - receiver turnover time synthesizer off, crystal oscillator on during tx/rx change with 10 mhz step 450 s t rx_tx_xtal_on receiver - transmitter turnover time synthesizer off, crystal oscillator on during rx/tx change with 10 mhz step 350 s t tx_rx_synt_on transmitter - receiver turnover time synthesizer and crystal oscillator on during tx/rx change with 10 mhz step 425 s t rx_tx_synt_on receiver - transmitter turnover time synthesizer and crystal oscillator on during rx/tx change with 10 mhz step 300 s ac characteristics (others) symbol parameter conditions/notes min typ max units c xl crystal load capacitance, see crystal selection guide programmable in 0.5 pf steps, tolerance +/- 10% 8.5 16 pf t por internal por timeout after v dd has reached 90% of final value (note 7) 150 ms t pbt wake-up timer clock accuracy crystal oscillator must be enabled to ensure proper calibration at startup (note 8) +/-10 % c in, d digital input capacitance 2 pf t r, f digital output rise/fall time 15 pf pure capacitive load 10 ns all notes for tables ab ove are on page 10. si4420 10 ac characteristics (continued) note 1: not using a 10 mhz crystal is allowed but not recommended because all crystal referred timing and frequency parameters will change accordingly. note 2: see the ber diagrams in the measurement results section for detailed information (not available at this time). note 3: see matching circuit parameters and antenna design guide for information. note 4: optimal antenna admittance/impedance: si4420 yantenna [s] zantenna [ohm] lantenna [nh] 315 mhz 1.5e-3 - j5.14e-3 52 + j179 98.00 433 mhz 1.4e-3 - j7.1e-3 27 + j136 52.00 868 mhz 2e-3 - j1.5e-2 8.7 + j66 12.50 915 mhz 2.2e-3 - j1.55e-2 9 + j63 11.20 note 5: adjustable in 8 steps. note 6: with selective resonant antennas (see: application no tes available from www.silabs.com/integration ). note 7: during this period, commands are not accepted by the chip. for detailed information see the reset modes section. note 8: the crystal oscillator start-up time strongly depends on the capacitance seen by the oscillator. using low capacitance and low esr crystal is recommended. when designing the pcb layout keep the trace connecting to the crystal short to minimize stray capacitance. si4420 11 control interface commands (or tx data) to the transceiver are sent serially. data bits on pin sdi are shifted into the device upon the rising ed ge of the clock on pin sck whenever the chip select pin nsel is low. when the nsel signal is high, it initializes the serial interface. all com mands consist of a command code, followed by a va rying number of parameter or data bits. all da ta are sent msb first (e.g. bit 15 for a 16-bit c ommand). bits having no influence (don?t care) are indicated with x. the power on reset (por) circuit sets default values in all control and command registers. the status information or received data can be read serially over the sdo pin. bits are shifted out upon the falling edge of cl k signal. when the nsel is high, the sdo output is in a high impedance state. the receiver will generate an interrupt request (it) for the microcontroller - by pulling the nirq pin low - on the following e vents: ? the tx register is ready to receive the next byte (rgit) ? the fifo has received the preprogrammed amount of bits (ffit) ? power-on reset (por) ? fifo overflow (ffov) / tx register underrun (rgur) ? wake-up timer timeout (wkup) ? negative pulse on the interrupt input pin nint (ext) ? supply voltage below the preprogrammed value is detected (lbd) ffit and ffov are applicable when the fifo is enabled. rgit and rg ur are applicable only when the tx register is enabled. to id entify the source of the it, the status bits should be read out. timing specification symbol parameter minimum value [ns] t ch clock high time 25 t cl clock low time 25 t ss select setup time (nsel falling edge to sck rising edge) 10 t sh select hold time (sck falling edge to nsel rising edge) 10 t shi select high time 25 t ds data setup time (sdi transition to sck rising edge) 5 t dh data hold time (sck rising edge to sdi transition) 5 t od data delay time 10 timing diagram si4420 12 control commands control command related parameters/functions related control bits 1 configuration setting command frequency band, crystal oscillator load capacitance, tx register, rx fifo el, ef, b1 to b0, x3 to x0 2 power management command receiver/transmitter mode c hange, synthesizer, xtal osc, pa, wake-up timer, clock output can be enabled here er, ebb, et, es, ex, eb, ew, dc 3 frequency setting command frequency of the local oscillator/carrier signal f11 to f0 4 data rate command bit rate cs, r6 to r0 5 receiver control command function of pin 16, valid data indicator, baseband bw, lna gain, digital rssi threshold p16, d1 to d0, i2 to i0, g1 to g0, r2 to r0 6 data filter command data filter type, clo ck recovery parameters al, ml, s, f2 to f0 7 fifo and reset mode command data fifo it level, fifo start control, fifo enable and fifo fill enable f3 to f0, al, ff, dr 8 receiver fifo read command rx fifo can be read with this command 9 afc command afc parameters a1 to a0, rl1 to rl0, st, fi, oe, en 10 tx configuration control command modulation parameters, output power, ea mp, m3 to m0, p2 to p0 11 transmitter register write command tx data regist er can be written with this command t7 to t0 12 wake-up timer command wake-up time period r4 to r0, m7 to m0 13 low duty-cycle command enable low duty-cycle mode. set duty-cycle. d6 to d0, en 14 low battery detector and microcontroller clock divider command lbd voltage and microcontroller clock division ratio d2 to d0, v4 to v0 15 status read command status bits can be read out in general, setting the given bit to one will activate the related function. in the following tables, the por column shows the default values of the command registers after power-on. description of the control commands 1. configuration setting command bit1514131211109876543210 por 10000000elefb1b0x3x2x1x0 8008h bit el enables the internal data register. if the data register is used the fsk pin must be connected to logic high level. bit ef enables the fifo mode. if ef =0 then data (pin 6) and dclk (pin 7) are used for data and data clock output. b1 b0 frequency band {mhz] 0 0 315 0 1 433 1 0 868 1 1 915 x3 x2 x1 x0 crystal load capacitance [pf] 0000 8.5 0001 9.0 0010 9.5 0011 10.0 1110 15.5 1111 16.0 ? si4420 13 2. power management command bit1514131211109876543210 por 10000010erebbetesexebewdc 8208h bit function of the control bit related blocks er enables the whole receiver chain rf front end, baseband, synthesizer, oscillator ebb the receiver baseband circuit c an be separately switched on baseband et switches on the pll, the power amplifier, and starts the transmission (if tx register is enabled) power amplifier, synthesizer, oscillator es turns on the synthesizer synthesizer ex turns on the crystal oscillator crystal oscillator eb enables the low battery detector low battery detector ew enables the wake-up timer wake-up timer dc disables the clock output (pin 8) clock output buffer the ebb, es, and ex bits are provided to optimize the tx to rx or rx to tx turnaround time. logic connections between power control bits: edge detector et er es ebb ex enable oscillator enable baseband circuits enable rf front end enable rf synthesizer start tx clear tx latch (if tx latch is used) (synt. must be on) (osc.must be on) enable power amplifier si4420 14 3. frequency setting command bit1514131211109876543210 por 1 0 1 0f11f10f9f8f7f6f5f4f3f2f1f0 a680h the 12-bit parameter f (bits f11 to f0 ) should be in the range of 96 and 3903. when f value sent is out of range, the previous value is kept. the synthesizer center frequency f 0 can be calculated as: f 0 = 10 * c1 * (c2 + f/4000) [mhz] the constants c1 and c2 are determined by the selected band as: ban d [ m hz ] c1 c2 315 1 31 433 1 43 868 2 43 915 3 30 4. data rate command bi t 1514131211109876543210 por 11000110csr6r5r4r3r2r1r0 c623h the actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit parameter r (bits r6 to r0 ) and bit cs . br = 10000 / 29 / (r+1) / (1+ cs *7) [kbps] in the receiver set r according to the next function: r= (10000 / 29 / (1+ cs *7) / br) ? 1, where br is the expected bit rate in kbps. apart from setting cu stom values, the standard bit rates from 600 bps to 115.2 kbps can be approxim ated with small error. data rate accuracy requirements: clock recovery in slow mode: ? br / br < 1 / (29*n bit ) clock recovery in fast mode: ? br / br < 3 / (29*n bit ) br is the bit rate set in the receiver and ? br is the bit rate difference between the transmitter and the receiver. n bit is the maximal number of consecutive ones or zeros in the data stream. it is recommended for long data packets to include enough 1/0 and 0/1 transitions , and be careful to use the same division ratio in the receiver and in the transmitter. 5. power setting command bit1514131211109876543210 por 1 0 0 1 0p16d1d0i2 i1 i0g1g0r2r1r0 9080h bit 10 (p16) : pin16 functi on select p16 function of pin 16 0 interrupt input 1 vdi output si4420 15 bits 9-8 (d1 to d0) : vdi (valid data indicator) signal response time setting: d1 d0 response 0 0f a s t 0 1 medium 1 0slow 1 1 always on d0 r/s ff logic high d1 cr_lock drssi dqd in0 in1 in2 in3 sel1 sel0 y q cr_lock dqd cr_lock dqd drssi set clr vdi mux fast medium slow bits 7-5 (i2 to i0) : receiver baseband bandwidth (bw) select: i2 i1 i0 bw [khz] 000 reserved 001 400 010 340 011 270 100 200 101 134 110 67 111 reserved si4420 16 bits 4-3 (g1 to g0) : lna gain select: g1 g0 relative to maximum [db] 00 0 01 -6 10 -14 11 -20 bits 2-0 (r2 to r0) : rssi detector threshold: r2 r1 r0 rssi setth [dbm] 0 00 -103 0 01 -97 0 10 -91 0 11 -85 1 00 -79 1 01 -73 1 10 reserved 1 11 reserved the rssi threshold depends on the lna gain, the real rssi threshold can be calculated: rssi th =rssi setth +g lna 6. data filter command bit 15 14131211109876543210 por 1 1000010alml1s1f2f1f0 c22ch bit 7 ( al ): clock recovery (cr) auto lock control, if set. cr will start in fast mode, then after locking it will automatically switch to slow mode. bit 6 ( ml ): clock recovery lock control 1: fast mode, fast attack and fast release (6 to 8 bit preamble (1010. ..) is recommended) 0: slow mode, slow attack and slow releas e (12 to 16 bit preamb le is recommended) using the slow mode requires more accurate bit timing (see data rate command ). bits 4 ( s ): select the type of the data filter: s filter type 0 digital filte r 1 analog rc filte r digital: this is a digital realization of an analog rc filter followed by a comparator with hysteresis. the time constant is automatically adjusted to the bit rate defined by the data rate command . note: bit rate can not exceed 115 kpbs in this mode. analog rc filter: the demodulator output is fed to pin 7 over a 10 kohm resistor. the filter cut-off frequency is set by the e xternal capacitor connected to this pin and vss. c = 1 / (3 * r * bit rate) , therefore the suggested value for 9600 bps is 3.3 nf note: if analog rc filter is selected the internal clock recovery circuit and the fifo can not be used. si4420 17 bits 2-0 ( f2 to f0 ): dqd threshold parameter. note : to let the dqd report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is close to the deviation. at higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as well. 7. fifo and reset mode command bit1514131211109876543210 por 11001010f3f2f1f00alffdr ca80h bits 7-4 ( f3 to f0 ): fifo it level. the fifo generates it when the number of received data bits reaches this level. bit 2 ( al ): set the input of the fifo fill start condition: al 0 synchron pattern 1 always fill note: synchron pattern in microcontroller mode is 2dd4h. ef* note: * for details see the configuration setting command ** for deatils see the power management command ff er** ffit nfifo_reset ffov synchron pattern al fifo_write _en fifo_logic bit 1 ( ff ): fifo fill will be enabled after synchron pattern reception. the fifo fill stops when this bit is cleared. bit 0 ( dr ): disables the highly sensitive reset mode. if this bit is cleared, a 600 mv glit ch in the power supply may caus e a system res et. for more detailed description see the reset modes section. note: to restart the synchron pattern recognition, bit 1 should be cleared and set. si4420 18 8. receiver fifo read command bit1514131211109876543210 por 1011000000000000 b000h with this command, the controller can read 8 bits from the receiver fifo. bit 6 (ef) must be set in configuration setting command. nsel sck sdi sdo 0 123456 received bits out ffit in rx mode / rgit otherwise msb lsb 7 8 9 10 11 12 13 14 15 note: the transceiver is in receive (rx) mode when bit er is set using the power management command 9. afc command bit 15 14131211109876543210 por 1 1000100a1a0rl1rl0stfioeen c4f7h bit 7-6 ( a1 to a0 ): automatic operation mode selector: a1 a0 00 auto mode off (strobe is controlled by microcontroller) 01 runs only once after each power-up 10 keep the f offset only during receiving 11 keep the f offset value bit 5-4 (rl1 to rl0) : range limit. limits the value of the frequency offset register to the next values: rl1 rl0 max deviation 0 0 no restriction 01 +15 f res to -16 f res 10 +7 f res to -8 f res 11 +3 f res to -4 f res f res : 315, 433 mhz bands: 2.5 khz 868 mhz band: 5 khz 915 mhz band: 7.5 khz bit 3 (st) : strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the afc block. bit 2 ( fi ): switches the circuit to high accuracy (fine) mode. in this case, the processing time is about twice longer, but the measurem ent uncertainty is about the half. bit 1 ( oe ): enables the frequency offset register. it allows the addition of the offset register to the frequency control word of the pl l. bit 0 ( en ): enables the calculation of the offset frequency by the afc circuit. si4420 19 oe 10mhz clk digital afc core logic st fi en parameter from frequency control word f<11:0> vdi* a1 to a0 /4 digital limiter if in>maxdev then out=maxdev if in si4420 20 bits 8-4 (mp, m3 to m0) : fsk modulation parameters: the resulting output frequency can be calculated as: f out = f 0 + (-1) sign * (m + 1) * (15 khz) where: f 0 is the channel center frequency (see the frequency setting command ) m is the four bit binary number < m3 : m0> sign = ( mp ) xor (fsk input) bits 2-0 (p2 to p0) : output power: p2 p1 p0 relative output power [db] 000 0 001 -3 010 -6 011 -9 100 -12 101 -15 110 -18 111 -21 out f out p 0 f fsk df fsk df mp=0 and fsk=0 mp=1 and fsk=1 mp=1 and fsk=0 mp=0 and fsk=1 or or the output power given in the table is relative to the maximum available power, which depends on the actual antenna impedance. (see: antenna applicatio n note: ia ism-an1) 11. transmitter register write command bit1514131211109876543210 por 10111000t7t6t5t4t3t2t1t0 b8aah with this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. bit 7 (el) must be set in configuration setting command. 12. wake-up timer command bit1514131211109876543210 por 1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 e196h the wake-up time period can be calculated by ( m7 to m0 ) and ( r4 to r0 ): t wake-up = m * 2 r [ms] note: ? for continual operation the et bit should be cleared and set at the end of every cycle. ? for future compatibility, use r in a range of 0 and 29. software reset: sending fe00h command to the chip triggers software reset. for more details see the reset modes section. si4420 21 13. low duty-cycle command bit 15 14131211109876543210 por 1 1001000d6d5d4d3d2d1d0en c80eh with this command, low duty-cycle operation can be set in order to decrease the average power consumption in receiver mode. the time cycle is determined by the wake-up timer command . the duty-cycle can be calculated by using ( d6 to d0 ) and m. (m is parameter in a wake-up timer command .) duty-cycle= (d * 2 +1) / m *100% receiver on dqd twake-up xtal osc. enable 2.25ms ton twake-up ton twake-up ton 2.25ms bit 0 (en) : enables the low duty-cycle mode. wake-up timer interrupt not generated in this mode. note: in this operation mode, bit er must be cleared and bit ew must be set in the power management command. 14. low battery detector and microcontroller clock divider command bit 15 14131211109876543210 por 1 1000000d2d1d0v4v3v2v1v0 c000h the 5 bit parameter (v4 to v0) represents the value v, which defines the threshold voltage v lb of the detector: v lb = 2.25 + v * 0.1 [v] clock divider configuration: clock output frequency [mhz] 000 1 001 1.25 010 1.66 011 2 100 2.5 101 3.33 110 5 111 10 d2 d1 d0 the low battery detector and the clock outp ut can be enabled or disabled by bits eb and dc, respectively, using the power management command. si4420 22 15. status read command the read command starts with a zero, whereas all other control commands start with a one. if a read command is identified, the status bits will be clocked out on the sdo pin as follows: status register read sequence with fifo read example: rgit tx register is ready to receive the next byte (can be cleared by transmitter register write command ) ffit the number of data bits in the rx fifo has reached the pre-programmed limit (can be cleared by any of the fifo read methods) por power-on reset (cleared after status read command ) rgur tx register under run, r egister over write (cleared after status read command ) ffov rx fifo overflow (cleared after status read command ) wkup wake-up timer overflow (cleared after status read command ) ext logic level on interrupt pin (pin 16) changed to low (cleared after status read command ) lbd low battery detect, the power supply voltage is below the pre-programmed limit ffem fifo is empty ats antenna tuning circuit detected strong enough rf signal rssi the strength of the incoming signal is above the pre-programmed limit dqd data quality detector output crl clock recovery locked atgl toggling in each afc cycle offs(6) msb of the measured frequency o ffset (sign of the offset value) offs(3) -offs(0) offset value to be added to the val ue of the frequency control parameter (four lsb bits) si4420 23 tx register buffered data transmission in this operating mode (enabled by bit el, the configuration control command ) the tx data is clocked into one of the two 8-bit data registers. the transmitter starts to send out the data from the first register (with the given bit rate) when bit et is set with the power management command . the initial value of the data registers (aah) can be used to generate preamble. during this mode, the sdo pin can be monitore d to check whether the register is ready (sdo is high) to receive the next byte from the microcontroller. tx register simplified block diagram (before transmit) tx register simplified block diagram (during transmit) typical tx register usage note: the content of the data registers are initialized by clearing bit et . si4420 24 rx fifo buffered data read in this operating mode, incoming data are clocked into a 16 bit fi fo buffer. the receiver starts to fill up the fifo when the v alid data indicator (vdi) bit and the synchron pattern recognition circuit indicates potentially real incoming data. this prevents the fi fo from being filled with noise and overloading the external microcontroller. polling mode: the nffs signal selects the buffer directly and its content can be clocked out through pin sdo by sck. set the fifo it level to 1. in this case, as long as ffit indicates received bits in the fifo, the controller may continue to take the bits away. when ffit goes low, no more bits need to be taken. an spi read command is also available. interrupt controlled mode: the user can define the fifo level (the number of received bits ), which will generate the nffit when exceeded. the status bits report the changed fifo status in this case. fifo read example with ffit polling nsel sck nffs sdo 0 1234 fo+1 fo+2 fifo out fo+4 fo+3 fifo read out ffit during fifo access f sck cannot be higher than f ref /4, where f ref is the crystal oscillator frequency. si4420 25 crystal selection guidelines the crystal oscillator of the si4420 requires a 10 mhz parallel mo de crystal. the circuit contains an integrated load capacitor in order to minimize the external component count. the internal load capacitance value is programmable from 8.5 pf to 16 pf in 0.5 pf steps . with appropriate pcb layout, the total load capacitance value can be 10 pf to 20 pf so a variety of crystal types can be used. when the total load capacitance is not more than 20 pf and a worst case 7 pf shunt capacitance (c 0 ) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 300 ohms esr (equivalent series loss resistance). however, low er c 0 and esr values guarantee faster oscillator startup. the crystal frequency is used as the reference of the pll, which generates the local oscillator frequency (f lo ). therefore f lo is directly proportional to the crystal frequency. the accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable local oscillator frequency error. whenever a low frequency error is essential for the application, it is possible to ?pull? the crystal to the accurate frequency by changing the load capacitor value. the widest pulling range can be achieved if the nominal required load capacitance of the crystal is in th e ?midrange?, for example 16 pf. the ?pull-ability? of the crystal is defined by its motional capacitance and c 0 . maximum xtal tolerances including temperature and aging [ppm] bit rate: 2.4kbps 30 45 60 75 90 105 120 315 mhz 25 50 75 100 100 100 100 433 mhz 20 30 50 70 90 100 100 868 mhz 10 20 25 30 40 50 60 915 mhz 10 15 25 30 40 50 50 bit rate: 9.6kbps 30 45 60 75 90 105 120 315 mhz 20 50 70 75 100 100 100 433 mhz 15 30 50 70 80 100 100 868 mhz 8 152530405060 915 mhz 8 152530405050 bit rate: 38.3kbps 30 45 60 75 90 105 120 315 mhz don't use 7 30 50 75 100 100 433 mhz don't use 5 20 30 50 75 75 868 mhz don't use 3 10 20 25 30 40 915 mhz don't use 3 10 15 25 30 40 deviation [+/- khz] deviation [+/- khz] deviation [+/- khz] si4420 26 reset modes the chip will enter into reset mode if any of the following conditions are met: ? power-on reset: during a power up sequence until the v dd has reached the correct level and stabilized ? power glitch reset: transients present on the v dd line ? software reset: special control command received by the chip ? hardware reset: nres input activated power-on reset after power up the supply voltage starts to rise from 0v. the reset block has an internal ramping voltage reference (reset-ramp signal), which is rising at 100mv/ms (typical) rate. the chip remains in reset state while the voltage difference between the actual v dd and the internal reset-ramp signal is higher than th e reset threshold voltage, which is 600 mv (typical). as long as the v dd voltage is less than 1.6v (typical) the chip stays in reset mode regardless the voltage difference between the v dd and the internal ramp signal. the reset event can last up to 150ms supposing that the v dd reaches 90% its final value within 1ms. during this period the chip does not accept control commands via the serial control interface. power-on reset example: power glitch reset the internal reset block has two basic mode of operation: normal and sensitive reset. the default mode is sensitive, which can be changed by the appropriate control command (see related control commands at the end of this section). in normal mode the power glitch detection circuit is disabled. there can be spikes or glitches on the v dd line if the supply filtering is not satisfactory or the internal resistance of the power supply is too high. in such cases if the sensitive reset is enabled an (unwanted) reset will be generated if the positive going edge of the v dd has a rising rate greater than 100mv/ms and the voltage difference between the internal ramp signal and the v dd reaches the reset threshold voltage (600 mv). typical case when the battery is weak and due to its increased internal resistance a sudden decrease of the current c onsumption (for example turning off the power amplifier) might lead to an increase in supply voltage. if for some reason the sensitive res et cannot be disabled step-by-step decrease of the current consumption (by tu rning off the different stages one by one) can help to avoid th is problem. any negative change in the supply voltage will not cause reset event unless the v dd level reaches the reset threshold voltage (250mv in normal mode, 1.6v in sensitive reset mode). if the sensitive mode is disabled and the power supply turned off the v dd must drop below 250mv in order to trigger a power-on reset event when the supply voltage is turned back on. if the decoupling ca pacitors keep their charges for a long time it could happen that no reset will be generated upon power-up because the power glitch detector circuit is disabled. note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again. si4420 27 sensitive reset enabled, ripple on v dd : time v dd reset threshold voltage (600mv) nres output h l 1.6v reset ramp line (100mv/ms) sensitive reset disabled: time v dd reset threshold voltage (600mv) nres output h l 250mv reset ramp line (100mv/ms) hardware reset the hardware reset puts the controller and the corresponding analog circuits into their default state and loads the power-on va lues of the registers. this mode can be activated by pu lling the nres input (pin 10) to logic low for at least 1us. the chip is ready for o peration 1ms after releasing (setting to logic h) the nres pin. software reset software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. the result of the command is the same as if power-on reset was occurred. when the nres pin connected to the reset pin of the microcontroller, usi ng the software reset command may cause unexpected problems. v dd line filtering during the reset event (caused by power-on, fast positive spike on the supply line or software reset command) it is very important to keep the v dd line as smooth as possible. noise or periodic disturbing sign al superimposed the supply voltage may prevent the part getting o ut from reset state. to avoid this phenomenon use adequate filtering on the power supply line to keep the level of the disturbing signal below 10mv p-p in the dc ? 50khz range for 200ms from v dd ramp start.. typical example when a switch-m ode regulator is used to supply the radio, switching noise may be present on the v dd line. follow the manufacturer?s recommendations how to decrease the ripple of the regulator ic and/or how to shift the switching frequency. related control commands ?fifo and reset mode command? setting bit<0> to high will change the reset mode to no rmal from the de fault sensitive. ?sw reset command? issuing fe00h command will trigger software reset. see the wake-up timer command . si4420 28 rx-tx alignment procedures rx-tx frequency offset can be caused only by the differences in the actual reference frequency. to minimize these errors it is suggested to use the same crystal type and the same pcb layout for the crystal placement on the rx and tx pcbs. to verify the possible rx-tx offset it is suggested to measure the clk output of both chips with a high level of accuracy. do n ot measure the output at the xtl pin since the measurement process itself will change the reference frequency. since the carrier frequencies are derived from the reference frequency, having identical reference frequenc ies and nominal frequency settings at the tx and rx side there should be no offset if the clk signals have identical frequencies. it is possible to monitor the actual rx-tx offset using the afc status report included in the status byte of the receiver. by r eading out the status byte from the receiver the actual measured offset frequency will be reported. in order to get accurate values the afc ha s to be disabled during the read by clearing the "en" bit in the afc control command (bit 0). typical applications repeater demo (915 mhz) schematics 6v 3,3v p0.0 2 p0.1 1 p0.2 28 p0.3 27 p0.4 26 p0.5 25 p0.6 24 p0.7 23 p1.0 22 p1.1 21 p1.2 20 p1.3 19 p1.4 18 p1.5 17 p1.6 16 p1.7 15 p2.0 14 p2.1 13 p2.2 12 p2.3 11 p2.4 10 p2.5 9 p2.6 8 p2.7 7 p3.0/c2d 6 /rst/c2ck 5 vdd 4 gnd 3 ic1 r1 r2 5 3 4 1 sw1 6 r3 r4 r5 r6 d1 d2 d3 d4 c1 21 sj1 r7 1 2 3 j1 1 2 3 debug c2 q1 1 2 34 5 ic3 gnd in on out pok r8 c3 c4 1 2 battery c5 c6 c7 l1 l3 c8 c9 x1 sdi 1 sck 2 nsel 3 sdo 4 nirq 5 fsk/data/nffs 6 dclk/cfil 7 nint/vdi 16 xtl/ref 9 clk 8 vss 11 rf2 12 rf1 13 vdd 14 arssi 15 nres 10 ic2 tx tx rx rx sel sel clk clk irq irq sck sck miso miso mosi mosi ffs ffs ffe ffe int/vdi int/vdi arssi arssi c8051f311 gnd vcc gnd 820 820 820 820 red green yellow red vcc gnd gnd vcc 100nf gnd gnd 1k 4,7nf 10mhz gnd gnd gnd vcc gnd ia2112-3.3v 100k 2,2uf 2,2uf vcc 1uf 100pf 10pf vcc gnd vcc gnd gnd ia4420-revc si4420 29 pcb layout top view bottom view si4420 30 package information 16-pin tssop detail ?a? gauge plane 0. 2 5 section b-b see detail ?a? min. nom. max. min. nom. max. 740,0 02,1 a 600,0 200,0 51,0 50,0 1a a2 0,80 0,90 1,05 0,031 0,035 0,041 210,0 700,0 03,0 91,0 b b1 0,19 0,22 0,25 0,007 0,009 0,010 800,0 400,0 02,0 90,0 c 600,0 400,0 61,0 90,0 1c d 4,90 5,00 5,10 0,193 0,197 0,201 e e e1 4,30 4,40 4,50 0,169 0,173 0,177 l 0,50 0,60 0,75 0,020 0,024 0,030 l1 400,0 90,0 r 400,0 90,0 1r 8 0 8 0 1 2 3 symbol dimensions in mm dimensions in inches .csb620.0 .csb56.0 6.40 bsc. 12 ref. 12 ref. 12 ref. 12 ref. 1.00 ref. 0.252 bsc. 0.39 ref. si4420 31 this page has been intentionally left blank. si4420 32 related products and documents si4420 universal ism band fsk transceiver description ordering number si4420 16-pin tssop si4420-ic cc16 rev d1 demo boards and development kits description ordering number development kit ia ism ? dk ism repeater demo ia ism ? darp related resources description ordering number antenna selection guide ia ism ? an1 antenna development guide ia ism ? an2 si4220/21 universal ism band fsk transmitters see www.silabs.com for details si4320 universal ism band fsk receiver see www.silabs.com for details note: volume orders must include chip revision to be accepted. silicon labs, inc. 400 west cesar chavez austin, texas 78701 tel: 512.416.8500 fax: 512.416.9669 toll free: 877.444.3032 www.silabs.com wireless@silabs.com the specifications and descriptions in this document are based on information available at the time of publication and are subject to change without notice. silicon laboratories assumes no responsibility for errors or omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes to the product and its documentation at any time. silicon laboratories makes no representations, warranties, or guarant ees regarding the suitability of its products for any particular purpose and does not assume any liability arising out of the application or use of an y product or circuit, and specifically disclaims any and all liability for c onsequential or incidental damages arising out of use or failure of the product. nothing in this document shall operate as an express or implied license or i ndemnity under the intellectual property rights of silicon laboratories or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. no warranties of any kind, including but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . ?2008 silicon laboratories, inc. all rights reserved. silicon laboratories is a trademark of silicon laboratories, inc. all other trademarks belong to their respective owners. mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: silicon laboratories: ? si4420-d1-ftr? si4420-d1-ft? 4420-DKDB2? 4420-dkdb1 |
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