View EVAL-ADRF6850EB1Z_7669351.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

100 mhz to 1000 mhz integrated broadband receiver adrf6850 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. features iq quadrature demodulator integrated fractional -n pll and vco gain control range: 60 db input frequency range: 100 mhz to 1000 mhz input p1db: +12 dbm at 0 db gain input ip3 : + 22.5 dbm at 0 db gain n oise figure : 11 db at > 39 db gain, 49 db at 0 d b gain baseband 1 db bandwidth: 250 mhz in wideband mode, 50 mhz in narrow - band mode spi/i 2 c serial interface power supply: +3.3 v/350 ma applications broadband co mmunications cellular c ommunications satellite c ommunications general description the adrf68 50 is a highly integrated broadband quadrature demodulator, frequency synthesizer, and variable gain amplifier (vga). the device covers an operating frequency range from 100 mhz to 1000 mhz for use in both narrow - band and wide band communications applicatio ns, performing quadrature demodu - lation from if directly to baseband frequencies. the adrf6850 demodulator includes a high modulus fractional - n frequency synthesizer with integrated vco, providing better than 1 hz frequency resolution, and a 60 db gain co ntrol range provided by a front - end vga. control of all the on - chip registers is through a user - selected spi interface or i 2 c interface. the device operates from a single power supply ranging from 3.15 v to 3.45 v. functional block dia gram qbb qbb r set sdi/sda clk/scl sdo cs gnd muxout 2 doubler 5-bit divider reference charge pum p current setting refin 2 phase frequenc y detect or sequenced gain inter f ace + ? driver vco core 0 /9 0 vcc1 vcc2 vcc3 vcc4 vcc5 vcc6 vcc7 vcc8 vcc9 lomon lomon adrf6850 rfi rfi rfcm vgain 60db gain contro l range n-counter integer register fractiona l register modulus 2 25 third-order fractiona l interpol at or rfcp4 rfcp3 rfcp2 rfcp1 cp lf3 lf2 ldet testlo testlo ibb ibb ccomp1 ccomp2 ccomp3 vtune vocm spi/ i 2 c inter f ace 09316-001 rfdiv figure 1.
adrf6850 rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 18 overview ...................................................................................... 18 pll synthesizer and vco ......................................................... 18 quadrature demodulator .......................................................... 20 variable gain amplifier (vga) ............................................... 20 i 2 c interface ................................................................................ 20 spi interface ................................................................................ 22 program modes .......................................................................... 24 register map ................................................................................... 26 register map summary ............................................................. 26 register bit descriptions ........................................................... 27 suggested power - up sequence ..................................................... 30 initial register write sequence ................................................ 30 evaluation board ............................................................................ 31 general descr iption ................................................................... 31 hardware description ............................................................... 31 pcb schematic ............................................................................ 33 pcb artwork ............................................................................... 34 bill of materials ........................................................................... 35 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 36 revision history 10/ 10 rev ision 0: initial version
adrf6850 rev. 0 | page 3 of 36 specifications v cc = 3.3 v; a mbient temperature (t a ) = 25c; z s = 50 ?; z l = 100 differential ; pll l oop bandwidth = 50 khz; refin = 13.5 mhz; pfd = 27 mhz; b aseband fr equency = 2 0 mhz, n arrow - band mode, unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit rf input rfi , rfi , vgain pins operating frequency range 100 1000 mhz input p1db 0 db gain +12 dbm 60 db gain ?48 dbm input ip3 0 db gain +2 2.5 dbm 60 db gain ?3 8 dbm input ip2 0 db gain, single - ended input + 40 dbm 60 db gain, single - ended input ?20 dbm noise figure (nf) 0 db gain 49 db <39 db gain nf rises 1:1 as gain in db falls >39 db gain 11 db maximum gain z s = 50 ? single - ended, z l = 100 ? differential 60 db minimum gain z s = 50 ? single - ended, z l = 100 ? differential 0 db gain conformance error 1 v gain from 200 mv to 1.3 v 0.5 db gain slope 25 mv/db v gain input impe dance 20 k? return loss rel ative to z s = 50 ? , 100 mhz to 1 ghz 15 db reference characteristics refin pin input frequency with r divide -by - 2 divider enabled 10 300 mhz with r divide -by - 2 divider disabled 10 165 mhz ref in input sensitivity 0.4 v cc v p -p ref in input capacitance 10 pf ref in input current 100 a charge pump cp and rset pins i cp sink/source programmable high value with r set = 4.7 k ? 5 ma low value 312.5 a absolute accuracy with r set = 4.7 k ? 2.5 % vco gain k vco 15 mhz/v synthesizer specifications loop bandwidth = 50 khz frequency increment 1 hz phase frequency detector 10 30 mhz spurs integer boundary < loop bandwidth ? 55 dbc >10 mhz offset from carrier ? 70 dbc phase noise lo frequency = 1000 mhz @ 10 hz offset ? 75 dbc/hz @ 100 hz offset ?80 dbc/hz @ 1 khz offset ? 90 dbc/hz @ 10 khz offset ? 98 dbc/hz @ 100 khz offset ? 110 dbc/hz @ 1 mhz offset ? 136 dbc/hz >10 mhz offset ? 149 dbc/h z integrated phase noise 1 khz to 8 mhz integration bandwidth 0.26 rms
adrf6850 rev. 0 | page 4 of 36 parameter test conditions/comments min typ max unit frequency settling any step size, maximum frequency error = 1 khz 260 s maximum frequency step for no autocalibration frequency step with no autocalibration routine; register c r24, bit 0 = 1 100 khz baseband outputs ibb, ibb , qbb, qbb , vocm pins maximum swing driving z l = 100 ? differential 2 .5 v p -p common - mode range 1.2 1.6 v output impedance differential 28 ? output dc of fset rf i terminated in z s = 50 ? 20 mv 1 db bandwidth wideband mode 250 mhz narrow - band mode 50 mhz iq balance amplitude wideband mode baseband frequency 250 mhz 0.1 db narrow - band mode baseband frequency 33.2 mhz 0. 1 db phase wideband mode baseband frequency 250 mhz 0.5 degrees narrow - band mode baseband frequency 33.2 mhz 0.25 degrees iq output impedance mismatch baseband frequency = 10 mhz 0.3 % group delay variation wideband mode baseb and f requency 210 mhz 0.25 ns baseband f requency 250 mhz 0.35 ns narrow - band mode baseband f requency 33.2 mhz 0. 2 ns lo to iq leakage 1 lo ?40 dbm 2 lo ?60 dbm 4 lo ?60 dbm rf to iq leakage relative to iq output level ? 40 dbc monitor output lomon and lomon pins nominal output power ?24 dbm logic inputs sdi/sda, clk/scl, cs pins input high voltage , v inh cs 1.4 v input low voltage , v inl cs 0.6 v i nput high voltage , v inh sdi/sda , cl k/scl 2.1 v input low voltage , v inl sdi/sd a, cl k/s cl 1.1 v input current , i inh /i inl cs, sdi/sda, cl k/s cl 1 a input capacitance , c in cs, sdi/sda, cl k/s cl 10 pf logic outputs output high voltage, v oh sdo, ldet pins; i oh = 500 a 2.8 v outp ut low voltage, v ol sdo, ldet pins; i ol = 500 a 0.4 v sda (sdi/sda) pins ; i ol = 3 ma 0.4 v power supplies vcc1, vcc2, vcc3, vcc4 , vcc5, vc c6, vcc7, vcc8, and vcc9 pins voltage range 3.15 3.3 3.45 v supply current 350 4 40 ma operating temp erature ?40 +85 c 1 difference between channel gain and linear fit to channel gain .
adrf6850 rev. 0 | page 5 of 36 timing characteristi cs i 2 c interface timing table 2 . parameter 1 symbol limit unit scl clock frequency f scl 400 khz max scl pulse width high t high 600 ns min scl pulse width low t low 1300 ns min start con dition hold time t hd;sta 600 ns min start condition setup time t su;sta 600 ns min data setup time t su;dat 100 ns min data hold time t hd; dat 300 ns min stop condition setup time t su;sto 600 ns min data valid time t vd;dat 900 ns max data valid acknowle dge time t vd;ack 900 ns max bus free time t buf 1300 ns min 1 see figure 2 . sda t hd;sta t su;dat start condition stop condition s s s p scl 1/ f scl t high t low t hd;dat t vd;dat and t vd;ack (ack signal only) t buf t su;sto t su;sta 09316-002 figure 2. i 2 c port timing diagram
adrf6850 rev. 0 | page 6 of 36 spi interface timing table 3 . parameter 1 symbol limit unit clk frequency f clk 20 mhz max clk pulse width high t 1 15 ns min clk pulse width low t 2 15 ns min start condition hold time t 3 5 ns min data setup time t 4 10 ns min data hold time t 5 5 ns min stop condition setup time t 6 5 ns min sdo access time t 7 15 ns min cs to sdo high impedance t 8 25 ns ma x 1 see figure 3 . t 1 t 3 cs clk sdi sdo t 6 t 8 t 7 t 2 t 5 t 4 09316-003 figure 3 . spi port timing diagram
adrf6850 rev. 0 | page 7 of 36 absolute maximum rat ings table 4 . absolute maximum ratings parameter rating supply voltage pins ( vcc1, vcc2, vcc3, vcc4, vcc5, vcc6, vcc7, vcc8, vcc9 ) ? 0.3 v to +4.0 v analog i nput /o utput ?0.3 v to + 4.0 v digital i nput /o utput ?0.3 v to + 4.0 v rfi, rfi , rfcm 0 v to 3 .0 v ja (exposed paddle soldered down) 26c/w maximum junction temperature 125c storage temperature range ? 65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adrf6850 rev. 0 | page 8 of 36 pin configuration and function descripti ons pin 1 indic at or 1 vcc1 2 ibb 3 ibb 4 qbb 5 qbb 6 gnd 7 vocm 8 gnd 9r set 10 lf3 11cp 12 lf2 13vcc2 14vcc3 35 ccomp3 36 vcc7 37 gnd 38 vtune 39 muxout 40 ldet 41 gnd 42 vcc8 34 ccomp2 33 ccomp1 32 gnd 31 vcc6 30 clk/sc l 29 sdi/sda 15vcc4 16vcc5 17 refin 19gnd 21gnd 20gnd 22 testlo 23 testlo 24gnd 25 lomon 26 lomon 27cs 28sdo 18 refin 45 gnd 46 gnd 47 gnd 48 gnd 49 vcc9 50 g nd 51 rfi 52 gnd 53 rfcm 54 gnd 44 gnd 43 vgain top view (not to scale) adrf6850 55 rfi 56 gnd notes 1. connect exposed pad to ground plane via a low impedance path. 09316-004 figure 4. pin configurati on table 5 . pin function descriptions pin no. mnemonic description 1, 13, 14, 15, 16, 31, 36, 42, 49 vcc1 to vcc9 positive power supplies . apply a 3.3 v power supply to all vcc x pins. decouple each pin with a power supply decouplin g capacitor. 6, 8, 19, 20, 21, 24, 32, 37, 41, 44, 45, 46, 47, 48, 50, 52, 54, 56 gnd analog ground. connect to a low impedance ground plane. 2, 3, 4, 5 ibb , ibb, qbb, qbb differential in - phase and quadrature baseband outputs . these low impedance outputs can drive 2 .5 v p- p in to 100 ? differential loads. 7 vocm baseband common - mode voltage input. when ac coupling the baseband output pins, ground vocm. there is an option to apply an external voltage, which may be relev ant when dc coupling the baseband output pins. note that register cr29, bit 6 must be set accordingly. 33 cco mp1 internal compensation node . this pin must be decoupled to ground with a 100 nf capacitor. 34 ccomp2 internal compensation node. this pin mus t be decoupled to ground with a 100 nf capacitor. 35 ccomp3 internal compensation node. this pin must be decoupled to ground with a 100 nf capacitor . 38 vtune control input to the vco . this voltage determines the output frequency and is derived from fil tering the cp output voltage. 9 rset charge pump current set . connecting a resistor between this pin and ground sets the maximum charge pump output current. the relationship between i cp and r set is set cpmax r i 5.23 = where r set = 4.7 k ? and i cp max = 5 ma. 11 cp charge pump output . when enabled, this provides i cp to the external loop filter, which in turn, drives the internal vco. 27 cs chip select . cmos i nput. when cs is high, the data stored in the shift register s is loaded into one of the 31 registers . in i 2 c mode, when cs is high, the slave address of the device is 0x78, and when cs is low, the slave address is 0x58. 29 sdi/sda serial data input for spi port, serial data input/output for i 2 c port. in spi mode. t his input is a high impedan ce cmos data input , and data is loaded in an 8 - bit word . in i 2 c mode, this pin is a bidirectional port. 30 clk/scl serial clock input for spi/i 2 c port . this serial clock is used to clock in the serial data to the registers. this input is a high impedance cmos input. 28 sdo serial data output for spi port. register states can be read back on the sdo data output line in an 8- bit word . 17 refin reference input . ac couple t his high impedance cmos input. 18 refin reference input bar . groun d t his pin.
adrf6850 rev. 0 | page 9 of 36 pin no. mnemonic description 51 , 55 rfi , rfi rf inputs . 50 ? internally biased rf inputs . for single - ended operation, rfi must be ac - coupled to the source , and rfi must be ac - coupled to the ground plane. 53 rfcm rf input common mode. c onnect to rfi when driving the input in single - ended mode. when driving the input differentially using a balun, connect this pin to the common terminal of the output coil of the balun. decouple rfcm to the ground plane. 25, 26 lomon, lomon differential monitor outputs. these pins provide a replica of the internal local oscillator frequency (1 lo) at four different power levels: ?6 dbm, ?12 dbm, ?18 dbm, and ?24 dbm, approximately. these open - collector outputs must be terminated with external resistors to vcc x . these outputs can be disabled through serial port programming and should be connected to vcc x if not used. 10 , 12 lf 3 /lf 2 extra loop filter pins for fastlock. use t hese pins to reduce lock time. 40 ldet lock detect. this pin provides an active high output when the pll freq u ency is locked. the lock dete ct timing is controlled by register cr14 ( bit 7 ) and register cr23 ( bit 3). 39 muxout muxout. this output is a test output for diagnostic use only. allow this pin to remain open circuit. 22, 23 testlo, testlo differential test inputs. for internal use only. these pins should be grounded. 43 vgain vga gain input. drive this pin by a voltage in the range from 0 v to 1.5 v. this voltage controls the gain of the vga. a 0 v input set s the vga gain to 0 db, wh ereas a 1.5 v input set s the vga gain to +6 0 db if the vga gain mode polarity bit cr30, bit 2 , is set to 0 . if the vga ga in mode polarity bit is set to 1, a 0 v input set s the vg a gain to +6 0 db, wh ereas a 1.5 v input set s the vga gain to 0 db. ep exposed paddle. connect the exposed pad to the ground plane via a low impedance path .
adrf6850 rev. 0 | page 10 of 36 typical performance characteristics a nominal condition is defined as 25 c, 3.30 v, and worst - case frequency. a worst - case condition is defined as having the worst - case temperature, supply voltage, and frequency. ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 ip1db (dbm) channe l gain (db) rf = 100mhz rf = 300mhz rf = 550mhz rf = 800mhz rf = 1000mhz 09316-011 0 60 50 40 30 20 10 figure 5 . input 1db compression poin t (ip1db) vs. channel gain, and rf input frequency, nominal conditions, narrow - band mode ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 ip1db (dbm) channe l gain (db) 3.30 v , 25 c 3.15 v, ? 40 c 3.45 v, ? 40 c 3.15 v , 85 c 3.45 v , 85 c 09316-012 0 60 50 40 30 20 10 figure 6 . input 1db compression point (ip1db) vs. channel gain, supply, and temperature, rf input frequency = 100 mhz, narrow - band mode ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 0 10 20 30 40 50 60 ip1db (db) channe l gain (db) 3.30v, +25c 3.15v, ?40c 3.45v, ?40c 3.15v, +85c 3.45v, +85c 09316-034 figure 7 . input 1db compression point (ip1db) vs. channel gain, supply, and temperature, rf input frequency = 1000 mhz, narrow - band mode 0 5 10 15 20 25 30 35 40 45 50 occurrence (%) input p1db a t channe l gain of 0db (dbm) nominal worst-case 09316-008 13.413.012.612.2 1 1.8 1 1.4 1 1.010.610.29.89.49.08.6 figure 8 . input 1db compression point (ip1db) distribution with channel gain = 0 db at nominal and worst - case conditions 0 5 10 15 20 25 30 35 40 45 50 55 60 occurrence (%) input p1db a t channe l gain of 60db (dbm) nominal worst-case 09316-009 ? 46.8 ? 47.2 ? 47.6 ? 48.0 ? 48.4 ? 48.8 ? 49.2 ? 49.6 ? 50.0 ? 50.4 figure 9 . input 1db compression point (ip1db) distribution with channel gain = 60 db at nominal and worst - case conditions ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 ?10 0 10 20 30 40 50 60 70 ip1db (dbm) channe l gain (db) rf = 100mhz rf = 300mhz rf = 550mhz rf = 800mhz rf = 1000mhz 09316-033 figure 10 . input 1 db compression point (ip1db) vs. channel gain, and rf input frequency, v ocm = 1.2 v, n ominal conditions, narrow - band mode
adrf6850 rev. 0 | page 11 of 36 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 ?10 0 10 20 30 40 50 60 70 ip1db (dbm) channe l gain (db) rf = 100mhz rf = 300mhz rf = 550mhz rf = 800mhz rf = 1000mhz 09316-057 figure 11 . input 1db compression point (ip1db) vs. channel gain, and rf input frequency, v ocm = 1.6 v, no minal conditions, narrow - band mode ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 ip1db (dbm) channe l gain (db) iq = 20mhz iq = 50mhz iq = 100mhz iq = 200mhz iq = 250mhz 09316-010 0 60 50 40 30 20 10 figure 12 . input 1db compression point (ip1db) vs. channel gain, and iq output frequency, lo = 1000 mhz, nominal conditions, w ideband mode ?50 ?40 ?30 ?20 ?10 0 10 20 30 input ip3 (dbm) channe l gain (db) 09316-015 0 60 70 50 40 30 20 10 rf = 100mhz rf = 300mhz rf = 550mhz rf = 800mhz rf = 1000mhz figure 13 . input ip3 vs. channel gain, and rf input frequency, nominal conditions ?50 ?40 ?30 ?20 ?10 0 10 20 30 input ip3 (dbm) channe l gain (db) 09316-016 0 60 70 50 40 30 20 10 rf = 100mhz rf = 300mhz rf = 550mhz rf = 800mhz rf = 1000mhz figure 14 . input ip3 vs. channel gain, and rf input frequency, wors t- case conditions 0 10 20 30 40 50 60 70 19.6 20.0 20.4 20.8 21.2 21.6 22.0 22.4 22.8 23.2 23.6 24.0 occurrence (%) iip3 at channel gain = 0db (dbm) nominal worst-case 09316-035 figure 15 . input ip3 distribution with channel gain = 0 db at nominal and worst- case conditions 0 5 10 15 20 25 30 35 ?40.0 ?40.4 ?39.6 ?39.2 ?38.8 ?38.4 ?38.0 ?37.6 ?37.2 ?36.8 ?36.4 ?36.0 occurrence (%) iip3 a t channe l gain = 60db (dbm) nominal worst-case 09316-036 figure 16 . input ip3 distribution with channel gain = 60 db at nominal and worst- case conditions
adrf6850 rev. 0 | page 12 of 36 ?50 ?40 ?30 ?20 ?10 0 10 20 30 ?10 0 10 20 30 40 50 60 70 input ip3 (dbm) channe l gain (db) iq frequencies = 16mhz and 19mhz iq frequencies = 46mhz and 49mhz iq frequencies = 96mhz and 99mhz iq frequencies = 196mhz and 199mhz iq frequencies = 246mhz and 249mhz 09316-037 figure 17 . input ip3 vs. channel gain, and iq output frequ ency, w ideband mode, nominal conditions ?50 ?40 ?30 ?20 ?10 0 10 20 30 ?10 0 10 20 30 40 50 60 70 input ip3 (dbm) channe l gain (db) iq frequencies = 16mhz and 19mhz iq frequencies = 46mhz and 49mhz iq frequencies = 96mhz and 99mhz iq frequencies = 196mhz and 199mhz iq frequencies = 246mhz and 249mhz 09316-038 figure 18 . input ip3 vs. channel gain, and iq output frequency, w ideband mode, worst - case conditions ?20 ?10 0 10 20 30 40 50 60 70 input ip2 (dbm) channe l gain (db) 09316-013 ?10 0 70605040302010 direct iip2 down-converted iip2 figure 19 . input ip2 vs. channel gain, w ideband mode, n ominal conditions ?20 ?30 ?10 0 10 20 30 40 50 60 70 input ip2 (dbm) channe l gain (db) 09316-014 ?10 0 70605040302010 direct iip2 down-converted iip2 figure 20 . input ip2 vs. channel gain, w ideband mode, worst- case conditions 09316-023 0 10 20 30 40 50 60 0 10 20 30 40 50 60 70 noise figure (db) channe l gain (db) rf = 100mhz rf = 300mhz rf = 550mhz rf = 800mhz rf = 1000mhz figure 21 . noise figure vs. channel gain, and rf input frequency, narrow - band mode, nominal conditions 09316-024 0 10 20 30 40 50 60 0 10 20 30 40 50 60 70 noise figure (db) channe l gain (db) rf = 100mhz rf = 300mhz rf = 550mhz rf = 800mhz rf = 1000mhz figure 22 . noise figure vs. channel gain, and rf input frequency, narrow - band mode, worst - case conditions
adrf6850 rev. 0 | page 13 of 36 0 10 20 30 40 50 60 0 10 20 30 40 50 60 70 noise figure (db) channe l gain (db) 09316-045 figure 23 . noise figure distribution vs. channel gain, narrow -b and mode, nominal condition s 0 10 20 30 40 50 60 0 10 20 30 40 50 60 70 noise figure (db) channe l gain (db) 09316-046 figure 24 . noise figure distribution vs. channel gain, narrow -b and mode, worst- case conditions 09316-025 0 10 20 30 40 50 60 0 10 20 30 40 50 60 70 noise figure (db) channe l gain (db) rf = 100mhz rf = 300mhz rf = 550mhz rf = 800mhz rf = 1000mhz figure 25 . noise figure vs. channel gain, and rf input frequency, w ideband mode, nominal conditions ?10 0 10 20 30 40 50 60 70 channe l gain (db) v gain (v) rf = 100mhz rf = 300mhz rf = 550mhz rf = 800mhz rf = 1000mhz 09316-007 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 figure 26 . channel gain vs. v gain and rf input frequency, nominal conditions 0 10 20 30 40 50 60 59.6 59.8 60.0 60.2 60.4 60.6 60.8 61.0 61.2 61.4 61.6 61. 8 62.0 62.2 occurrence (%) channe l gain range (db) nominal worst-case 09316-006 figure 27 . channel gain range distribution at nominal and worst- case conditions 09316-021 100 200 300 400 500 600 700 800 900 1000 channe l gain (db) rf input frequenc y (mhz) ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0.5 1.0 3.30 v , 25 c 3.15 v, ? 40 c 3.45 v, ? 40 c 3.15 v , 85 c 3.45 v , 85 c figure 28 . minimum channel gain vs. rf input frequency, supply, and temperature
adrf6850 rev. 0 | page 14 of 36 0 5 10 15 20 25 30 occurrence (%) minimum channe l gain (db) nominal worst-case 09316-019 ?2.0 ?2.2 ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.2 0.4 0.6 0.8 1.0 1.2 0 figure 29 . minimum channel gain distribution at nominal and worst- case conditions 09316-018 maximum channe l gain (db) 3.30 v , 25 c 3.15 v, ? 40 c 3.45 v, ? 40 c 3.15 v , 85 c 3.45 v , 85 c 60.0 60.5 61.0 61.5 62.0 62.5 63.0 100 200 300 400 500 600 700 800 900 1000 rf input frequenc y (mhz) figure 30 . maximum channel gain vs. rf input frequency, supply, and temperature 0 5 10 15 20 25 occurrence (%) maximum channe l gain (db) nominal worst-case 09316-017 62.2 62.0 61.8 61.6 61.4 61.2 61.0 60.8 60.6 60.4 60.2 60.0 59.8 59.6 figure 31 . maximum channel gain distribution at nominal and worst- case conditions ?3 ?2 ?1 0 1 2 3 channe l g ain conformance error (db) vgain (v) rf = 100mhz rf = 300mhz rf = 550mhz rf = 800mhz rf = 1000mhz 09316-005 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 figure 32 . channel gain conformance error vs. v gain and rf input frequency, nom inal conditions ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 100 200 300 400 500 600 700 800 900 1000 return loss (db) rf input frequenc y (mhz) v gain = 0v v gain = 0.5v v gain = 1.0v v gain = 1.5v 09316-039 figure 33 . input return loss vs. rf input frequency and channel gain, nominal conditions ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 200 300 400 500 600 700 800 900 1000 integer bounda ry spurs (dbc) lo frequenc y (mhz) integer boundary spur at 9.6khz offset integer boundary spur at 19.2khz offset integer boundary spur at 38.4khz offset 09316-044 figure 34 . integer boundary spurs vs. lo frequency, channel gain, supply, and temperature
adrf6850 rev. 0 | page 15 of 36 reference spur (dbc) ?120 ?100 ?80 ?60 ?40 ?20 0 100 200 300 400 500 600 700 800 900 1000 lo frequenc y (mhz) v gain = 1.5v v gain 1.0v 09316-049 figure 35 . reference spurs at 13.5 mhz from carrier vs. lo frequency, channel gain, supply, and temperature ?120 ?100 ?80 ?60 ?40 ?20 0 100 200 300 400 500 600 700 800 900 1000 pfd spur (dbc) lo frequenc y (mhz) v gain = 1.5v v gain 1.0v 09316-048 figure 36 . pfd spurs at 27 mhz from carrier vs. lo frequency, channel gain, supply, and temp erature ?170 ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 10 100 1k 10k 100k 1m 10m phase noise (dbc/hz) offset frequenc y (hz) table of distribution data: offset frequency (hz): 10 100 1k 10k 100k 1m 10m typical range (dbc/hz): ?91/?100 ?99/?111 ?107/?115 ?118/?121 ?129/?132 ?150/?154 ?151/?153 worst-case range (dbc/hz): ?90/?105 ?95/?108 ?105/?116 ?118/?121 ?128/?131 ?151/?154 ?151/?153 09316-052 figure 37 . phase noise performance including distribution table at lo frequency = 100 mhz at nominal and worst - case conditions 10 100 1k 10k 100k 1m 10m phase noise (dbc/hz) offset frequenc y (hz) ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 table of distribution data: offset frequency (hz): 10 100 1k 10k 100k 1m 10m typical range (dbc/hz): ?75/?85 ?78/?89 ?84/?95 ?97/?100 ?110/?113 ?136/?138 ?149/?153 worst-case range (dbc/hz): ?72/?82 ?74/?89 ?89/?96 ?97/?100 ?110/?112 ?136/?138 ?149/?152 09316-051 figure 38 . phase noise performance including distribution table at lo frequency = 1000 mhz at nominal and worst - case conditions 0 0.1 0.2 0.3 0.4 100 200 300 400 500 600 700 800 900 1000 rms jitter (degrees) lo frequenc y (mhz) 3.30v; +25c 3.15v; +85c 3.45v; +85c 3.15v; ?40c 3.45v; ?40c 09316-041 figure 39 . integrated phase noise vs. lo frequency, supply, and temperature 0 5 10 15 20 25 30 0.19 0.21 0.23 0.25 0.27 0.29 0.31 0.33 occurrence (%) rms jitter (degrees) nominal worst-case 09316-040 figure 40 . integrated phase noise distribution with lo frequency = 1000 mhz at nominal and worst - case conditions
adrf6850 rev. 0 | page 16 of 36 ?50 0 50 100 150 200 250 300 350 400 450 500 550 error frequenc y (hz) start of acquisition on cr0 write cr23[3] = 1 cr23[3] = 0 acquisition to 1khz best case typical worst case ldet ldet 1 0.1 0.01 10 100 1k 10k 100k 1m 10m 100m 1g time ( s) 09316-055 figure 41 . p ll frequency settling time with ty pical, best -case, and worst - case frequency hop with lock detect shown, nominal conditions 0 2 4 6 8 10 12 14 16 18 20 ?18 ?14 ?10 ?6 ?2 2 6 10 14 18 22 26 30 occurrence (%) output dc offset (mv) i output q output 09316-050 figure 42 . output dc offset distribution for i and q outputs, nominal conditions ?30 ?25 ?20 ?15 ?10 ?5 0 5 0.1 1 10 100 1000 output power (db) iq output frequenc y (mhz) wb mode nb mode= 50mhz nb mode = 43mhz nb mode = 37mhz nb mode= 30mhz 09316-047 figure 43 . normalized iq output bandwidth, narrow - band , and wideband mode s , nominal conditions 09316-031 0 5 10 15 20 25 30 0.005 0 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 0.055 0.060 0.065 0.070 0.075 0.080 0.085 0.090 0.095 0.100 occurrence (%) absolute iq amplitude balance (db) figure 44 . absolute iq amp litude balance, narrow -band mode, nominal conditions 0 2 4 6 8 10 12 14 16 18 20 ?0.45 ?0.35 ?0.25 ?0.15 ?0.05 0.05 0.15 0.25 0.35 0.45 occurrence (%) iq phase balance (degrees) 09316-042 figure 45 . iq phase balance, narrow -band mode, nominal conditions 09316-026 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ? 10 0 v gain = 1.5v 200100 300 400 500 600 700 800 900 1000 1 lo feedthrough (dbm) lo frequenc y (mhz) v gain = 0 v , 0.5 v , 1v figure 46 . 1 lo feedthrough vs. lo frequency, v gain , supply, and temperature ( narrow - band mode)
adrf6850 rev. 0 | page 17 of 36 09316-029 ?80 ?100 ?120 ?60 ?40 ?20 0 100 200 300 400 500 600 700 800 900 1000 2 lo feedthrough (dbm) lo frequenc y (mhz) figure 47 . 2 lo feedthrough vs. lo frequency, v gain , supply, and temperature ( narrow - band mode) 09316-030 ?80 ?100 ?120 ?60 ?40 ?20 0 4 lo feedthrough (dbm) 100 200 300 400 500 600 700 800 900 1000 lo frequenc y (mhz) figure 48 . 4 lo feedthrough vs. lo frequency, v gain , supply, and temperature ( narrow - band mode) 09316-020 ?46.5 ?46.0 ?45.5 ?45.0 ?44.5 ?44.0 ?43.5 ?43.0 ?42.5 ?42.0 ?41.5 ?41.0 ?40.5 ?40.0 ?39.5 ?39.0 ?38.5 ?38.0 ?37.5 ?37.0 ?36.5 ?36.0 0 5 10 15 20 25 occurrence (%) 1 lo feedthough (dbm) nominal worst-case figure 49 . 1 lo feedthrough distribution at nominal and worst -case conditions with lo frequency > 300 mhz , narrow - band mode 09316-022 ?120 ? 100 ?80 ? 60 ?40 ?20 0 330 430 530 630 730 830 930 1 lo feedthrough (dbm) lo frequenc y (mhz) v gain = 0 v , 0.5 v , 1v v gain = 1.5v v gain = 1.3v figure 50 . 1 lo feedthrough vs. lo frequency, v gain , su pply , and temperature, fourth- order filter at 300 mhz applied, w ideband mode 09316-028 ?80 ?100 ?120 ?60 ?40 ?20 0 v gain = 1.5v v gain = 0 v , 0.5 v , 1v 100 200 300 400 500 600 700 800 900 1000 1 rf t o iq leakage (dbc) rf frequenc y (mhz) figure 51 . 1 rf feedthrough vs. r f input frequency, v gain , supply, and temperature, narrow - band mode 09316-027 ?140 ?80 ?100 ?120 ?60 ?40 ?20 0 v gain = 1.5v v gain = 1.0v v gain = 1.3v v gain = 0 v , 0.5 v , 1v 330 430 530 630 730 830 930 1 rf t o iq leakage (dbc) rf frequenc y (mhz) figure 52 . 1 rf fe edthrough vs . rf input frequency, v gain , supply, and temperature, fourth -o rder filter at 300 mhz applied, w ideband mode
adrf6850 rev. 0 | page 18 of 36 theory of operation overview th e adrf6850 device can be sep a rated into the following basic building blocks: ? pll synthesizer and vco ? quadrature demodulator ? variable gain amp lifier (vga) ? i 2 c/spi interface each of these building blocks is described in detail in the sections that follow. pll synthesizer and vco overview the phase - locked loop (pll) consists of a fractional - n frequency synth esizer with a 25- bit fixed modulus, allowing a frequency resolution of less than 1 hz over the entire frequency range. it also has an integrated voltage controlled oscillator (vco) with a fundamental output frequency rang ing from 2000 mhz to 400 0 mhz. an r f divider, controlled by register cr28, bits[2:0] , extends the lower limit of the frequency range to less than 400 mhz. this 400 mhz to 4000 mhz frequency output is then applied to a divide - by - 4 quadrature circuit to provide a local oscillator ( lo ) ranging from 100 mhz to 1000 mhz to the quadrature de modulator . reference input section the reference input stage is shown in figure 53 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power - down is initiated, sw3 i s closed, and sw1 and sw2 are open. this ensures that there is no loading of the refin pin at power - down. buffer to r-divider refin 100 k ? nc sw2 sw3 nc nc sw1 power-down control 09316-060 figure 53 . reference input stage reference input path the on - chip reference frequency doubler allows the input frequency of the reference signal to be doubled. this is useful for increasing the pfd comparison frequency. making the pfd freq uency higher improves the noise performance of the system . doub ling the pfd fr equency usually improves the in - band phase noise performance b y 3 dbc/hz. the 5 - bit r - divider allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 32 are allowed. an additional divide - by - 2 (2) function in the reference input path allows for a greater division range. 2 doubler 5-bit r-divider from refin pin to pfd 2 09316-061 figure 54 . reference input path the pfd frequency equation is f pfd = f refin [(1 + d )/( r (1 + t ))] (1 ) where: f refin is the reference input frequency. d is the doubler bit. r is the programmed di vide ratio of the binary 5 - bit programmable reference divider (1 to 32). t is the 2 bit (0 or 1). rf fractional - n divider the rf fractional - n divider allows a division ratio in the pll feedback path that can range from 23 to 4095. the relationship between the fractional - n divider and the lo frequency is described in the following section. int and frac relationship the integer (int) and fractional (frac) values make it possible to generate output frequencies that are spaced by fractions of the phase frequen cy detector (pfd) frequency. see the programming the correct lo frequency section for more information. the lo frequency equation is lo = f pfd ( int + ( frac /2 25 ))/ 2 2 rfdiv (2 ) where: lo is the local oscillator frequency. f pf d is the pfd frequency. int is the integer component of the required division factor and is controlled by the cr6 and cr7 registers. frac is the fractional component of the required division factor and is controlled by the cr0 to cr3 registers. rfdiv is th e setting in register cr28 , bits [2:0] , and controls the setting of a divider at the output of the pll . n-counter int reg to pfd rf n-divider n = int + frac/2 25 from vco output dividers frac value third-order fractional interpolator 09316-062 figure 55 . rf fractional - n divider phase frequency detector (pfd) and charge pump the pfd takes inputs from the r - divider and the n - counter and produces an output proportional to the phase and frequency differ - ence between them (see figure 56 for a simplified schematic). the pfd includes a fixed delay element that sets the width of the antibacklash pulse, ensuring that there is no dead zone in the pfd transfer function.
adrf6850 rev. 0 | page 19 of 36 u3 clr2 q2 d2 u2 down up hi hi cp ?in +in charge pump del ay clr1 q1 d1 u1 09316-063 figure 56 . pfd simplified schematic lock detect (ldet) ldet (pin 40 ) signals when the pll has achieved lock to an erro r frequency of less than 1 k hz. on a write to register cr0, a new pll acquisition cycle starts, and the ldet signal goes low. when lock has been achieved, this signal returns high. voltage controlled oscillator (vco) the vco core in the adrf6 8 50 consists of three separate vcos , each with 16 overlap ping bands. this configuration of 48 bands allows the vco frequency range to extend from 2000 mhz to 4000 mhz. the thre e vcos are divided externally by a program - mable divider (rfdiv controlled by register cr28, bits[2:0]). this divider p rovides divisions of 1, 2, 4, and 8 to ensure that the frequency range is extended from 250 m hz (2000 mhz/8) to 4000 mhz (4000 mhz/ 1). a lower limit of only 400 mhz is required . a divide - by - 4 quadrature circuit provides the full lo frequency range from 100 mhz to 1000 mhz. figure 57 shows a sweep of v tune vs. lo f requency demonstrating the three vco s overlap ping and the multiple overlapping bands within each vco at the lo frequency range of 100 mhz to 1000 mhz . no te that this plot in clude s the rfdiv divider being incorporated to provide further divisions of the fundamental vco frequency ; thus, each vco is u sed on four different occasions throughout the full lo frequency range. the choice of three 16 - band vcos and an rfdi v divider allo ws the wide frequency range to be covered without large vco sensitivity (k vco ) or resu l tant poor phase noise and spurious performance. 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 100 200 300 400 500 600 700 800 900 1000 v tune (v) lo frequenc y (mhz) 09316-056 figure 57 . v tune vs. lo frequency the correct vco and band are chosen automatically by the vco and band select circuitry when register cr0 is updated. this is referred to as autocalibration. the au tocalibration time is set by register cr25. autocalibration time = ( bscdiv 24)/ pfd (3) w here: bscdiv = register cr25 , bits [7:0] . pfd = pfd f requency . for a pfd frequency o f 27 mhz, bscdiv = 112 to set an autocalibration time of 100 s. note that bscdiv must be re calculated if the pfd frequency is changed. the recommended autocalibration setting is 10 0 s. during this time, the vco v tune is disconnected from the output of the loop filter and is connected to an internal re f erence voltage. a typical frequency acquisition is shown in figure 58 . 1 10 100 1k 10k 100k 1m 10m 100m 1g 0 50 100 150 200 250 300 350 400 450 500 frequenc y error (hz) time ( s) acquisition to 1khz autocal time (s) 09316-054 figure 58 . pll acquisition after autocalibrat ion, normal pll action resumes , and the correct frequency is acquired to within a frequency error of 1 khz in 26 0 s typically. for a maximum cumulative step of 100 khz, autocalibration can be turned off by register cr24, bit 0. this enables cumu lative pll acquisitions of 100 khz or less to occur without the autocalibration procedure, which improves acquisition times significantly (see figure 59). 1 10 100 1k 10k 100k 1m 10m 100m 1g 0 20 40 60 80 100 120 140 160 180 200 frequenc y error (hz) time ( s) acquisition to 1khz 09316-053 figure 59 . pll acquisition without autocalibration for a 1 00 khz step
adrf6850 rev. 0 | page 20 of 36 the vco displays a variation of k vco as v tune varies within the band and from band to band. figure 60 shows how the k vco varies across the fundamental lo frequency range from 5 00 mhz to 1000 mhz . note that k vco is sh own at the lo frequency rather than at the vco frequency . figure 60 is useful when calculating the loop filter bandwidth and individual loop filter components using adisimpll ?. adisimpll is an analog devices , inc., simulator that aids in pll design, particularly with respect to the loop filter. it reports parameters such as phase noise, integrated phase noise, acquisition time, and so forth for a particular set of input co nditions. adisimpll can be down loaded from www.analog.com . 0 5 10 15 20 25 500 550 600 650 700 750 800 850 900 950 1000 lo frequenc y (mhz) vco sensitivit y (mhz/v) 09316-059 figure 60 . k vco vs. lo frequency programming the correct lo frequency t here are two steps to program ming the correct lo frequency. the user can calculate the n - divider ratio that is required in the pll and the rfdiv value based on the required lo frequency and pfd frequency. 1. calculate the value of rfdiv , whi ch is used to program register cr28 , bits [2:0], from the following lookup table ( table 6 ) . see also table 24 . table 6 . rfdiv lookup table lo frequency (mhz) rfdiv = register cr28[2:0] 500 to 1000 000 = divide -by -1 250 to 500 001 = divide -by -2 125 to 250 010 = divide -by -4 100 to 12 5 011 = divide -by -8 2. using the following equation, calculate the value of the n- divider : n = (2 rfdiv 2 lo )/ ( f pfd ) (4 ) where: n is the n - divider value. rfdiv is the setting in r egister cr28 , bits [2:0]. lo is the local oscillator frequency. f pfd is the pfd frequency. this equation is a different representation of equation 2. example to p rogram the correct lo frequency assum e that the pfd frequency is 27 mhz and the required lo frequency is 330 mhz. step 1 . from table 6 , 2 rfdiv = 2. step 2 . n = (2 2 330e+6)/ ( 27 e+6) = 48.88888889 . the n - divider value is composed of integer (int) and fractional (frac) components according to the following equation: n = int + frac /2 25 (5 ) int = 48 and frac = 29 ,826, 162 . the appr op riate registers must then be programmed according to the r egister map , ensuring that register cr0 is the last register to be programmed because this write starts a new pll acquisi - tion cycle. quadrature demodulat or the quadrature demodulator can be power ed up by r egister cr29 , bit 0 . it has an output filter with narrow - band and wideband modes , whic h are selected by r egister cr29, bit 3 . wide band mode has a 1 db filter cut off of 250 mhz . narrow - ba nd mode has selectable cut off filters of 30 mhz through 50 m hz by pro - gr amming register cr29, bits[ 5:4]. a dc bias voltage of 1.4 v (v ocm ) can be set internally by setting register cr29 , bit 6 = 1. to select an external dc bias voltage, s et register cr2 9, bit 6 = 0, and drive pin 7, vocm, with the requisite externa l bias voltage. variable gain amplifier (vga) the variable gain amplifier (vga) at the input to the demodulator can b e driven either single- ended or differentially. to drive single - ended, connect pin 53, rfcm , to pin 51, rfi , and decouple both pins to ground with a 10 nf capacitor. drive t he input signal t hrough pin 55, rfi . to drive differ entially, use a balun with the rfi and rfi pins driven by the balanced outputs of the balun , and connect the rfcm pin to the common ba lun output terminal. decouple rfcm to ground. the vga gain range is approximately 60 db and is achieved by varying the vgain voltage from 0 v to 1.5 v . the typical performance characteristics section has more infor mation on the vga gain performance . a 0 v input on vgain sets the vga gain to 0 db, whereas a 1.5 v in put sets the vga gain to +60 db if the vga gain mode polar ity bit cr30, bit 2 , is set to 0. if the vga gain mode polarity bit is set to 1, a 0 v input vol tage on vgain sets the vga gain to +60 db, whereas a 1.5 v input sets the vga gain to 0 db. the vga can be powered down by setting register cr30, bit 0 , to 0 and can be powered up by setting this same bit to 1. i 2 c interface the adrf6850 supports a 2 - wire, i 2 c- compatible serial bus that drives multiple peripherals. the part powers up in i 2 c mode but is not locked in this mode. to remain in i 2 c mode, it is
adrf6850 rev. 0 | page 21 of 36 recommended that the user tie the cs line to either 3.3 v or gnd, thus disabling spi mode. the serial data (sda) and serial clock (scl) inputs carry infor- mation between any devices that are connected to the bus. each slave device is recognized by a unique address. the adrf6850 has two possible 7-bit slave addresses for both read and write operations, 0x78 and 0x58. the msb of the 7-bit slave address is set to 1. bit 5 of the slave address is set by the cs pin (pin 27). bits[4:0] of the slave address are set to 11000. the slave address consists of the seven msbs of an 8-bit word. the lsb of the word sets either a read or a write operation (see figure 61). logic 1 cor- responds to a read operation, whereas logic 0 corresponds to a write operation. to control the device on the bus, the following protocol must be followed: 1. the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda while scl remains high. this indicates that an address/ data stream follows. 2. all peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the r/w bit). the bits are transferred from msb to lsb. 3. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. 4. all other devices then withdraw from the bus and maintain an idle condition. during the idle condition, the device monitors the sda and scl lines waiting for the start condition and the correct transmitted address. 5. the r/w bit determines the direction of the data. logic 0 on the lsb of the first byte indicates that the master writes information to the peripheral. logic 1 on the lsb of the first byte indicates that the master reads information from the peripheral. the adrf6850 acts as a standard slave device on the bus. the data on the sda pin is eight bits long, supporting the 7-bit addresses plus the r/w bit. the adrf6850 has 34 subaddresses to enable the user-accessible internal registers; therefore, it interprets the first byte as the device address and the second byte as the starting subaddress. auto-increment mode is supported, which allows data to be read from or written to the starting subaddress, and each subsequent address, without manually addressing the subsequent subaddress. a data transfer is always terminated by a stop con- dition. the user can also access any unique subaddress register on a one-by-one basis without updating all registers. stop and start conditions can be detected at any stage of the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. if an invalid subaddress is issued by the user, the adrf6850 does not issue an acknowledge and returns to the idle condition. in a no acknowledge condition, the sda line is not pulled low on the ninth pulse. see figure 62 and figure 63 for sample write and read data transfers, figure 64 for the timing protocol, and figure 2 for a more detailed timing diagram. 1a500000x msb = 1 set by pin 27 0 = wr 1 = rd slave address[6:0] r/w ctrl 09316-064 figure 61. slave address configuration s slave addr, lsb = 0 (wr) a(s) a(s) a(s) data subaddr a(s) p data s = start bit p = stop bit a(s) = acknowledge by slave 09316-067 figure 62. i 2 c write data transfer s s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a(m) = no acknowledge by master s slave addr, lsb = 0 (wr) slave addr, lsb = 1 (rd) a(s) a(s) subaddr a(s) data a(m) data p a(m) 09316-065 figure 63. i 2 c read data transfer start bit s stop bit p ack ack wr ack d0 d7 a0 a7 a5 a6 slave addr[4:0] slave address subaddress data subaddr[6:1] data[6:1] scl sda 09316-066 figure 64. i 2 c data transfer timing
adrf6850 rev. 0 | page 22 of 36 spi interface the adrf6850 supports the spi protocol; however, the part powers up in i 2 c mode. to select and lock the spi mode, three pulses must be sent to the cs pin, as shown in figure 65. when the spi protocol is locked in, it cannot be unlocked while the device remains powered up. to reset the serial interface, the part must be powered down and powered up again. serial interface selection the cs pin controls selection of the i 2 c or spi interface. figure 65 shows the selection process that is required to lock in the spi mode. to communicate with the part using the spi protocol, three pulses must be sent to the cs pin. on the third rising edge, the part selects and locks the spi protocol. consistent with most spi standards, the cs pin must be held low during all spi communication to the part and held high at all other times. spi serial interface functionality the spi serial interface of the adrf6850 consists of the cs, sdi (sdi/sda), clk (clk/scl), and sdo pins. cs is used to select the device when more than one device is connected to the serial clock and data lines. clk is used to clock data in and out of the part. the sdi line is used to write to the registers. the sdo pin is a dedicated output for the read mode. the part operates in slave mode and requires an externally applied serial clock to the clk pin. the serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. figure 66 shows an example of a write operation to the adrf6850. data is clocked into the registers on the rising edge of clk using a 24-bit write command. the first eight bits represent the write command (0xd4), the next eight bits are the register address, and the final eight bits are the data to be written to the specific register. figure 67 shows an example of a read operation. in this example, a shortened 16-bit write command is first used to select the appro- priate register for a read operation, the first eight bits representing the write command (0xd4) and the final eight bits representing the specific register. then the cs line is pulsed low for a second time to retrieve data from the selected register using a 16-bit read command, the first eight bits representing the read command (0xd5) and the final eight bits representing the contents of the register being read. figure 3 shows the timing for both spi read and spi write operations. 09316-077 spi locked on third rising edge spi framing edge c b a spi locked on third rising edge spi framing edge c b a cs ( startin g high) cs ( startin g low) figure 65. selecting the spi protocol
adrf6850 rev. 0 | page 23 of 36 register address write command [0xd4] ? ? ? ? ? ? ? ? ? st art cs clk sdi d7 d6 d5 d4 d3 d2 d1 d0 d0 d7 d6 d5 d4 d3 d2 d1 ? ? ? ? ? ? ? ? ? dat a byte stop cs (continued) clk (continued) sdi (continued) d7 d6 d5 d4 d3 d2 d1 d0 09316-068 figure 66 . spi byte write example register address write command [0xd4] st art d at a byte read command [0xd5] st art stop cs clk sdi cs clk sdi sdo d7 d6 d5 d4 d3 d2 d1 d0 d0 d7 d6 d5 d4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x x x x x x x x x ? ? ? ? ? ? ? ? ? 09316-069 fi gure 67 . spi byte read example
adrf6850 rev. 0 | page 24 of 36 program modes the adrf6850 has 34 8-bit registers to allow program control of a number of functions. only 31 of these registers are writeable. either an spi or an i 2 c interface can be used to program the register set. for details about the interfaces and timing, see figure 61 to figure 67. the registers are documented in table 8 to table 27. several settings in the adrf6850 are double buffered. these settings include the frac value, the int value, the rfdiv value, the 5-bit r-divider value, the reference doubler, the r 2 divider, and the charge pump current setting. this means that two events must occur before the part uses a new value for any of the double buffered settings. first, the new value is latched into the device by writing to the appropriate register. next, a new write must be performed on register cr0. when register cr0 is written, a new pll acquisition occurs. for example, updating the fractional value involves a write to register cr3, register cr2, register cr1, and register cr0. register cr3 should be written to first, followed by register cr2 and register cr1 and, finally, register cr0. the new acquisition begins after the write to register cr0. double buffering ensures that the bits written to do not take effect until after the write to register cr0. 12-bit integer value register cr7 and register cr6 program the integer value (int) of the feedback division factor (n); see equation 5 for details. the int value is a 12-bit number whose msbs are programmed through register cr7, bits[3:0]. the lsbs are programmed through register cr6, bits[7:0]. the lo frequency setting is described by equation 2. an alternative to this equation is pro- vided by equation 4, which details how to set the n-divider value. note that these registers are double buffered. 25-bit fractional value register cr3 to register cr0 program the fractional value (frac) of the feedback division factor (n); see equation 5 for details. the frac value is a 25-bit number whose msb is programmed through register cr3, bit 0. the lsb is programmed through register cr0, bit 0. the lo frequency setting is described by equation 2. again, an alternative to this equation is described by equation 4, which details how to set the n-divider value. note that these registers are double buffered. rfdiv value the rfdiv value is dependent on the value of the lo frequency. the rfdiv value can be selected from the list in table 6. apply the selected rfdiv value to equation 4, together with the lo frequency and pfd frequency values, to calculate the correct n- divider value. reference input path the reference input path consists of a reference doubler, a 5-bit frequency divider, and a divide-by-2 function (see figure 54). the doubler is programmed through register cr10, bit 5. the 5-bit divider is enabled by programming register cr5, bit 4; and the division ratio is programmed through register cr10, bits[4:0]. the r 2 divider is programmed through register cr10, bit 6. note that these registers are double buffered. charge pump current register cr9, bits[7:4], set the charge pump current setting. with an r set value of 4.7 k, the maximum charge pump current is 5 ma. the following equation applies: i cp max = 23.5/ r set (6) the charge pump current has 16 settings from 325 a to 5 ma. power-down/power-up control bits the four programmable power-up and power-down control bits are as follows: ? register cr12, bit 2. master power control bit for the pll, including the vco. this bit is normally set to a default value of 0 to power up the pll. ? register cr27, bit 2. controls the lo monitor outputs, lomon and lomon . the default is 0 when the monitor outputs are powered down. setting this bit to 1 powers up the monitor outputs to one of ?6 dbm, ?12 dbm, ?18 dbm, or ?24 dbm, as controlled by register cr27, bits[1:0]. ? register cr29, bit 0. controls the quadrature demodulator power. the default is 0, which powers down the demodulator. write a 1 to this bit to power up the demodulator. ? register cr30, bit 0. this bit controls the vga power and must be set to a 1 to power up the vga. lock detect (ldet) lock detect is enabled by setting register cr23, bit 4, to 1. register cr23, bit 3, in conjunction with register cr14, bit 7, sets the number of up/down pulses generated by the pfd before lock detect is declared by the ldet pin returning high. the options are 2048 pulses, 3072 pulses, and 4096 pulses. the default setting is 3072 pulses, which is selected by program- ming register cr23, bit 3, to 0, and register cr14, bit 7, to 0. a more aggressive setting of 2048 is selected when register cr23, bit 3, is set to 1 and register cr14, bit 7, is set to 0. this improves the lock detect time by 50 s (for a pfd frequency of 27 mhz). note, however, that it does not affect the acquisition time to an error frequency of 1 khz. a setting of 4096 pulses is selected when register cr14, bit 7, is set to 1. for best operation, set register cr23, bit 2 to 0. this bit sets up the pfd up/down pulses to a coarse or low precision setting. baseband vocm reference register cr29, bit 6, selects whether the common-mode reference for the baseband outputs is internal or external. when the base- band outputs are ac-coupled, then the internal reference must be selected by setting register cr29, bit 6, to 1, and by grounding pin 7, vocm. when the baseband outputs are dc-coupled, it is likely that an external bias is needed unless the internal dc bias provided is
adrf6850 rev. 0 | page 25 of 36 within a suitable range to match the specification of the follow- on device. this is accomplished by setting register cr29, bit 6, to 0, and driving pin 7, vocm, with the requisite external bias voltage. narrow-band and wideband filter mode by default, the second-order low-pass filter in the output buffers of the baseband output signal paths is selected, and the baseband outputs are in narrow-band mode. by setting register cr29, bits[5:4], this filter can be set to a cutoff frequency of 50 mhz, 43 mhz, 37 mhz, or 30 mhz. by setting register cr29, bit 3, to 1, this filter is bypassed and wideband mode is selected. table 7. baseband filter settings cr29[5:4] filter cutoff frequency (mhz) 00 50 01 43 10 37 11 30 vga gain mode polarity the polarity of the vga gain is set by programming bit 2 of register cr30. by setting register cr30, bit 2, to 0, a positive gain slope is selected where v gain = 0 v sets the vga gain to be 0 db, and v gain = 1.5 v sets the vga gain to be 60 db. by setting register cr30, bit 2, to 1, a negative gain slope is selected.
adrf6850 rev. 0 | page 26 of 36 register map register map summary table 8 . register map summary register address (hex) register name type description 0x00 cr0 read/write fractional w ord 4 0x01 cr1 read/write fractional w ord 3 0x02 cr2 read/w rite fractional w ord 2 0x03 cr3 read/write fractional w ord 1 0x04 cr4 read/write reserved 0x05 cr5 read/write reference 5-b it , r- divider enable 0x06 cr6 read/write integer w ord 2 0x07 cr7 read/write integer w ord 1 0x08 cr8 read/write reserved 0x09 c r9 read/write charge pump current setting 0x0a cr10 read/write reference frequency control 0x0b cr11 read/write reserved 0x0c cr12 read/write pll power -up 0x0d cr13 read/write reserved 0x0e cr14 read/write lock detector control 2 0x0f cr15 read/write reserved 0x10 cr16 read/write reserved 0x11 cr17 read/write reserved 0x12 cr18 read/write reserved 0x13 cr19 read/write reserved 0x14 cr20 read/write reserved 0x15 cr21 read/write reserved 0x16 cr22 read/write reserved 0x17 cr23 read/write lock de tector cont rol 1 0x18 cr24 read/write autocalibration 0x19 cr25 read/write autocalibrati on t imer 0x1a cr26 read/write reserved 0x1b cr27 read/write lo monitor output 0x1c cr28 read/write lo selection 0x1d cr29 read/write demodulator power and filter selection 0x1e cr30 read/write vga 0x1f cr31 read only reserved 0x20 cr32 read only reserved 0x21 cr33 read only revision code
adrf6850 rev. 0 | page 27 of 36 register bit descrip tions table 9 . register cr0 (address 0x00), fractional word 4 bit description 7 fractional word f7 1 6 fractional word f6 1 5 fractional word f5 1 4 fractional word f4 1 3 fractional word f3 1 2 fractional word f2 1 1 fractional word f1 1 0 fractional word f0 (lsb) 1 1 double buffered. load on the write to register cr0. table 10 . register cr1 (address 0x01), fractional word 3 bit description 7 fractional word f15 1 6 fractional word f14 1 5 fractional word f13 1 4 fractional word f12 1 3 fractional word f11 1 2 fractional word f10 1 1 fractional word f9 1 0 fractional word f8 1 1 double buffered. load on the write to register cr0. table 11 . register cr2 (address 0x02), fractional word 2 bit description 7 fractional word f23 1 6 fractional word f22 1 5 fractional word f21 1 4 fraction al word f20 1 3 fractional word f19 1 2 fractional word f18 1 1 fractional word f17 1 0 fractional word f16 1 1 double buffered. load on the write to register cr0. table 12 . register cr3 (address 0x03), fractional word 1 bit descrip tion 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 reserved 1 reserved 0 fractional word f24 (msb) 1 1 double buffered. load on the write to register cr0. table 13 . register cr5 (address 0x05), reference 5 - bit , r- divider enable bit description 7 reserved 6 reserved 5 reserved 4 5- bit r - divider enable 1 0 = disable 5 - bit r - divider (default) 1 = enable 5 - bit r - divider 3 reserved 2 reserved 1 reserved 0 reserved 1 double buffered. load on the write to reg ister cr0. table 14 . register cr6 (address 0x06), integer word 2 bit description 7 integer word n7 1 6 integer word n6 1 5 integer word n5 1 4 integer word n4 1 3 integer word n3 1 2 integer word n2 1 1 integer word n1 1 0 integer word n0 1 1 double buffered. load on the write to register cr0. table 15 . register cr7 (address 0x07), integer word 1 bit description [7:4] muxout control 0000 = tristate 0001 = l ogic high 0010 = l ogic low 1101 = rclk /2 1 110 = nclk /2 3 integer word n11 1 2 integer word n10 1 1 integer word n9 1 0 integer word n8 1 1 double buffered. load on the write to register cr0.
adrf6850 rev. 0 | page 28 of 36 table 16 . register cr9 (address 0x09), charge pump current setting bit descripti on [7:4] charge pump current 1 0000 = 0.31 ma (default) 0001 = 0.63 ma 0010 = 0.94 ma 0011 = 1.25 ma 0100 = 1.57 ma 0101 = 1.88 ma 0110 = 2.19 ma 0111 = 2.50 ma 1000 = 2.81 ma 1001 = 3.13 ma 1010 = 3.44 ma 1011 = 3.75 ma 1100 = 4.06 ma 1101 = 4.38 ma 1110 = 4.69 ma 1111 = 5.00 ma 3 reserved 2 reserved 1 reserved 0 reserved 1 double buffered. load on the write to register cr0. table 17 . register cr10 (address 0x0a), reference frequency control bit description 7 reserved 1 6 r divide -by - 2 divider enable 1 0 = bypass r divide -by - 2 divider 1 = enable r divide -by - 2 divider 5 r- doubler enable 1 0 = disable doubler (default) 1 = enable doubler [4:0] 5- bit r - divider setting 1 00000 = divide by 32 (default) 00001 = divide by 1 00010 = divide by 2 11110 = divide by 30 11111 = divide by 31 1 double buffered. load on the write to register cr0. table 18 . register cr12 (address 0x0c), pll power -up bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 pll power - down 0 = power up pll (default) 1 = power down pll 1 reserved 0 reserved t able 19 . register cr14 (address 0x0e), lock detector control 2 bit description 7 lock detector up/d ow n c ount 2 0 = 2048/3072 up/d ow n pulses 1 = 4096 up/d ow n pulses 6 reserved 5 reserved 4 reserved 3 reserved 2 reserved 1 reserved 0 reserved table 20 . register cr23 (address 0x17), lock detector control 1 bit description 7 reserved 6 reserved 5 reserved 4 lock detector enable 0 = lock detector disabled (default) 1 = lock detector enabled 3 lock detector up/d own count with register cr14[7] = 0: 0 = 3072 up/d ow n pulses 1 = 2048 up/d ow n pulses 2 lock detector precision 0 = low, coarse (16 ns) 1 = high, fine (6 ns) 1 reserved 0 reserved
adrf6850 rev. 0 | page 29 of 36 table 21 . register cr24 (address 0x18), autocalibration bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 reserved 1 reserved 0 disable autocalibration 0 = enable autocalibration (default) 1 = disable autocalibration table 22 . register cr25 (address 0x19 ), autocalibration timer bit description [7 :0 ] autocalibration t imer table 23 . register cr27 (address 0x1b), lo monitor output bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 power - up monitor output 0 = power down (default) 1 = power up [1:0] mo nitor output power into 50 ? 00 = ?24 dbm (default) 01 = ?18 dbm 10 = ?12 dbm 11 = ?6 dbm table 24 . register cr28 (address 0x1c), lo selection bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved ; s et to 1 [2:0] rfdiv 000 = d ivide by 1; lo = 500 mhz to 1000 mhz 001 = d ivide by 2; lo = 250 mhz to 500 mhz 010 = d ivide by 4; lo = 125 mhz to 250 mhz 011 = d ivide by 8; lo = 100 mhz to 125 mhz table 25 . register cr29 (address 0x1d), de modulator power and filter selection bit description 7 reserved 6 internal baseband (v ocm ) select 0 = select external baseband (v ocm ) reference 1 = select internal baseband (v ocm ) r eference [5:4] narrow - band filter cut off 00 = 50 mhz 01 = 43 mh z 10 = 37 mhz 11 = 30 mhz 3 baseband wideband/narrow - band mode s 0 = narrow - band mode 1 = wideband mode 2 reserved; set to 0 1 reserved; set to 0 0 power - up demodulator 0 = power down (default) 1 = power up table 26 . register cr30 (address 0x1e), vga bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 vga gain mode polarity 0 = positive gain slope 1 = n egative gain slope 1 reserved 0 power - up vga 0 = power down 1 = power up table 27 . register cr33 (address 0x21), revision code 1 bit description 7 revision code 6 revision code 5 revision code 4 revision code 3 revision code 2 revision code 1 revision code 0 revision code 1 read - only register.
adrf6850 rev. 0 | page 30 of 36 suggest ed power - up sequence initial register wri te sequence after applying power to the device , adhere to the following write sequence, particularly with respect to the reserved register settings . note that register cr33, register cr32, and register cr31 are rea d- only registers. also note that all writ e able registers should be written to on power - up. refer to the register map section for more details on all registers. 1. write the following to register cr30 = 0x00. set vga power to off and the vga gain slope to be positive. 2. write the following to register cr29: 0x41. t he demodulator is powered up. the baseband narrow - band mode is selected and set to a cut off frequency of 50 mhz. the internal baseband v ocm reference is selec ted. 3. write the following to register cr28 : 0x0x rfdiv depends on the value of the lo frequency to be used and is set according to table 6 . note that register cr28, bit 3 , is set to 1. 4. write the following to registe r cr27: 0x00. power the lo monitor in a power - down state . 5. write the following to register cr26: 0x00. reserved register. 6. write the following to register cr25: 0x70. set the autocalibration time to 100 s with a pfd frequency setting of 27 mhz. if the pfd frequency is different, set cr25 according to equation 3. 7. write the following to register cr24: 0x3 8. enable autocalibration. 8. write the following to register cr23: 0x70. enable lock detector and set loc k detector counter = 3072 up/d ow n pulses. 9. write the following to register cr22: 0x00. reserved register. 10. write the following to register cr21: 0x00. reserved register. 11. write the following to register cr20: 0x00. reserved register. 12. write the following to re gister cr19: 0x00. reserved register. 13. write the following to register cr18: 0x6 0. reserved register. 14. write the following to register cr17: 0x00. reserved register. 15. write the following to register cr16: 0x00. reserved register. 16. write the following to regist er cr15: 0x00. reserved register. 17. write register cr14: 0x00. lock detector co ntrol 2. 18. write register cr13: 0x0 8. reserved register. 19. write the following to register cr12: 0x18. pll powered up. 20. write the following to register cr11: 0x00. reserved register. 21. w rite the following to register cr10: 0x21 . the reference path doubler is enabled and the 5 - bit divider and r divide - by -2 divider are bypassed. 22. write the following to register cr9: 0x70. with the recommended loop filter component values and r set = 4.7 k ?, the charge pump current is set to 2. 5 ma for a loop bandwidth of 50 khz. 23. write the following to register cr8: 0x00. reserved register. 24. write the following to register cr7: 0 x0x. set according to equation 4 and equation 5 in the theory of operation section. 25. write the following to register cr6: 0 xxx. set according to equation 4 and equation 5 in the theory of operation section. 26. write register cr5: 0x00. disable the 5 - bit r eference divider. 27. wr ite the following to register cr4: 0x01. reserved register. 28. write the following to register cr3: 0 x0x. set according to equation 4 and equation 5 in the theory of operation section. 29. write the fo llowing to register cr2: 0 xxx. set according to equation 4 and equation 5 in the theory of operation section. 30. write the following to register cr1: 0 xxx. set according to equation 4 and equation 5 in the theory of operation section. 31. write the following to register cr0: 0 xxx. set according to equation 4 and equation 5 in the theory of operation section. register cr0 must be the last re gister written for all the double buffered bit writes to take effect. 32. monitor the ldet output or wait 260 s to ensure that the pll is locked. 33. write the following to register cr30: 0x01. set the vga to power on.
adrf6850 rev. 0 | page 31 of 36 evaluation board general description th e evaluation board is designed to allow the user to evaluate the performance of the adrf6850. it contains the following: ? the adrf6850 dut. this is an i/q demodulator with an integrated fractional - n pll and vco . ? spi and i 2 c interface connectors . ? baseband out put connectors. ? fourth - order low - pass loop filter circuitry . ? 13.5 mhz reference clock , and the ability to drive the reference input external to the board. ? circuitry to support differential signaling to the testlo inputs, including dc biasing circuitry . ? cir cuitry to monitor the lomon outputs . ? sma connectors for power supplies, the vgain input and a single - ended rf input. the evaluation board comes with associated software to allow easy programming of the adrf6850. hardware description for more information, r efer to the circuit diagram in figure 69 . power supplies an external +3.3 v supply (dut + 3.3 v) powers each of the nine vccx supplies on the adrf6850 as well as the 13.5 mhz clock reference. recommended decoupling for supplies in itially, t he external +3.3 v supply is decoupled by a 10 f capacitor and then further by a parallel combination of 100 nf and 56 pf capacitors that are placed as close to the dut as possible for good local decoupling. the impedance of all these capacitors should be low and constant across a broad frequency r ange. surface - mount multilayered ceramic chip (mlcc) class ii capacitors provide very low esl and esr, which assist in decoupling supply noise effectively. they also provide good tempera ture stability a nd good aging characteristics. capacitance changes per the bias voltage that is applied . larger case sizes have less capacitance change vs. applied bias voltage , and also lower esr but higher esl. a combination of 0402 size cases for the 56 pf capacitors a nd 0603 size cases for the 100 nf capacitors give a good compromise allowing the 56 pf capacitors to be placed as close as possible to the supply pins on the top side of the pcb with the 100 nf capacitors placed on the bottom side of the pcb quite close to the supply pins. x5r and x7r capacitors are examples of these types of capacitors and are recommended for decoupling. spi and i 2 c interface the spi interface connector is a nine - way, d - type connector that can be connected to the printer port of a pc. figure 68 shows the pc cable diagram that must be used with the provided software. there is also an option to use the i 2 c interface by using the i 2 c receptacle connector. this is a standard i 2 c connector. a supply voltage of +3.3 v i s provided by the i 2 c bus master. pull - up resistors are required on the signal lines. the cs pin can be used to set the slave address of the adrf6850. cs high sets the slave address to 0x78, and cs low sets the slave address to 0x58. 6 7 8 9 1 9-way female d-type 25-way male d-type to pc printer port gnd clk data le 2 3 4 5 21 22 23 24 25 8 9 10 11 12 4 5 6 7 1 2 3 16 17 18 19 20 14 15 13 pc 09316-070 figure 68 . spi pc cable diagram
adrf6850 rev. 0 | page 32 of 36 baseband outputs and vocm the pair of i and q baseband outputs are connected to the board by sma connectors. they are ac - coupled to the output connectors. vocm , which sets the common -m ode output voltage , is grounded and the internal baseb and (v ocm ) reference is selected by register cr29, bit 6 . if the external b aseband (v ocm ) reference is sel ected by setting this bit to a 0 , then a voltage needs to be applied through j6 and r20 needs to be removed. loop filter a fourt h- order loop filter is provided at the output of the charge pump and is required to adequately filter noise from the - modulator used in the n - divider. with the charge pump current set to a midscale value of 2.5 ma and using the on - chip vco, the loop bandwidth is approximately 50 khz, and the phase margin is 55. c 0 g capacitors are recommended for use in the loop filter because they have low dielectric absorption, which is required for fast and accurat e settling time. the use of non c0 g capacitors may res ult in a long tail being introduced into the pll settling time transient. reference input the reference input can be supplied by a 13.5 mhz jauch clock generator or by an external clock through the use of connector j7. the frequency range of the reference input is from 10 mhz to 300 mhz with the pfd frequency limited to a maximum of 30 mhz . doub le t he 13.5 mhz clock to 27 mhz by using the on - chip reference frequency doubler to optimize phase noise performance. testlo inputs these pins are differential test inputs that allow a variety of debug options. on this board, the capability is provided to driv e these pins with an external 4 lo signal that is then applied to an anaren balun to provide a differential input signal. when driving the testlo pins, the pll can be bypassed, and the demodulator can be driven directly by this external lo signal. the frequency of the lo signal needs to be 4 times the operating frequency. these inputs also require a dc bias. a dc bias of 3.3 v is the default option used o n the board. lomon outputs these pins are differential lo monitor outputs that provide a replica of the internal lo frequency at 1 lo. the single - ended power in a 50 ? load can be programmed to ?24 dbm, ?18 dbm, ?12 dbm, or ?6 dbm. these open - collector outputs must be terminated to 3.3 v. because both outputs must be terminated to 50 ?, options are provided to terminate to 3.3 v using on - board 50 ? resist ors or by series inductors (or a ferrite bead), in which case the 50 ? termination is provided by the measuring instrument. ccompx pins the ccompx pins are internal compensation nodes that must be decoupled to ground with a 100 nf capacitor. muxout muxout is a test output that allows different internal nodes to be monitored. it is a cmos output stage that requires no termination. lock detect (ldet) lock detect is a cmos output that indicates the state of the pll. a high level indicates a locked condition, and a low level indicates a loss of lock condition. rf inputs ( rfi , rfcm, and rfi ) rfi and rfi are 50 ? internally biased rf inputs . for single - ended operation as demonstrated on the evaluation board, rfi must be ac - coupled to the source and rfi must be ac - coupled to the ground plane. rfcm is the rf input common - mode pin. it should be con nected to rfi when driving the input in single - ended mode. when driving the input differentially using a balun, connect this pin to the common terminal of the output coil of the balun. vgain the v gain pin sets the gain of the vga. the v ga in voltage range is from 0 v to 1.5 v. this allows the gain of the vga to vary from 0 db to +6 0 db.
adrf6850 rev. 0 | page 33 of 36 pcb schematic 09316-058 figure 69 . applications circuit
adrf6850 rev. 0 | page 34 of 36 pcb artwork component placement 09316-071 figure 70 . evaluati on board, top side component 09316-073 figure 71 . evaluation board, top side layer 1 09316-075 figure 72 . evaluation board, ground layer 2 09316-072 figure 73 . evaluation board, bottom side compone nt placement 09316-076 figure 74 . evaluation board power layer 3 09316-074 figure 75 . evaluation board, bottom side layer 4
adrf6850 rev. 0 | page 35 of 36 bill of materials table 28 . bill of materials qty . reference desig nator description manufacturer part number 1 dut adrf6850 lfcsp, 56 - lead 8 mm 8 mm analog devices adrf6850bcpz 1 y2 vco, 13.5 mhz jauch 0 13.50 - vx7 -g- 3.3 -1- t1 -lf 1 spi connector, 9 - pin, d - sub plug, d - sub9mr itw mcmurdo fec 1071806 1 i 2 c connector, i 2 c, semconn receptacle digikey 5- 1761185 -1- nd 2 c1, c34 capacitor, 10 f, 25 v, tantalum, taj -c avx fec 197518 10 c4, c6, c10, c12, c14, c16, c40, c48, c53, c55 capacitor, 56 pf, 50 v, ceramic, c0g, 0402 avx fec 1658861 14 c5, c7, c11, c13, c15, c17, c22 , c27, c47, c49 to c52, c54 capacitor, 100 nf, 25 v, x7r, ceramic, 0603 avx fec 317287 1 c3 capacitor, 1.8 nf, 50 v, c0g, ceramic, 0603 murata fec 140 2814 1 c35 capacitor, 68 nf, 50 v, npo, ceramic, 1206 kemet fec 1535582 4 c2, c21, c38, c39 capacitor, 1 nf, 50 v, c0g, ceramic, 0603 murata fec 8819920 2 c44, c46 capacitor, 100 pf, 50 v, c0g, ceramic, 0402 murata fec 8819572 2 c43, c56 capacitor, 10 nf, 50 v, x7r , ceramic, 0402 murata fec 1414575 1 c18 capacitor, 10 pf, 50 v, c0g, ceramic, 0402 murata fec 8819564 4 c30 to c33 capacitor, 10 f, 6.3 v, x5r, ceramic, 0603 phycomp fec 1458902 12 j2 to j12, j14 sma end launch connector johnson/emerson 142- 0701 - 851 2 j20, j21 jumper, 3 - pin plus shunt harwin fec 148533 + fec 150411 2 l1, l2 inductor, 20 nh, 0402, lqw series murata lqw15an20n 2 l3, l4 inductor, 10 h, 0805, lqm series murata lqm21fn1n100m 2 r20, r36 resistor, 0 ?, 1/16 w, 1%, 0402 vishay draloric fec 1158241 1 r13 res istor, 4.7 k ? , 1/ 10 w, 1%, 0603 mult icomp fec 157 6293 2 r14, r39 res i stor, 1.2 k ? , 1/ 10 w, 5%, 0603 ph ycomp fec 9233393 1 r1 resistor, 220 ?, 1/16 w, 1%, 0603 multicomp fec 9330801 2 r3, r4 resistor, 200 ?, 1/16 w, 5%, 0402 vishay dale fec 151 4682 2 r17, r18 resistor, 0603, spacing (do not install) 3 r35, r44, r45 res istor, 51 ?, 1/16 w, 1%, 0402 multicomp fec 135 8008 4 r48 to r51 resistor, 330 ?, 1/10 w, 5%, 0805 vishay draloric fec 173 9223 2 r60, r61 resistor, 100 ?, 1/10 w, 5%, 0805 bourns digi key rr12p100dtr -nd 2 r46, r47 resistor, 10 k ?, 1/16 w, 1%, 0402 phyco mp fec 9239359 7 cs, ldet, muxout, vtune, sclk, sda, sdo test point, 1 - pin, 0.035 inch diameter not i nserted 1 bal1 balun, 0805, 50 ? to 100 ? b alanced (1.3 ghz to 3.1 ghz) anaren bd1631j50100a00
adrf6850 rev. 0 | page 36 of 36 outline dimensions compliant to jedec standards mo-220-vlld-2 081809-b top view 1 56 14 15 43 42 28 29 5.25 5.10 sq 4 .95 0.50 0.40 0.30 0.30 0.23 0.18 0.20 ref 12 max 0.8 0 max 0.65 typ 1.00 0.85 0.80 6.50 ref seating plane 0.60 max 0.60 max coplanarity 0.08 0.05 max 0.02 nom 0.25 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. pin 1 indicator 8.10 8.00 sq 7.90 7.85 7.75 sq 7.65 0.50 bsc bottom view exposed pad pin 1 indicator figure 76 . 56 - lead lead frame chip scale package [lfcsp_vq] 8 mm 8 mm body, very thin quad (cp - 56 - 5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adrf6850bcpz ? 40c to +85 c 56- lead lead frame chip scale package [lfcsp_vq], tray cp -56 -5 adrf6850bcpz -r7 ? 40c to +85 c 56- lead lead frame chip scale package [lfcsp_vq], 7" tape and reel cp -56 -5 eval - adrf6850eb1z evaluation board 1 z = rohs compliant part. i 2 c refers to a communications protocol originally deve loped by philips semiconductors (now nxp semiconductors) . ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09316 -0- 10/10(0)

▲Up To Search▲

Price & Availability of EVAL-ADRF6850EB1Z

	To Download EVAL-ADRF6850EB1Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .