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synchronous burst sram 128k x 36 sram +3.3v core supply, +2.5v i/o supply registered inputs, burst counter gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. pentium is a trademark of intel corporation . powerpc is a trademark of ibm corporation . galvantech, inc. reserves the right to change rev. 5/9 8 products or specifications without notice . galvantech, inc. 3080 oakmead village drive, santa clara, ca 9505 1 tel (408) 566-0688 fax (408) 566-069 9 flow-through feature s ? fast access times: 7.5, 8, 8.5, and 10n s ? fast clock speed: 117, 100, 90, and 50 mh z ? provide high performance 2-1-1-1 access rat e ? fast oe# access times: 4.0n s ? 3.3v -5% and +10% core power suppl y ? 2.5v or 3.3v i/o suppl y ? 5v tolerant inputs except i/o? s ? clamp diodes to vssq at all inputs and output s ? common data inputs and data output s ? byte write enable and global write contro l ? three chip enables for depth expansion and address pipelin e ? address, data and control register s ? internally self-timed write cycl e ? burst control pins (interleaved or linear burst sequence ) ? automatic power-down for portable application s ? low profile 119 lead, 14mm x 22mm bga (ball grid array) and 100 pin tqfp package s option s markin g ? timin g 7.5ns access/8.5ns cycle - 7 8ns access/10ns cycle - 8 8.5ns access/11ns cycle -9 10ns access/20ns cycle -1 0 ? package s 119-lead bga b 100-pin tqfp t general descriptio n the galvantech synchronous burst sram family employs high-speed, low power cmos designs using advanced triple-layer polysilicon, double-layer metal technology. each memory cell consists of four transistors and two high valued resistors . the gvt71128e36 sram integrates 131,072x36 sram cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce#), depth-expansion chip enables (ce2# and ce2), burst control inputs (adsc#, adsp#, and adv#), write enables (bw1#, bw2#, bw3#, bw4#,and bwe#), and global write (gw#) . asynchronous inputs include the output enable (oe#), burst mode control (mode), and sleep mode control (zz). the data outputs (q), enabled by oe#, are also asynchronous . addresses and chip enables are registered with either address status processor (adsp#) or address status controller (adsc#) input pins. subsequent burst addresses can be internally generated as controlled by the burst advance pin (adv#) . address, data inputs, and write controls are registered on- chip to initiate self-timed write cycle. write cycles can be one to four bytes wide as controlled by the write control inputs. individual byte write allows individual byte to be written. bw1# controls dq1-dq8 and dqp1. bw2# controls dq9-dq16 and dqp2. bw3# controls dq17-dq24 and dqp3. bw4# controls dq25-dq32 and dqp4. bw1#, bw2# bw3#, and bw4# can be active only with bwe# being low. gw# being low causes all bytes to be written . the gvt71128e36 operates from a +3.3v core power supply and all outputs operate on a +2.5v supply. all inputs and outputs are jedec standard jesd8-5 compatible. the device is ideally suited for 486, pentiu m t m , 680x0, and powe r p c t m systems and for systems that are benefited from a wide synchronous data bus .
may 29, 199 8 2 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. functional block diagra m note: the functional block diagram illustrates simplified device operation. see truth table, pin descriptions and timing diagrams for detailed information. d q d q bw3# bw4# ce# ce2 ce2# byte 3 write byte 4 write enable oe# byte 3 write adsp# adsc# address register binary counter & logic clr a16-a2 a1-a0 adv# mode 128k x 9 x 4 sram array output buffers input register
may 29, 199 8 3 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. pin assignment (top view ) pin description s bga pin s qfp pin s symbo l typ e descriptio n 4p, 4n, 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 2r, 6r, 3t, 4t, 5 t 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49,5 0 a0-a1 6 input - synchronou s addresses: these inputs are registered and must meet the setup and hold times around the rising edge of clk. the burst counter generates internal addresses associated with a0 and a1, during burst cycle and wait cycle . 5l, 5g, 3g, 3 l 93,94,95,9 6 bw1#, bw2#, bw3#, bw4# input - synchronou s byte write: a byte write is low for a write cycle and high for a read cycle. bw1# controls dq1-dq8 and dqp1. bw2# controls dq9-dq16 and dqp2. bw3# controls dq17-dq24 and dqp3. bw4# controls dq25-dq32 and dqp4. data i/o are high impedance if either of these inputs are low, conditioned by bwe# being low . 4 m 8 7 bwe # input - synchronou s write enable: this active low input gates byte write operations and must meet the setup and hold times around the rising edge of clk . 4 h 8 8 gw # input - synchronou s global write: this active low input allows a full 36-bit write to occur independent of the bwe# and bwn# lines and must meet the setup and hold times around the rising edge of clk . 4 k 8 9 cl k input - synchronou s clock: this signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock?s rising edge . 4 e 9 8 ce # input - synchronou s chip enable: this active low input is used to enable the device and to gate adsp# . 6 b 9 2 ce2 # input - synchronou s chip enable: this active low input is used to enable the device . 100-pin pqfp or 100-pin tqfp 100 99 98 97 96 95 94 93 92 91 90 89 88 1 2 3 4 5 6 7 8 9 10 31 32 33 34 35 36 37 38 39 40 41 42 43 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 a6 a7 ce# adsc# adsp# adv# clk oe# a8 a9 vcc vss gw# bwe# ce2# dqp2 dq16 dq15 vssq vccq dq10 dq9 dq8 dq7 vccq vssq dq6 dq5 vss nc vcc zz a5 a4 a3 a2 a1 a0 vss vcc a10 a14 a13 a12 a11 mode nc nc nc nc a15 a16 ce2 bw4# bw3# bw2# bw1# vccq vssq dq14 dq13 dq12 dq11 dq4 dq3 dq2 dq1 dqp1 vssq vccq dqp3 dq17 dq18 vssq vccq dq23 dq24 dq25 dq26 vccq vssq dq27 dq28 vss nc vcc nc vccq vssq dq19 dq20 dq21 dq22 dq29 dq30 dq31 dq32 dqp4 vssq vccq top view 119 lead bga 1 2 3 4 5 6 7 a b c d e f g h j k l m n p r t u nc nc nc a6 a4 ce2 a10 ce2# gw# oe# a8 a12 vss a11 nc dqp 2 dq 15 dq 13 dq 11 dq 10 nc nc zz dq8 dq1 dq 17 vss vss vcc vss vss vss nc vss vss vss vcc vss vss vccq vss vss vccq adsp# adsc# nc vcc a15 nc nc vccq dq 23 dq 22 dq 19 dq 27 dq 29 dq p 4 dq 26 dq 30 vccq nc nc a14 a5 mode a13 vcc a1 vss a0 dq3 vccq bwe# vccq nc dq5 clk vccq vcc nc adv# ce# vss vss nc nc nc nc nc dq 32 dqp1 dq2 dq 31 dq4 dq 28 dq6 bw1# bw4# dq 25 dq7 vccq dq 24 dq9 dq 12 dq 21 bw2# bw3# dq 20 vccq dq 18 dq 14 dqp3 dq 16 a7 a2 vccq a16 a3 a9
may 29, 199 8 4 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. pin descriptions (continued ) burst address table (mode = nc/vccq ) burst address table (mode = gnd ) bga pin s qfp pin s symbo l typ e descriptio n 2 b 9 7 ce 2 input - synchronou s chip enable: this active high input is used to enable the device . 4 f 8 6 oe # inpu t output enable: this active low asynchronous input enables the data output drivers . 4 g 8 3 adv # input - synchronou s address advance: this active low input is used to control the internal burst counter. a high on this pin generates wait cycle (no address advance). 4 a 8 4 adsp # input - synchronou s address status processor: this active low input, along with ce# being low, causes a new external address to be registered and a read cycle is initiated using the new address . 4 b 8 5 adsc # input - synchronou s address status controller: this active low input causes device to be de-selected or selected along with new external address to be registered. a read or write cycle is initiated depending upon write control inputs . 3 r 3 1 mod e input - stati c mode: this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst . 7 t 6 4 z z input- asynchronou s snooze: this active high input puts the device in low power consumption standby mode. for normal operation, this input has to be either low or nc (no connect) . 7p, 7n, 6n, 6m, 6l, 7l, 6k, 7k, 7h, 6h, 7g, 6g, 6f, 6e, 7e, 7d, 1d, 1e, 2e, 2f, 1g, 2g, 1h, 2h, 1k, 1l, 2k, 2l, 2m, 1n, 2n, 1 p 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72-75, 78, 79, 2, 3, 6-9, 12, 13, 18, 19, 22-25, 28, 2 9 dq1-dq3 2 input / outpu t data inputs/outputs: first byte is dq1-dq8. second byte is dq9-dq16. third byte is dq17-dq24. fourth byte is dq25-dq32. input data must meet setup and hold times around the rising edge of clk . 6p, 6d, 2d, 2 p 51, 80, 1, 3 0 dqp1 - dqp 4 input/ outpu t parity inputs/outputs: dqp1 is parity bit for dq1-dq8 and dqp2 is parity bit for dq9-dq16. dqp3 is parity bit for dq17-dq24 and dqp4 is parity bit for dq25-dq32 . 4c, 2j, 4j, 6j, 4 r 15, 41,65, 9 1 vc c suppl y core power supply: +3.3v -5% and +10 % 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5 p 17, 40, 67, 9 0 vs s groun d ground: gnd . 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7 u 4, 11, 20, 27, 54, 61, 70, 7 7 vcc q i/o suppl y output buffer supply: +2.5v (from 2.375v to vcc ) 5, 10, 21, 26, 55, 60, 71, 7 6 vss q i/o groun d output buffer ground: gn d 1b, 7b, 1c, 7c, 4d, 3j, 5j, 4l, 1r, 5r, 7r, 1t, 2t, 6t, 2u, 3u, 4u, 5u, 6 u 14, 16, 38, 39, 42, 43, 6 6 n c - no connect: these signals are not internally connected . first address (external ) second address (internal ) third address (internal ) fourth address (internal ) a...a0 0 a...a0 1 a...a1 0 a...a1 1 a...a0 1 a...a0 0 a...a1 1 a...a1 0 a...a1 0 a...a1 1 a...a0 0 a...a0 1 a...a1 1 a...a1 0 a...a0 1 a...a0 0 first address (external ) second address (internal ) third address (internal ) fourth address (internal ) a...a0 0 a...a0 1 a...a1 0 a...a1 1 a...a0 1 a...a1 0 a...a1 1 a...a0 0 a...a1 0 a...a1 1 a...a0 0 a...a0 1 a...a1 1 a...a0 0 a...a0 1 a...a1 0
may 29, 199 8 5 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. truth tabl e note: 1. x means ?don?t care.? h means logic high. l means logic low. write# = l means [bwe# + bw1#*bw2#*bw3#*bw4#]*gw# equals low. write# = h means [bwe# + bw1#*bw2#*bw3#*bw4#]*gw# equals high . 2. bw1# enables write to dq1-dq8 and dqp1. bw2# enables write to dq9-dq16 and dqp2. bw3# enables write to dq17- dq24 and dqp3. bw4# enables write to dq25-dq32 and dqp4 . 3. all inputs except oe# must meet setup and hold times around the rising edge (low to high) of clk . 4. suspending burst generates wait cycle . 5. for a write operation following a read operation, oe# must be high before the input data required setup time plus high-z time for oe# and staying high throughout the input data hold time . 6. this device contains circuitry that will ensure the outputs will be in high-z during power-up . 7. adsp# low along with chip being selected always initiates an read cycle at the l-h edge of clk. a write cycle can be performed by setting write# low for the clk l-h edge of the subsequent wait cycle. refer to write timing diagram for clarification . partial truth table for read/writ e operatio n addres s use d ce # ce2 # ce 2 adsp # adsc # adv # write # oe # cl k d q deselected cycle, power dow n non e h x x x l x x x l- h high- z deselected cycle, power dow n non e l x l l x x x x l- h high- z deselected cycle, power dow n non e l h x l x x x x l- h high- z deselected cycle, power dow n non e l x l h l x x x l- h high- z deselected cycle, power dow n non e l h x h l x x x l- h high- z read cycle, begin burs t externa l l l h l x x x l l- h q read cycle, begin burs t externa l l l h l x x x h l- h high- z write cycle, begin burs t externa l l l h h l x l x l- h d read cycle, begin burs t externa l l l h h l x h l l- h q read cycle, begin burs t externa l l l h h l x h h l- h high- z read cycle, continue burs t nex t x x x h h l h l l- h q read cycle, continue burs t nex t x x x h h l h h l- h high- z read cycle, continue burs t nex t h x x x h l h l l- h q read cycle, continue burs t nex t h x x x h l h h l- h high- z write cycle, continue burs t nex t x x x h h l l x l- h d write cycle, continue burs t nex t h x x x h l l x l- h d read cycle, suspend burs t curren t x x x h h h h l l- h q read cycle, suspend burs t curren t x x x h h h h h l- h high- z read cycle, suspend burs t curren t h x x x h h h l l- h q read cycle, suspend burs t curren t h x x x h h h h l- h high- z write cycle, suspend burs t curren t x x x h h h l x l- h d write cycle, suspend burs t curren t h x x x h h l x l- h d functio n gw # bwe # bw1 # bw2 # bw3 # bw4 # rea d h h x x x x rea d h l h h h h write one byt e h l l h h h write all byte s h l l l l l write all byte s l x x x x x
absolute maximum ratings * voltage on vcc supply relative to vss......-0.5v to +4.6 v v in .........................................................-0.5v to vcc+0.5 v storage temperature (plastic) .......................-5 5 o c to +12 5 o junction temperature ...................................................+12 5 o power dissipation ..........................................................1.6 w short circuit output current (per i/o).........................20m a *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device.this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability . may 29, 199 8 6 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. dc electrical characteristics and recommended operating condition s ( 0 o c t a 70c; vcc = 3.3v -5% and +10% unless otherwise noted ) descriptio n condition s symbo l mi n ma x unit s note s input high (logic 1) voltag e data inputs (dqxx ) v ih d 1. 7 vcc+0. 3 v 1, 2 all other input s v i h 1. 7 4. 6 v 1, 2 input low (logic 0) voltag e v i l -0. 3 0. 7 v 1, 2 input leakage curren t 0v < v i n < vc c i l i - 2 2 u a 1 4 output leakage curren t output(s) disabled, 0 v < v ou t < vc c i l o - 2 2 u a output high voltag e i o h = -2.0m a v o h 1. 7 v 1, 1 1 output low voltag e i o l = 2.0m a v o l 0. 7 v 1, 1 1 supply voltag e vc c 3.13 5 3. 6 v 1 i/o supply voltag e vcc q 2.37 5 vc c v 1 descriptio n condition s sy m ty p - 7 - 8 - 9 -1 0 unit s note s power supply current: operatin g device selected; all inputs < v i l or > v i h ;cycle time > t kc min; vcc =max; outputs ope n ic c 15 0 37 0 32 0 29 0 20 0 m a 3, 12, 1 3 cmos standb y ttl standb y clock runnin g device deselected; vcc = max ; all inputs < vss +0.2 or > vcc -0.2 ; all inputs static; clk frequency = 0 i sb 2 5 1 0 1 0 1 0 1 0 m a 12,1 3 device deselected; all inputs < v i l or > v i h ; all inputs static ; vcc = max; clk frequency = 0 i sb 3 1 0 2 0 2 0 2 0 2 0 m a 12,1 3 device deselected ; all inputs < v i l or > v i h ; vcc = max ; clk cycle time > t kc mi n i sb 4 4 0 8 0 7 0 6 0 4 0 m a 12,1 3
may 29, 199 8 7 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. ac electrical characteristics (note 5) ( 0 o c t a 7 0 o c; vcc = 3.3v -5% and +10% ) capacitanc e thermal consideratio n typical output buffer characteristic s descriptio n - 7 - 8 - 9 - 1 0 sy m mi n ma x mi n ma x mi n ma x mi n ma x unit s note s cloc k clock cycle tim e t k c 8. 5 1 0 1 1 2 0 n s clock high tim e t k h 3 4 4. 5 4. 5 n s clock low tim e t k l 3 4 4. 5 4. 5 n s output time s clock to output vali d t k q 7. 5 8 8. 5 1 0 n s clock to output invali d t kq x 2 2 2 2 n s clock to output in low- z t kql z 0 0 0 0 n s 4, 6, 7 clock to output in high- z t kqh z 2 3. 5 2 3. 5 2 3. 5 2 3. 5 n s 4, 6, 7 oe to output vali d t oe q 4. 0 4. 0 4. 0 4. 0 n s 9 oe to output in low- z t o e l z 0 0 0 0 n s 4, 6, 7 oe to output in high- z t o e h z 3. 5 3. 5 3. 5 3. 5 n s 4, 6, 7 setup time s address, controls and data i n t s 1. 5 2. 0 2. 0 2. 0 n s 1 0 hold time s address, controls and data i n t h 0. 5 0. 5 0. 5 0. 5 n s 1 0 descriptio n condition s symbo l ty p ma x unit s note s input capacitanc e t a = 2 5 o c; f = 1 mh z vcc = 3.3 v c i 4 5 p f 4 input/output capacitance (dq ) c o 7 8 p f 4 descriptio n condition s symbo l tqfp ty p unit s note s thermal resistance - junction to ambien t still air, soldered on 4.25 x 1.125 inch 4-layer pc b q j a 2 5 o c/ w thermal resistance - junction to cas e q j c 9 o c/ w output high voltag e pull-up curren t output low voltag e pull-down curren t voh (v ) ioh ( m a) m i n ioh ( m a) m a x vol (v ) i o l ( m a) m i n i o l ( m a) m a x -0. 5 -3 8 -10 5 -0. 5 0 0 0 -3 8 -10 5 0 0 0 0. 8 -3 8 -10 5 0. 4 1 0 2 0 1.2 5 -2 6 -8 3 0. 8 2 0 4 0 1. 5 -2 0 -7 0 1.2 5 3 1 6 3 2. 3 0 -3 0 1. 6 4 0 8 0 2. 7 0 -1 0 2. 8 4 0 8 0 2. 9 0 0 3. 2 4 0 8 0 3. 4 0 0 3. 4 4 0 8 0
ac test condition s input pulse level s 0v to 2.5v input slew rat e 1.0v/ns output rise and fall times(max ) 1.8ns input timing reference level s 1.25v output reference level s 1.25v output loa d see figures 1 output load s vt = 1.25v dq z 0 = 50 w fig. 1 output load equivalent 50 w may 29, 199 8 8 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. note s 1. all voltages referenced to vss (gnd) . 2. overshoot: v i h +6.0v for t t kc /2 . undershoot: v i l -2.0v for t t kc / 2 3. i c c is given with no output current. i c c increases with greater output loading and faster cycle times . 4. this parameter is sampled . 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted . 6. measured at + 200mv from steady state . 7. at any given temperature and voltage condition, t kqhz is less than t kqlz and t oehz is less than t oelz . 8. a read cycle is defined by byte write enables all high or adsp# low along with chip enables being active for the required setup and hold times. a write cycle is defined by at one byte or all byte write per read/write truth table . 9. oe# is a ?don?t care? when a byte write enable is sampled low . 10. this is a synchronous device. all synchronous inputs must meet specified setup and hold time, except for ?don?t care? as defined in the truth table . 11. ac i/o curves are available upon request . 12. ?device deselected? means the device is in power -down mode as defined in the truth table. ?device selected? means the device is active . 13. typical values are measured at 3.3v, 2 5 o c and 20ns cycle time . 14. mode pin has an internal pull-up and zz pin has an internal pull-down. these two pins exhibit an input leakage current of + 30 m a . 15. capacitance derating applies to capacitance different from the load capacitance shown in fig. 1.
may 29, 199 8 9 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. read timin g note: ce# active in this timing diagram means that all chip enables ce#, ce2, and ce2# are active . clk adsp# adsc# address bw1#, bw2#, bw3#, bw4#, bwe#, gw# ce# (see note) adv# oe# dq a1 a2 q(a1) q(a2) q(a2+1) q(a2+2) q(a2+3) q(a2) q(a2+1) q(a2+2) t kq t kqlz t oelz
may 29, 199 8 1 0 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. write timin g note: ce# active in this timing diagram means that all chip enables ce#, ce2, and ce2# are active . clk adsp# adsc# address bw1#, bw2#, bw3#, bw4#, bwe# ce# (see note) adv# oe# dq a1 a2 d(a2) d(a2+2) d(a2+3) d(a3) d(a3+1) d(a3+2) t s t s t h t h t s t h gw# a3 d(a1) d(a2+2) t kqx t oehz q d(a2+2) single write burst write burst write
may 29, 199 8 1 1 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. read/write timin g note: ce# active in this timing diagram means that all chip enables ce#, ce2, and ce2# are active . clk adsp# adsc# address bw1#, bw2#, bw3#, bw4#, bwe#, gw# ce# (see note) adv# oe# dq a1 a2 a3 q(a1) q(a2) t s t h t s t h a4 d(a3) q(a4) q(a4+1) q(a4+2) q(a4+3) d(a5) d(a5+1) single write burst read burst write single reads a5
may 29, 199 8 1 2 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. 100 pin tqfp package dimension s
may 29, 199 8 1 3 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. 7 x 17 (119-lead) bga dimension s note: all dimensions in millimeters 0.60 + 0.10 0.90 + 0.10 a b c d e f g h j k l m n p r t u 1 2 3 4 5 6 7 20.32 1.27 22.00 + 0.20
may 29, 199 8 1 4 galvantech, inc. reserves the right to change products or specifications without notice . rev. 5/9 8 gvt71128e36 128k x 36 synchronous burst sram galvantec h , inc. ordering informatio n gv t 71128e3 6 x - x x galvantech prefi x part numbe r package (b = 119 lead bga, speed (7 = 7.5ns access/8.5ns cycle t = 100 pin tqfp) 8 = 8.0ns access/10ns cycle 9 = 8.5ns access/11ns cycle 10 = 10ns access/20ns cycle)

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