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? 2014 microchip technology inc. preliminary ds70005165a-page 1 features ? high gain: - typically 39 db gain across 2.4?2.5 ghz over temperature -20c to +85c ? high linear output power: - >30 dbm p1db - please refer to ?absolute maximum stress ratings? on page 5 - meets 802.11g ofdm spectrum mask require- ment up to 28 dbm - typically 25 dbm with <3% evm, 802.11g, 54 mbps, 350 ma current - typically 24 dbm with <2.5% evm, 802.11n, mcs7-ht20, 50% duty cycle - typically 23 dbm with <1.75% evm, mcs9- ht40, 50% duty cycle, 320 ma current - meets 802.11b acpr requirement up to 28 dbm with 30% power-added efficiency ? high-speed power-up/down - turn on/off time (10%-90%) <100 ns ? 10:1 vswr survivability (unconditionally stable up to 28 dbm) ? on-chip power detection - >20 db dynamic range - vswr- and temperature-insensitive ? simple input/output matching ? packages available - 16-contact uqfn (3mm x 3mm) ? all non-pb (lead-free) devices are rohs compli- ant applications ? wlan (ieee 802.11b/g/n) ? wlan 256 qam ? ap router ? home rf ? cordless phones ? 2.4 ghz ism wireless equipment 1.0 product description SST12CP21 is a high-power and high-gain power amplifier (pa) based on the highly-reliable ingap/gaas hbt technology. this pa can be easily configured for high-power appli- cations with high power-added efficiency while operat- ing over the 2.4-2.5 ghz frequency band. it typically provides 39 db gain with 25% power-added efficiency @ p out = 28 dbm for 802.11g. SST12CP21 has excellent linearity, typically 25 dbm at 3% evm with 54 mbps 802.11g operation while meet- ing 802.11g spectrum mask at 28 dbm. SST12CP21 also has a single-ended power detector which lowers the users? cost for power control. the power amplifier ic also features easy board-level usage along with high-speed power-up/-down control. SST12CP21 is of fered in 16-contact uqfn package. see figure 3-1 for pin assignments and table 4-1 for pin descriptions. SST12CP21 2.4 ghz high-gain, high-efficiency power amplifier
SST12CP21 ds70005165a-page 2 preliminary ? 2014 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing communications department via e- mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. ? 2014 microchip technology inc. preliminary ds70005165a-page 3 SST12CP21 2.0 functional blocks figure 2-1: functional block diagram 2 56 8 16 nc 15 1 14 nc vcc1 49 11 12 10 13 vcc2 nc nc det nc nc rfout/vcc3 rfout/vcc3 nc rfin 3 vref nc vccb bias circuit 7 70005165 b1.1 SST12CP21 ds70005165a-page 4 preliminary ? 2014 microchip technology inc. 3.0 pin assignments figure 3-1: pin assignments for 16-contact uqfn 4.0 pin descriptions 56 8 16 nc 15 14 nc vcc1 9 11 12 10 13 vcc2 nc nc det nc nc rfout/vcc3 rfout/vcc3 nc 2 1 4 3 rfin vref nc vccb 7 70005165 p1.0 top view (contacts facing down) rf and dc gnd 0 table 4-1: pin description symbol pin no. pin name type 1 1. i=input, o=output function gnd 0 ground the center pad should be connected to rf ground rfin 1 rf in i rf input, dc decoupled vref 2 v ref pwr pa enable and idle-current control nc 3 no connection no internal connection vccb 4 power supply pwr supply voltage for bias circuit nc 5 no connection no internal connection nc 6 no connection no internal connection vdet 7 v det o on-chip power detector nc 8 no connection no internal connection nc 9 no connection no internal connection rfout 10 rf out o rf output rfout 11 rf out o rf output nc 12 no connection no internal connection vcc2 13 v cc2 pwr pwr power supply, 2 nd stage nc 14 nc no internal connection vcc1 15 v cc1? pwr pwr power supply, 1 st stage nc 16 no connection no internal connection ? 2014 microchip technology inc. preliminary ds70005165a-page 5 SST12CP21 5.0 electrical specifications the dc and rf specifications for the power amplifier are specified below. refer to table 5-2 for the dc volt- age and current specifications. absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maxi- mum stress ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) input power to pin 1 (p in ) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 dbm 1. maximum input power for v cc = 5v with 50% duty cycle, 802.11g 54 mbps, with maximum output vswr = 10:1. at v cc =5v, a10 resistor must be included on v cc1 , as shown in figures 6-8 and 6-9. supply voltage at pins 4, 10, 11, 13 and 15 (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v reference voltage to pin 2 (v ref1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.2 v dc supply current (i cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 ma operating temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oc to +85oc storage temperature (t stg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oc to +120oc maximum junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oc surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds table 5-1: operating range range ambient temp v cc industrial -20c to +85c 5.0v table 5-2: dc electrical characteristics at 25oc symbol parameter min. typ max. unit v cc supply voltage 4.0 5.0 5.5 v i cc dc current for 802.11g, 28 dbm 440 ma for 802.11b, 28 dbm 440 ma i cq idle current 275 ma v reg reference voltage see figure 6-8 on page 10 2.9 2.95 3.1 v i reg reference current 8ma SST12CP21 ds70005165a-page 6 preliminary ? 2014 microchip technology inc. table 5-3: ac electrical characteristics for configuration at v cc = 5v, v ref = 2.95v, 25oc, 50% duty cycle symbol parameter min. typ max. unit f l-u frequency range in 802.11b/g applications 2400 2500 mhz p out output power at 3% evm with 802.11g ofdm at 54 mbps 25 dbm output power at 2.5% evm with 802.11n mcs7 ht20 24 dbm output power at 1.75% evm with 256 qam mcs9 ht40 23 dbm output power meeting 802.11g spectral mask, 6 mbps 28 dbm output power meeting 802.11n ht20 spectral mask 26 dbm output power meeting mcs9-ht40 spectral mask 26 dbm output power meeting 802.11b spectral mask with 11 mbps cck 28 dbm g power gain for 802.11b/g/n/256 qam 37 39 db g var gain variation over band 0.5 db 2f second harmonic at 29 dbm, 802.11b mask compliance 1 -50 dbm/mhz 3f third harmonic at 29 dbm, 802.11b mask compliance 1 -50 dbm/mhz 1. see figure 6-9 ? 2014 microchip technology inc. preliminary ds70005165a-page 7 SST12CP21 6.0 typical performance characteristics test conditions: v cc = 5.0v, v reg = 2.95v, t a = 25c, ieee 802.11g, 54 mbps, 50% duty cycle unless otherwise specified figure 6-1: s-parameter figure 6-2: dynamic evm versus output power -60 -50 -40 -30 -20 -10 0 10 20 30 40 012345678910 mag (db) frequency (ghz) s - parameter s11 s21 s12 s22 70005165 f6-1 70005165 f6-2 0 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 evm (%) output power (dbm) 2412 2442 2472 SST12CP21 ds70005165a-page 8 preliminary ? 2014 microchip technology inc. figure 6-3: dynamic evm versus output power 802.11ac, mcs0-ht40, 50% duty cycle figure 6-4: power gain versus output power 70005165 f6-3 7000 5165 f6- 3 70005165 f6-4 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 power gain (db) output power (dbm) freq=2.412 ghz freq=2.442 ghz freq=2.472 ghz ? 2014 microchip technology inc. preliminary ds70005165a-page 9 SST12CP21 figure 6-5: dc current versus output power figure 6-6: detector output voltage versus output power 70005165 f6-5.1 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 supply current (ma) output power (dbm) freq=2.412 ghz freq=2.442 ghz freq=2.472 ghz 70005165 f6-6.1 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 0123456789101112131415161718192021222324252627282930 detector voltage (v) output power (dbm) freq=2.412 ghz freq=2.442 ghz freq=2.472 ghz SST12CP21 ds70005165a-page 10 preliminary ? 2014 microchip technology inc. figure 6-7: dynamic evm versus output power (with harmonic filter) figure 6-8: typical schematic for 256 qam applications 70005165 f6-6 0 1 2 3 4 5 6 7 8 9 10 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 evm (%) output power (dbm) 2412 2442 2472 rfout 1.5 pf 50 /0.7mm vreg vcc 0.1 f vdet 70005165 schematic.1.2 suggested operation conditions: 1. v cc = 5.0v/ v reg = 2.95v 2. center slug to rf ground * note: r = 10 for robustness at 5.5v v cc 0.1 f 50 /3.7mm 1.6 pf 100 pf 10 f 2 56 8 16 15 1 14 49 11 12 10 13 3 7 rfin 50 15 0.1 f 2.7 nf bias circuit 15 nh 1 f 0 * ? 2014 microchip technology inc. preliminary ds70005165a-page 11 SST12CP21 figure 6-9: schematic with harmonic filter for 256 qam applications rfout 2.7 pf 50 /1mm vreg vcc vdet 70005165 schematic.2.1 suggested operation conditions: 1. v cc = 5.0v/ v reg = 2.95v 2. center slug to rf ground * note: r = 10 for robustness at 5.5v v cc 0.1 f 1.0nh 1.0 pf 10 pf 10 f 2 56 8 16 15 1 14 49 11 12 10 13 3 7 rfin 50 15 0.1 f 2.7 nf bias circuit 15 nh 1 f 1.3nh 2.0 pf 2.7nh 1.0 pf 0.1 f 0 * SST12CP21 ds70005165a-page 12 preliminary ? 2014 microchip technology inc. 7.0 packaging diagrams ) r u w k h p r v w f x u u h q w s d f n d j h g u d z l q j v s o h d v h v h h w k h 0 l f u r f k l s 3 d f n d j l q j 6 s h f l i l f d w l r q o r f d w h g d w k w w s z z z p l f u r f k l s f r p s d f n d j l q j note: 0 l f u r f k l s 7 h f k q r o r j \ ' u d z l q j & |