?001 fairchild semiconductor corporation IRFD320 rev. a file number 2325.4 IRFD320 0.5a, 400v, 1.800 ohm, n-channel power mosfet this n-channel enhancement mode silicon gate power ?ld effect transistor is an advanced power mosfet designed, tested, and guaranteed to withstand a speci?d level of energy in the breakdown avalanche mode of operation. all of these power mosfets are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. these types can be operated directly from integrated circuits. formerly developmental type ta17404. features 0.5a, 400v ? ds(on) = 1.800 ? single pulse avalanche energy rated soa is power dissipation limited nanosecond switching speeds linear transfer characteristics high input impedance related literature - tb334 ?uidelines for soldering surface mount components to pc boards symbol packaging hexdip ordering information part number package brand IRFD320 hexdip IRFD320 note: when ordering, use the entire part number. g d s source gate drain data sheet july 1999 t itle fd 0 ) b- t 5 a, 0 v, 0 0 m , a n- w er o s- t ) u tho e y- r ds 5 a, 0 v, 0 0 m , a n- w er o s- t , e r- r po- on, x- p ) e - r () o ci o
?001 fairchild semiconductor corporation IRFD320 rev. a absolute maximum ratings t c = 25 o c, unless otherwise speci?d IRFD320 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ds 400 v drain to gate voltage (r gs = 20k ?) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 400 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d 0.5 a pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 2.0 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d 1.0 w linear derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.008 w/ o c single pulse avalanche energy rating (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as 100 mj operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j, t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 125 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 9) 400 - - v gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 2.0 - 4.0 v zero gate voltage drain current i dss v ds = rated bv dss , v gs = 0v - - 25 a v ds = 0.8 x rated bv dss , v gs = 0v, t c = 125 o c- -250 a on-state drain current (note 2) i d(on) v ds > i d(on) x r ds(on)max , v gs = 10v 0.5 - - a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance (note 2) r ds(on) i d = 0.25a, v gs = 10v (figures 7, 8) - 1.5 1.8 ? forward transconductance (note 2) g fs v ds 10v, i d = 2.0a (figure 11) 1.7 2.0 - s turn-on delay time t d(on) v dd = 0.5 x rated bv dss , i d 0.5a, r g = 9.1 ?, v gs = 10v, r l = 398 ? for v dss = 200v mosfet switching times are essentially independent of operating temperature -2040ns rise time t r -2550ns turn-off delay time t d(off) - 50 100 ns fall time t f -2550ns total gate charge (gate to source + gate to drain) q g(tot) v gs = 10v, i d = 0.5a, v ds = 0.8 x rated bv dss , i g(ref) = 1.5 a (figure 13), gate charge is essentially independent of operating temperature -1215nc gate to source charge q gs - 6.0 - nc gate to drain ?iller?charge q gd - 6.0 - nc input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 10) - 455 - pf output capacitance c oss -100- pf reverse transfer capacitance c rss -20- pf internal drain inductance l d measured from drain lead, 2.0mm (0.08in) from package to center of die modified mosfet symbol showing the internal device inductances - 4.0 - nh internal source inductance l s measured from the source lead, 2.0mm (0.08in) from package to source bonding pad - 6.0 - nh thermal resistance junction to ambient r ja free air operation - - 120 o c/w l s l d g d s IRFD320
?001 fairchild semiconductor corporation IRFD320 rev. a source to drain diode speci?ations parameter symbol test conditions min typ max units continuous source to drain current i sd modified mosfet symbol showing the integral reverse p-n junction rectifier --0.5a pulse source to drain current (note 3) i sdm --2.0a source to drain diode voltage (note 2) v sd t j = 25 o c, i sd = 2.0a, v gs = 0v (figure 12) - - 1.6 v reverse recovery time t rr t j = 150 o c, i sd = 2.0a, di sd /dt = 100a/ s - 450 - ns reverse recovery charge q rr t j = 150 o c, i sd = 2.0a, di sd /dt = 100a/ s- 3.1 - c notes: 2. pulse test: pulse width 300 s, duty cycle 2%. 3. repetitive rating: pulse width limited by maximum junction temperature. 4. v dd = 40v, starting t j = 25 o c, l = 29.09mh, r g = 50 ?, peak i as = 2.5a. typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. forward bias safe operating area figure 4. output characteristics g d s t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 50 100 i d , drain current (a) t c , case temperature ( o c) 150 25 75 125 0.5 0.3 0.1 v ds , drain to source voltage (v) i d , drain current (a) 100 s 1ms dc 10 s t j = max rated single pulse 2 1 0.1 00.1 0.001 1 10 100 1000 10ms 100ms 1s t c = 25 o c i d , drain current (a) 0 100 200 300 1 2 3 4 5 v ds , drain to source voltage (v) 0 6 pulse duration = 80 s v gs = 5.0v v gs = 4.5v v gs = 4.0v v gs = 5.5v v gs = 6.0v v gs = 10v duty cycle = 0.5% max IRFD320
?001 fairchild semiconductor corporation IRFD320 rev. a figure 5. saturation characteristics figure 6. transfer characteristics note: heating effect of 2 s pulse is minimal. figure 7. drain to source on resistance vs gate voltage and drain current figure 8. normalized drain to source on resistance vs junction temperature figure 9. normalized drain to source breakdown voltage vs junction temperature figure 10. capacitance vs drain to source voltage typical performance curves unless otherwise speci?d (continued) 0 1 0 4 812 20 2 3 i d , drain current (a) v ds , drain to source voltage (v) 4 16 5 v gs = 10v v gs = 6.0v v gs = 5.5v v gs = 5.0v v gs = 4.5v v gs = 4.0v pulse duration = 80 s duty cycle = 0.5% max 5 4 3 2 1 0 0123 4 6 v gs , gate to source voltage (v) t j = 125 o c t j = 25 o c t j = -55 o c i d , drain current (a) 5 6 pulse duration = 80 s duty cycle = 0.5% max 0 3 2 46 r ds(on) , drain to source i d , drain current (a) 8 4 0 1 2 5 2 s pulse test v gs = 20v v gs = 10v 10 12 6 on resistance ( ? ) duty cycle = 0.5% max normalized drain to source 2.2 1.4 1.0 0.6 0.2 -40 0 40 t j , junction temperature ( o c) 120 1.8 80 on resistance pulse duration = 80 s duty cycle = 0.5% max v gs = 10v, i d = 0.25a normalized drain to source 1.25 1.05 0.95 0.85 0.75 -40 0 40 t j , junction temperature ( o c) 120 1.15 80 160 breakdown voltage i d = 250 a 1000 200 0 0 20 50 c, capacitance (pf) 600 v ds , drain to source voltage (v) 800 400 c iss c oss c rss 10 30 40 c iss = c gs + c gd c rss = c gd c oss c ds + c gd v gs = 0v, f = 1mhz IRFD320
?001 fairchild semiconductor corporation IRFD320 rev. a figure 11. transconductance vs drain current figure 12. source to drain diode voltage figure 13. gate to source voltage vs gate charge test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms typical performance curves unless otherwise speci?d (continued) i d , drain current (a) g fs , transconductance (s) 01 2 34 1 2 3 4 5 5 0 t j = 125 o c t j = -55 o c t j = 25 o c 6 pulse duration = 80 s duty cycle = 0.5% max 01234 v sd , source to drain voltage (v) 100 10 1 i sd , source to drain current (a) t j = 150 o c t j = 25 o c t j = 150 o c t j = 25 o c pulse duration = 80 s duty cycle = 0.5% max 048121620 q g , gate charge (nc) v gs , gate to source voltage (v) 0 5 10 15 20 i d = 0.5a v ds = 200v v ds = 80v v ds = 320v t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 IRFD320
?001 fairchild semiconductor corporation IRFD320 rev. a figure 16. switching time test circuit figure 17. resistive switching waveforms figure 18. gate charge test circuit figure 19. gate charge waveforms test circuits and waveforms (continued) v gs r l r g dut + - v dd t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 0.3 f 12v battery 50k ? v ds s dut d g i g(ref) 0 (isolated v ds 0.2 f current regulator i d current sampling i g current sampling supply) resistor resistor same type as dut q g(tot) q gd q gs v ds 0 v gs v dd i g(ref) 0 IRFD320
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