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techwell, inc. 1 rev c 02/07/2008 TW8811 -- tft flat panel controller with built-in 3d video decoder, triple adcs, and pip support preliminary data sheet from techwell, inc. information may chang e without notice disclaimer this document provides technical information for the user. techwell inc. reserves the right to modify the information in this document as necessary. the customer should make sure that they have the most recent data sheet version. techwell inc. holds no responsibility for any errors that may appear in this document. customers should take appropriate action to ensure their use of the products does not infringe upon any patents. techwell inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights.
TW8811 ? tft flat panel controller preliminary techwell, inc. 2 rev c 02/07/2008 introduction.......................................................................................4 applications ................................................................................................ 4 analog rgb inputs................................................................................. 4 24bit digital rgb and 8/16/24-bit ycbcr inputs................................. 4 tft panel support ................................................................................. 4 on screen display.................................................................................. 5 image processing ................................................................................... 5 pip function............................................................................................. 5 sdram .................................................................................................... 5 host interface........................................................................................... 5 clock generation .................................................................................... 5 power management............................................................................... 5 miscellaneous .......................................................................................... 5 order information.............................................................................6 functional description ....................................................................8 overview ...................................................................................................... 8 analog front-end....................................................................................... 9 video source selection.......................................................................... 9 clamping and automatic gain control ................................................ 9 video decoder ............................................................................................ 9 sync processor........................................................................................ 9 color decoding...................................................................................... 10 automatic standard detection.............................................................. 11 video format support........................................................................... 11 analog rgb / ypbpr processor .......................................................... 12 analog front-end .................................................................................. 12 sync processor ..................................................................................... 12 component processor ......................................................................... 12 digital input support ............................................................................... 12 tft panel support................................................................................... 12 dithering.................................................................................................. 12 image control ........................................................................................... 13 input image control .............................................................................. 13 image scaling ........................................................................................ 13 display timing ....................................................................................... 16 on screen display................................................................................... 16 bitmapped mode................................................................................... 16 external osd port................................................................................. 16 microcontroller interface ....................................................................... 17 power management ................................................................................ 21 gamma correction.................................................................................. 21 memory interface ..................................................................................... 21 test modes ................................................................................................ 21 pin diagram.....................................................................................22 pin description ...............................................................................23 parametric information..................................................................29 ac/dc electrical parameters................................................................ 29 filter curves....................................................................................31 anti-alias filter ......................................................................................... 31 decimation filter ..................................................................................... 31 chroma band pass filter curves....................................................... 32 luma notch filter curve for ntsc and pal.................................... 32 chrominance low-pass filter curve ................................................. 33 mechanical data 208 qfp ...........................................................34 TW8811 register summary ..........................................................36 general (common for any page)........................................................ 36 decoder .................................................................................................. 37 decoder .................................................................................................. 38 rgb/ypbpr (analog) ........................................................................... 38 lcdc ? 3d comb/nr control............................................................ 39 internal test............................................................................................ 39 lcdc ? osd i....................................................................................... 40 lcdc ? reserve................................................................................... 41 ccfl control......................................................................................... 41 lcdc ? external osd & misc. ........................................................... 41 lcdc ? dma ........................................................................................ 42 lcdc ? status & interrupt ................................................................... 42 lcdc : adc/llpll ............................................................................. 43 lcdc ? gamma................................................................................... 43 lcdc ? input measurement ............................................................... 44 lcdc - scaling......................................................................................45 lcdc ? image adjustment .................................................................46 lcdc ? display control .......................................................................47 lcdc ? memory control .....................................................................47 lcdc ? pip/mpip control ..................................................................48 lcdc ? power management .............................................................49 lcdc ? tcon ......................................................................................50 lcdc ? pll & dac.............................................................................51 TW8811 register description ...................................................... 52 0x000 ? product id code register (id) ............................................52 0x001 ? chip status register (cstatus).......................................52 0x002 ? input format (inform)........................................................52 0x003 ? qclamp ................................................................................52 0x004 ? ckhy.......................................................................................53 0x005 ? reserved.................................................................................53 0x006 ? analog control register (acntl).......................................53 0x007 ? cropping register, high (crop_hi)..................................53 0x008 ? vertical delay regi ster, low (vdelay_lo).....................53 0x009 ? vertical active register, low (vactive_lo) ...................53 0x00a ? horizontal delay r egister, low (hdelay_lo) ...............54 0x00b ? horizontal active re gister, low (hactive_lo) .............54 0x00c ? control register i (cntrl1) ...............................................54 0x010 ? brightness control register (bright) ......................55 0x011 ? contrast control register (contrast) ...................55 0x012 ? sharpness control register i (sharpness)............55 0x013 ? chroma (u) gain register (sat_u)...................................55 0x014 ? chroma (v) gain register (sat_v) ...................................55 0x015 ? hue control register (hue).................................................55 0x016 ? reserved.................................................................................55 0x017 ? vertical peaking control i......................................................55 0x018 ? coring control register (coring).....................................56 0x019 ? reserved.................................................................................56 0x01a ? cc/eds status register (cc_status)..........................56 0x01b ? cc/eds data register (cc_data)..................................56 0x01c ? standard selection (sdt)....................................................57 0x01d ? standard recognition (sdtr) ............................................57 0x01e ? component video format (cvfmt) .................................57 0x01f ? control register ....................................................................58 0x020 ? clamping gain (clmpg) .....................................................59 0x021 ? individual agc gain (iagc) ................................................59 0x022 ? agc gain (agcgain).........................................................59 0x023 ? white peak threshold (peakwt)......................................59 0x024? clamp level (clmpl).............................................................59 0x025? sync amplitude (synct)......................................................59 0x026 ? sync miss count register (misscnt) ..............................59 0x027 ? clamp position register (pclamp)...................................59 0x028 ? vertical control register........................................................60 0x029 ? vertical control ii ....................................................................60 0x02a ? color killer level control ......................................................60 0x02b ? comb filter control ...............................................................60 0x02c ? luma delay and hsync control.......................................60 0x02d ? miscellaneous control register i (misc1) ........................61 0x02e ? miscellaneous control register ii (misc2)........................61 0x02f ? miscellaneous control iii (misc3).......................................61 0x030 ? macrovision detection...........................................................62 0x031 ? cstatus iii..........................................................................62 0x032 ? hfref ....................................................................................62 0x033 ? miscellaneous control register ...........................................62 0x034 ? nsen/ssen/psen/wkth ................................................62 0x035 ? clamp cntl2 ............................................................................63 0x038 ? analog cntl..............................................................................63 0x03a ? 0x03e reserved....................................................................63 0x03f ? dac current reference .......................................................63 3d comb control (0x060 to 0x06f) ...................................................64 0x060 ? mdth ......................................................................................64 0x062 ? 3d_mode..............................................................................64 0x065 ? str..........................................................................................64 0x067 ? nrlevel ...............................................................................64 0x068 ? nsmode................................................................................64 0x069 ? nslevel1 .............................................................................64
TW8811 ? tft flat panel controller preliminary techwell, inc. 3 rev c 02/07/2008 0x06a ? nslevel2............................................................................. 64 0x06b ? nshys ................................................................................... 65 0x0c0 to 0x0cf ? internal test .......................................................... 66 0x100 to 0x12f ? osd1 ...................................................................... 68 0x138 ? ccfl/led control i .............................................................. 73 0x139 ? ccfl/led sense threshold............................................... 73 0x13a ? ccfl/led control ii............................................................. 73 0x13b ? ccfl/led pwm .................................................................. 73 0x13c ? ccfl/led dim frequency................................................. 73 0x13d ? ccfl/led dim control ....................................................... 73 0x13e ? pwmtop............................................................................... 73 0x151 to 0x15f ? external osd & misc............................................ 74 host parallel interface / dma configuration registers .................... 76 0x1a0 ? mode setting register .......................................................... 76 0x1a1? total transfer count high byte register ............................ 76 0x1a2? total transfer count low byte register............................. 76 0x1a3 ? memory access address high byte register................... 76 0x1a4 ? memory access address medium byte register ............ 76 0x1a5? memory access address low byte register .................... 76 0x1a6? data access (r ead/write) register..................................... 77 0x1a7 ? command register............................................................... 77 0x1a8? status read register............................................................. 77 0x1b0 to 0x1bf ? status and interrupt registers ............................ 78 adc/llpll configuration registers ................................................. 82 0x1c0 ? llpll input control register .............................................. 82 0x1c1 ? llpll input detection register .......................................... 82 0x1c2 ? llpll control register........................................................ 83 0x1c3 ? llpll divider high register ............................................... 83 0x1c4 ? llpll divider low register................................................ 83 0x1c5 ? llpll clock phase register .............................................. 83 0x1c6 ? llpll loop control register.............................................. 83 0x1c7 ? llpll vco control register.............................................. 84 0x1c8 ? llpll vco control register.............................................. 84 0x1c9 ? llpll pre coast register................................................... 84 0x1ca ? llpll post coast register................................................. 84 0x1cb ? sog threshold register..................................................... 84 0x1cc ? scaler sync selection register .......................................... 84 0x1cd ? pll initialization register .................................................... 85 0x1ce ? rgb adc misc. register.................................................... 85 0x1cf ? rgb adc misc2. register.................................................. 85 0x1d0 ? clamp gain control register .............................................. 85 0x1d1 ? y channel gain adjust register ......................................... 86 0x1d2 ? c channel gain adjust register......................................... 86 0x1d3 ? v channel gain adjust register ......................................... 86 0x1d4 ? clamp mode control register............................................. 86 0x1d5 ? clamp start position register ............................................. 86 0x1d6 ? clamp stop position register ............................................. 86 0x1d7 ? clamp master location register ........................................ 86 0x1d8 ? adc test register ............................................................. 87 0x1d9 ? y clamp reference register .............................................. 87 0x1da ? c clamp reference register.............................................. 87 0x1dc ? hsync width register....................................................... 87 0x1dd ? r channel adc offset register ........................................ 87 0x1de ? g channel adc offset register ........................................ 87 0x1df ? b channel adc offset register ......................................... 87 0x1f0 to 0x1fe ? lcdc ? gamma .................................................. 88 flat panel display registers................................................................ 89 0x20e to 0x20f ? input type registers ........................................... 89 0x210 to 0x21f ? input and input related registers...................... 89 0x220 to 0x22f ? input format measurement registers ...............93 0x230 to 0x23f ? scaling/zoom control ...........................................95 0x240 to 0x26f ? image adjustment .................................................96 0x270 to 0x28f ? display control........................................100 0x2a0 to 0x2af ? memory control..................................................104 0x2ae to 0x2c9 ? pip control..........................................................105 0x2ca to 0x2ec ? mpip control registers....................................107 0x2ed ? dual-view control registers.............................................110 0x2f4 to 0x2f8 ? power management registers.........................111 timing controller configuration registers .......................................112 0x300 ? output mode control register ...........................................112 0x301 ? display control register......................................................112 0x302 ? display direction control register.....................................112 0x303 ? control signal polarity selection register ........................113 0x304 ? control signal generation method register ....................113 0x305 ? inversion signal oper ating period register .........................113 0x306 ? panel type select register .................................................114 0x30a ? special lcd module control register .............................114 0x30b ? revv(tcpolp) / revc(tcpoln) control registers114 0x30c ? vertical active start high register ....................................114 0x30d ? vertical active start low register.....................................114 0x30e ? vertical active end high register .....................................114 0x30f ? vertical active end low register ......................................114 column driver chip control si gnals relative registers................115 0x310 ? polarity control high register ............................................115 0x311 ? polarity control low register.............................................115 0x312 ? load/latch pulse start high register...............................115 0x313 ? load/latch pulse start low register................................115 0x314 ? load/latch pulse width high register.............................115 0x315 ? load/latch pulse width low register..............................115 0x31a ? column driver start pulse high register.........................115 0x31b ? column driver start pulse low register .........................115 0x31c ? column driver start pulse width high register .............115 0x31d ? column driver start pulse width low register..............115 row driver chip control signals relative registers .....................116 0x320 ? clock start pulse high register.........................................116 0x321 ? clock start pulse low register .........................................116 0x322 ? clock start pulse width high register .............................116 0x323 ? clock start pulse width low register ..............................116 0x324 ? row start pulse high register ..........................................116 0x325 ? row start pulse low register ...........................................116 0x326 ? row start pulse width high register ...............................116 0x327 ? row start pulse width low register................................116 0x32c ? row output enable high register ...................................116 0x32d ? row output enable low register ....................................116 0x32e ? row output enable width high register ........................116 0x32f ? row output enable width low register .........................117 0x334 ? register .................................................................................117 0x335 ?register ..................................................................................117 0x336 ?register ..................................................................................117 0x337 ?register ..................................................................................117 0x338 ?register ..................................................................................117 0x339 --register ..................................................................................117 0x3a0 to 0x3a0 -- pll control registers........................................117 copyright notice.......................................................................... 120 trademark acknowledgment .................................................... 120 disclaimer..................................................................................... 120 life support policy...................................................................... 120 revision history...................................................................................121
TW8811 ? tft flat panel controller preliminary techwell, inc. 4 rev c 02/07/2008 introduction applications - lcd tvs for home and mobile use - computer lcd panel monitors with television - portable dvd and dvrs players - progressive scan tv, dtv and hdtv monitors - portable media player features the TW8811 incorporates many of the features required to create multi-purpose in-car lc d display system in a single package. it integrates a high quality 3d comb ntsc/pal/secam video decoder, triple high speed rgb adcs, dual scalers for pip and multi-pip support, bit- mapped osd, tcon, triple dacs and images enhancement functions which include black and white stretch, favorite color enhancement and edge enhancement. to furt her facilitate the move to wide screen displays, it also supports panoramic scaling. on the input side, it supports a rich co mbination of cvbs, s-video, ypbpr, analog rgb as well as digital ypbpr/rgb inputs. on the output side, it supports both digital and analog panel type with its ttl and analog rgb output. TW8811 also has a pip (picture in picture) function that can display two sources display simultaneously on single display window. it also has built-in bit-mapped osd with acceleration as well as 16-bit external osd support. analog video decoder ntsc (m, 4.34) and pal (b, d, g, h, i, m, n, n combination), pal (60), secam with automatic format detection ? three 10-bit adcs and analog clamping circuit. ? fully programmable static gain or automatic gain control for the y or cvbs channel ? programmable white peak control for the y or cvbs channel ? software selectable analog inputs allows any of the following combinations: ? up to 4 composite video ? up to 2 s-video ? up to 1 ypbpr ? high quality motion adaptive 3d co mb filter for both ntsc and pal with concurrent 3d noise reduction ? pal delay line for color phase error correction ? image enhancement with 2d dynamic peaking and cti. ? digital sub-carrier pll for accurate color decoding ? digital horizontal pll an d advanced synchronization processing for vcr playback and weak signal performance. ? programmable hue, brightness, sa turation, contrast, sharpness. ? high quality horizontal and vert ical filtered down scaling with arbitrary scale down ratio ? detection of level of copy pr otection according to macrovision standard ? supports ypbpr input up to 1080i with sub-sampled resolution ? support automatic standard det ection for ypbpr input analog rgb inputs ? triple high speed 10-bit adcs with clamping and programmable gain amplifier. ? up to three independent rgb / ypbpr channels with corresponding sog ? built-in line locked pll with sync separator ? allows high resolution com ponents inputs like dtv 480p, 720p, 1080i 24bit digital rgb and 8/16/24-bit ycbcr inputs ? allows connection with alternative video and pc graphics inputs. ? support both 656 and 601 video formats ? allows connection to external hdmi receiver tft panel support ? supports panel with resolution up to wxga ? supports 3, 4, 6 or 8 bits per pixel up to 16.8 million colors with built-in dithering engine ? support single channel ttl panel ? support analog panel with analog rgb output from pc ntsc / pal / secam tuner techwell TW8811 audio a m p micro- controller
TW8811 ? tft flat panel controller preliminary techwell, inc. 5 rev c 02/07/2008 ? built-in programmable timing controller on screen display ? supports dual window bitmapped osd. ? built-in osd controller with bitblit engine ? supports variety functions incl uded like blinking, transparency and blending. ? supports external 16-bit osd with external alpha blending control. ? support osd compression image processing ? built-in 2d de-interlacing engine with proprietary low angle compensation circuit for smooth video rendering. ? built-in high quality scaler with nonlinear scaling support ? programmable hue, brightne ss, saturation, contrast ? sharpness control with vertical peaking up to +12db ? programmable color transi ent improvement control ? supports programmable cropping of input video and graphics. ? independent rgb gain and offset controls ? panorama / water-glass scaling ? dtv hue adjustment ? programmable 10-bit gamma correction for each color ? operated in frame sync mode only ? black/white stretch ? programmable favorite color enhancement pip function ? pip with variable sub window size ? pop ? multiple pip support ? built-in high quality down scaling engine for pip sdram ? support 16bits bus width sdram host interface ? supports 2-wire serial bus interface ? supports 8bits parallel host interface ? support dma transfer clock generation ? frequency synthesizer with sp read spectrum generate memory and display clocks ? spread spectrum profile based on triangular modulation with center spread ? modulation frequency and spr ead width can be selectable power management ? supports panel power sequencing. ? supports dpms for monitor power management. ? 1.8 / 3.3 v operation miscellaneous ? built-in single ccfl back light controller ? built-in single led back light controller ? power-down mode ? single 27mhz crystal ? 208-pin pqfp package
TW8811 ? tft flat panel controller preliminary techwell, inc. 6 rev c 02/07/2008 order information package description part # name descripti on pin count body size TW8811 qfp 208 quad flat package 208 28 x 28 mm^2
TW8811 ? tft flat panel controller preliminary techwell, inc. 7 rev c 02/07/2008 vin analog front end mux mux mux mux dtv i/f rgb adcs component processor sync processor 3d adaptive comb filter chroma demodulation yuv processing in mux color matrix line buffers scaler / deinterlacer image enhancement gamma / dither output formatter bitmapped osg panel timing generator registers parallel host bus input format measurement yin0 yin1 yin2 yin3 rin0 rin1 gin0 gin1 bin0 bin1 yout fpr[7:0] fpg[7:0] fpb[7:0] fpvs fphs fpde fpclk fppwc fpbias mc_ sda mc_sclk mc siad dtvclk dtvvs dtvhs dtvde dtvd[23:0] coast mem_data[15:0] mem_adr[11:0] memras,memcas memwen memba[1:0] memory controller down scale rgbmix / csc pip mux 2 wire serial bus had[7:0] hcs,hale hrdn,hwen pip write pip read up scale memdqm[1:0] output mux tcon color matrix cin1 mux down scale mpip write mpip read image control dac rout gout bout cin0 reft refb ccfl controller TW8811 flat panel tv/monitor controller functional block diagram
TW8811 ? tft flat panel controller preliminary techwell, inc. 8 rev c 02/07/2008 functional description overview techwell?s TW8811 flat panel tv/monitor controller is a highly integrated tft panel controller. it integrates a high quality ntsc/pal/se cam 3d video decoder, triple hi gh speed adc, dual scalers for pip support, timing controller, and flexible bit-mapp ed osd engine. this unique level of mixed signal integration turns a tft panel into a flexible display system. its built-in triple adcs and pll allow both ypbpr and rgb input support. separate flexible digital in puts interface also allow it to connect other front- end chips. it incorporates easy-to-operate and powerful features in a single package for multi-purpose pc display and lcd entertainment systems. the TW8811 contains all the logic required to convert standard tv, dtv, and pc monitor signals to the digital control and data signals required to drive va rious tft panel types. it supports ttl as well as analog tft panel resolutions up to wxga. the chip accepts cvbs (composite) analog input or s-video analog input or ypbp r component input or analog rgb input for use as a video monitor. up to 13 analog inputs can be connected simultaneously under external microprocessor control. the integrated analog front-end contains total six adcs with clamping circuits and automatic gain control (agc) circuit on certain channel to minimize external component count. it employs proprietary 3d comb filter y/c processing technologies to produce exceptionally high quality pictures. TW8811 flat panel tv or tv + pc monitor system a nalo g & di g ital from pc vga ou t ntsc / pal / secam tune r techwell TW8811 audio a m p micro- controlle r
TW8811 ? tft flat panel controller preliminary techwell, inc. 9 rev c 02/07/2008 TW8811 has three high speed adcs that can support various analog signal inputs up to wxga. the chip's internal logic synchronizes the panel frame rate to the incoming input frame rate. a high quality image-scaling engine is used to convert the lower resolu tion formats or high resolution dtv formats to the output panel resolution. an internal de-interlacing engine also allows interlaced video to be supported. on screen display is supported th rough either external osd chip or on-chip osd for maximum flexibility. a closed caption decoder is built in. the TW8811 also accepts a 24 bit digital rgb input from external hdmi tm receiver or adcs. in addition, it accepts 8/16/24 bits digital ycbcr input. for the variety for usage, TW8811 has a built-in tcon for direct connecting with low cost tcon-less panel. the TW8811 also supports tft panel power sequ encing, dpms (vesatm di splay power management signaling) signaling and power management. it also has built-in single channel ccfl or led back light controller to further simplify the system design. the control interface supports both a 2-wire serial bus interface and 8bit parallel interface. the TW8811 core operates at 1.8 v, the io at 3.3 v and packaged in a 208-pin lqfp package. analog front-end the analog front-end converts analog video signals to the required digital format. there are six analog front-end channels. three channels are dedicated to analog video support. every channel contains analog anti-aliasing filter, clamping circuit and 10-bit a dcs. it allows the support of cvbs, s-video and ypbpr component input signals for main or sub display. the other three channels are dedicated to ypbpr component video or rgb input support. every channel contains the analog clamping circuit, variable gain amplifier and adcs. it allows three separate inputs to be connected simultaneously. a built-in line locked pll is used to generate the sampling clock for various inputs. video source selection TW8811 has total 13 analog inputs for maximum flexibil ity. of the 13 inputs, 6 are used for 2 channels of ypbpr/rgb input with corresponding sog pin. the other 7 inputs are used by video decoder to allow up to 4 cvbs or 2 s-video or 1 component input. all inputs are software selectable. clamping and automatic gain control all six channels have built-in clamping circuit that rest ores the signal dc level. the y channel restores the back porch of the digitized video to a programmable level. the c, pb and pr channels restore the back porch of the digitized video to a level of 128. the r, g, and b channels restore the blank to a level of 16. this operation is automatic th rough internal feedback loop. in the case of rgb channel, two clamping modes are provided. when the input is ypbpr signal, the clamping to pre-determined dc level is done through internal feedback loop. when the input is pc rgb signal, the input is self clamped to the zero level. the automatic gain control (agc) of the y channel adjusts input gain so that the sync tip is at a desired level. the white peak protection logic is included to prevent saturation in the case of abnormal proportion between sync and white peak level. video decoder sync processor TW8811 has two sync processors, one for rgb channel and one for video channel. the sync processor of video input detects horizontal synchronization and vertical synchronization signals in the composite video or in the y signal of an s-video or component signal. the processor contains a digital phase-
TW8811 ? tft flat panel controller preliminary techwell, inc. 10 rev c 02/07/2008 locked-loop and decision logic to achieve reliable sync detection in stable signal as well as in unstable signals such as those from vc r fast forward or backward. horizontal sync processing the horizontal synchronization proc essing contains a sync separator, a phase-locked-loop (pll), and the related decision logic. the horizontal pll locks onto the extr acted horizontal sync in all conditions to provide jitter free image output. from there, the pll also provides orthogonal sampling raster for the down stream processor. it has wide lock-in range for tracking any non-standard video signal. vertical sync processing the vertical sync separator detects the vertical synchronization pattern in the input video signals. a detection window controls the determination of sync . this provides more reliable synchronization. it simulates the functionality of a pll without the comple xity of a pll. the field status is determined at vertical synchronization time based on the vertical and horizontal sync relationship. color decoding y/c separation the color-decoding block contains the luma / chroma separation for the composite video signal and multi- standard color demodulation. for ntsc and pal standard signals, the luma / chroma separation can be done either by comb filter or notch/band-pass filt er combination. for secam standard signals, only notch/band-pass filter is available. the default selection for ntsc/pal is comb filter. the characteristics of the band-pass filter can be found in the filter curve section. in the case of comb filter, the TW8811 separates luma (y) and chro ma (c) of a ntsc/pal composite video signal using a proprietary 3d/2d adaptive comb filter. this technique leads to good y/c separation with small cross luma and cross color at both horizontal and vertical edges. due to the line buffer used in the comb filter, there is always two lines processing delay in the output images no matter what standard or filter option is chosen. color demodulation the color demodulation for ntsc and pal standard is done by quadrature mixing the chroma signal to the base band and extracting the chroma components with low-pass filter. the low-pass filter characteristic can be selected for optimized transient color performance. for the pal system, the pal id or the burst phase switching is identified to aid the pal color demodulation. the secam color demodulation process consists of bell filtering, fm demodulator and de-emphasis filtering. the chroma carrier frequency is identified in the process and used to control the secam color demodulation. the sub-carrier signal for use in the color demodulator is generated by direct digital synthesis pll that locks onto the input sub-carrier reference (color burst). this arrangement allows any sub-standard of ntsc and pal to be demodulated easily. automatic chroma gain control the automatic chroma gain control (acc) compensates for reduced amplitudes caused by transmission loss in video signal. in the ntsc/pal standard, the color reference signal is the burst on the back porch. this color-burst amplitude is calculated and compared to standard amplitude. the chroma (cx) signals are then compensated in amplitude accordingly. the range of acc control is ?6db to +24db. low color detection and removal for low color amplit ude signals, black and white video, or very noisy signals, the colo r will be ?killed?. the color killer uses the burst amplitude measurement to switch-off the color when the measured burst amplitude falls below a programmed threshold. the threshold has programmed hysteresis to prevent
TW8811 ? tft flat panel controller preliminary techwell, inc. 11 rev c 02/07/2008 oscillation of the color killer operation. this func tion can be disabled by programming a low threshold value. automatic standard detection the TW8811 has build-in automatic standard discrimination circuitry. the circuit uses burst-phase, burst- frequency and frame rate to identi fy ntsc, pal or secam color sign als. the standards that can be identified are ntsc (m), ntsc (4.4 3), pal (b, d, g, h, i), pal (m), pal (n), pal (60) and secam (m). each standard can be included or excluded in the standard recognition process by software control. the identified standard is indicated by the standard se lection (sdt) register. automatic standard detection can be overridden by software controlled standard selection. video format support TW8811 supports all common video formats as shown in table 1. the video decoder needs to be programmed appropriately for each of the composite video input formats. table 1. video input formats supported by the TW8811 format lines fields fsc country ntsc-m 525 60 3.58 mhz u.s., many others ntsc-japan (1) 525 60 3.58 mhz japan pal-b, g, n 625 50 4.43 mhz many pal-d 625 50 4.43 mhz china pal-h 625 50 4.43 mhz belgium pal-i 625 50 4.43 mhz great britain, others pal-m 525 60 3.58 mhz brazil pal-cn 625 50 3.58 mhz argentina secam 625 50 4.406mhz 4.250mhz france, eastern europe, middle east, russia pal-60 525 60 4.43 mhz china ntsc (4.43) 525 60 4.43 mhz transcoding notes: (1). ntsc-japan has 0 ire setup. component processing luminance processing the TW8811 decoder adjusts bright ness by adding a programmable va lue (in register brightness) to the y signal. it adjusts the picture contrast by changing the gain (in register contrast) of the y signal. the TW8811 decoder also provides a sharpness contro l function through a control register. the center frequency of the peaking filter is selectable. a coring function is provided along with the sharpness control to reduce enhancement to the noise. the hue and saturation when decoding ntsc signals, TW8811 decoder can adjust the hue of the chroma signal. the hue is defined as a phase shift of the subcarrier with respect to the burst. this phase shift can be programmed through a control register. the color saturation can be adjusted by changing the gain of cb and cr signals for all ntsc, pal and secam formats. the cb and cr gain can be adjusted independently for flexibility.
TW8811 ? tft flat panel controller preliminary techwell, inc. 12 rev c 02/07/2008 analog rgb / ypbpr processor analog front-end this input path has three adcs to support analog rgb input or ypbpr input. the built-in clamping circuit works based on the mode selected. every channel includ es variable gain amplifier for gain adjustment. both gain and offset can be adjusted for flexibility. two software selectable inputs are available for each channel to allow two inputs to be connected simultaneously. both separated h/v sync and sync-on-green are supported. sync processor the sync processor for the rgb channel either takes the separated h/v sync input or separates the composite sync input from one of the sog inputs into h/v sync for driving the on-chip sampling pll. it contains necessary logics to detect and bypass irregular syncs. the on-chip pll has sub-phase control to enable accurate sampling timing. component processor there are built-in color space converter and tint control logic for the ypbpr input. during ypbpr component input operation, luminance contrast and brightness as well as pb / pr saturation can be controlled by registers. in the case of rgb mode, the gain and offset of rgb can also be digitally controlled. digital input support in addition to analog inputs, the TW8811 has a 24-bit digital input for ypbpr or rgb data. the input includes vsync, hsync, pixel clock and the optional data qualifier. for inte rlaced video, the timing relationship between vsync and hsync determine the field flag. the optional data qualifier is needed when input video data is not continuously valid within a line. for the ypbpr mode, TW8811 can support 8- bit 656 as well as 8/16-bit 601 modes. the 656 interface supports both interlaced and progressive standard. tft panel support the TW8811 supports varieties of active matrix tft panels including ttl, as well analog panel. it supports panel with resolu tion up wxga resolution. dithering if the color depth of the input data is larger than the lcd panel color depth, the TW8811 can be set to dither the image. up to four bits of apparent color depth can be added with the in ternal dithering ability of the TW8811. this allows lcd panels with 4, 6 or 8 bits per color per pixel to display up to 16.8 million colors and lcd panels with 3 bi ts per color per pixel to can display up to 2.1 million colors. the TW8811 has both spatial and frame modulation dithering. when dithering with the least significant 4- bits of input data the TW8811 uses spatial modulation with 4x4 blocks of pixels. when dithering with the least significant 1 to 3 bits of inpu t data, the TW8811 uses either spat ial modulation with 2x2 pixel blocks, or frame modulation.
TW8811 ? tft flat panel controller preliminary techwell, inc. 13 rev c 02/07/2008 image control input image control the input cropping control provides a way for progr amming the active display window region for the selected input video or graphic. in the normal operation, the first active line starts with the vsync signal. this and vertical active length register setting are used to determine the active vertical window. the active pixel starts hsync. this and the horizontal active width register are used to determine the active horizontal window. the vertical window is programmed in line increments. the horizontal window is programmed in one pixel increments for single pixel input mode or two pixels increments for double pixels input mode. if data qualifier is used, then only qualified pixels will be counted in the window size. image scaling the TW8811 internal image-scaling engine operates in several modes. the first is the bypass mode. no image scaling is done in this mode. the number of active output lines per frame and the number of active output pixels per line are identical to the input active lines and pixels, respectively. this mode is best used for displaying computer graphic at panel's native resolution. by default, the input active window is zoomed up to the full screen for display. this is used for non- interlaced data like pc graphics or progressive scan video. the vertical and horizontal magnification ratio can be adjusted independently. TW8811 has frame-sy nc mode which does not use frame buffer. in this mode, the zoom ratio and output clock rate should be coordinated appropriately to avoid internal buffer overrun. the TW8811 has a de-interlacing mode to process interlaced video inputs. in this mode, every input field is zoomed to the full output frame resolution. the de-interlaced fields can also be properly compensated to have fields aligned correctly to avoid any artifact s. the offset can be programmed to provide maximum flexibility. the horizontal scaler can be programmed to perform non-linear scaling : panorama scaling for displaying 4:3 input on a 16:9 display and water-glass scaling for displaying 16:9 input on a 4:3 display. image enhancement processing adaptive black/white stretch this feature is to expand dynamic range of the input image, which creates more vivid image impression. favorite color enhancement TW8811 provides three independent color enhancements. the center axis of each color can be adjusted over a 360 degrees range provided none of those two are overlapped. the range and the amount of enhancement can also be independently adjusted. picture-in-picture double window / picture-in-picture (pip) TW8811 can display two live pictures on a single display. in the case of what we called pip, small size of sub-window can be displayed over full size of main-window. the frame (outline of window) can be added with choice of color and width. example of double window modes main sub main sub main sub
TW8811 ? tft flat panel controller preliminary techwell, inc. 14 rev c 02/07/2008 multiple window in case of multiple window, multiple images come from one of the source can be displayed on a single display. only one of the window can be live (motion pict ure) and the others will be previously stored still image. user also can freeze live window by register set. user can overlay main-window over multiple-windows. example of multiple window modes pip alpha blending pip image can be used as an osd type ov erlay graphics. us er can specify specific color as a ?key color? which disabling overlaying and sh owing behind main image. wher e pip and main image are overlaid, user can define blending ratio (alpha1). and also can define blending ratio of main image with black color (alpha2) as a dimming function. [usage] - enable pip alpha blending (0x2ef[7] = 1). enable 565 mode (0x2ef[6] = 1) as well, if it is preferred. - set ?key color? center level by us ing rkey (0x2f0), gkey (0x2f1) and bkey (0x2f2). also set ?key range? (0x2f3) for the ?key color? devi ation from its center setting. - turn on ?key position display? mode if you want to make sure the area detected as ?keyed?. - adjust alpha1 (0x2ef[4:0]) and alpha2 (0x2e6[4:0]). live still still still still still still still still still still still live
TW8811 ? tft flat panel controller preliminary techwell, inc. 15 rev c 02/07/2008 [limitations] - when 565 mode, color depth is limited and may show steps on original gradation. - when 565 mode, try to c hoose color of input image which truncate d portion (lsb 2 bit will be truncated in y, lsb 3 bit in cb and cr) has about middle value (if 3 bit is truncated, these portion better have value of around 3 or 4) to avoid input level translated into 2 diffe rent output level due to noise. (if input is digital signal, this situation may be avoidable.) key color gui menu main image gui menu pip image blending pip and main dimming is available as an option
TW8811 ? tft flat panel controller preliminary techwell, inc. 16 rev c 02/07/2008 display timing the TW8811 is operated in frame sync mode only with no external memory required. in this mode, the output frame rate is synchronized with the input frame rate. since there is no frame buffer, the display clock frequency and zoom ratio have to be properly selected to match the panel resolution. the internal scaling engine absorbs the difference between the input line rate and output line rate as well as the difference between the input pixel rate and output pixel rate. the frequency of the flat panel clock output pin can be controlled by an internal frequency synthesizer. it also has spread spectrum function to reduce emi. the frequency equation of the flat panel clock output signal is described in the register section. on screen display TW8811 osd controller supports bitmap with 4/8 bit- per-pixel mode. the powerful bit-blit engine makes your system more fancy. any pixel can be assigned any one of 16 user-defined true colors. using 24 bits x 16 look-up-table, user can achieve 16 true color from 24 bits true color. the TW8811 osd architecture doesn't use any internal memory. bitmapped mode the bitmap is loaded into external sdram with same way as character-mapped mode. user can define the displayed pixel colors on a pixel by pixel basis. the pixels can be represented using either 4 bits per pixel(16 simultaneous colors). the maximum bitmapped image size depends on panel resolution and sdram size. our recommendation is 512(h) x 512(v). external osd port a dedicated port is provided for an external os d controller. the TW8811 pr ovides the hactive, vsync and dot clock signals, and external osd controller provides a 18 bits color data values together with valid data indicator (6 bits for each r, g and b color). it's compatible with popu lar osd controllers from renesas (mitsubishi) and other companies. in case of 18 bit osd data reception, color palette is not used and 18 bit data represents 262144 color space directly. fphs fpde fpr/g/b0 fpr/g/b1 fpclk fphs fpde fpvs flat panel output signals
TW8811 ? tft flat panel controller preliminary techwell, inc. 17 rev c 02/07/2008 microcontroller interface the TW8811 registers are accessed via 2-wire serial bu s interface as well as parallel host interface. it operates as a slave device. two wire serial bus interface figure 1. definition of the serial bus interface bus start and stop figure 2. one complete register write sequence via the serial bus interface mc sd a start condition stop condition mc_sclk mc_sclk device id (1-7) r/w index (1-8) data (1-8) mc_sda start condition stop condition ack ack ack
TW8811 ? tft flat panel controller preliminary techwell, inc. 18 rev c 02/07/2008 figure 3. one complete register read sequence via the serial bus interface the two wire serial bus interface is used to allow an external micro-controller to write control data to, and read control or other information from the TW8811 registers. mc_sclk is the serial clock and mc_sda is the data line. both lines are pulled high by resistors connected to vdd. ics communicate on the bus by pulling mc_sclk and mc_sda low through open drain outputs. in normal operation the master generates all clock pulses, but contro l of the mc_sda line alternates back and forth between the master and the slave. for both read and write, each byte is tran sferred msb first, and the data bit is valid whenever mc_sclk is high. the TW8811 is operated as a bus slave device. it can be programmed to respond to one of two 7-bit slave device addresses by tying the addrsel (seria l interface address) pin ether to vdd or gnd (see table 2.). if the addrsel pin is tied to vdd, then the least significant bit of the 7-bit address is a ?1?. if the addrsel pin is tied to gnd then the least significant bit of the 7-bit address is a ?0?. the most significant 6-bits are fixed. the 7-bit address field is concatenated with the read/write control bit to form the first byte transferred during a new transfer. if the read/write control bit is high the next byte will be read from the slave device. if it is low th e next byte will be a write to the slave. when a bus master (the host microprocessor) drives mc_sda from high to low, while mc_sclk is high, this is defined to be a start condition (see figure 1.). all slaves on the bus listen to determine when a start condition has been asserted. after a start condition, all slave devices listen fo r the their device addresses. the host then sends a byte consisting of the 7-bit slave device id and the r/w bit. this is shown in figure 2. (for the TW8811, the next byte is normally the index to t he TW8811 registers and is a write to the TW8811 therefore the first r/w bit is normally low.) after transmitting the device addre ss and the r/w bit, the master must release the mc_sda line while holding mc_sclk low, and wait for an acknowledgement from the slave. if the address matches the device address of a slave, the slave will respond by driving the mc_sda line low to acknowledge the condition. the master will then continue with the next 8-bit transfer. if no device on the bus responds, the master transmits a stop cond ition and ends the cycle. notice that a successful transfer always includes nine clock pulses. re-start condition mc_sclk device id (1-7) r/w index (1-8) mc_sda ack ack data (1-8) stop condition nack start condition device id (1-7) r/w ack
TW8811 ? tft flat panel controller preliminary techwell, inc. 19 rev c 02/07/2008 to write to the internal register of the TW8811, the master sends another 8-bits of data, the TW8811 loads this to the register pointed by the internal index register. the TW8811 will acknowledge the 8-bit data transfer and automatically in crement the index in preparation for the next data. the master can do multiple writes to the TW8811 if they are in as cending sequential order. after each 8-bit transfer the TW8811 will acknowledge the rece ipt of the 8-bits with an acknowle dge pulse. to end all transfers to the TW8811 the host w ill issue a stop condition. serial bus interface 7-bit slave address read/write bit 1 0 0 0 1 0 addrsel 1=read 0=write table 2. TW8811 serial bus interface 7-bit slave address and read write bit a TW8811 read cycle has two phases. the first phase is a write to the internal index register. the second phase is the read from the data register. (see figure 3). the host initiates the first phase by sending the start condition. it then sends the slave dev ice id together with a 0 in the r/w bit position. the index is then sent followed by either a stop condition or a second start condition. the second phase starts with the second start condition. the master then resends the same slave device id with a 1 in the r/w bit position to indicate a read. the slave will transfer the contents of the desired register. the master remains in control of the clo ck. after transferring eight bits, the slave releases and the master takes control of the mc_sda line and acknowledges the receipt of data to the slave. to terminate the last transfer t he master will issue a negative a cknowledge (mc_sda is left high during a clock pulse) and issue a stop condition.
TW8811 ? tft flat panel controller preliminary techwell, inc. 20 rev c 02/07/2008 parallel host interface for 8bit micro processor figure 4. parallel interface mode1 timing diagram. (host = 0) figure 5. parallel interface mode2 timing diagram. (host =1) hale hcs hwrn hrdn a ddress write dat a a ddress read dat a had_osd[7:0] write read se q uenc y write read hale hwrn hrdn a ddress read data had_osd[7:0] addres data hcs hwrn hrdn a ddress write data had_osd[7:0]
TW8811 ? tft flat panel controller preliminary techwell, inc. 21 rev c 02/07/2008 power management the TW8811 supports panel power sequencing. typical tft panels require different parts of the panel power to be applied in the right sequence to avoid pr emature damage to the panel. pins are provided to control the panel backlight generator, digital circuitry and panel driver, separately. the TW8811 controls the power up and power down sequence for the lcd panels. the time lapses between different stages of the sequence are independently programmable to meet various power sequencing requirements. the TW8811 also supports vesa tm dpms for monitor power management. it can detect the dpms status from input sync signals and automatically change into on/off mode. to support the power management, the TW8811 has three operating modes: power on mode, power off mode, and panel off mode. all the dpms power saving mode will be covered by the power off mode. gamma correction TW8811 has built-in independent rgb 10-bit gamma ram for the purpose of table lookup gamma correction. memory interface TW8811 supports external sdram for various functions including bit-mapped osd, 3d comb, 3d noise reduction and pip that require memory buffer. the memory controller of the TW8811 supports 16bit data width up to 133 mhz clock rate. when power is up, it is reset by the internal reset si gnal and wait for the initia l memory- timing period. to configuration of the sdram internal register memory controller performs in itial cycle. after all initial cycles performed, memory controller does the normal operat ion. the memory controller performs arbitration, access timing generation and refresh and configuration. test modes the test1 input pin provides test mode selection. if th is pin is low at the rising edge of the reset# pin and remains low, the TW8811 is in its normal operating mode. table 3 shows the other test modes made available with this pin. table 3 test modes test mode test1 before reset# rising edge test1 after reset# rising edge description normal 0 0 normal operation output tri-state 0 1 in this mode, all pin out put drivers are tri-stat ed. pin leakage current parameters can be measured. outputs high 1 0 in this mode, all pin output drivers are forced to the high output state. v oh and i oh can be measured. outputs low 1 1 in this mode, all pin output drivers are forced to the low output state. v ol and i ol can be measured.
TW8811 ? tft flat panel controller preliminary techwell, inc. 22 rev c 02/07/2008 pin diagram hcs / eoclk eodap hwaitl / eohs dmaack / eovs dmareq / eoden eodib5 hale / eodib4 hwrl / eodib3 hrdl / eodib2 had7 / eodib1 had6 / eodib0 had5 / eodig5 vddo vdd vss had4 / eodig4 had3 / eodig3 had2 / eodig2 had1 / eodig1 had0 / eodig0 vsso mdata15 mdata14 mdata13 mdata12 vddo mdata11 mdata10 mdata9 mdata8 mdata0 mdata1 mdata2 mdata3 vsso vdd vss mdata4 mdata5 mdata6 mdata7 mdqm0 mwen mcasn mrasn vddo mcsn mba0 mba1 madr10 madr0 madr1 vdda rin1 vssa r rin0 reft refb gin1 vssa g gin0 bin1 vssab bin0 vssa vdda vin yout yin3 yin2 yin1 yin0 v ssa y cin0 cin1 vssa davdd davdd rout gout bout sen 0 sen1 davs s davss xtal27i xtal27o vsync gpio[0] gpio[1] vddo fpbias/ccflp fppwc fppwm/ccfln pwm2 vss vdd vsso tclrl trclk trudl tcinv/tcrev tcpolp tcpoln filt sogin0 sogin1 pvdda pvssa dvd d dvs s ssvd d ssvs s hsync pclk dtvde dtvvs dtvhs dtvclk vss o dtvd[23] dtvd[22] dtvd[21] dtvd[20] dtvd[19] dtvd[18] dtvd[17] dtvd[16] vd d vs s dtvd[15] dtvd[14] dtvd[13] dtvd[12] vdd o dtvd[11] dtvd[10] dtvd[9] dtvd[8] dtvd[7] dtvd[6] dtvd[5] / eodir5 dtvd[4] / eodir4 dtvd[3] / eodir3 dtvd[2] / eodir2 dtvd[1] / eodir1 dtvd[0] / eodir0 vss o vd d vs s resetn mc_sclk mc_sda mc_siad test host tclp fpclk/tccl k vdd o fpvs / trspt fphs / tcspl fpde / troe tcspr trspb vs s vd d vss o fpr[0] fpr[1] fpr[2] fpr[3] fpr[4] fpr[5] fpr[6] fpr[7] vdd o fpg[0] fpg[1] fpg[2] fpg[3] fpg[4] fpg[5] fpg[6] fpg[7] vss o fpb[0] fpb[1] fpb[2] fpb[3] fpb[4] fpb[5] fpb[6] fpb[7] vs s vd d vdd o madr4 madr5 madr6 madr7 madr8 madr9 madr11 mclk0 mdqm1 vsso madr3 madr2 TW8811 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
TW8811 ? tft flat panel controller preliminary techwell, inc. 23 rev c 02/07/2008 pin description this section provides a detailed description of each pin for the TW8811. the pins are arranged in functional groups according to their associated interface. the active state of the signal is determi ned by the trailing symbol at the end of the signal na me. a "#" symbol indicates that the signal is active or asserted at a low voltage level. when "#" is not present after the signal name, the signal is active at the high voltage level. the pin description also includes the buffer direction and type used for that pin. pin# i/o pin name description 1 p vdda a/d power +1.8v 2 i rin1 analog red input 1 3 p vssar analog ground for r-channel 4 i rin0 analog red input 0 5 i reft rgb a/d voltage reference top 6 i refb rgb a/d voltage reference bottom 7 i gin1 analog green input 1 8 p vssag analog ground for g-channel 9 i gin0 analog green input 0 10 i bin1 analog blue input 1 11 p vssab analog ground for b-channel 12 i bin0 analog blue input 0 13 p vssa analog ground 14 p vdda analog power +1.8v 15 i vin analog component v input 16 o yout y output (y out or y+c out) 17 i yin3 analog composite or luma input 3 18 i yin2 analog composite or luma input 2 19 i yin1 analog composite or luma input 1 20 i yin0 analog composite or luma input 0 21 p vssay video a/d ground 22 i cin0 analog component c input 0 23 i cin1 analog component c input 1 24 p vssa analog ground 25 p davdd dac analog power +3.3v 26 p davdd dac analog power +3.3v 27 o rout dac analog red data output 28 o gout dac analog green data output 29 o bout dac analog blue data output 30 i sen0 analog sensing 0 input / ccfl or led current sensing 31 i sen1 analog sensing 1 input / ccfl or led voltage sensing 32 p davss dac analog ground
TW8811 ? tft flat panel controller preliminary techwell, inc. 24 rev c 02/07/2008 pin# i/o pin name description 33 p davss dac analog ground 34 i xtal27i crystal terminal (if crystal is used) 35 o xtal27o crystal terminal (if crystal is used) or oscillator input 36 i vsync vertical sync input 37 i/o gpio[0] general purpose input/output or irq output 38 i/o gpio[1] general purpose input/output 39 p vddo digital i/o power +3.3v 40 o fpbias / ccflp power on/off control for panel backli ght bias / ccfl driver polarity (positive) 41 o fppwc power on/off control for flat panel display 42 o fppwm / ccfln pwm control for panel backli ght / ccfl driver polarity (negative) 43 o pwm2 pwm control2 44 p vss digital core ground 45 p vdd digital core power +1.8v 46 i vsso digital i/o ground 47 o tclrl left right selection (left : high, right : low) 48 o trclk tcon - row driver shift clock 49 o trudl tcon - up down selection (up : high, down : low) 50 o tcinv / tcrev tcon - column driver inversion / column driver reverse 51 o tcpolp tcon - column driver polarity (positive) - sharp : revc 52 o tcpoln tcon - column driver polarity (negative) ** only use some companies sharp : revv tmd : tcpoln 53 o tclp tcon - column driver load pulse 54 o fpclk / tcclk tcon - flat panel clock output / column driver clock 55 p vddo digital i/o power +3.3v 56 o fpvs / trspt flat panel vsync / tcon - row driver starting pulse (top start) 57 o fphs / tcspl flat panel hsync / tcon - column driver start pulse (left to right scan) 58 o fpde / troe flat panel data enable / tcon - row driver output enable 59 o tcspr tcon - column driver start pulse (right to left scan) 60 o trspb tcon - row driver starting pulse (bottom start) 61 p vss digital core ground 62 p vdd digital core power +1.8v 63 p vsso digital i/o ground 64 o fpr[0] red flat panel output bits 65 o fpr[1] red flat panel output bits 66 o fpr[2] red flat panel output bits 67 o fpr[3] red flat panel output bits 68 o fpr[4] red flat panel output bits 69 o fpr[5] red flat panel output bits 70 o fpr[6] red flat panel output bits 71 o fpr[7] red flat panel output bits 72 p vddo digital i/o power +3.3v
TW8811 ? tft flat panel controller preliminary techwell, inc. 25 rev c 02/07/2008 pin# i/o pin name description 73 o fpg[0] green flat panel outputs bit 74 o fpg[1] green flat panel outputs bit 75 o fpg[2] green flat panel outputs bit 76 o fpg[3] green flat panel outputs bit 77 o fpg[4] green flat panel outputs bit 78 o fpg[5] green flat panel outputs bit 79 o fpg[6] green flat panel outputs bit 80 o fpg[7] green flat panel outputs bit 81 p vsso digital i/o ground 82 o fpb[0] blue flat panel outputs bit 83 o fpb[1] blue flat panel outputs bit 84 o fpb[2] blue flat panel outputs bit 85 o fpb[3] blue flat panel outputs bit 86 o fpb[4] blue flat panel outputs bit 87 o fpb[5] blue flat panel outputs bit 88 o fpb[6] blue flat panel outputs bit 89 o fpb[7] blue flat panel outputs bit 90 p vss digital core ground 91 p vdd digital core power +1.8v 92 p vddo digital i/o power +3.3v 93 o madr4 sdram interface memory address bit 94 o madr5 sdram interface memory address bit 95 o madr6 sdram interface memory address bit 96 o madr7 sdram interface memory address bit 97 o madr8 sdram interface memory address bit 98 o madr9 sdram interface memory address bit 99 o madr11 sdram interface memory address bit 100 o mclk0 clock output for external sdram. 101 o mdqm1 sdram interface memory data mask 102 p vsso digital i/o ground 103 o madr3 sdram interface memory address bit 104 o madr2 sdram interface memory address bit 105 o madr1 sdram interface memory address bit 106 o madr0 sdram interface memory address bit 107 o madr10 sdram interface memory address bit 108 o mba1 sdram interface memory bank address 109 o mba0 sdram interface memory bank address 110 o mcsn sdram interface memory chip select, low active 111 p vddo digital i/o power +3.3v 112 o mrasn sdram interface memory row address strobe, low active 113 o mcasn sdram interface memory column address strobe, low active 114 o mwen sdram interface memory write enable 115 o mdqm0 sdram interface memory data mask
TW8811 ? tft flat panel controller preliminary techwell, inc. 26 rev c 02/07/2008 pin# i/o pin name description 116 i/o mdata7 sdram interface memory data bit 117 i/o mdata6 sdram interface memory data bit 118 i/o mdata5 sdram interface memory data bit 119 i/o mdata4 sdram interface memory data bit 120 p vss digital core ground 121 p vdd digital core power +1.8v 122 p vsso digital i/o ground 123 i/o mdata3 sdram interface memory data bit 124 i/o mdata2 sdram interface memory data bit 125 i/o mdata1 sdram interface memory data bit 126 i/o mdata0 sdram interface memory data bit 127 i/o mdata8 sdram interface memory data bit 128 i/o mdata9 sdram interface memory data bit 129 i/o mdata10 sdram interface memory data bit 130 i/o mdata11 sdram interface memory data bit 131 p vddo digital i/o power +3.3v 132 i/o mdata12 sdram interface memory data bit 133 i/o mdata13 sdram interface memory data bit 134 i/o mdata14 sdram interface memory data bit 135 i/o mdata15 sdram interface memory data bit 136 p vsso digital i/o ground 137 i had0 / eodig0 host interface address data / external osd g data input 138 i had1 / eodig1 host interface address data / external osd g data input 139 i had2 / eodig2 host interface address data / external osd g data input 140 i had3 / eodig3 host interface address data / external osd g data input 141 i had4 / eodig4 host interface address data / external osd g data input 142 p vss digital core ground 143 p vdd digital core power +1.8v 144 p vddo digital i/o power +3.3v 145 i had5 / eodig5 host interface address data / external osd g data input 146 i had6 / eodib0 host interface address data / external osd b data input 147 i had7/ eodib1 host interface address data / external osd b data input 148 i hrdl / eodib2 host interface read indicate signal / external osd b data input 149 i hwrl / eodib3 host interface write indi cate signal / external osd b data input 150 i hale / eodib4 host interface address latch enable signal / external osd b data input 151 i eodib5 external osd b data input 152 i dmareq / eoden dma request signal / external osd data enable 153 o dmaack / eovs dma acknowledge signal / ex ternal osd vertical sync signal 154 o hwaitl / eohs host interface wait signa l / external osd horizontal sync signal 155 i eodap external osd alpha blending control signal 156 o hcs / eoclk host interface chip select signal / external osd clock 157 i host host interface mode selection
TW8811 ? tft flat panel controller preliminary techwell, inc. 27 rev c 02/07/2008 pin# i/o pin name description 158 i test chip test mode selection 159 i mc_siad 2-wire microprocessor interface address pin 160 i/o mc_sda 2-wire microprocessor interface data pin 161 i mc_sclk 2-wire microprocessor interface clock pin 162 i resetn reset pin 163 p vss digital core ground 164 p vdd digital core power +1.8v 165 p vsso digital i/o ground 166 i dtvd[0] / eodir0 digital input, cr/ b external osd r data input 167 i dtvd[1] / eodir1 digital input, cr/ b. external osd r data input 168 i dtvd[2] / eodir2 digital input, cr/ b external osd r data input 169 i dtvd[3] / eodir3 digital input, cr/ b external osd r data input 170 i dtvd[4] / eodir4 digital input, cr/ b external osd r data input 171 i dtvd[5] / eodir5 digital input, cr/ b external osd r data input 172 i dtvd[6] digital input, cr/ b 173 i dtvd[7] digital input, cr/ b 174 i dtvd[8] digital input, cb/ g 175 i dtvd[9] digital input, cb/ g 176 i dtvd[10] digital input, cb/ g 177 i dtvd[11] digital input, cb/ g 178 p vddo digital i/o power +3.3v 179 i dtvd[12] digital input, cb/ g 180 i dtvd[13] digital input, cb/ g 181 i dtvd[14] digital input, cb/ g 182 i dtvd[15] digital input, cb/ g 183 p vss digital core ground 184 p vdd digital core power +1.8v 185 i dtvd[16] digital input, y/ r 186 i dtvd[17] digital input, y/ r 187 i dtvd[18] digital input, y/ r 188 i dtvd[19] digital input, y/ r 189 i dtvd[20] digital input, y/ r 190 i dtvd[21] digital input, y/ r 191 i dtvd[22] digital input, y/ r 192 i dtvd[23] digital input, y/ r 193 p vsso digital i/o ground 194 i dtvclk clock input for dtv interface 195 i dtvhs horizontal sync for dtv interface
TW8811 ? tft flat panel controller preliminary techwell, inc. 28 rev c 02/07/2008 pin# i/o pin name description 196 i dtvvs vertical sync for dtv interface 197 o dtvde data valid for dtv interface or raw hsync for dtv interface (set by register 0xf6 bit #1) 198 i/o pclk input : external clock for panel clock pll test (test mode only) output : panel clock pll output 199 i hsync digital hsync input 200 p ssvss ss-pll analog ground 201 p ssvdd ss-pll analog power +1.8v 202 p dvss analog ground for low voltage analog power (dvdd) 203 p dvdd low voltage analog power +1.8v 204 p pvssa pll(internal analog) ground 205 p pvdda pll (internal analog) power +1.8v 206 i sogin1 sync on green input 1 207 i sogin0 sync on green input 0 208 i filt filter input
TW8811 ? tft flat panel controller preliminary techwell, inc. 29 rev c 02/07/2008 parametric information ac/dc electrical parameters table 4. absolute maximum ratings parameter symbol min typ max units davdd (measured to davss) 3.3v v ddaem - - 3.6 v vdda (measured to vssa) 1.8v v ddam - - 1.92 v vdd (measured to vss) v ddm - - 1.98 v vddo (measured to vsso) v ddem - - 3.6 v voltage on any digital signal pin (see the note below) - vsso ? 0.5 - v ddem + 0.5 v analog input voltage (supplied by 1.8v) - vssa ? 0.5 - 1.92 v analog input voltage (supplied by 3.3v) - davss - 0.5 3.6 v storage temperature t s ?65 - +150 c junction temperature t j - - +125 c vapor phase soldering(15 seconds) t vsol - - +220 c note: stresses above those listed may cause permanent damage to the devic e. this is a stress rating only, and functional operation at these or any other conditions above those listed in the operational section of this specification is not imp lied. exposure to absolute maxim um rating conditions for extended periods may affect device reliability. this device employs high-impedance cmos devic es on all signal pins. it must be handled as an esd-sensitive device. voltage on a ny signal pin that exceeds the ranges list in table 4 can induce destructive latch-up. table 5. characteristics parameter symbol min typ max units supply power supply ? io v dde 3.15 3.3 3.6 v power supply ? digital v dd 1.62 1.8 1.98 v power supply ? analog 3.3v v ddae 3.15 3.3 3.6 v power supply ? analog v dda 1.62 1.8 1.92 v ambient operati ng temperature t a -40 +85 c - tbd - ma analog supply current (cvbs only) (s-video) iaa - tbd - ma digital i/o supply current idde - tbd - ma digital core supply current idd - tbd - ma digital inputs input high voltage (ttl) v ih 2.0 - - v input low voltage (ttl) v il - - 0.8 v input high voltage (xti) v ih 2.0 - v dde + 0.5 v input low voltage (xti) v il - - 0.8 v input high current (v in =v dd ) i ih - - 10 a input low current (v in =vss) i il - - ?10 a input capacitance (f=1 mhz, v in =2.4 v) c in - 5 - pf
TW8811 ? tft flat panel controller preliminary techwell, inc. 30 rev c 02/07/2008 parameter symbol min typ max units digital outputs output high voltage (i oh = ?4ma) v oh 2.4 - v dde v output low voltage (i ol = 4ma) v ol - 0.2 0.4 v 3-state current i oz - - 10 a output capacitance c o - 5 - pf analog input analog pin input voltage vi - 1 - vpp yin0, yin1 , yin2 and yin3 input range (ac coupling required) 0.5 1.0 2.0 vpp cin0, cin1 amplitude range (ac coupling required) 0.5 1.0 2.0 vpp vin amplitude range (ac coupling required) 0.5 1.0 2.0 vpp sen0, sen1 dc input range 0.65 1.65 2.65 v analog pin input capacitance c a - 7 - pf adcs adc resolution adcr - 9 - bits adc integral non-linearity ainl - 1 - lsb adc differential non-linearity adnl - 1 - lsb adc clock rate f adc - 27 60 mhz video bandwidth (-3db) bw - 10 - mhz horizontal pll line frequency (50hz) f ln - 15.625 - khz line frequency (60hz) f ln - 15.734 - khz static deviation ? f h - - 6.2 % subcarrier pll subcarrier frequency (ntsc-m) f sc - 3579545 - hz subcarrier frequency (pal-bdghi) f sc - 4433619 - hz subcarrier frequency (pal-m) f sc - 3575612 - hz subcarrier frequency (pal-n) f sc - 3582056 - hz lock in range ? f h 450 - - hz crystal spec nominal frequency (fundamental) - 27 - mhz deviation - - 50 ppm load capacitance cl - 20 - pf series resistor rs - 80 - ohm
TW8811 ? tft flat panel controller preliminary techwell, inc. 31 rev c 02/07/2008 filter curves anti-alias filter decimation filter 0 2 4 6 8 10 12 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) magnitude response (db) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10 7 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) gai n (db)
TW8811 ? tft flat panel controller preliminary techwell, inc. 32 rev c 02/07/2008 chroma band pass filter curves luma notch filter curve for ntsc and pal 0 1 2 3 4 5 6 7 8 9 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) magnitude response (db) pal/seam ntsc 0 1 2 3 4 5 6 7 8 x 10 6 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 frequency (hertz) gain (db) ntsc pal
TW8811 ? tft flat panel controller preliminary techwell, inc. 33 rev c 02/07/2008 chrominance low-pass filter curve low med high 0 1 2 3 4 5 6 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) gain (db) cbw = 0 cbw = 3 cbw = 1 cbw = 2
TW8811 ? tft flat panel controller preliminary techwell, inc. 34 rev c 02/07/2008 mechanical data 208 qfp
TW8811 ? tft flat panel controller preliminary techwell, inc. 35 rev c 02/07/2008 notes: 1. dimensions d1 and e1 do not include mold protrusion. 2. dimension b does not include dambar protrusion. allo wable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and a adjacent lead is 0.07mm. the top package body size may be smaller than the bottom package body size. millimeter inch symbol min nom max min nom max a --- --- 4.10 --- --- 0.161 a1 0.25 --- --- 0.010 --- --- a2 3.15 3.32 3.60 0.124 0.131 0.142 d 30.60 bsc. 1.205 bsc. d1 28.00 bsc. 1.102 bsc. e 30.60 bsc. 1.205 bsc. e1 28.00 bsc. 1.102 bsc. r2 0.08 --- 0.25 0.003 --- 0.010 r1 0.08 --- --- 0.003 --- --- 0 3.5 7 0 3.5 7 1 0 --- --- 0 --- --- 2 8 ref 8 ref 3 8 ref 8 ref c 0.09 0.15 0.20 0.004 0.006 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.30 ref 0.051 ref s 0.20 --- --- 0.008 --- --- b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 bsc. 0.020 bsc. d2 25.50 1.004 e2 25.50 1.004 tolerances of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc --- 0.08 --- --- 0.003 --- ddd --- 0.08 --- --- 0.003 --- control dimensions are in millmeters.
TW8811 ? tft flat panel controller preliminary techwell, inc. 36 rev c 02/07/2008 TW8811 register summary the registers are organized in functional groups in this regist er summary. a register containing different functional bits may appear more than once in different functional groups. if a particular bit of a register is not related to that functional group, it is printed in smaller font than those related. for example, bit 7 of index 006 is classified as ?general? and is printed in normal size; the other bits in this register are printed in smaller size for their functionality is not classified a s ?general?. general (common for any page) index (hex) 7 6 5 4 3 2 1 0 reset value 0x0ff 0x1ff 0x2ff 0x3ff * * * * * * page[1:0] 00h total pages : 4 ( 0 to 3 ) page # register group #0 decoder / 3d com / nr control / hi speed adc / internal test #1 osd / vbi interrupt / font osd / host if / dma / gamma #2 input ctrl / input measure / scaling / image / display / power mgm / memory ctrl / pip / mpip #3 tcon / others
TW8811 ? tft flat panel controller preliminary techwell, inc. 37 rev c 02/07/2008 === page 0 : decoder/3d com/hadc === decoder index (hex) 7 6 5 4 3 2 1 0 reset value 000 id rev 28h 001 vdloss hlock slock field vlock * mono det50 - 002 ysel2 fc27 ifsel ysel csel * 40h 003 * 20h 004 * ckhy * 00h 005 * afh 006 sreset * fbp agc_en clkpdn y_pdn c_pdn v_pdn 00h 007 vdelay_hi vactive_hi hdelay_hi hactive_hi 02h 008 vdelay_lo 12h 009 vactive_lo f0h 00a hdelay_lo 0ch 00b hactive_lo d0h 00c pbw dem palsw set7 comb hcomp ycomb pdly cch 00d * * * * 15h 00e * * * - 00f * - 010 brightness 00h 011 contrast 60h 012 scurve vsf cti sharpness 51h 013 sat_u 80h 014 sat_v 80h 015 hue 00h 016 - - - 017 shcor * vshp 80h 018 ctcor ccor vcor cif 44h 019 * - 01a * eds_en cc_en parity ff_ovf ff_emp cc_eds lo_hi 01b cc_data 01c dtstus stdnow atreg standard 07h 01d start pal60 palcn palm ntsc4 secam palb ntsc 7fh 01e * cvstd cvfmt 08h 01f test 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 38 rev c 02/07/2008 decoder index (hex) 7 6 5 4 3 2 1 0 reset value 020 clpend clpst 50h 021 nmgain wpgain agcgain 42h 022 agcgain f0h 023 peakwt d8h 024 clmpld clmpl bch 025 synctd synct b8h 026 misscnt hswin 44h 027 pclamp 2ah 028 vlcki vlcko vmode detv afld vint 00h 029 bsht vsht 00h 02a ckillmax ckillmin 78h 02b htl vtl 44h 02c cklm ydly hflt 30h 02d hplc evcnt palc sdet tbc_en bypass syout hadv 14h 02e hpm acct spm cbvv a5h 02f nkill pkill skill cbal fcs lcs ccs bst e0h 030 sid_fail pid_fail fsc_fail slock_f ail csbad mvcsn cstripe ctype - 031 vcr wkair wkair1 vstd nintl wssdet edsdet ccdet - 032 hfref/gval/pherrdo/cgaino/bampo/minavg/sythrd/syamp - 033 frm ynr clmp psp 05h 034 index nsen/ssen/psen/wkth 1ah 035 ctest yclen cclen vclen gtest vlpf ckly cklc 00h rgb/ypbpr (analog) index (hex) 7 6 5 4 3 2 1 0 reset value 036 - 00h 037 - 00h 038 - sy_c 00h 039 - 03a - 03b - 03c - 03d - 03e - 03f fbstus - - - 0h
TW8811 ? tft flat panel controller preliminary techwell, inc. 39 rev c 02/07/2008 lcdc ? 3d comb/nr control index (hex) 7 6 5 4 3 2 1 0 reset value 060 md_th 08h 061 * 50h 062 3den mixmd1 mixmd2 * * test3d tm_3d 00h 063 * 80h 064 * 53h 065 mstretch 4ch 066 * 4bh 067 testnr nren nrgain nrlevel 14h 068 nonstd * * * * ns_lnum ns_llen ns_flen 07h 069 nsth1 04h 06a nsth2 03h 06b nson nsoff c1h 06c * 00h 06d * 98h 06e * * * * * * * * 00h 06f * * * * * * * * 00h internal test index (hex) 7 6 5 4 3 2 1 0 reset value 0c0 counter_read_byte_0 00h 0c1 counter_read_byte_1 00h 0c2 counter_read_byte_2 00h 0c3 counter_read_byte_3 00h 0c4 pccinia_index frc_2f frc_1f pccinia_sub_indx 00h 0c5 pccinid 00h 0c6 sel_c grayd data_0 ldchma tlmode romsft ramsft 00h 0c7 bwymin - 0c8 bwymax - 0c9 bwfmin - 0ca bwfmax - 0cb bwbtilt - 0cc bwwtilt - 0cd 0ce test_mode 00h 0cf * * * * * * * 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 40 rev c 02/07/2008 === page 1 : osd/ vbi int. === lcdc ? osd i index (hex) 7 6 5 4 3 2 1 0 reset value 100 * * xf_zoom[1:0] * * yf_zoom[1:0] 11h 101 bc_blink[3:0] fill_color[3:0] 0ch 102 * * * wc_ mode2 wc_mode3[1:0] wc_mode1[1:0] 00h 103 * * * b_fill_ en * * * b_tran_ en 00h 104 * * * * * * * bt_ start 00h 105 * * * bitmap _en * * * source _en 00h 106 grh_map_st[7:0] 00h 107 grh_map_st[15:8] 00h 108 * * * grh_map_st[20:16] 0ah 109 graphv_st[7:0] 14h 10a graphh_st[7:0] 20h 10b graphv_st[11:8] graphh_st[11:8] 03h 10c graphv_ln[7:0] 80h 10d graphh_ln[7:0] 80h 10e graphv_ln[11:8] graphh_ln[11:8] 00h 10f b1phv_st[7:0] 00h 110 b1phh_st[7:0] 00h 111 b1phv_st[11:8] b1phh_st[11:8] 00h 112 b1phv_ln[7:0] 00h 113 b1phh_ln[7:0] 00h 114 b1phv_ln[11:8] b1phh_ln[11:8] 00h 115 b2phv_st[7:0] 00h 116 b2phh_st[7:0] 00h 117 b2phv_st[11:8] b2phh_st[11:8] 00h 118 up_data[7:0] 00h 119 * * * * * * * grh_en 00h 11a stable_add[7:0] 00h 11b st_en st_sel color_sel[1:0] table_sel[3:0] 00h 11c color_attribute_data 00h 11d win_lt _sel * * color _con * con_sel[2:0] 00h 11e color_control_selection 10h 11f * * * * * vbend bwend twend -
TW8811 ? tft flat panel controller preliminary techwell, inc. 41 rev c 02/07/2008 lcdc ? reserve index (hex) 7 6 5 4 3 2 1 0 reset value 120 * * lut_sel _win1 lut_sel _win0 c8t_win _sel c8t_wen c8t_sel[1:0] 00h 121 c8t_add[7:0] 00h 122 c8t_data[7:0] 00h 123 * * * pkt_en * * rlc_rst rlc_ bypass 01h 124 dat_bit[3:0] cnt_bit[3:0] 00h 125 * * * * * * * grh_en _w1 00h 126 * * xf_zoom_w1[1:0] * * yf_zoom_w1[1:0] 11h 127 grh_map_st_w1[7:0] 00h 128 grh_map_st_w1[15:8] 00h 129 * * * grh_map_st_w1[20:16] 0ah 12a graphv_st_w1[7:0] 00h 12b graphh_st_w1[7:0] 00h 12c graphv_st_w1[11:8] graphh_st_w1[11:8] 00h 12d graphv_ln[7:0] 00h 12e graphh_ln[7:0] 00h 12f graphv_ln[11:8] graphh_ln[11:8] 00h 130 rf_xzoom_w0 rf_yzoom_w0 00h 131 rf_xzoom_w1 rf_yzoom_w1 00h 132 * logic _sel 00h 133 rf_logic 00h 134 rf_logic_c15~8 00h 135 rf_logic_c7~0 00h 136 * rf_d_w * rf_d_h 00h ccfl control index (hex) 7 6 5 4 3 2 1 0 reset value 138 oven oien uien fben lo ckv lockh ccflenb ccflden f2h 139 lvt lilt lit adh 13a * * ccfl_ledc_st lstp 04h 13b fpwm 80h 13c fdim 84h 13d ledc_dig _en * * ddim 00h 13e pwmtop 20h lcdc ? external osd & misc. index (hex) 7 6 5 4 3 2 1 0 reset value 151 * * * osd_w_ mask * * osd_ wait * 1-h 152 osd_ mode polarity[2:0] osddelay[2:0] osd_ porten 80h 153 * * * * * * exsync_ sel exhact _sel 00h 154 * ocktps[2:0] * osd_gain[2:0] 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 42 rev c 02/07/2008 155 osd_test_mode 00h 156 * * sub_sel[1:0] * * main_sel[1:0] 00h 157 * * * ext_alpha_con[4:0] 00h 158 * * * dma_w_ mask * * * dma_ wait 00h 159 aeosd eoden_dly[2:0] aeo_vs- pol aeo_hs- pol * rlc_ intr 00h lcdc ? dma index (hex) 7 6 5 4 3 2 1 0 reset value 1a0 * wait dma_sel 02h 1a1 xfer_cnt[15-8] 00h 1a2 xfer_cnt[7-0] 00h 1a3 mem_adr[20-16] 00h 1a4 mem_adr[15-8] 00h 1a5 mem_adr[7-0] 00h 1a6 data_ch 00h 1a7 * rd_wr 00h 1a8 * rd_mon wr_mon wait_mo n 00h lcdc ? status & interrupt index (hex) 7 6 5 4 3 2 1 0 reset value 1b0 lb_ovf lb_unf v_los_c h_los_ c vdlos_c v_loss h_loss syncs 00h 1b1 m_rdy pws_c v_prd_c h_prd_c lbounf vdc_c vh_los_c syncs_c 00h 1b2 irq_b_b17 irq_b_b16 irq_b_b15 irq_b_b14 irq_b_b13 irq_b_b12 irq_b_b11 irq_b_b10 ffh 1b3 * * irq_b_vd irq_b_cc irq_b_50 07h 1b4 p_vlos_c p_vlos_c p_vloss p_hloss p_syncs 00h 1b5 p_vprd_c p_hprd_c p_vhlosc p_syncsc 00h 1b6 m_vlos_c m_vlos_c m_vloss m_hloss m_syncs 00h 1b7 m_vprd_c m_hprd_c m_vhlosc m_syncs 00h 1b8 meas_sel irq_1b5_5 irq_1b5_4 irq_1b5_1 irq_1b5_0 00h 1b9 irq_1b7_5 irq_1b7_4 irq_1b7_1 irq_1b7_0 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 43 rev c 02/07/2008 lcdc : adc/llpll index (hex) 7 6 5 4 3 2 1 0 reset value 1c0 inp_sel cs_inv cs_sel sog_sel hs_pol hs_sel ck_sel 00h 1c1 vs_pol hs_pol vs_det hs_det cs_det in_src 1c2 llc_post llc_vco * llc_ipmp 00h 1c3 * llc_ackn[11:8] 03h 1c4 llc_ackn[7:0] 5ah 1c5 llc_pha 00h 1c6 llc_acpl llc_apg * llc_apz 20h 1c7 * llc_acki[11:8] 04h 1c8 llc_acki[7:0] 00h 1c9 pre_coast 06h 1ca post_coast 06h 1cb pusog pupll * sog_th 30h 1cc * vsy_sel * vsy_polc hsy_polc 00h 1ce adc_clk_ sel * dtv * pda * inrefi inrefi 00h 1cf inp_sel_adc save 24h 1d0 * gainy[8] gainc[8] gainv[8] 00h 1d1 gainy f0h 1d2 gainc f0h 1d3 gainv f0h 1d4 rgb_mode * cl_edge ckly cklc y_cl_en c_cl_en v_cl_en 00h 1d5 cl_start 00h 1d6 cl_end 10h 1d7 cl_loc 70h 1d8 * llc_dbg_sel cl_test adc_test cl_y_test cl_uv_tes t 00h 1d9 cl_y_val 10h 1da cl_uv_val 80h 1dd offsetr 00h 1de offsetg 00h 1df offsetb 00h lcdc ? gamma index (hex) 7 6 5 4 3 2 1 0 reset value 1f0 gamae_r gamae_g gamae_b * auto_in c * gamma_rgb_indx 00h 1f1 gamma_ram_starting_addr 00h 1f2 gamma_ram_data[9:8] 00h 1f3 gamma_ram_data[7:0] 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 44 rev c 02/07/2008 === page 2 : image/display/memory === lcdc ? input type index (hex) 7 6 5 4 3 2 1 0 reset value 20e * * * * * * * dual_656 00h 20f seqrgb_ltg[1:0] seqrgb_order[1:0] seqrgb_sel8bit[1:0] seqrgb_ pol seqrgb 00h lcdc ? input and input related index (hex) 7 6 5 4 3 2 1 0 reset value 210 ofdm rvoddp slvsfld ecsync de_pol hs_pol vs_pol dclk_pol 00h 211 epden pden_pol ext_ha selde * dtvck_delay 20h 212 vgafld selfvs vsdl_656 selfths cr601 input_data_bus_routing 04h 213 internal_clk_pol yuv_rgb_hs rgb 01h 214 coast_range vga_inp b8601 comp yuv_rgb ip_sel 28h 215 ofd_det_end ofd_det_st 54h 216 csync_vs_offset 20h 217 ip_ha_st_lo 00h 218 ip_ha_end_lo cfh 219 ip_ha_end_hi * ip_ha_st_hi 20h 21a ip_va_st_odd_lo 13h 21b ip_va_st_evn_lo 13h 21c ip_va_length_lo 00h 21d * ip_va_length_hi ip_va_st_evn_hi ip_va_st_odd_lo 30h 21e hscktps 2[2] gpioen2 gpioen1 gpioen0 irq_al * hscktps2[1:0] 00h 21f gpio1_p gpio1_src gpio1_d gpio0_p gpio0_src gpio0_d 00h lcdc ? input measurement index (hex) 7 6 5 4 3 2 1 0 reset value 220 * 221 mea_win_h_st_lo 20h 222 mea_win_h_end_lo ffh 223 mea_win_h_end_hi * mea_win_h_st_hi 10h 224 mea_win_v_st_lo 20h 225 mea_win_v_end_lo fah 226 * mea_win_v_end_hi * mea_win_v_st_hi 00h 227 result_0 - 228 result_1 - 229 result_2 - 22a result_3 - 22b result_sel field_sel rd_lock startm 00h 22c u_27m noise_mask err_toler endet 00h 22d threshold_for_act_det enalu nofsel de_mea 30h 22e 22f
TW8811 ? tft flat panel controller preliminary techwell, inc. 45 rev c 02/07/2008 lcdc - scaling index (hex) 7 6 5 4 3 2 1 0 reset value 230 x_scale_up_mid b4h 231 x_scale_down_lo 80h 232 y_scale_up/down_mid 50h 233 panora_ ma lndb pxdb zoombp y_scale_up/ down_hi x_scale _down_h i x_scale _up_hi 00h 234 x_offset 00h 235 y_odd_offset 80h 236 h_non_display_pixel / h_panorama_pixel 00h 237 lb_ce * * * * * h_non_display / h_panorman_pixel 00h 238 x_scale_up_lo (at_the_side_for_panorama) 00h 239 x_scale_up_lo 00h 23a y_scale_up_lo 00h 23b y_even_offset 00h 23c 23d 23e 23f
TW8811 ? tft flat panel controller preliminary techwell, inc. 46 rev c 02/07/2008 lcdc ? image adjustment index (hex) 7 6 5 4 3 2 1 0 reset value 240 * indx_cb hue 20h 241 contrast_r / contrast_y 80h 242 contrast_g / contrast_cb 80h 243 contrast_b / contrast_cr 80h 244 brightness_r / brightness_y 80h 245 brightness_g 80h 246 brightness_b 80h 247 h_sharp_cor h_sharpness 3fh 248 h_sharp_f req * dynr * hflt 00h 249 indx_cb2 hue2 20h 24a contrast_r2 / contrast_y2 80h 24b contrast_g2 / contrast_cb2 80h 24c contrast_b2 / contrast_cr2 80h 24d brightness_r2 / brightness_y2 80h 24e brightness_g2 80h 24f brightness_b2 80h 250 h_sharp_cor2 h_sharpness2 3fh 251 h_sharp_f req2 * dynr2 * hflt2 00h 252 v_sharp_ a v_sharp_b dis_edg index_for_07a 00h 253 edge_enhancement_threshold_reg_0/1/2/3/4 - 254 * * rsv 04h 255 t_bw * pedlvl whtlvl * * bpbw * 1ch 256 bw_line_st_lo 08h 257 bw_line_end_lo f6h 258 * bw_line_end_hi bw_line_st_hi 08h 259 bw_h_delay 10h 25a * bw_h_filter_gain 0dh 25b bw_black_tilt 67h 25c bw_white_tilt 94h 25d bw_black_gain 2ah 25e bw_white_gain d0h 25f pdof_en pip_dn_off* cah 260 * bw_gain 02h 261 hred_en mpip_h_reduction 00h 262 * * 18h 263 ce_center0 3dh 264 ce_center1 c3h 265 ce_center2 fch 266 ce_en ce_spread0 ce_gain0 00h 267 * ce_spread1 ce_gain1 00h 268 * ce_spread2 ce_gain2 00h 269 * 00h 26a * * * * 00h 26b * * 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 47 rev c 02/07/2008 lcdc ? display control index (hex) 7 6 5 4 3 2 1 0 reset value 270 dblop fpdeah fphsah fpvsah rvfpck rvhilo rvbit fpclkc 40h 271 tcons usereg demode op6b trifp fpclk_delay 00h 272 fphs_period_lo 3ah 273 fphs_active_pw 10h 274 fp_h_back_porch 1bh 275 fpde_active_lo 00h 276 fpde_active_hi fphs_period_hi 45h 277 fpvs_period_lo 26h 278 fpvs_active_pw 06h 279 fp_v_back_porch 1fh 27a fp_v_active_lo 00h 27b early_s t fp_v_active_hi * fpvs_period_hi 33h 27c * dither_option * dither_format 00h 27d vsync_delay 08h 27e frclong frcshrt epwmx pwm_al vh_disha frerun autoc sdelvs 00h 27f disp_sngfld rvf_ac tvvsf4 noevni evndly 00h 280 ini_cnt_evn_lo 00h 281 ini_cnt_odd_lo 00h 282 ini_cnt_evn_hi ini_cnt_odd_hi 00h 283 evnpm number_of_lines_to_black_out 00h 284 pwmc_d 2 pwm_counter 40h 285 286 287 dual_se lh 289 lcdc ? memory control index (hex) 7 6 5 4 3 2 1 0 reset value 2a0 rd_ph mclkosel nomcst testen bconfig a2h 2a1 tafrsh 07h 2a2 rasmax 20h 2a3 trp trcd 22h 2a4 ad21 * * * trfc 07h 2a5 * rdltnc tminc 43h 2a6 * * cycdel * casltnc 13h 2a7 * * * * * * * 40h 2a8 2a9 2aa 2ab 2ac 2ad 2ae pip_h_pos_adj 20h 2af pip_v_pos_adj 2ch
TW8811 ? tft flat panel controller preliminary techwell, inc. 48 rev c 02/07/2008 lcdc ? pip/mpip control index (hex) 7 6 5 4 3 2 1 0 reset value 2b0 pipgw_xst[7:0] 10h 2b1 pipgw_width[7:0] 60h 2b2 ppfil_ma n pipgw_width[10:8] ppfil_sel pipgw_xst[9:8] 20h 2b3 pipgw_yst[7:0] 02h 2b4 pipgw_height[7:0] e0h 2b5 pipwhgt[ 8] * pipefdoff pipwyst[ 8] * pipofdoff 00h 2b6 pipdnsxfac[7:0] 00h 2b7 pipdnsyfac[7:0] 00h 2b8 pipdnsyfac[11:8] pipdnsxfac[11:8] 11h 2b9 pip_wr_base 00h 2ba pip_wr_width[7:0] 30h 2bb pip_wr_height[7:0] 70h 2bc pipwren wcph pipofen pipofph height[8] * pip_wr_width[9:8] 01h 2bd prden wr_pdn pipen sngl_fd pfppol pxdb * black 00h 2be pupsxfac[7:0] 00h 2bf pupsyfac[7:0] 00h 2c0 pupsyfac[11:8] pupsxfac[11:8] 88h 2c1 pipwbasex[7:0] 80h 2c2 pipwbasey[7:0] 80h 2c3 ck_inv pipwbasey[10:8] pipwbasex[11:8] 12h 2c4 pipwyoff pipwxoff 2ch 2c5 pipwwidth[7:0] 30h 2c6 pipwheight[7:0] e0h 2c7 prcph pipwheight[10:8] pipwwidth[11:8] 01h 2c8 mpip_h_pos_adj 2ch 2c9 mpip_v_pos_adj 2eh 2ca mpipgw_xst[7:0] 00h 2cb mpipgw_width[7:0] 00h 2cc mpfil_man mpipgw_width[10:8] mpfil_sel mpipgw_xst[9:8] 00h 2cd mpipgw_yst[7:0] 00h 2ce mpipgw_height[7:0] 00h 2cf mpipwhgt [8] * mpipefdoff mpipwyst [8] * mpipofdoff 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 49 rev c 02/07/2008 index (hex) 7 6 5 4 3 2 1 0 reset value 2d0 mpipdnsxfac[7:0] 00h 2d1 mpipdnsyfac[7:0] 00h 2d2 mpipdnsyfac[11:8] mpipdnsxfac[11:8] 11h 2d3 mpip_wr_base 00h 2d4 mpip_wr_width[7:0] 00h 2d5 mpip_wr_height[7:0] 00h 2d6 mpwren wcph mpofen mpofph height[8] * mpip_wr_width[9:8] 00h 2d7 mprden wr_pdn mpipen * mpfppol pxdb * black 00h 2d8 pupsxfac[7:0] 00h 2d9 pupsyfac[7:0] 00h 2da pupsyfac[11:8] pupsxfac[11:8] 88h 2db pipwbasex[7:0] 20h 2dc pipwbasey[7:0] 2ch 2dd pipvups_off* 80h 2de pipwyoff pipwxoff 00h 2df pipwwidth[7:0] 00h 2e0 pipwheight[7:0] 00h 2e1 ck_inv pipwheight[10:8] pipwwidth[11:8] 00h 2e2 prcph init_en 00h 2e3 mpiporgx[7:0] 00h 2e4 mpiporgy[7:0] 00h 2e5 init_color 00h 2e6 key_dsp alpha2 10h 2e7 mpiphight [8] mpipwidth[9:8] mpiporgy [8] mpiporgx[9:8] 00h 2e8 mpip_vspace[3:0] mpip_hspace[3:0] 00h 2e9 mpip_ymax[1:0] mpip_xmax[1:0] mpip_winxy1:0] mpip_winx[1:0] 00h 2ea mpip_borderw[2:0] mpip_hly[1:0] mpip_hlx[1:0] 00h 2eb mpip_frmcolor1[7:0] 1ch 2ec mpip_frmcolor2[7:0] e0h 2ed 00h 2ee dtvde pip_inmx_sel[1:0] mpip_inmx_sel[1:0] 00h 2ef pipab_en md565 key_inv alpha1 00h 2f0 rkey 00h 2f1 gkey 00h 2f2 bkey 00h 2f3 key_range 00h lcdc ? power management index (hex) 7 6 5 4 3 2 1 0 reset value 2f4 divde_down_counter_msb 00h 2f5 pclk_pdn clksel_fppwr pwr_state manpwr edpms pwr_state_wt 00h 2f6 suspend_stdby_cnt on_suspend_cnt 00h 2f7 off_stdby_cnt stdby_off_cnt 00h 2f8 stdby_suspend_cnt suspend_on_cnt 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 50 rev c 02/07/2008 === page 3 : tcon/ pll === lcdc ? tcon index (hex) 7 6 5 4 3 2 1 0 reset value 300 sig_off tcck_ph roe_en * div_ck 20h 301 * rev_en * inv_sel 00h 302 * top_btm lft_rht 05h 303 * roe_p rsp_p clp_p csp_p 0fh 304 pgm_sha rp sp_ctrl pgm_rc k pgm_roe pgm_rsp pgm_pol pgm_clp pgm_csp 00h 305 * inv_sw 00h 306 rev_sel anal_lc d 02h 30a * rsp_width * company 02h 30b revv_revc 4dh 30c * v_st[11:8] 00h 30d v_st[7:0] 06h 30e * v_ed[11:8] 01h 30f v_ed[7:0] e2h 310 cp_sw[11:8] 02h 311 cp_sw[7:0] d0h 312 * clp_st[11:8] 02h 313 clp_st[7:0] d0h 314 * clp_ed[11:8] 00h 315 clp_ed[7:0] 06h 31a * csp_st[11:8] 00h 31b csp_st[7:0] c8h 31c * csp_ed[11:8] 00h 31d csp_ed[7:0] 01h 320 * rck_st[11:8] 00h 321 rck_st[7:0] 00h 322 * rck_ed[11:8] 02h 323 rck_ed[7:0] 30h 324 * rsp_st[11:8] 00h 325 rsp_st[7:0] 06h 326 * rsp_ed[11:8] 00h 327 rsp_ed[7:0] 01h 32c * roe_st[11:8] 00h 32d roe_st[7:0] 0ah 32e * roe_ed[11:8] 00h 32f roe_ed[7:0] 40h 334 * sharp_str_h 00h 335 sharp_str_l 20h 336 * sharp_end_h 01h 337 sharp_end_l e2h 338 * clpw csync_m ode clpsel cspsel 00h 339 * pol_step[3:0] 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 51 rev c 02/07/2008 lcdc ? pll & dac index (hex) 7 6 5 4 3 2 1 0 reset value 3a0 ip_p freq_p[19:15] 40h 3a1 freq_p[14:7] 00h 3a2 freq_p[6:0] * 00h 3a3 ssfreq_p[7:0] 00h 3a4 ssg_p vco_p post_p 00h 3a5 ip_m freq_m[19:15] 40h 3a6 freq_m[14:7] 00h 3a7 freq_m[6:0] * 00h 3a8 ssfreq_m[7:0] 00h 3a9 selpadpclk selpadmclk pd_p pd_m pllinsel ssd 00h 3aa ssg_m vco_m post_m 00h 3ab * * * da_rgain 3ac * * * da_ggain 3ad * * * da_bgain 3ae dacpd test_clk_sel dac_iref * 00h 3f0 hswid 10h 3f1 3ff page_num 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 52 rev c 02/07/2008 TW8811 register description 0x000 ? product id code register (id) bit function r/w description reset 7-3 id r the TW8811 product id code is 00101. 00101b 2-0 revision r revision number 000b 0x001 ? chip status register (cstatus) bit function r/w description reset 7 vdloss r 1 = video not present. (sync is not dete cted in a number of consecutive video lines specified by misscnt register) 0 = video detected. 0 6 hlock r 1 = horizontal sync pll is locked to the incoming video source. 0 = horizontal sync pll is not locked. 0 5 slock r 1 = sub-carrier pll is locked to the incoming video source. 0 = sub-carrier pll is not locked. 0 4 field r 0 = odd field is being decoded. 1 = even field is being decoded. 0 3 vlock r 1 = vertical logic is locked to the incoming video source. 0 = vertical logic is not locked. 0 2 reserved r reserved 0 1 mono r 1 = no color burst signal detected. 0 = color burst signal detected. 0 0 det50 r 0 = 60hz source detected 1 = 50hz source detected the actual vertical scanning frequency depends on the current standard invoked. 0 0x002 ? input format (inform) bit function r/w description reset 7 ysel[2] r/w msb of ysel. (see description below) 0 6 fc27 r/w 1 = input crystal clock frequency is 27mhz. 0 = square pixel mode. must use 24.54mhz for 60hz field rate source or 29.5mhz for 50hz field rate source. 1 5-4 ifsel r/w 10 = component video decoding 01 = s-video decoding 00 = composite video decoding 00 3-2 ysel[1:0] r/w these three bits control the y input video selection mux. 000 : yout = yin0 001 : yout = yin1 010 : yout = yin2 011 : yout = yin3 1xx : na 00 1 csel r/w this bit controls the c input source selection. 0 = cin0 1 = cin1 0 0 reserved r/w 0 0x003 ? qclamp bit function r/w description reset 7-0 qclamp r/w reserved 20h
TW8811 ? tft flat panel controller preliminary techwell, inc. 53 rev c 02/07/2008 0x004 ? ckhy bit function r/w description reset 7 reserved r/w reserved 0 6-5 ckhy r/w color killer time constant 0: fast 3: slow 0 4-0 reserved r/w reserved for test. 0x005 ? reserved bit function r/w description reset 7-0 sagcgain r/w afh 0x006 ? analog control register (acntl) bit function r/w description reset 7 sreset w a 1 written to this bit resets the device to its default state but all register content remain unchanged. this bit is self-resetting. 0 6 r/w reserved 0 5 fbyp r/w 1 = anti-alias filter bypass 0 = enable 0 4 agc_enb r/w 0 = agc loop function enabled. 1 = agc loop function disabled. gain is set to by agcgain. 0 3 clk_pdn r/w 0 = normal clock operation. 1 = 27 mhz clock in power down mode. 0 2 y_pdn r/w 0 = luma adc in normal operation. 1 = luma adc in power down mode. 0 1 c_pdn r/w 0 = chroma adc in normal operation. 1 = chroma adc in power down mode. 1 0 v_pdn r/w 0 =v channel adc in normal operation. 1 = v channel adc in power down mode. 1 0x007 ? cropping register, high (crop_hi) bit function r/w description reset 7-6 vdelay_hi r/w these bits are bit 9 to 8 of the 10-bit vertical delay register. 0 5-4 vactive_hi r/w these bits are bit 9 to 8 of the 10- bit vactive register. refer to description on reg09 for its shadow register. 0 3-2 hdelay_hi r/w these bits are bit 9 to 8 of the 10-bit horizontal delay register. 0 1-0 hactive_hi r/w these bits are bit 9 to 8 of the 10-bit hactive register. 10b 0x008 ? vertical delay register, low (vdelay_lo) bit function r/w description reset 7-0 vdelay_lo r/w these bits are bit 7 to 0 of the 10- bit vertical delay register. the two msbs are in the crop_hi register. it defines the number of lines between the leading edge of vsync and the start of the active video. 15h 0x009 ? vertical active register, low (vactive_lo) bit function r/w description reset 7-0 vactive_lo r/w these bits are bit 7 to 0 of the 10-bi t vertical active register. the two msbs are in the crop_hi register. it defines the number of active video lines per frame output. the vactive register has a shadow register for use with 50hz source when atreg of reg0x1c is not set. this register can be a ccessed through the same index address by first changing the format standard to any 50hz standard. f0h
TW8811 ? tft flat panel controller preliminary techwell, inc. 54 rev c 02/07/2008 0x00a ? horizontal delay register, low (hdelay_lo) bit function r/w description reset 7-0 hdelay_lo r/w these bits are bit 7 to 0 of the 10-bi t horizontal delay register. the two msbs are in the crop_hi register. it defines the number of pixels between the leading edge of the hsync and the start of the image cropping for active video. the hdelay_lo register has two shadow regi sters for use with pal and secam sources respectively. these register can be accessed us ing the same index address by first changing the decoding format to the corresponding standard. 84h 0x00b ? horizontal active register, low (hactive_lo) bit function r/w description reset 7-0 hactive_lo r/w these bits are bit 7 to 0 of the 10-bi t horizontal active register. the two msbs are in the crop_hi register. it defines the number of active pixels per line output. d0h 0x00c ? control register i (cntrl1) bit function r/w description reset 7 pbw r/w 1 = wide chroma bpf bw 0 = normal chroma bpf bw 1 6 dem r/w color killer sensitivity. 1= low 0 = high 0 5 palsw r/w 1 = pal switch sensitivity low. 0 = pal switch sensitivity normal. 0 4 set7 r/w 1 = the black level is 7.5 ire above the blank level. 0 = the black level is the same as the blank level. 0 3 comb r/w 1 = adaptive comb filter on for ntsc/pal 0 = notch filter 1 2 hcomp r/w 1 = operation mode 1. (recommended) 0 = operation mode 0. 1 1 ycomb r/w this bit controls the comb operation in the case of monochrome video. 1 = comb enabled. 0 = comb disabled. 0 0 pdly r/w pal delay line. 0 = enabled. 1 = disabled. 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 55 rev c 02/07/2008 0x010 ? brightness control register (bright) bit function r/w description reset 7-0 brightness r/w these bits control the brightness. they have value of ?128 to 127 in 2's complement form. positive value increases brightness. a value 0 has no effect on the data. 00h 0x011 ? contrast control register (contrast) bit function r/w description reset 7-0 contrast r/w these bits control the contrast. t hey have value of 0 to 3.98 (ffh). a value of 1 (`100_0000`) has no effect on the video data. 60h 0x012 ? sharpness control register i (sharpness) bit function r/w description reset 7 scurve r/w this bit controls the center fr equency of the peaking filter. the corresponding gain adjustment is hflt. 0 = low 1 = center 0 6 vsf r/w reserved 1 5-4 cti r/w color transient improvement level contro l. there are 4 enhancement levels with 0 being the lowest and 3 being the highest. 1 3-0 sharp r/w these bits control the amount of sh arpness enhancement on the luminance signals. there are 16 levels of control with '0' having no effect on the output image. 1 through 15 provides sharpness enhancement with ?15? being the strongest. 1 0x013 ? chroma (u) gain register (sat_u) bit function r/w description reset 7-0 sat_u r/w these bits control the digital gain adju stment to the u (or cb) component of the digital video signal. the color saturation can be adjusted by adjusting the u and v color gain components by the same amount in the normal situation. the u and v can also be adjusted independently to provide greater flexibility. the range of adjustment is 0 to 200%. 80h 0x014 ? chroma (v) gain register (sat_v) bit function r/w description reset 7-0 sat_v r/w these bits control the digital gain adju stment to the v (or cr) component of the digital video signal. the color saturation can be adjusted by adjusting the u and v color gain components by the same amount in the normal situation. the u and v can also be adjusted independently to provide greater flexibility. the range of adjustment is 0 to 200%. 80h 0x015 ? hue control register (hue) bit function r/w description reset 7-0 hue r/w these bits control the color hue. they have value from +96 o (7fh) to -96 o (80h) with an increment of 0.75 o . the default value is 0 (00h). 00h 0x016 ? reserved bit function r/w description reset 7-4 reserved r/w c 3-0 reserved r/w 8 0x017 ? vertical peaking control i bit function r/w description reset 7-4 shcor r/w these bits provide cori ng function for the sharpness control. 3 3 reserved reserved 0 2-0 vshp r/w these bits control the vertical peaking level with '0' being the minimum and '7' being the maximum. 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 56 rev c 02/07/2008 0x018 ? coring control register (coring) bit function r/w description reset 7-6 ctcor r/w these bits control the coring function for the cti. it has internal step size of 2. 1 5-4 ccor r/w these bits control the low level coring function for the cb/cr output. 0h 3-2 vcor r/w these bits control the coring function of the vertical peaking logic. it has an internal step size of 2. 1h 1-0 cif r/w these bits control the if compensation level. 0 = none 1 = 1.5 db 2 = 3 db 3 = 6 db (secam) 0h 0x019 ? reserved bit name r/w description reset 7-0 reserved reserved 0x01a ? cc/eds status register (cc_status) bit function r/w description reset 7-0 reserved r/w reserved 0 0x01b ? cc/eds data register (cc_data) bit function r/w description reset 7-0 reserved r reserved 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 57 rev c 02/07/2008 0x01c ? standard selection (sdt) bit function r/w description reset 7 detstus r 0 = idle 1 = detection in progress 0 6-4 stdnow r current standard invoked 0 = ntsc(m) 1 = pal (b,d,g,h,i) 2 = secam 3 = ntsc4.43 4 = pal (m) 5 = pal (cn) 6 = pal 60 7 = not valid 0 3 atreg r/w 1 = disable the shadow registers. 0 = enable vactive and hdelay shadow registers value depending on standard 0 2-0 standard r/w standard selection 0 = ntsc(m) 1 = pal (b,d,g,h,i) 2 = secam 3 = ntsc4.43 4 = pal (m) 5 = pal (cn) 6 = pal 60 7 = auto detection 0h 0x01d ? standard recognition (sdtr) bit function r/w description reset 7 atstart r/w writing 1 to this bit will manually initiate the auto format detection process. this bit is a self- resetting bit. 0 6 pal6_en r/w 1 = enable recognition of pal60. 0 = disable recognition. 0 5 paln_en r/w 1 = enable recognition of pal (cn). 0 = disable recognition. 0 4 palm_en r/w 1 = enable recognition of pal (m). 0 = disable recognition. 0 3 nt44_en r/w 1 = enable recognition of ntsc 4.43. 0 = disable recognition. 0 2 sec_en r/w 1 = enable recognition of secam. 0 = disable recognition. 0 1 palb_en r/w 1 = enable recognition of pal (b,d,g,h,i). 0 = disable recognition. 0 0 ntsc_en r/w 1 = enable recognition of ntsc (m). 0 = disable recognition. 0 0x01e ? component video format (cvfmt) bit name r/w description reset 7 rsv r reserved 0 6-4 cvstd r component video input format detection. 0 = 480i, 1 = 576i, 2 = 480p, 3 = 576p 0h 3-0 cvfmt r/w component video format selection. 0 = 480i, 1 = 576i, 2 = 480p, 3 = 576p, 8 = auto 8h
TW8811 ? tft flat panel controller preliminary techwell, inc. 58 rev c 02/07/2008 0x01f ? control register bit name r/w description reset 7-3 r reserved 0 2 vref r/w video adc voltage reference control. 0=normal operation 0 1 iref r/w video adc bias control, 0=normal operation 0 0 save r/w video adc reference current control, 0=normal current, 1=2/3 of normal current 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 59 rev c 02/07/2008 0x020 ? clamping gain (clmpg) bit function r/w description reset 7-4 clpend r/w these 4 bits set the end time of the clam ping pulse in the increment of 8 system clocks. the clamping time is determined by this together with clpst. 5 3-0 clpst r/w these 4 bits set the start time of the cl amping pulse in the increment of 8 system clocks. it is referenced to pclamp position. 0 0x021 ? individual agc gain (iagc) bit function r/w description reset 7-4 nmgain r/w these bits control the nor mal agc loop maximum correction value. 4 3-1 wpgain r/w peak agc loop gain control. 1 0 agcgain[8] r/w this bit is the msb of the 9-bit register that controls the agc gain when agc loop is disabled. 0 0x022 ? agc gain (agcgain) bit function r/w description reset 7-0 agcgain[7:0] r/w these bits are the lower 8 bits of the 9-bit register that controls the agc gain when agc loop is disabled. f0h 0x023 ? white peak threshold (peakwt) bit function r/w description reset 7-0 peakwt r/w these bits control the white peak detection threshold. d8h 0x024? clamp level (clmpl) bit function r/w description reset 7 clmpld r/w 0 = clamping level is set by clmpl. 1 = clamping level preset at 60d. 1 6-0 clmpl r/w these bits determine the clamping level of the y channel. 3ch 0x025? sync amplitude (synct) bit function r/w description reset 7 synctd r/w 0 = reference sync amplitude is set by synct. 1 = reference sync amplitude is preset to 38h. 1 6-0 synct r/w these bits determine the standard sync pulse amplitude for agc reference. 38h 0x026 ? sync miss count register (misscnt) bit function r/w description reset 7-4 misscnt r/w these bits set the threshold for horizontal sync miss count threshold. 4 3-0 hswin r/w these bits set the size for the horizontal sync detection window. 4 0x027 ? clamp position register (pclamp) bit function r/w description reset 7-0 pclamp r/w these bits set the clamping position from the pll sync edge 2ah
TW8811 ? tft flat panel controller preliminary techwell, inc. 60 rev c 02/07/2008 0x028 ? vertical control register bit function r/w description reset 7-6 vlcki r/w vertical lock in time. 0 = fastest 3 = slowest. 0 5-4 vlcko r/w vertical lock out time. 0 = fastest 3 = slowest. 0 3 vmode r/w this bit controls the vertical detection window. 1 = search mode. 0 = vertical count down mode. 0 2 detv r/w 1 = recommended for special switching application only. 0 = normal vsync logic 0 1 afld r/w auto field generation control 0 = off 1 = on 0 0 vint r/w vertical integration time control. 1 = long 0 = normal 0 0x029 ? vertical control ii bit function r/w description reset 7-5 bsht r/w burst pll center frequency control. (reserved) 0 4-0 vsht r/w vsync output delay control in the increment of half line length (reserved) 15h 0x02a ? color killer level control bit function r/w description reset 7-6 ckilmax r/w these bits control the amount of co lor killer hysteresis. the hysteresis amount is proportional to the value. 2 5-0 ckilmin r/w these bits control the color killer th reshold. larger value gives lower killer level. 20h 0x02b ? comb filter control bit function r/w description reset 7-4 htl r/w adaptive comb filter combing control. 4 3-0 vtl r/w adaptive comb filter combing control. 4 0x02c ? luma delay and hsync control bit function r/w description reset 7 cklm r/w color killer mode. 0 = normal 1 = fast (for special application) 0 6-4 ydly r/w luma delay fine adjustment. this 2's co mplement number provides ?4 to +3 unit delay control. 3 3-0 hflt r/w peaking control 2. the peak ing curve is controlled by scurve bit. 000
TW8811 ? tft flat panel controller preliminary techwell, inc. 61 rev c 02/07/2008 0x02d ? miscellaneous control register i (misc1) bit function r/w description reset 7 hplc r/w reserved for internal use. 0 6 evcnt r/w 1 = even field counter in special mode. 0 = normal operation. 0 5 palc r/w reserved for future use. 0 4 sdet r/w id detection sensitivity. a ?1? is recommended. 1 3 tbc_en r/w reserved. 0 2 bypass r/w debug use 1 1 syout r/w reserved. 0 0 hadv r/w reserved. 0 0x02e ? miscellaneous control register ii (misc2) bit function r/w description reset 7-6 hpm r/w horizontal pll acquisition time. 0 = slow 1 = auto1 2 = auto 3 = fast 2 5-4 acct r/w acc time constant 00 = no acc 01 = slow 10 = medium 11 = fast 2 3-2 spm r/w burst pll control. 0 = slowest 1 = slow 2 = fast 3 = fastest 1 1-0 cbw r/w chroma low pass filter bandwidth control. 0 = low 1 = medium 2 = high 3 = extended 1 0x02f ? miscellaneous control iii (misc3) bit function r/w description reset 7 nkill r/w 1 = enable noisy signal co lor killer function in ntsc mode. 0 = disabled. 1 6 pkill r/w 1 = enable automatic noisy color killer function in pal mode. 0 = disabled. 1 5 skill r/w 1 = enable automatic noisy color killer function in secam mode. 0 = disabled. 1 4 cbal r/w 0 = normal output 1 = special output mode. 0 3 fcs r/w 1 = force decoder output value determined by ccs. 0 = disabled. 0 2 lcs r/w 1 = enable pre-determined output value indicated by ccs when video loss is detected. 0 = disabled. 0 1 ccs r/w when fcs is set high or video loss condi tion is detected when lcs is set high, one of two colors display can be selected. 1 = bluer. 0 = black. 0 0 bst r/w 1 = enable blue stretch. 0 = disabled. 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 62 rev c 02/07/2008 0x030 ? macrovision detection bit function r/w description reset 7 sid_fail r secam status 6 pid_fail r pal status 5 fsc_fail r fsc status 4 slock_fail r pll status 3 csbad r 1 = macrovision color stripe detection may be un-reliable 2 mcvsn r 1 = macrovision agc pulse detected. 0 = not detected. 1 cstripe r 1 = macrovision color stripe protection burst detected. 0 = not detected. 0 ctype2 r this bit is valid only when color st ripe protection is detected, i.e. cstripe=1. 1 = type 2 color stripe protection 0 = type 3 color stripe protection 0x031 ? cstatus iii bit function r/w description reset 7 vcr r 1 = vcr mode 6 wkair r 1= weak signal 0 = normal 5 wkair1 r weak signal indicator. 4 vstd r 1= standard signal 0 = non ? standard signal 3 nintl r 1 = non-interlaced signal 0 = interlaced signal 2 wssdet r 1 = wss data detected. 0 = not detected. 1 edsdet r 1 = eds data detected. 0 = not detected. 0 ccdet r 1 = cc data detected. 0 = not detected. 0x032 ? hfref bit function r/w description reset 7-0 reserved r href[9:2] / gval[8:1] / pherrdo / cgaino / bampo / minavg / sythrd / syamp - 0x033 ? miscellaneous control register bit function r/w description reset 7-6 frm r/w free run mode. 0x = auto mode 10 = 60 hz 11 = 50 hz 00 5-4 ynr r/w y hf noise reduction. 0 = none 1 = smallest 2 = small 3 = medium 00 3-2 clmd r/w clamping mode control. 00 = sync top 1 = auto 2 = pedestal 3 = n/a 01 1-0 psp r/w slice level for sync top mode. 0 = low 1 = medium 2 = high 3=highest 01 0x034 ? nsen/ssen/psen/wkth bit function r/w description reset 7-6 index r/w these two bits indicate which of the four lower 6-bit registers is currently being controlled. the write sequence is a two steps process unless t he same register is written. a write of {id,000000} selects one of the four registers to be written. a subsequent write will actually write into the register. 00 5-0 nsen / ssen / psen / wkth r/w idx = 0 controls the ntsc id detection sensitivity (nsen). idx = 1 controls the secam id detection sensitivity (ssen). idx = 2 controls the pal id detection sensitivity (psen). ids = 3 controls the weak signal detection sensitivity (wkth). 1a / 20 / 1c / 2a
TW8811 ? tft flat panel controller preliminary techwell, inc. 63 rev c 02/07/2008 0x035 ? clamp cntl2 bit function r/w description reset 7 ctest r/w clamping control for debug use. 0 6 yclen r/w 1 = y channel clamp disabled 0 = enabled. 0 5 cclen r/w 1 = c channel clamp disabled 0 = enabled. 0 4 vclen r/w 1 = v channel clamp disabled 0 = enabled. 1 3 gtest r/w 1 = test. 0 = normal operation. 0 2 vlpf r/w clamping filter control 0 1 ckly r/w clamping current control for y. 0 0 cklc r/w clamping current control for c/v. 0 0x038 ? analog cntl bit function r/w description reset 7-6 reserved 0 sy_c r/w yout control 0 = y 1 = y+c 0 0x03a ? 0x03e reserved 0x03f ? dac current reference bit function r/w description reset 7-4 fbstus r reserved - 3 sysel r/w y(cvbs) input selection 0 = g adc input selection 1 = y adc input selection 0 2 fbtyp r/w reserved 0 1-0 fbthd r/w reserved 00
TW8811 ? tft flat panel controller preliminary techwell, inc. 64 rev c 02/07/2008 3d comb control (0x060 to 0x06f) 0x060 ? mdth bit function r/w description reset 7-0 mdth r/w motion detection threshold (smaller value yields more 2d) 08h 0x062 ? 3d_mode bit function r/w description reset 7 3d_en r/w 1 : 3d comb enable, 0 : disable (2d only and no sdram access) 0 6 mixmd1 r/w 1: fixed mode (chosen by bit 5), 0 : adaptive mode 0 5 mixmd2 r/w when 0x72 bit 6 is ?1?, this bit defines fixed mode selection 1: 2d, 0 : 3d 0 4-3 reserved - 00 2 test3d r/w 1: 3d comb test mode enable. should be ?0? for normal operation 0 1-0 tm_3d r/w 3d-comb test mode. according to the setting of these bits, vd[15:0] will output following signals. 0: frame delay test 1 (f0 and f1), 1: frame delay test 2 (f1 and f2), 2: frame- combed y and motion test, 3: frame-combed y and c test 0h 0x065 ? str bit function r/w description reset 7-0 m_strch r/w stretch of detected motion 4ch 0x067 ? nrlevel bit function r/w description reset 7 testnr r/w 1: 3d-nr test mode enable. vd[15:8] will output current y and vd[7:0] will output 1 frame delayed y. should be ?0? for normal operation. 0 6 nr_en r/w 1: 3d-nr enable, 0: disable in some mode, 3d-nr is not available with 3d-coymb. please refer the description of ?memory controller? in the previous section for detail. 0 5-4 nrgain r/w noise reduction correction gain 0: ? , 1: ?, 2: ?, 3: 1/8 1h 3-0 nrlevel r/w noise identification level (bigger val ue will correct bigger noise but may induce obvious tailing) 4h 0x068 ? nsmode bit function r/w description reset 7 nonstd r 1: non-standard signal, 0: standard signal 6-3 reserved r/w 0 2 ns_lnum r/w 1: check line number per frame, 0: ignore line number 1 1 ns_llen r/w 1: check line length error, 0: ignore length error 1 0 ns_flen r/w 1: check frame length error, 0: ignore frame length error 1 0x069 ? nslevel1 bit function r/w description reset 7-0 nsth1 r/w non standard detection threshold 1 02h 0x06a ? nslevel2 bit function r/w description reset 7-0 nsth2 r/w non standard detection threshold 2 03h
TW8811 ? tft flat panel controller preliminary techwell, inc. 65 rev c 02/07/2008 0x06b ? nshys bit function r/w description reset 7-4 nson r/w non standard detection hysteresis for on point ch 3-0 nsoff r/w non standard off point 1h
TW8811 ? tft flat panel controller preliminary techwell, inc. 66 rev c 02/07/2008 0x0c0 to 0x0cf ? internal test address bit r/w description reset 0x0c0 0x0c1 0x0c2 0x0c3 7 - 0 r these four index addresses provide real time data read out of some internal counters. the index of these counters is set by 0x22b[7:4]. index 0x0c0 0x0c1 0x0c2 0x0c3 0 lvpcnt_odd[7:0] lvpcnt_odd[15:8] lvpcnt_odd[23:16 ] 1 lvpcnt_evn[7:0] lvpcnt_evn[15:8] lvpcnt_evn[23:16 ] 2 livcnt_odd[7:0] livcnt_odd[11:8] 3 livcnt_evn[7:0] livcnt_evn[11:8] 4 lhpcnt[7:0] lhpcnt[13:8] lbovfc[7:0] lbovfc[10:8] 0000 address bit r/w description reset 7 - 4 r/w index for simulation initialization of internal auto calculation counters. 0: vpcnt[23:0] pixel counter for 1 vsync period 1: lvpcnt_odd[23:0] pixel count er for 1 odd field vsync period 2: lvpcnt_evn[23:0] pixel counter for 1 even field vsync period 3: ivcnt[11:0] line counter for 1 vsync period 4: livcnt_odd[11:0] line counter for 1 odd field vsync period 5: livcnt_evn[11:0] line counter for 1 even field vsync period 6: gocnt[23:0] pixel counter from vsync to the beginning of output display 7: lgoocnt[23:0] pixel counter from vsync to the beginning of output display (odd) 8: lgoecnt[23:0] pixel counter from vsync to the beginning of output display (even) 0000 3 r/w 1: force auto calculation to treat input as two fields. 0 2 r/w 1: force auto calculation to treat input as one field. 0 0x0c4 1 - 0 r/w sub index for the above counters, providing byte wide data read/write from/to 0x0c1. 00: bits [7:0] of the counter pointed by the index 01: bits [15:8] of the counter pointed by the index 10: bits [23:16] of the counter pointed by the index 00 address bit r/w description reset 0x0c5 7 - 0 r/w data port for those counters mentioned in index 0x0c0. - address bit r/w description reset 7 r/w chip test usage only. data output selection for analog circuit test. 0: v data 1: c data 0 6 r/w when set, gray scale data replace the normal data output to panel. the content of index 61 is used as the first pixel data. 0 5 r/w if this bit is set to ?1?, the scaler output is forced to all 0?s. 0 4 r/w load chmax counter (for debugging). 0 3-2 r/w gray scale data selection. 0 1 r/w start osd rom self test. 0 0x0c6 0 r/w start osd ram self test. 0 address bit r/w description reset 0x0c7 7 - 0 r bwymin address bit r/w description reset 0x0c8 7 - 0 r bwymax address bit r/w description reset 0x0c9 7 - 0 r bwfmin address bit r/w description reset 0x0ca 7 - 0 r bwfmax address bit r/w description reset 0x0cb 7 - 0 r bwbtilt
TW8811 ? tft flat panel controller preliminary techwell, inc. 67 rev c 02/07/2008 address bit r/w description reset 0x0cc 7 - 0 r bwwtilt address bit r/w description reset 0x0cd 7 - 0 address bit r/w description reset 0x0ce 7 - 0 wr test_mode this register is reserved for testing purpose. in normal operation, only 0 should be written into this register. 03h = digital video decoder & rgb mix direct input test this test mode allows digital data to be input from dtvd[23:0] pins to the input of t he digital logic of the video decoder (replaces ycadc output) as the case when the contents of this register is 04h. besides this, the fpg1/fpb1/fpr1 pins become inputs and provide data in place of rgbadc data output. 04h = digital video decoder direct input test this test mode allows digital data to be input from dtvd pins to the input of the digital logi c of the video decoder. (replaces adc output) dtvd(23-16) > ?y? decoder input data, dtvd(15-8) > ?u? decoder input data dtvd(7-0) > ?v? decoder input data 05h = closed caption test mode. 06h = ycadc test mode (dtvd pins become output s) ycadc digital output is made available externally. ?y? adc output data > dtvd(15-8), ?c? & ?fb? adc output data > dtvd(7-0) index-63-bit-7 = 1 > ?c? data index-63-bit-7 = 0 > ?fb? data. 07h = digital video decoder output test (dtvd pins become outputs) the output of the digital video decoder output is available externally. ?r? decoder out data > dtvd(23-16), ?g ? decoder out data > dtvd(15-8) ?b? decoder out data > dtvd(7-0) ?vsync? > clamp ?hsync? > gpio[1] ?hactive? > gpio[0] 08h = rgbadc test mode (dtvd pins become outputs) rgbadc digital output is made available externally. ?g? adc output data > dtvd(15-8), ?b? & ?r? adc output data > dtvd(7-0) index-63-bit-7 = 1 > ?b? data index-63-bit-7 = 0 > ?r? data. 09h = dac test mode. dtvd[7:0] inputs are routed to the dac data input ?din?. 11h = tw88 internal node to flat panel output address bit r/w description reset 0x0cf 7-0 r/w reserved 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 68 rev c 02/07/2008 0x100 to 0x12f ? osd1 address bit r/w description reset 7 - 6 -- reserved. 0 5 - 4 r/w osd window0 horizontal zoom up control 00: x1, 01: x2, 10: x3, 11: x4 01 3 - 2 -- reserved 0 0x100 1 - 0 r/w osd window0 vertical zoom up control 00: x1, 01: x2, 10: x3, 11: x4 01 address bit r/w description reset 7 - 4 r/w osd window blinking background color 0000 0x101 3 - 0 r/w osd window auto fill color 0000 address bit r/w description reset 7 - 5 -- reserved. 000 4 r/w bitmap color write assign mode2 0: 1pixel/8bits, 1: 1pixel/4bits (4bits color max) 0 3 - 2 r/w bitmap color write assign mode3 (0x102 bit[1:0]=2?b11, 8-bit mode case) 00: 1pixel/8bits, 01: 1pixel/4bits, 10: 1pixel/2bit, 11: 1pixel/1bit 00 0x102 1 - 0 r/w bitmap color write assign mode1 00: 1pixel/4bits, 01: 1pixel/2bits, 10: 1pixel/1bit, 11: 1pixel/8bit (8-bit mode selection) 00 address bit r/w description reset 7 - 5 -- reserved. 000 4 r/w block fill mode enable/disable control (1: enable) 0 3 - 1 -- reserved. 000 0x103 1 r/w block transfer mode enable/disable control (1: enable) 0 address bit r/w description reset 7 - 1 -- reserved. 000 0000 0x104 0 r/w block fill/transfer mode start (1: start, 0: auto clear) 0 address bit r/w description reset 7 - 5 -- reserved. 000 4 r/w bitmap data write enable 0 3 - 1 -- reserved. 000 0x105 0 r/w source bitmap data write enable 0 address bit r/w description reset 0x106 7 - 0 r/w bitmapped window0 start address (7 ? 0) 0000 0000 address bit r/w description reset 0x107 7 - 0 r/w bitmapped window0 start address (15 ? 8) 0000 0000 address bit r/w description reset 7 - 5 -- reserved. 000 0x108 4 - 0 r/w bitmapped window0 start address (20 ? 16) 0 1010 address bit r/w description reset 0x109 7 - 0 r/w bitmap window0 v- start locati on (lower 8 bits) : 1 scanline per step 0001 0100 address bit r/w description reset 0x10a 7 - 0 r/w bitmap window0 h ? start location (1 pixel per step) 0010 0000 address bit r/w description reset 7 - 4 r/w bitmap window0 v- start location (upper 4 bits) 0000 0x10b 3 - 0 r/w bitmap window0 h- start location (upper 4 bits) 0011 address bit r/w description reset 0x10c 7 - 0 r/w bitmap window0 v ? length (1 line per step) 1000 0000
TW8811 ? tft flat panel controller preliminary techwell, inc. 69 rev c 02/07/2008 address bit r/w description reset 0x10d 7 - 0 r/w bitmap window0 h - length (1 pixel per step) 1000 0000 address bit r/w description reset 7 - 4 r/w bitmap window0 v - length (upper 4 bits) 0000 0x10e 3 - 0 r/w bitmap window0 h - length (upper 4 bits) 0000 address bit r/w description reset 0x10f 7 - 0 r/w source window v - start locat ion (lower 8 bits) : 1 scanline per step 0000 0000 address bit r/w description reset 0x110 7 - 0 r/w source window h - start location (1 pixel per step) 0000 0000 address bit r/w description reset 7 - 4 r/w source window v - start location (upper 4 bits) 0000 0x111 3 - 0 r/w source window h - start location (upper 4 bits) 0000 address bit r/w description reset 0x112 7 - 0 r/w source/destination window v- length (lower 8 bits) : 1 scanline per step 0000 0000 address bit r/w description reset 0x113 7 - 0 r/w source/destination window h ? length (1 pixel per step) 0000 0000 address bit r/w description reset 7 - 4 r/w source/destination window v- length (upper 4 bits) 0000 0x114 3 - 0 r/w source/destination window h- length (upper 4 bits) 0000 address bit r/w description reset 0x115 7 - 0 r/w destination window v- start locat ion (lower 8 bits) : 1 scanline per step 0000 0000 address bit r/w description reset 0x116 7 - 0 r/w destination window h ? start location (1 pixel per step) 0000 0000 \address bit r/w description reset 7 - 4 r/w destination window v- start location (upper 4 bits) 0000 0x117 3 - 0 r/w destination window h- start location (upper 4 bits) 0000 address bit r/w description reset 0x118 7 - 0 r/w write data from host interface to osd the internal write enable signal is generated automatically when 0x118 is accessed. 0000 0000 address bit r/w description reset 7 - 1 -- reserved. 000 0000 0x119 0 r/w bitamp osd window0 enable/disable (1: enable) 0 address bit r/w description reset 0x11a 7 - 0 r/w special color look-up table selection address[7:0] 0000 0000 address bit r/w description reset 7 r/w special color look-up table operation on/off 1: on , 0: off 0 6 r/w special color look-up table select 0 5 - 4 r/w color look-up table data select 00: r 01: g 10: b 11: color attribute data 00 0x11b 3 - 0 r/w color look-up table select 0000: table0 ~ 1111: table15 0000 address bit r/w description reset 0x11c 7 - 0 r/w color look-up table write data when 0x11b[5:4] attr. = 11, bit[5] : blink, bit[4:0] : alpha blending 0 ~10000(maximum) 0000 0000
TW8811 ? tft flat panel controller preliminary techwell, inc. 70 rev c 02/07/2008 address bit r/w description reset 7 r/w look-up table write window selection. (0x 11a, 0x11b, 0x11c : control by this bit) 0: window 0 1: window 1 0 6 - 5 -- reserved. 00 4 r/w color look-up table conversion enable 0: disable, 1: enable 0 3 -- reserved. 0 0x11d 2 - 0 r/w color look-up table conversion selection for 4 bit display, 000: conversion[1:0] 001: conversion[3:2] 010: conversion[5:4] 011: conversion[7:6] 100: conversion[9:8] 101: conversion[b:a] 110: conversion[d:c] 111: conversion[f:e] for 8 bit display, 000 : table0 ~ 111 : table 7 000 address bit r/w description reset 0x11e 7 - 0 r/w color look-up table conversion value write. 0001 0000 address bit r/w description reset 7 - 3 -- reserved. 0 0000 2 r for every end of active window, this signal is toggled. - 1 r for every end of bitmap window active, this signal is toggled. - 0x11f 0 r for every end of teletext window active, this signal is toggled. - address bit r/w description reset 7 - 6 -- reserved. 00 5 r/w window 1, 8-bit mode case : 16 color table or 256 color table selection 0 4 r/w window 0, 8-bit mode case : 16 color table or 256 color table selection 0 3 r/w color 8-bit table write window selection 0: window 0 1: window 1 0 2 r/w color 8-bit table write enable/disable 0: disable 1: enable 0 0x120 1 - 0 r/w color 8-bit table write select 00: all table 01: r table 10: g table 11: b talbe 00 address bit r/w description reset 0x121 7 - 0 r/w color 8-bit table write address[7:0] 0000 0000 address bit r/w description reset 0x122 7 - 0 r/w color 8-bit table write data[7:0] 0000 0000 address bit r/w description reset 7 - 5 -- reserved. 000 4 r/w rlc packet enable 0: disable 1: enable 0 3 - 2 -- reserved. 00 1 r/w rlc reset 0: normal 1: reset 0 0x123 0 r/w rlc bypass mode 0: disable 1: bypass enable 1 address bit r/w description reset 7 - 4 r/w data count bit 0000 0x124 3 - 0 r/w counter count bit 0000 address bit r/w description reset 7 -1 -- reserved. 000 0000 0x125 0 r/w bitamp osd window1 enable/disable (1: enable) 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 71 rev c 02/07/2008 address bit r/w description reset 7 - 6 -- reserved. 0 5 - 4 r/w osd window1 horizontal zoom up control 00: x1, 01: x2, 10: x3, 11: x4 01 3 - 2 -- reserved 0 0x126 1 - 0 r/w osd window1 vertical zoom up control 00: x1, 01: x2, 10: x3, 11: x4 01 address bit r/w description reset 0x127 7 - 0 r/w bitmapped window1 start address (7 ? 0) 0000 0000 address bit r/w description reset 0x128 7 - 0 r/w bitmapped window1 start address (15 ? 8) 0000 0000 address bit r/w description reset 7 - 5 -- reserved. 000 0x129 4 - 0 r/w bitmapped window1 start address (20 ? 16) 0 1010 address bit r/w description reset 0x12a 7 - 0 r/w bitmap window1 v- start locati on (lower 8 bits) : 1 scanline per step 0000 0000 address bit r/w description reset 0x12b 7 - 0 r/w bitmap window1 h ? start location (1 pixel per step) 0000 0000 address bit r/w description reset 7 - 4 r/w bitmap window1 v- start location (upper 4 bits) 0000 0x12c 3 - 0 r/w bitmap window1 h- start location (upper 4 bits) 0000 address bit r/w description reset 0x12d 7 - 0 r/w bitmap window1 v ? length (1 line per step) 0000 0000 address bit r/w description reset 0x12e 7 - 0 r/w bitmap window1 h - length (1 pixel per step) 0000 0000 address bit r/w description reset 7 - 4 r/w bitmap window1 v - length (upper 4 bits) 0000 0x12f 3 - 0 r/w bitmap window1 h - length (upper 4 bits) 0000 address bit r/w description reset 7 - 4 r/w bitmap window0 h zoom fraction control 0000 0x130 3 - 0 r/w bitmap window0 v zoom fraction control 0000 address bit r/w description reset 7 - 4 r/w bitmap window1 h zoom fraction control 0000 0x131 3 - 0 r/w bitmap window1 v zoom fraction control 0000 address bit r/w description reset 7-4 r/w reserved 0000 0x132 3-0 r/w select osd logic color table 0~0x0f 0000 address bit r/w description reset 0x133 7-0 r/w data for logic operation, it can be one of color look up table number. 00h address bit r/w description reset 7 r/w enable logical operation table 15 0 6 r/w enable logical operation table 14 0 5 r/w enable logical operation table 13 0 4 r/w enable logical operation table 12 0 3 r/w enable logical operation table 11 0 2 r/w enable logical operation table 10 0 1 r/w enable logical operation table 9 0 0x134 0 r/w enable logical operation table 8 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 72 rev c 02/07/2008 address bit r/w description reset 7 r/w enable logical operation table 7 0 6 r/w enable logical operation table 6 0 5 r/w enable logical operation table 5 0 4 r/w enable logical operation table 4 0 3 r/w enable logical operation table 3 0 2 r/w enable logical operation table 2 0 1 r/w enable logical operation table 1 0 0x135 0 r/w enable logical operation table 0 0 address bit r/w description reset 7 -5 r/w reserved 0000 4 r/w double width control during block transfer. 1: enable 0 3-1 r/w reserved 000 0x136 0 r/w double height control during block transfer. 1: enable 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 73 rev c 02/07/2008 0x138 ? ccfl/led control i bit function r/w description reset 7 oven r/w over voltage feedback control 0 = disable 1 = enable 1 6 oien r/w over current feedback control 0 = disable 1 = enable 1 5 uien r/w under current feedback control 0 = disable 1 = enable 1 4 fben r/w ccfl feedback loop control 0 = open loop 1 = close loop 1 3 lockv r/w 0 = dimming frequency set by fdim 1 = dimming frequency locked to panel vertical sync. 0 2 lockh r/w 0 = pwm frequency set by fpwm 1 = pwm frequency locked to panel horizontal frequency 0 1 ccflenb r/w 0 = analog sense power down 1 = analog sense power up. 1 0 ccflden r/w 0 = ccfl out disable. 1 = ccfl out enable. 0 0x139 ? ccfl/led sense threshold bit function r/w description reset 7-6 lvt r/w lamp voltage threshold 2h 5-4 lilt r/w lamp low current threshold 2h 3-0 lit r/w lamp normal current threshold dh 0x13a ? ccfl/led control ii bit function r/w description reset 7-6 reserved r/w 00 5-4 cc_led_st r/w ccfl or ledc status - 3-0 lstp r/w feedback gain control with 1 being the smallest gain. 4h 0x13b ? ccfl/led pwm bit function r/w description reset 7-0 fpwm r/w pwm control frequency. in ccfl mode, freq = 6.75mhz / fpwm. in led mode, freq = 27mhz / fpwm and fpwm[7:6] should be 0. 80h 0x13c ? ccfl/led dim frequency bit function r/w description reset 7-0 fdim r/w dimming frequency control. freq = 13.18khz / fdim 84h 0x13d ? ccfl/led dim control bit function r/w description reset 7 led_dig_en r/w 0 = ledc disable, 1 = ledc enable 0 4-0 ddim r/w dimming control. 0=full brightness, 1f=lowest brightness 00h 0x13e ? pwmtop bit function r/w description reset 7-0 pwmtop r/w reserved 20h
TW8811 ? tft flat panel controller preliminary techwell, inc. 74 rev c 02/07/2008 0x151 to 0x15f ? external osd & misc. address bit r/w description reset 7 - 5 -- reserved. 000 4 r/w osd wait mask signal 0: mask enable, 1: mask disable 1 3 - 2 -- reserved. 00 1 r osd wait signal (active high) - 0x151 0 -- reserved. 0 address bit r/w description reset 7 r/w external osd clock mode 0: free-run, 1: triggered osd_clk 1 6 r/w external osd vs polarity control 0 5 r/w external osd horizontal active polarity control 0 4 r/w external osd clock polarity control 0 3 - 1 r/w external osd access latency control 000 0x152 0 r/w external osd port enable/disable 0: disable, 1: enable 0 address bit r/w description reset 7 - 2 -- reserved. 00 0000 1 r/w external osd horizontal active signal mode selection 0: fontmap window type, 1: internal h-active window type 0 0x153 0 r/w external osd sync mode selection 0: hactive style, 1: hsync, vsync style 0 address bit r/w description reset 7 -- reserved. 0 6 - 4 r/w external osd clock eocl k delay time selection. 000: no delay time inserted. each increment increases the delay by 1 ns. 000 3 -- reserved. 0 0x154 2 - 0 r/w bitmap window osd gain value control gain[2:0] osd value 0 1.000 1 0.953 2 0.906 3 0.859 4 0.797 5 0.750 6 0.703 7 0.656 000 address bit r/w description reset 0x155 7 - 0 r/w osd test mode 0000 0000 address bit r/w description reset 7 r/w reserved. 0 6 -- reserved. 0 5 -4 r/w sub path osd selection 00: no osd, 01: bitmap0 & ext, 10: bitmap1, 11: all osd 00 3 -- reserved. 0 2 -- reserved. 0 0x156 1 - 0 r/w main path osd selection 00: no osd, 01: bitmap0 & ext, 10: bitmap1, 11: all osd 00 address bit r/w description reset 7 - 5 -- reserved. 000 0x157 4 - 0 r/w external osd alpha-blending level control.
TW8811 ? tft flat panel controller preliminary techwell, inc. 75 rev c 02/07/2008 address bit r/w description reset 7 - 5 -- reserved. 000 4 r/w dma interface wait mask signal 0: mask enable, 1: mask disable 0 3 - 1 -- reserved. 000 0x158 0 r dma interface wait signal 0 address bit r/w description reset 7 r/w analog external osd input enable 0 6:4 r/w external osd input data enable signal delay : 0 ~ 7 clock cycle delay 000 3 r/w analog external osd vsync polarity inversion 0 2 r/w analog external osd hsync polarity inversion 0 1 r/w * 0 0x159 0 r rlc wait signal (active high) -
TW8811 ? tft flat panel controller preliminary techwell, inc. 76 rev c 02/07/2008 host parallel interface / dma configuration registers 0x1a0 ? mode setting register bit function r/w description reset 7-2 r/w reserved --- 1 wait r/w generation wait signal 0 : wait signal doesn?t working (always off) 1 : wait signal working depend on status 1 0 dma_sel r/w select data transfer type 0 : host parallel path 1 : dma 0 0x1a1? total transfer count high byte register bit function r/w description reset 7-0 xfer_cnt r/w it is indicate that how many bytes dat a transfer base on four bytes unit either read or write to/from chip per command. it?s support up to 64kbbytes a command so bit[15:8]. 00h 0x1a2? total transfer count low byte register bit function r/w description reset 7-0 xfer_cnt r/w it is indicate that how many bytes dat a transfer base on four bytes unit either read or write to/from chip per command. this is bit 7-0. the data transfer must be multiple of four. (ex) 4bytes = 04h, 8bytes = 08h 00h 0x1a3 ? memory access address high byte register bit function r/w description reset 7-5 r/w reserved --- 4-0 mem_adr r/w memory access address include in row and column address. bit[20-16] 00h 0x1a4 ? memory access address medium byte register bit function r/w description reset 7-0 mem_adr r/w memory access address include in row and column address. bit[15-8] 00h 0x1a5? memory access address low byte register bit function r/w description reset 7-0 mem_adr r/w memory access address include in row and column address. bit[7-0] 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 77 rev c 02/07/2008 0x1a6? data access (read/write) register bit function r/w description reset 7-0 data_ch r/w data access channel from /to memory to/from microprocessor. 00h 0x1a7 ? command register bit function r/w description reset 7-1 r/w reserved --- 0 rd_wr r/w data transfer direction command bit 0 : read command (data flow : mcu data read from memory) 1 : write command (data flow : mcu data write to memory) *** it?ll be write access later than other register setting because of immediately start operation after access this bit. 0 0x1a8? status read register bit function r/w description reset 7-3 reserved --- 2 rd_mon r read (microprocessor from memory) operation done 0 : still operation 1 : read data transfer done 0 1 wr_mon r write (microprocessor to memory) operation done 0 : still operation 1 : write data transfer done 0 0 wait_mon r wait status monitoring bit 0 : no wait 1 : wait 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 78 rev c 02/07/2008 0x1b0 to 0x1bf ? status and interrupt registers address bit r/w name description reset 7 r line buffer over flow this bit is set if t he fp clock count exceeds the maximum number in between two consecutive fphs pulse s for the even field, cleared by writing back a "1". 0 6 r line buffer under flow this bit is set if the fp clock count exceeds the maximum number in between two consecutive fphs pulse s for the odd field, cleared by writing back a "1". 0 5 r input vsync loss status changed this bit is set when the status bit of "input vsync loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 4 r input hsync loss status changed this bit is set when the status bit of "input hsync loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 3 r/w video input status changed indication vdloss status bit change (register 1 bit 7) or det50 status bit change (register 1 bit 0) write a one to this bit to reset. 0 2 r input vsync loss this bit is set when the input vsync pulse is lost, reset by re- appearance of vsync. an 11-bit counter is used for vsync period measurement. if this counter overflows 4 times, the vsync is considered to be lost. 0 1 r input hsync loss this bit is set when the input hsync pulse is lost, reset by re-appearance of hsync. an 11-bit counter is used for hsync period measurement. if this counter overflows 4 times, the hsync is considered to be lost. 0 0x1b0 0 r sync detect status logic function of: inverted ?bit 1? anding with inverted ?bit 2? address bit r/w name description reset 7 r input measurement data ready this bit is set when the measurement data is ready for readout, reset when a new "startm" is set. 0 6 r power state changed this bit is set when the power management state has changed, reset by writing back a "1". 0 5 r input vsync period change detected this bit is set when the input vsync period is changed, reset when "endet" is cleared. when "endet" bit is set, the vsync period is measured for every frame. if the difference from the last measurement result stored in the registers, is larger than the error tolerance, the vsync period is considered to have changed. 0 4 r input hsync period change detected this bit is set when the input hsync period is changed, reset when "endet" is cleared. when "endet" bi t is set, the hsync period is measured for every scan line. if the difference from the last measurement result stored in the registers, is larger than the error tolerance, the hsync period is considered to have changed. 0 3 r line buffer overflow or underflow 0 2 r vdccdet high if there is a change in vdloss or det50 or ccvalid 0 1 r vloss/ hloss status changed this bit reflects the ?or? condition of status bit index b0 bit 5 (vloss status changed) and index b0 bit 4 (hloss status changed). 0 0x1b1 0 r "sync detect status" changed this bit is set when the status bit of "sync detect status" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 address bit r/w description reset 7 r/w enable/disable 0x1b1 bit 7 as an irq source 0: enable 1: disable 1 6 r/w enable/disable 0x1b1 bit 6 as an irq source 0: enable 1: disable 1 0x1b2 5 r/w enable/disable 0x1b1 bit 5 as an irq source 0: enable 1: disable 1
TW8811 ? tft flat panel controller preliminary techwell, inc. 79 rev c 02/07/2008 address bit r/w name description reset 4 r/w enable/disable 0x1b1 bit 4 as an irq source 0: enable 1: disable 1 3 r/w enable/disable 0x1b1 bit 3 as an irq source 0: enable 1: disable 1 2 r/w enable/disable 0x1b1 bit 2 as an irq source 0: enable 1: disable 1 1 r/w enable/disable 0x1b1 bit 1 as an irq source 0: enable 1: disable 1 0 r/w enable/disable 0x1b1 bit 0 as an irq source 0: enable 1: disable 1 address bit r/w description reset 7 - 3 r/w * 00h 2 r/w enable/disable vdloss as an irq source 0: enable 1: disable 1 1 r/w reserved 1 0x1b3 0 r/w enable/disable det50 as an irq source 0: enable 1: disable 1 address bit r/w name description reset 7 r line buffer over flow same as 0x1b0[7] 0 6 r line buffer under flow same as 0x1b0[6] 0 5 r pip input vsync loss status changed this bit is set when the status bit of "input vsync loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 4 r pip input hsync loss status changed this bit is set when the status bit of "input hsync loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 3 r/w video input status changed indication same as 0x1b0[3] 0 2 r pip input vsync loss this bit is set when the input vsync pulse is lost, reset by re- appearance of vsync. an 11-bit counter is used for vsync period measurement. if this counter overflows 4 times, the vsync is considered to be lost. 0 1 r pip input hsync loss this bit is set when the input hsync pulse is lost, reset by re-appearance of hsync. an 11-bit counter is used for hsync period measurement. if this counter overflows 4 times, the hsync is considered to be lost. 0 0x1b4 0 r pip sync detect status logic function of: inverted ?bit 1? anding with inverted ?bit 2? address bit r/w name description reset 7 r input measurement data ready same as 0x1b1[7] 0 6 r power state changed same as 0x1b1[6] 0 5 r pip input vsync period change detected this bit is set when the input vsync period is changed, reset when "endet" is cleared. when "endet" bi t is set, the vsync period is measured for every frame. if the di fference from the last measurement result stored in the registers, is larger than the error tolerance, the vsync period is considered to have changed. 0 0x1b5 4 r pip input hsync period change detected this bit is set when the input hsync period is changed, reset when "endet" is cleared. when "endet" bi t is set, the hsync period is measured for every scan line. if the difference from the last measurement result stored in the registers, is larger than the error tolerance, the hsync period is considered to have changed. 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 80 rev c 02/07/2008 address bit r/w name description reset 3 r line buffer overflow or underflow same as 0x1b1[3] 0 2 r vdccdet same as 0x1b1[2] 0 1 r pip vloss/ hloss status changed this bit reflects the ?or? condition of status bit index b0 bit 5 (vloss status changed) and index b0 bit 4 (hloss status changed). 0 0 r pip "sync detect status" changed this bit is set when the status bit of "sync detect status" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 address bit r/w name description reset 7 r line buffer over flow same as 0x1b0[7] 0 6 r line buffer under flow same as 0x1b0[6] 0 5 r mpip input vsync loss status changed this bit is set when the status bit of "input vsync loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 4 r mpip input hsync loss status changed this bit is set when the status bit of "input hsync loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 3 r/w video input status changed indication same as 0x1b0[3] 0 2 r mpip input vsync loss this bit is set when the input vsync pulse is lost, reset by re- appearance of vsync. an 11-bit counter is used for vsync period measurement. if this counter overflows 4 times, the vsync is considered to be lost. 0 1 r mpip input hsync loss this bit is set when the input hsync pulse is lost, reset by re-appearance of hsync. an 11-bit counter is used for hsync period measurement. if this counter overflows 4 times, the hsync is considered to be lost. 0 0x1b6 0 r mpip sync detect status logic function of: inverted ?bit 1? anding with inverted ?bit 2? address bit r/w name description reset 7 r input measurement data ready this bit is set when the measurement data is ready for readout, reset when a new "startm" is set. 0 6 r power state changed same as 0x1b1[6] 0 5 r mpip input vsync period change detected this bit is set when the input vsync period is changed, reset when "endet" is cleared. when "endet" bi t is set, the vsync period is measured for every frame. if the di fference from the last measurement result stored in the registers, is larger than the error tolerance, the vsync period is considered to have changed. 0 4 r mpip input hsync period change detected this bit is set when the input hsync period is changed, reset when "endet" is cleared. when "endet" bi t is set, the hsync period is measured for every scan line. if the difference from the last measurement result stored in the registers, is larger than the error tolerance, the hsync period is considered to have changed. 0 3 r line buffer overflow or underflow same as 0x1b1[3] 0 2 r vdccdet same as 0x1b1[2] 0 1 r mpip vloss/ hloss status changed this bit reflects the ?or? condition of status bit index b0 bit 5 (vloss status changed) and index b0 bit 4 (hloss status changed). 0 0x1b7 0 r mpip "sync detect status" changed this bit is set when the status bit of "sync detect status" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 address bit r/w name description reset
TW8811 ? tft flat panel controller preliminary techwell, inc. 81 rev c 02/07/2008 address bit r/w name description reset 7-6 r/w measurement input selection 0,1: main, 2: pip, 3: mpip 00 5 r/w 0: enable 0x1b5[5] as an irq source 0 4 r/w 0: enable 0x1b5[4] as an irq source 0 3-2 r/w reserved 00 1 r/w 0: enable 0x1b5[1] as an irq source 0 0x1b8 0 r/w 0: enable 0x1b5[0] as an irq source 0 address bit r/w name description reset 7-6 r/w reserved 00 5 r/w 0: enable 0x1b7[5] as an irq source 0 4 r/w 0: enable 0x1b7[4] as an irq source 0 3-2 r/w reserved 00 1 r/w 0: enable 0x1b7[1] as an irq source 0 0x1b9 0 r/w 0: enable 0x1b7[0] as an irq source 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 82 rev c 02/07/2008 adc/llpll configuration registers 0x1c0 ? llpll input control register bit function r/w description reset 7-6 inp_sel r/w sog input selection. 0=sog0, 1=sog1, 2,3=na 0 5 cs_inv r/w csync detection input polarity, active low needed. 0 : no inversion 1 : inversion 0 4 cs_sel r/w pll input selection 0 : slicer or hs 1 : cs_pas 0 3 sog_sel r/w csync detection selection 0 : sog slicer 1 : hsync 0 2 hs_pol r/w pll input polarity 0 : inversion 1 : normal 0 1 reserved r/w 0 0 ck_sel r/w pll output clock selection 0 : select pll clock 1 : select oscillator clock 0 0x1c1 ? llpll input detection register bit function r/w description reset 7 vs_pol r detected vsync polarity, 0 = low active - 6 hs_pol r detected hsync polarity, 0 = low active - 5 vs_det r vsync detection - 4 hs_det r hsync detection - 3 cs_det r composite sync detection - 2-0 det_fmt r composite sync format detection 0 : 480i, 1 : 576i, 2 : 480p, 3 : 576p 4 : 1080i, 5 : 720p 6: 1080p 7: none of above -
TW8811 ? tft flat panel controller preliminary techwell, inc. 83 rev c 02/07/2008 0x1c2 ? llpll control register bit function r/w description reset 7-6 llc_post r/w pll post divider 0= 1 1= ? 2= ? 3= 1/8 0 5-4 llc_vco r/w vco range select (mhz) 00 = 5 ~ 27 01 = 10 ~ 54 10 = 20 ~ 108 11 = 40 ~ 216 0 3 reserved 2-0 llc_ipmp r/w charge pump currents (ua) 000 = 1.5 001 = 2.5 010 = 5 011 = 10 100 = 20 101 = 40 110 = 80 111 = 160 0 0x1c3 ? llpll divider high register bit function r/w description reset 7-4 reserved r/w reserved - 3-0 llc_ackn[11:8] r/w pll feedback divider. 3h 0x1c4 ? llpll divider low register bit function r/w description reset 7-0 llc_ackn[7:0] r/w pll feedback divider 5ah 0x1c5 ? llpll clock phase register bit function r/w description reset 7-5 reserved r/w reserved - 4-0 llc_pha r/w this 5bit value adjusts the samplin g phase in 32 steps across on pixel time. each step represents an 11.25 degree shift in sampling phase. 00h 0x1c6 ? llpll loop control register bit function r/w description reset 7 llc_acpl r/w pll loop control 0: closed loop 1: open loop 0 6-4 llc_apg r/w pll loop gain control 2h 3 reserved r/w reserved 0 2-0 llc_apz r/w pll filter control 0h
TW8811 ? tft flat panel controller preliminary techwell, inc. 84 rev c 02/07/2008 0x1c7 ? llpll vco control register bit function r/w description reset 3-0 llc_acki[11-8] r/w pll vco nominal frequency. reserved for internal use. 4h 0x1c8 ? llpll vco control register bit function r/w description reset 7-0 llc_acki[7-0] r/w pll_vco nominal frequency. reserved for internal use. 00h 0x1c9 ? llpll pre coast register bit function r/w description reset 7-0 pre_coast r/w sets the number of hsync peri ods that coast is active before vsync edge. 06h 0x1ca ? llpll post coast register bit function r/w description reset 7-0 post_coast r/w sets the number of hsync per iods that coast is active after vsync edge. 06h 0x1cb ? sog threshold register bit function r/w description reset 7 pusog r/w sog power down control, 0 ? power down 0 6 pupll r/w pll power down control, 0 - power down 0 5 coast_en r/w pll coast control, 1 - enable 1 4-0 sog_th[4:0] r/w sog slicer threshold this bits control the comparator threshold of the sog slicer at 10mv per every step. the setting value of 5??b00000 equals 330mv and the maximum setting value is 5?11111 which equals 10mv. 10h 0x1cc ? scaler sync selection register bit function r/w description reset 7-5 reserved r/w reserved 0 4 vsy_sel r/w active vsync select 0 : composite sync separation output 1 : vsync input pin 0 3-2 hsy_sel r/w active hsync select 00 - hsync pin 01 ? cs_pas 10 ? sync separator output 11 ? hso 0h 1 vsy_polc r/w vsync polarity control 0 ? no inversion 1 - inversion 0 0 hsy_polc r/w hsync polarity control 0 ? no inversion 1 - inversion 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 85 rev c 02/07/2008 0x1cd ? pll initialization register bit function r/w description reset 0 init r/w pll initialization, self-resetting 0 0x1ce ? rgb adc misc. register bit function r/w description reset 7 adc_clk_sel r/w rgb path clock selection 1: select xtall clock 0: select original line lock clock 0 6 r/w reserved 0 5 dtv r/w adc input mode selection 1: dtv 0: rgb 0 4 r/w reserved 0 3 pda r/w adc g-channel power down 1 : power down 0: normal operation 0 2 r/w reserved 0 1 inrefv r/w adc reference voltage select 1: internal reference disable 0: internal reference enable 0 0 inrefi r/w adc bias reference current select 1: bias current boost 0: bias current normal 0 0x1cf ? rgb adc misc2. register bit function r/w description reset 7:6 inp_sel_adc r/w adc data input pin select 3: select input #3 2: select input #2 1: select input #1 0: select input #0 00 5:0 save r/w pga/adc power save mode [5:3]=: pga bias current control : big ger value means smaller current setting [2:0] = adc bias current control : bigger value means smaller current setting 001001 0x1d0 ? clamp gain control register bit function r/w description reset 7-4 reserved r/w reserved - 3 reserved r/w reserved - 2 gainy[8] r/w y channel gain adjust bit[8] 0 1 gainc[8] r/w c channel gain adjust bit[8] 0 0 gainv[8] r/w v channel gain adjust bit[8] 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 86 rev c 02/07/2008 0x1d1 ? y channel gain adjust register bit function r/w description reset 7-0 gainy[7-0] r/w y channel gain adjust bit[7-0] f0h 0x1d2 ? c channel gain adjust register bit function r/w description reset 7-0 gainc[7-0] r/w c channel gain adjust bit[7-0] f0h 0x1d3 ? v channel gain adjust register bit function r/w description reset 7-0 gainv[7-0] r/w v channel gain adjust bit[7-0] f0h 0x1d4 ? clamp mode control register bit function r/w description reset 7 rgb_sel r/w rgb or ycv selection 0 : ycv mode 1 : rgb mode 0 6 reserved r/w reserved - 5 cl_edge r/w clamp reference edge 0 4 clky r/w clamping current control 1 0 3 clkc r/w clamping current control 2 0 2 cl_y_en r/w green / y channel clamp 0 : enable, 1 : disable 0 1 cl_c_en r/w blue / c channel clamp 0 : enable, 1 : disable 0 0 cl_v_en r/w red / v channel clamp 0 : enable, 1 : disable 0 0x1d5 ? clamp start position register bit function r/w description reset 7-0 cl_st r/w this register sets pr ogrammable clamping start position. it is start count value that after the trailing edge of the hsync signal. 00h 0x1d6 ? clamp stop position register bit function r/w description reset 7-0 cl_ed r/w this register sets programmable clamping stop position. clamping duration set between start and stop position. 10h 0x1d7 ? clamp master location register bit function r/w description reset 7-0 cl_loc r/w this bit sets the rgb(ycv) clamp position from the h sync edge. 70h
TW8811 ? tft flat panel controller preliminary techwell, inc. 87 rev c 02/07/2008 0x1d8 ? adc test register bit function r/w description reset 7 reserved 0 6-4 llc_dbg_se l r/w debugging register for internal use 00h 3 reserved 2 rgb_adc_ test r/w internal test only 0 1 cl_test_y r/w programmable green / y select 0: use default value (g:0x10, u/v:0x3c) 1: programmable value 0 0 cl_test_uv r/w programmable blue and red / u and v select 0: use default value (r/b:0x10, u/v:0x80) 1: programmable value 0 0x1d9 ? y clamp reference register bit function r/w description reset 7-0 cl_y_val r/w green/ y channel clamping reference level in programmable mode. 10h 0x1da ? c clamp reference register bit function r/w description reset 7-0 cl_c_val r/w blue and red/ u and v channel clamping reference level in programmable mode. 80h 0x1dc ? hsync width register bit function r/w description reset 7-6 r/w reserved 00 5-0 hswid r/w hsync widith. the unit of hwsid is one clock cycle. 00h 0x1dd ? r channel adc offset register bit function r/w description reset 7-0 offsetr r/w r channel adc offset value. 80h 0x1de ? g channel adc offset register bit function r/w description reset 7-0 offsetg r/w g channel adc offset value. 80h 0x1df ? b channel adc offset register bit function r/w description reset 7-0 offsetb r/w b channel adc offset value. 80h
TW8811 ? tft flat panel controller preliminary techwell, inc. 88 rev c 02/07/2008 0x1f0 to 0x1fe ? lcdc ? gamma address bit r/w description reset 7 r/w enable red gamma correction. 0 6 r/w enable green gamma correction. 0 5 r/w enable blue gamma correction. 0 4 r/w reserved. 0 3-2 r/w enable gamma table address auto increment for reading/writing gamma data port. 00: disable, 01: read only, 10: write only, 11: read/write 00 0x1f0 1 - 0 r/w gamma tables access selection: index address 0x1f1 to 0x1f2 are used for gamma table accesses. there are 3 sets of gamma table, one table for one color, sharing the same address port and data port. these 2 bits identifies which table is accessed. 00: rgb gamma table 01: red gamma table 10: green gamma table 11: blue gamma table 00 address bit r/w description reset 0x1f1 7-4 r/w gamma table address port. 0000 0000 address bit r/w description reset 7 - 2 r/w reserved 00 0000 0x1f2 1 - 0 r/w gamma table data port (upper bits) 00 address bit r/w description reset 0x1f3 7 - 0 r/w gamma table data port (lower bits) 0000 0000
TW8811 ? tft flat panel controller preliminary techwell, inc. 89 rev c 02/07/2008 flat panel display registers 0x20e to 0x20f ? input type registers address bit r/w description reset 7 reserve 6 reserve 5 reserve 4 reserve 3 reserve 2 reserve 1 reserve 0x20e 0 r/w dual_656 input enable; 1=enable, 0=disable 0 address bit r/w description reset 7:6 r/w sequentiall rgb alternative line data based on rgb input order 3 = g->b->r 2 = r->g->b 1 = b->r->g 0 = g->b->r 0 5:4 r/w sequentiall rgb input order 3 = r->g->b 2 = b->r->g 1 = g->b->r 0 = r->g->b 0 3:2 r/w sequentiall rgb input 8 bit selection out of [23:0] 3 = select 8 bit for [7:0] 2 = select 8 bit for [23:16] 1 = select 8 bit for [15:0] 0 = select 8 bit for [7:0] 0 1 r/w 0 = sequential rgb clock polarity disable 1 = sequential rgb clock polarity inversion 0 0x20f 0 r/w 0 = sequential rgb mode disable 1 sequential rgb mode enable 0 0x210 to 0x21f ? input and input related registers address bit r/w description reset 7 r/w this bit has dual function. it serves as odd field detection method selection or itu656 progressive/interlaced se lection. if bits 3:2 of index 0x214h does not choose itu656: odd field detection method for digital input port 0: use internal default method 1: use detection method defined by register 0x215 if bits 3:2 selects itu656, this bit sets the input to interlaced (0) or progressive(1). 0 6 r/w invert internal detected field signal 0 5 r/w field is determined by the leading or tr ailing edge of input vsync when using 0x215 for field determination. 1: trailing edge. 0 4 r/w enable csync (composite sync); input pin dtvhs is treated as a csync input. 0 3 r/w de polarity of the digital source. 0: active high 0 2 r/w hsync polarity of the digital source. 0: active high 0 1 r/w vsync polarity of the digital source. 0: active high 0 0x210 0 r/w invert digital input port dtvclk polarity, 0: rising edge 1: falling edge 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 90 rev c 02/07/2008 address bit r/w description reset 7 r/w epden 0 6 r/w pden_pol. 0 5 r/w select explicit de ( data enable also called ha for horizontal active); 0: ha is asserted in the input active region defined by registers 0x217 through 0x21d 1: ha is sourced by individual video source 0 4 r/w 0 = dtvde is used as the data enable (de). 1 = dtvde is used as hsync input 0 3 - reserved. 0 0x211 2 - 0 r/w input clock dtvclk delay time selection. 000: no delay time inserted. each increment increases the delay by 1 ns. 000 address bit r/w description reset 7 r/w enable field detection for digital input port when index 0x214 bit 1 & 0 is 2?b10. 0 6 r/w set this bit to ?1? if the dtvvs input is not a pulse but a ?field? signal. 0 5 r/w itu656 even field vsync delay. 1: delay the assertion to the falling edge of ?ha?. 0: no delay 0 4 r/w use filtered hsync to maintain constant input hsync period. 0 3 r/w set this bit to 1 in 8 bit 601 mode if the cr data arrives before cb data. 0 0x212 2 - 0 r/w data bus routing selection for digital input port for 24 bit ypbpr or 24 bit rgb dtvd[23:16] dtvd[15:8] dtvd[7:0] 000: pr/b y/r pb/g 001: pr/b pb/g y/r 010: pb/g y/r pr/b 011: pb/g pr/b y/r 100: y/r pb/g pr/b 101: y/r pr/b pb/g for 16 bit ypb/pr: follow the table above with y and pb. example: if y data is connected to dtvd[23:16] and pb/pr data is connected dtvd[7:0], the bus routing selection should be set to ?101?. if explicit de, inde0x214 bit [4], is set, the very first dtvde is assumed to have pb data. on the other hand if explicit de is reset, index 0x210 bit [3] is used to select the order of pb /pr. for 8 bit y/pb/pr: follow the table above with pr. example: if y/pb/pr data is connected to dtvd[ 15:8], the bus routing selection can be set to ?011? or ?101?. use the table below for the correct data order. explicit de index-0x210-bit-3 index 0x27a-bit-5 data order 1 x 0 pb-y-pr-y 1 x 1 pr-y-pb-y 0 0 0 pb-y-pr-y 0 0 1 pr-y-pb-y 0 1 0 y-pb-y-pr 0 1 1 y-pr-y-pb 100
TW8811 ? tft flat panel controller preliminary techwell, inc. 91 rev c 02/07/2008 address bit r/w description reset 7:1 r/w internal clock polarity control 000_0000 0x213 0 r/w rgb color space selection 1: rgb, 0: yuv 0 address bit r/w description reset 7 - 6 r/w coast is driven to ?enabled? state in the window defined below 00: coast enabled 1 hsync period before vsync and 7 hsync periods after vsync 01: coast enabled 2 hsync periods before vsync and 8 hsync periods after vsync 10: coast enabled 3 hsync periods before vsync and 9 hsync periods after vsync 11: coast enabled 4 hsync periods before vsync and10 hsync periods after vsync 00 5 r/w reserved. 0 4 r/w 1: choose 8 bit 601 input mode 0: choose 8bit 656 input mode 0 3 - 2 r/w input format selection; 00: 422 (16 bit itu601), 01: itu656 (8 bits) or itu601 (8 bit) ; determined by bit 4. 10: 444, 11: rgb 10 0x214 1 - 0 r/w input video source selection; 00: internal analog video decoder, 01: rgb 10: digital input 11: pip 00 address bit r/w description reset 7 - 4 r/w horizontal ending locations of internal odd field detection for digital input port 0101 3 -0 r/w horizontal starting locations of internal odd field detection for digital input port 0100 0x215 start pixel end pixel start pixel end pixel 0000 32 64 1000 512 1024 0001 64 128 1001 576 1152 0010 128 256 1010 640 1280 0011 192 384 1011 704 1408 0100 256 512 1100 768 1536 0101 320 640 1101 832 1664 0110 384 768 1110 896 1792 0111 448 896 1111 960 1920 address bit r/w description reset 0x216 7 - 0 r/w offset amount to re-construct vsync from csync input. the l to h transition of csync input provides the l to h transition of hsync. this r egister defines the amount of offset from this transition edge for generating vsync. 0010 0000 address bit r/w description reset 0x217 7 - 0 r/w input active window definition: ho rizontal starting pixel position - low byte. 0000 0000 address bit r/w description reset 0x218 7 - 0 r/w input active window definition: horizontal ending pixel position - low byte 1100 1111
TW8811 ? tft flat panel controller preliminary techwell, inc. 92 rev c 02/07/2008 address bit r/w description reset 7 - 4 r/w input active window definition: horizontal ending pixel position ? high (total 12 bits). this position is referenced to the rising edge of input hsync. 0010 3 r/w reserved. 0x219 2 - 0 r/w input active window definition: horizontal starting pixel position - high (total 11 bits) this position is referenced to the rising edge of input hsync. 000 *note: the value written in this register does not come into effect until a register write to index 0x217 or 0x218 is followed. address bit r/w description reset 0x21a 7-0 r/w input active window definition: odd field vertical line start position - low byte 0001 0011 address bit r/w description reset 0x21b 7-0 r/w input active window definition: even field vertical line start position - low byte 0001 0011 address bit r/w description reset 0x21c 7-0 r/w input active window definition: vertical length - low byte 0000 0000 address bit r/w description reset 7 r/w reserved. 0 6 - 4 r/w input active window definition: vertical length - high (total 11 bits)* the unit of this length is one input hsync. 011 3 - 2 r/w input active window definition: even field vertical line start posi tion - high (total 10 bits)*. this position is referenced to the rising edge of input vsync. 00 0x21d 1 - 0 r/w input active window definition: odd field vertical line start posi tion - high (total 10 bits)*. this position is referenced to the rising edge of vsync. 00 *note: when the explicit-de is not used (regi ster 0x211, bit 5), the input active window is defined by the above h-active and v -active registers. address bit r/w description reset 7 r/w line lock pll output clock polarity 0 6 r/w reserved 0 5 r/w gpio[1] input/output selection. 1: output (see 0x213 for data source). 0 : input 0 4 r/w gpio[0] input/output selection. 1: output (see 0x213 for data source). 0 : input 0 3 r/w set irq active low 0 2 r/w * 0 0x21e 1 - 0 r/w line lock pll output clock delay [1:0] 00 address bit r/w description reset 7 r/w invert gpio[1] output. 0 6 - 5 r/w output source selection gpio[1]. 00: data written to bit 4, 01: vdloss, 10: hlock, 11: bw_active 00 4 r/w read: shows the sampled input value of gpio[1] write: holds the data that can be output to gpio[1] 0 3 r/w invert gpio[0] output. 0 2 - 1 r/w output source selection gpio[0]. 00: data written to bit 0, 01: field, 10: hz50, 11:irq 000 0x21f 0 r/w read: shows the sampled input value from gpio[0] write: holds the data that can be output to gpio[0] 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 93 rev c 02/07/2008 0x220 to 0x22f ? input format measurement registers address bit r/w description reset 0x220 7:0 reserved address bit r/w description reset 0x221 7-0 r/w input measurement window definition: horizontal start - low byte 0010 0000 address bit r/w description reset 0x222 7-0 r/w input measurement window definition: horizontal stop - low byte 1111 1111 address bit r/w description reset 7-4 r/w input measurement window definition: horizontal stop - high three bits (total 12 bits) this horizontal stop position if referenced to the rising edge of input hsync and the unit is one input pixel. 0001 3 reserved 0 0x223 2-0 r/w input measurement window definition: horizontal start - high three bits (total 11 bits) this horizontal start position if referenced to the rising edge of input hsync and the unit is one input pixel. 000 address bit r/w description reset 0x224 7-0 r/w input measurement window definition: vertical start - low byte 0010 0000 address bit r/w description reset 0x225 7-0 r/w input measurement window definition: vertical stop - low byte 1111 1010 address bit r/w description reset 7 reserved 0 6-4 r/w input measurement window definition: vertical stop - high three bits (total 11 bits) this vertical stop position is referenced to the rising edge of input vsync and the unit is one input hsync. 000 3 reserved 0 0x226 2-0 r/w input measurement window definition: vertical start - high three bits (total 11 bits) this vertical start position is referenced to the rising edge of input vsync and the unit is one input hsync. 000 address bit r/w description reset 0x227 7-0 r result 0: data port 0 to read input measurement result (0x22b bits 7-4 specifies which result to read out) 0000 0000 address bit r/w description reset 0x228 7-0 r result 1: data port 1 to read input measurement result (0x22b bits 7-4 specifies which result to read out) 0000 0000 address bit r/w description reset 0x229 7-0 r result 2: data port 2 to read input measurement result (0x22b bits 7-4 specifies which result to read out) 0000 0000 address bit r/w description reset 0x22a 7-0 r result 3: data port 3 to read input measurement result (0x22b bits 7-4 specifies which result to read out) 0000 0000
TW8811 ? tft flat panel controller preliminary techwell, inc. 94 rev c 02/07/2008 address bit r/w description reset 7 - 4 r/w select which measurement result to read out from 0x227~0x22a 0000: phase measurement result - blue (use result 3-0 registers) 0001: phase measurement result - green (use result 3-0 registers) 0010: phase measurement result - red (use result 3-0 registers) 0011: minimum value (result2: r, result1: g, result 0:b) 0100: maximum value (result2: r, result1: g, result 0:b) 0101: vsync period (result3, 2) hsync period (result 1, 0) 0110: hsync rise to hsync fall interval (result 1, 0) and hsync rise to hactive fall interval (result 3, 2). 0111: vsync pulse width (result 1,0), ho rizontal pixel counter value at the leading edge of vsync (result 3, 2). 1000: min horizontal active st arting pixel (results 1 & 0) max horizontal active starting pixel (results 3 & 2) 1001: min horizontal active ending pixel (results 1 & 0) max horizontal active ending pixel (results 3 & 2) 1010: vertical active starting line recorded with a. the first horizontal active starting pixel (results 1 & 0) b. the first horizontal active ending pixel (results 3 & 2) 1011: vertical active ending line recorded with a. the last horizontal active starting pixel (results 1 & 0) b. the last horizontal active ending pixel (results 3 & 2) 1100: horizontal counter value when buffer read pointer starts to toggle. (results 1 & 0) 1101: luminance values. minimum luminance (result 0) maximum luminance (result 1) average luminance (result2) 1110: vsync period measured with 27 mhz clock (result 2, 1 & 0). 0000 3 - 2 r/w field select for input measurement 00: odd field only 01: even field only 1x: disregard field 00 1 r/w reserved. 0 0x22b 0 r/w startm start input measurement. this bit is se lf-cleared after the measurement is done. 0 address bit r/w description reset 7 r/w use 27mhz clock for input hsync period measurement. 0 6 - 4 r/w noise mask bits for each of the 3 lsb input signals. 000 3 - 1 r/w error tolerance before asserting "change detected" status 000: exact match 001: up to 4 counts 0 10: up to 8 counts 011: up to 16 counts 100: up to 32 counts 101: up to 64 counts 110: up to 128 counts 111: up to 256 counts. 000 0x22c 0 r/w endet enable input vsync, hsync period change/loss detection. when this bit is set, the internal circuitry will perform new measurements. the new results are compared against the results retained in the registers obtained by the most recent "startm" measurement. 0 address bit r/w description reset 7 - 4 r/w threshold value for input active region detection. each increment increases the threshold value by 16. 0011 3 r/w enable luminance measurement. 0 2 - 1 r/w noise filter selection for luminance measurement. 000 0x22d 0 r/w de measurement enable. 0 address bit r/w description reset 0x22f 7 - 0 *
TW8811 ? tft flat panel controller preliminary techwell, inc. 95 rev c 02/07/2008 0x230 to 0x23f ? scaling/zoom control address bit r/w description reset 0x230 7 ? 0 r/w horizontal (x-direction) scale up factor ? higher fraction byte (coarse adjustment) 65536 * (input horizontal active pixel number) / (flat panel horizontal active pixel number) example: vga 640x480 , panel resolution: 1024x768 65536 * 640 / 1024 = 40960 = 0a000h example: decoder 720x240, panel resolution: 1024x768 65536 * 720 / 1024 = 46080 = 0b400h 1011 0100 address bit r/w description reset 0x231 7 ? 0 r/w horizontal (x-direction) scale down factor - fraction byte 128 * (input horizontal active pixel number) / (flat panel horizontal active pixel number) example: decoder 720x240, panel resolution: 640x480 128 * 720 / 640 = 144 = 090h 1000 0000 address bit r/w description reset 0x232 7 ? 0 r/w vertical (y-direction) scale up factor ? higher fraction byte (coarse adjustment) 65536 * (input vertical active pixel number) / (flat panel vertical active pixel number) example: vga 640x480 , panel resolution: 1024x768 65536 * 480 / 768 = 40960 = 0a000h example: decoder 720x240, panel resolution: 1024x768 65536 * 240 / 768 = 20480 = 05000h 0101 0000 address bit r/w description reset 7 r/w enable panorama / water-glass scaling. 0 6 r/w 1: line doubling, 0: normal vertical scaling 0 5 r/w 1: pixel doubling, 0: normal horizontal scaling 0 4 r/w set zoom by-pass. when this bit is set, the horizontal and vertical scale up factors has no effects. 0 3 - 2 r/w integer portion of vertical (y-direction) scale fact or (total 18 bits). for vertical scale up, maximum value is 0x10000. for vertical y-dire ction scale down, the value should be larger than 0x100. vertical scale factor < 0x10000 : up scaling vertical scale factor = 0x10000 : no scaling vertical scale factor > 0x10000 : down scaling the max vertical down scaling factor that the scaler can handle is 0x20000. 00 1 r/w horizontal (x-direction) scale down factor ? high bit (total of 9 bits) 0 0x233 0 r/w horizontal (x-direction) scale up fact or ? integer portion bit (total 17 bits) 0 address bit r/w description reset 0x234 7 - 0 r/w horizontal (x-direction) scale up offset this offset is used to adjust the initial value for the x-direction scale up operation. 0000 0000 address bit r/w description reset 0x235 7 - 0 r/w vertical (y-direction) scal e up offset for odd field this offset is used to adjust the initial value for the y-direction scale up operation. 1000 0000 address bit r/w description reset 0x236 7 - 0 r/w horizontal non-display pixel number applied to both left and right sides. this is useful when displaying 4:3 image on wide screen 16:9 panel. example: a wide screen panel with 1024 horizontal pixels. if this register has a value of 100, the active horizontal display will be 824 pixels. each side is ?blacked? out by 100 pixels. this register also serves as the panorama horizontal width definition. 0000 0000 address bit r/w description reset 7 r/w line buffer srams? ce are always active. 0000 0000 6 - 2 r/w * 0000 0000 0x237 1 - 0 r/w high 2 bits of 0x246 register. 0000 0000 address bit r/w description reset 0x238 7 ? 0 r/w horizontal scale at the side of display in panorama scaling mode. 0000 0000 address bit r/w description reset 0x239 7 - 0 r/w horizontal (x-direction) scale up factor ? lower fraction byte (fine adjustment) 0000 0000
TW8811 ? tft flat panel controller preliminary techwell, inc. 96 rev c 02/07/2008 address bit r/w description reset 0x23a 7 - 0 r/w vertical (y-direction) scale up factor ? lower fraction byte (fine adjustment) 0000 0000 address bit r/w description reset 0x23b 7 - 0 r/w vertical (y-direction) scal e up offset for even field this offset is used to adjust the initial value for the y-direction scale up operation. 0000 0000 0x240 to 0x26f ? image adjustment address bit r/w description reset 7 r/w * 0 6 r/w there are 2 sets of registers for index 0x241 ~ 0x246. 0: select the 1 st set, r/g/b contrast and r brightness 1: select the 2 nd set, y/cb/cr contrast and y brightness 0 0x240 5 - 0 r/w hue adjustment for main path. these bits control the color hue. the range is +45 degrees to ?45 degrees in 1.4 degree increments. 0 degrees is the default (xx10 0000) 10 0000 address bit r/w description reset 0x241 7 - 0 r/w red (or y) contrast adjustment for main path 80h+ : higher contrast, 80h: neutral, 80h-: lower contrast 1000 0000 address bit r/w description reset 0x242 7 - 0 r/w green (or cb) contrast adjustment for main path 80h+ : higher contrast, 80h: neutral, 80h-: lower contrast 1000 0000 address bit r/w description reset 0x243 7 - 0 r/w blue (or cr) contrast adjustment for main path 80h+ : higher contrast, 80h: neutral, 80h-: lower contrast 1000 0000 address bit r/w description reset 0x244 7 - 0 r/w red (or y) brightness adjustment for main path 80h+ : higher brightness, 80h: neutral, 80h-: lower brightness 1000 0000 address bit r/w description reset 0x245 7 - 0 r/w green brightness adjustment for main path 80h+ : higher brightness, 80h: neutral, 80h-: lower brightness 1000 0000 address bit r/w description reset 0x246 7 - 0 r/w blue brightness adjustment for main path 80h+ : higher brightness, 80h: neutral, 80h-: lower brightness 1000 0000 address bit r/w description reset 7 - 4 r/w coring function for sharpness control of main path. 0011 0x247 3 - 0 r/w sharpness adjustment for main path 1111 address bit r/w description reset 7 r/w main path sharpness frequency select. 0 = low freq. 1 = high freq. 0 6 r/w reserved. 000 5 - 4 r/w main path ynr. 000 3 r/w reserved. 000 0x248 2 - 0 r/w main path hflt. 000 address bit r/w description reset 7 r/w * 0 6 r/w there are 2 sets of registers for index 71 ~ 76. 0: select the 1 st set, r/g/b contrast and r brightness 1: select the 2 nd set, y/cb/cr contrast and y brightness 0 0x249 5 - 0 r/w hue adjustment for sub path. these bits contro l the color hue. the range is +45 degrees to ? 45 degrees in 1.4 degree increments. 0 degrees is the default (xx10 0000) 10 0000
TW8811 ? tft flat panel controller preliminary techwell, inc. 97 rev c 02/07/2008 address bit r/w description reset 0x24a 7 - 0 r/w red (or y) contrast adjustment for sub path 80h+ : higher contrast, 80h: neutral, 80h-: lower contrast 1000 0000 address bit r/w description reset 0x24b 7 - 0 r/w green (or cb) contrast adjustment for sub path 80h+ : higher contrast, 80h: neutral, 80h-: lower contrast 1000 0000 address bit r/w description reset 0x24c 7 - 0 r/w blue (or cr) contrast adjustment for sub pat h. 80h+ : higher contrast, 80h: neutral, 80h-: lower contrast 1000 0000 address bit r/w description reset 0x24d 7 - 0 r/w red (or y) brightness adjustment for sub path. 80h+ : higher brightness, 80h: neutral, 80h-: lower brightness 1000 0000 address bit r/w description reset 0x24e 7 - 0 r/w green brightness adjustment for sub path. 80h+ : higher brightness, 80h: neutral, 80h-: lower brightness 1000 0000 address bit r/w description reset 0x24f 7 - 0 r/w blue brightness adjustment for sub path 80h+ : higher brightness, 80h: neutral, 80h-: lower brightness 1000 0000 address bit r/w description reset 7 - 4 r/w coring function for sharpness control of sub path. 0011 0x250 3 - 0 r/w sharpness adjustment for sub path 1111 address bit r/w description reset 7 r/w sub path sharpness frequency select. 0 = low freq. 1 = high freq. 0 6 r/w reserved. 000 5 - 4 r/w sub path ynr. 000 3 r/w reserved. 000 0x251 2 - 0 r/w sub path hflt. 000 address bit r/w description reset 7 - 4 r/w edge enhancement parameter 0100 3 r/w disable edge enhancement. 0 0x252 2 - 0 r/w index for registers s haring the address space 0x25a 000 address bit r/w description reset 0x253 (252[2:0]=0) 7 - 0 r/w 2d edge enhancement register threshold #0 0011 0000 0x253 (252[2:0]=1) 7 - 0 r/w 2d edge enhancement register threshold #1 0011 0000 0x253 (252[2:0]=2) 7 - 0 r/w 2d edge enhancement register threshold #2 0011 0000 0x253 (252[2:0]=3) 7 - 0 r/w 2d edge enhancement register threshold #3 0000 0000 0x253 (252[2:0]=4) 7 - 0 r/w 2d edge enhancement register threshold #4 0000 0000 address bit r/w description reset 7 - 4 r/w reserved. 0000 0x254 3 - 0 r/w 0100
TW8811 ? tft flat panel controller preliminary techwell, inc. 98 rev c 02/07/2008 address bit r/w description reset 7 r/w test bw. should be 0 for normal operation. 0 6 r/w reserved 0 5 r/w black level selection. 0: 0 1: 16d 0 4 r/w white level selection. 0: 235d 1: 255d 1 3 r/w reserved 1 2 r/w reserved 1 1 r/w reserved. 00 0x255 0 r/w 1: bw stretch enable, 0: bw disable 0 address bit r/w description reset 0x256 7 - 0 r/w black/white stretch line start for det ection window, lower 8 bits ( total 10 bits). 0000 1000 address bit r/w description reset 0x257 7 - 0 r/w black/white stretch line end for det ection window, lower 8 bits ( total 10 bits). 1111 0110 address bit r/w description reset 7 - 4 r/w reserved. 0000 3 - 2 r/w black/white stretch line end for detection window, upper 2 bits. 10 0x258 1 - 0 r/w black/white stretch line startfor detection window, upper 2 bits. 00 address bit r/w description reset 0x259 7 - 0 r/w bwhdly, black/white stretc horizontal distance from start/end pixel of hactive. 0001 0000 address bit r/w description reset 7 - 6 r/w reserved 00 0x25a 5 - 0 r/w y min/max horizontal filter gain. 00 1011 address bit r/w description reset 0x25b 7 - 0 r/w tilt point for black stretch. 0110 0111 address bit r/w description reset 0x25c 7 - 0 r/w tilt point for white stretch. 1001 0100 address bit r/w description reset 0x25d 7 - 0 r/w black stretch limit 0010 1010 address bit r/w description reset 0x25e 7 - 0 r/w white stretch limit 1101 0000 address bit r/w description reset 0x25f 7 - 0 r/w see pip register explanation 1100 1010 address bit r/w description reset 7 r/w reserved. 0 0x260 6 - 0 r/w black/white stretch field recursive filter gain. 000 0010 address bit r/w description reset 7 r/w 1: mpip write height reduction enable, 0: no rmal operation (write and read height are same) 0 0x261 6 - 0 r/w mpip write height reduction amount 0000000 address bit r/w description reset 0x262 7 - 0 r/w reserved. 0001 1000 address bit r/w description reset 0x263 7 - 0 r/w color enhancement center color phase for color 1. the range for center color phase is ?180 ~ + 180 3dh address bit r/w description reset 0x264 7 - 0 r/w color enhancement center color phase for color 2. the range for center color phase is ?180 ~ + 180 c3h address bit r/w description reset 0x265 7 - 0 r/w color enhancement center color phase for color 3. the range for center color phase is ?180 ~ + 180 fch address bit r/w description reset 0x266 7 r/w 1: color enhancement enable, 0: disable 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 99 rev c 02/07/2008 address bit r/w description reset 7 r/w test bw. should be 0 for normal operation. 0 6 r/w reserved 0 5 r/w black level selection. 0: 0 1: 16d 0 4 r/w white level selection. 0: 235d 1: 255d 1 3 r/w reserved 1 2 r/w reserved 1 1 r/w reserved. 00 0x255 0 r/w 1: bw stretch enable, 0: bw disable 0 address bit r/w description reset 0x256 7 - 0 r/w black/white stretch line start for det ection window, lower 8 bits ( total 10 bits). 0000 1000 address bit r/w description reset 0x257 7 - 0 r/w black/white stretch line end for det ection window, lower 8 bits ( total 10 bits). 1111 0110 address bit r/w description reset 6 - 5 r/w color enhancement gain spread range for color 1 00 : no enhance 01 : -8 ~ +8 of center color phase 10 : -16 ~ +16 of center color phase 11 : -32 ~ + 32 of center color phase 00 4 - 0 r/w color enhancement gain for color 1. the minimum gain value is 00000 and maximum is 11111 from 0 to 0.484 with 31 step of 1/64. 0h address bit r/w description reset 7 r/w reserved 6 - 5 r/w color enhancement gain spread range for color 2 00 0x267 4 - 0 r/w color enhancement gain for color 2 0h address bit r/w description reset 7 r/w reserved 6 - 5 r/w color enhancement gain spread range for color 3 00 0x268 4 - 0 r/w color enhancement gain for color 3 0h
TW8811 ? tft flat panel controller preliminary techwell, inc. 100 rev c 02/07/2008 0x270 to 0x28f ? display control address bit r/w description reset 7 r/w set double pixel output to flat panel. 0: single pixel 0 6 r/w set fpde active high 0: active low 1 5 r/w set fphs active high 0: active low 0 4 r/w set fpvs active high 0: active low 0 3 r/w invert fpclk polarity 0: output signals to flat panel (fpvs, fphs , ? etc.) are referenced to the falling edge of fpclk. 0 2 r/w reverse the pixel order on panel data bus for dual pixel output. 0: first pixel is out on fpr0/fpg0/fpb0. 1: first pixel is out on fpr1/fpg1/fpb1 0 1 r/w reverse the bit order on panel data bus. 0: msb is on fpr0[7], fpr1[7], fpg0[7], fpg1[7], fpb0[7], and fpb1[7]. 1: msb is on fpr0[0], fpr1[0], fpg0[0], fpg1[0], fpb0[0], and fpb1[0]. 0 0x270 0 r/w set this bit to 1 making fpclk become inactive during vertical blanking time. 0 address bit r/w description reset 7 r/w tcon output. 1: set panel output pins to tcon interface signals. 00 6 r/w when this bit is set, the internal circuitr y uses the programmed value of index b6[3:0] and index b2[7:0] as the fphs period disregarding the setting of ?auto calculation?, bit 1 of index be. 0 5 r/w de mode selection. 1: fpvs and fphs are forced to inactive state. 0 4 r/w fp data outputs shift down 2 bits. when set, fpr0, fpr1, fpg0, fpg1, fpb0, fpb1 bus signals are shifted down by 2 bits. 0 3 r/w tri-state all the output signals to flat panel. 0 0x271 2 - 0 r/w panel clock fpclk delay time selection. 000: no delay time inserted. each increment increases the delay by 1 ns. 000 address bit r/w description reset 0x272 7 - 0 r/w fphs period - low byte 0011 1010 address bit r/w description reset 0x273 7 - 0 r/w fphs active pulse width this register is usually filled in with the mini mum fphs pulse width requirement from the flat panel specification 0001 0000 address bit r/w description reset 0x274 7 - 0 r/w flat panel horizontal back porch widt h --- the duration from the trailing edge of fphs to the leading edge of fpde. this register is usually filled in with the mi nimum horizontal back porch requirement from the flat panel specification. 00011011 address bit r/w description reset 0x275 7 - 0 r/w fpde horizontal active length 0000 0000
TW8811 ? tft flat panel controller preliminary techwell, inc. 101 rev c 02/07/2008 address bit r/w description reset 7 - 4 r/w fpde horizontal active lengt h ? high three bits (total 11 bits) this horizontal active length is equivalent to t he panel horizontal resolution. for example, the horizontal resolution of an xga panel is 1024. 100 0x276 3 - 0 r/w fphs period ? high three bits (total 12 bits) the following formula gives the correct number to fill in for fphs period. fphs_period = f _pllcki / ( f _ihsync * vsur) where f _pllcki is the frequency of pclk, f _ihsync is the frequency of input hsync, and vsur is the vertical scale up ratio. vsur = (panel vertical resolution) / (input vertical resolution) example: input is vga with hsync frequency 31.5khz with 60 hz refresh rate to be displayed on an xga panel. vsur = 768/480 = 1.6 choose f _pllcki = 69 mhz fphs_period = 69000000 / (31500 * 1.6) = 1369.05 ? 1369 = 559h 0101 note: the unit for index 0x272 through 0x276 is one panel pixel cloc k, which is either the output of internal pll or pclk. the fphs period should be larger than the sum of 1) fphs ac tive pulse width, 2) fphs back porch width, and 3) fpde horizontal active length. address bit r/w description reset 0x277 7 - 0 r/w fpvs period - low byte 0010 0110 address bit r/w description reset 0x278 7 - 0 r/w fpvs active pulse width the unit of this pulse width is one fphs. this register is usually filled in with the mini mum fpvs pulse width requirement from the flat panel specification. 0000 0110 address bit r/w description reset 0x279 7 - 0 r/w flat panel vertical back porch width the unit of this pulse width is one fphs. the following formula gives the correct number to fill in for fpvs back porch. fpvs_back_porch = (vas?vsync_pw+2)* vsur?fpvs_pulse_width where vas is the input vertical active starting line number, vsync_pw is the input vsync pulse width, vsur is the vertical scale up ratio. vsur = (panel vertical resolution) / (input vertical resolution) 0001 1111 address bit r/w description reset 0x27a 7 - 0 r/w flat panel vertical active length - low byte 0000 0000 address bit r/w description reset 7 r/w early start. start to output data earlier in non auto calculation mode. 0 6 - 4 r/w flat panel vertical active length - high three bits (total 11 bits) the unit of this active length is one fphs this vertical active length is equivalent to t he panel vertical resolution. for example, the vertical resolution of an xga panel is 768. 011 3 reserved 0 0x27b 2 - 0 r/w fpvs period ? high three bits (total 11 bits) the unit of this period is one fphs. 011 note: the unit for index 0x277 through 0x27b is one fphs, i.e. w henever there is an active fphs, the count is incremented by 1. the fpvs period should be larger than the sum of 1) fpvs active pulse width, 2) fpvs back porch width, and 3) flat panel vertical active length. note: the value written in this register does not come into effe ct until it is followed by a register write to index 0x277 or 0 x27a.
TW8811 ? tft flat panel controller preliminary techwell, inc. 102 rev c 02/07/2008 address bit r/w description reset 7 reserved 0 6 - 4 r/w dither option code "010" is recommended for 6:6:6 output 000 3 r/w reserved 0 0x27c 2 - 0 r/w dither output format selection "001" is recommended for 6:6:6 output 000 table 6 dither output selection and calculations dither output format selection flat panel rgb bit format output dither option code input lsbs used in dither calculation dither method dither output format selection flat panel rgb bit format output dither option code input lsbs used in dither calculation dither method 001 (5) (5) (5) 2x2 010 (5,4) (5,4) (5,4) 2x2 000 8:8:8 000 n/a none 011 (5,4,3) (5,4,3) (5,4,3) 2x2 001 (3) (3) (3) 2x2 100 4:4:4 100 (5,4,3,2) (5,4,3,2) (5,4,3,2) 4x4 010 (3,2) (3,2)(3,2) 2x2 001 (6) (6) (6) 2x2 011 (3,2,1) (3,2,1)(3,2,1) 2x2 010 (6,5) (6,5) (6,5) 2x2 001 6:6:6 100 (3,2,1,0) (3,2,1,0)(3,2,1,0) 4x4 011 (6,5,4) (6,5,4) (6,5,4) 2x2 001 (4) (3) (4) 2x2 101 3:3:3 100 (6,5,4,3) (6,5,4,3) (6,5,4,3) 4x4 010 (4,3) (3,2) (4,3) 2x2 001 (6) (6) (7) 2x2 011 (4,3,2) (3,2) (4,3,2) 2x2 010 (6,5) (6,5) (7,6) 2x2 010 5:6:5 100 4 ,3,2,1) (3,2,1) (4,3,2,1) 4x4 011 (6,5,4) (6,5,4) (6,5,4) 2x2 001 (4) (4) (4) 2x2 110 3:3:2 100 (6,5,4,3) (6,5,4,3) (7,6,5,4) 4x4 010 (4,3) (4,3) (4,3) 2x2 011 (4,3,2) (4,3,2) (4,3,2) 2x2 011 5:5:5 100 (4,3,2,1) (4,3,2,1) (4,3,2,1) 4x4 address bit r/w description reset 0x27d 7 - 0 r/w output vsync delay from input vsync 0000 1000 address bit r/w description reset 7 r/w force long. in auto calculation with th is bit set, the fphs period assumes the next higher integer value if the calculated fphs contains fractional part. 0 6 r/w force short. in auto calculation with is bit set, the fphs period assumes the integer part; i.e. the fractional part of the calculat ed fphs period is discarded. 0 5 r/w tri-state pwm pin. 0 4 r/w pwm polarity. 1: active low 0 3 r/w when set, the input ?hactive? or ?de? is forced to inactive if either vsync or hsync is active. 0 2 r/w force into free run mode. 0 1 r/w enable auto calculation. when this bit is se t, an internal circuitry calculates the optimum fphs period, and then adjusts the fphs period dynamically so that for one vsync (fpvs) period it has integer multiples of fphs. the internal circuitry also adjust the fphs active position to minimize the line buffer overflow/underflow. 0 0x27e 0 r/w when this bit is set, the input vsync is delayed by the amount specified by index 0x27d in the unit of input hsync. the regular meaning of index 0x27d -- ?output vsync delay from input vsync? is fixed at 2. 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 103 rev c 02/07/2008 address bit r/w description reset 7 - 6 r/w display single field on flat panel. 0x : function disabled. 10 : display odd field. 11 : display even field. 00 5 r/w when set the field signal is reversed in the auto calculation circuitry. 000 4 r/w select different vertical sync source in single field input. 000 3 r/w no even field initialization 0 0x27f 2 - 0 r/w even field delay. 001= +1, 010= +2, ? 101= +5, 110= -1, 111= -2 000 address bit r/w description reset 0x280 7 r/w bits 8 to 1 of 13 bi t counter ? 0x282(3-0), 0x280(7-0) address bit r/w description reset 0x281 7 r/w bits 8 to 1 of 13 bi t counter ? 0x282(7- 4), 0x281(7-0) address bit r/w description reset 7 - 4 r/w upper 4 bits (bits 13 to 9) of 13 bit counter ? 0x282(7-4), 0x281(7-0) for non-free-run mode, this specifies the upper 12-bits of the initial value of a 13-bit counter for the even field. for free-run with calibrate bit set, this specifies the value for the vertical line counter to load at the falling edge of input vsync. 0x282 3 - 0 r/w upper 4 bits (bits 13 to 9) of 13 bit counter ? 0x282(3-0), 0x280(7-0) for non-free-run mode, this specifies the upper 12-bits of the initial value of a 13-bit counter for the odd field. for free-run with calibrate bit set, this specifies the value for pixel counter to load at the falling edge of input vsync. 0 address bit r/w description reset 7 - 6 r/w even field vertical start point adjustment. 00 : even field start with the same line count specified in 0x27d as odd field. 01 : even field start with one extra line count specified in 0x27d. 10 : even field start with one less line count specified in 0x27d. 0 0x283 5 - 0 r/w number of lines to be black out from top and the bottom of the display. 00 0000 address bit r/w description reset 7 r/w pwm clock selection 0: 27 mhz (xtal27i input frequency) 1: 27/2 mhz 0 0x284 6 - 0 r/w positive pulse width of the pwm. if this register has an ?n? value, the positi ve pulse width duration is ?n+1? pwm clocks. 100 0000 address bit r/w description reset 0x285 7 ? 0 r/w reserved 0000 0000 address bit r/w description reset 0x286 7 ? 0 r/w reserved address bit r/w description reset 7 r/w 0: dual output selection lower 24 of 48 bits 1: dual output selection upper 24 of 48 bits 0 0x287 6 - 0 r/w reserved 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 104 rev c 02/07/2008 0x2a0 to 0x2af ? memory control address bit r/w description reset 7 r/w memory read phase control. 0 6-4 r/w this is for the control of clock phase of memory clock output. 0 3 r/w nomcst 0 2 r/w test enable for memory controller. 0 0x2a0 1-0 r/w memory configuration type. 10 address bit r/w description reset 0x2a1 7-0 r/w this is for the refresh request timing setting. t he values that written in registers uses to calculate the refresh request period. 07h address bit r/w description reset 0x2a2 7-0 r/w this is for the control of the ras max timing setting. 20h address bit r/w description reset 7-4 r/w ras pre-charge time for memory operation. 0010 0x2a3 3-0 r/w ras to cas delay time for memory operation. 0010 address bit r/w description reset 7 r/w this bit indicates bit21 of the address. 0 6-4 r/w * 0 0x2a4 3-0 r/w refresh back time for memory operation. 0111 address bit r/w description reset 7 r/w * 0 6-4 r/w data read time adjustor based on memory clock period. 100 0x2a5 3-0 r/w minimum time for mode register setting. 0011 address bit r/w description reset 7 r/w reserved. 0 6-4 r/w data delay 001 3 r/w reserved. 0 0x2a6 2-0 r/w cas latency timing for mode register setting. 011 address bit r/w description reset 7 r/w * 0 6 r/w * 0 5 r/w * 0 4 r/w * 0 3 r/w * 0 2 r/w * 0 0x2a7 1-0 r/w * 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 105 rev c 02/07/2008 0x2ae to 0x2c9 ? pip control address bit r/w description reset 7 r/w 1: pip down scaler offset enable (interlace i nput), 0: offset disabled (progressive input) 0 0x25f 6 - 0 r/w pip down scaler offset address bit r/w description reset 0x2ae 7 - 0 r/w pip horizontal position offset adjustment 20h address bit r/w description reset 0x2af 7 - 0 r/w pip vertical position offset adjustment 2ch address bit r/w description reset 0x2b0 7 - 0 r/w horizontal input cropping start[7:0]. these bits indicate the start point of the cropping window of the pip data which is going to be written into memory. 10h address bit r/w description reset 0x2b1 7 - 0 r/w horizontal input cropping window width[7:0]. these bits indicate the width of the cropping window of the pip data which is going to be written into memory. 60h address bit r/w description reset 7 r/w 1: down scaler pre-filter manual selection enable. 0: auto selection (default) 00 6 - 4 r/w horizontal input cropping window width[10:8]. these bits indicate the width of the cropping window of the pip data which is going to be written into memory. 010 3 ? 2 r/w down scaler pre-filter manual se lection. 0: no filter, 1: weak filter, 2: strong filter, 3: medium filter 00 0x2b2 1 - 0 r/w horizontal input cropping start[9:8]. these bits indicate the start point of the cropping window of the pip data which is going to be written into memory. 00 address bit r/w description reset 0x2b3 7 - 0 r/w vertical input cropping start[7:0]. these bits indi cate the start point of the cropping window of the pip data which is going to be written into memory. 02h address bit r/w description reset 0x2b4 7 - 0 r/w vertical input cropping window height[7:0]. these bits indicate the height of the cropping window of the pip data which is going to be written into memory. e0h address bit r/w description reset 7 r/w vertical input cropping start[8]. 0 6 - 4 r/w vertical input cropping window height[10:8]. 000 3 - 2 r/w even field offset for the cropping window. 00 0x2b5 1 - 0 r/w odd field offset for the cropping window. 00 address bit r/w description reset 0x2b6 7 - 0 r/w pip horizontal down scaling ratio [7:0]. 100h for no down scaling. 00h address bit r/w description reset 0x2b7 7 - 0 r/w pip vertical down scaling ratio [7:0]. 100h for no down scaling 00h address bit r/w description reset 7 - 4 r/w pip vertical down scaling ratio [11:8]. 0001 0x2b8 3 - 0 r/w pip horizontal down scaling ratio [11:8]. 0001 address bit r/w description reset 0x2b9 7 - 0 r/w pip window write buffer base address. it defines start address of pip memory area. 00h address bit r/w description reset 0x2ba 7 - 0 r/w pip window write width[7:0]. these bits indicate the width of the pip window written into the memory. 30h address bit r/w description reset 0x2bb 7 - 0 r/w pip window write height[7:0]. these bits indicate the height of the pip window written into the memory. 70h
TW8811 ? tft flat panel controller preliminary techwell, inc. 106 rev c 02/07/2008 address bit r/w description reset 7 r/w 1 : pip window write enable. when disabled read-out image will freeze. 0 6 r/w write data color phase control. 0 5 r/w reserved 0 4 r/w reserved 0 3 r/w pip window write height[8]. 0 0x2bc 2 - 0 r/w pip window write width[10:8]. these bits indicate the width of the pip window written into the memory. maximum width is 400h. 00 address bit r/w description reset 7 r/w 1 : pip window read enable. 0 6 r/w 1: pip write power down (image will freeze), 0: normal 0 5 r/w pip mode enable. 0 4 r/w 1: pip blending single field mode, 0: normal 0 3 r/w pip read buffer field polarity. 0 2 r/w 1: pixel doubling when up scaling, 0: normal. 0 1 r/w reserved. 0 0x2bd 0 r/w 1: force black, 0: normal. 0 address bit r/w description reset 0x2be 7 - 0 r/w pip horizontal up scaling ratio [7:0]. 800h for no up scaling. 00h address bit r/w description reset 0x2bf 7 - 0 r/w pip vertical up scaling ratio [7:0]. 800h for no up scaling. 00h address bit r/w description reset 7 - 4 r/w pip vertical up scaling ratio [11:8]. 1000 0x2c0 3 - 0 r/w pip horizontal up scaling ratio [11:8]. 1000 address bit r/w description reset 0x2c1 7 - 0 r/w pip window position base x start[7:0]. these bits indicate the origin of the pip window. 80h address bit r/w description reset 0x2c2 7 - 0 r/w pip window position base y start[7:0]. these bits indicate the origin of the pip window. 80h address bit r/w description reset 7 r/w 1: pip clock inverse, 0: normal. 0 6 ? 4 r/w pip window position base y start[10:8]. these bits indicate the origin of the pip window. 1h 0x2c3 3 - 0 r/w pip window position base x start[11:8]. these bits indicate the origin of the pip window. 2h address bit r/w description reset 7 ? 4 r/w pip window position base y start offset. these bits indicate the base position of the pip window. 2h 0x2c4 3 - 0 r/w pip window position base x start offset. these bits indicate the base position of the pip window. ch address bit r/w description reset 0x2c5 7 ? 0 r/w pip window width[7:0]. these bits indicate the display width of the pip window. 30h address bit r/w description reset 0x2c6 7 ? 0 r/w pip window height[7:0]. these bits indicate the display height of the pip window. e0h address bit r/w description reset 7 r/w pip window color phase control for 16 to 24 conversion. 0 6 ? 4 r/w pip window height[10:8]. these bits indicate the display height of the pip window. 0h 0x2c7 3 ? 0 r/w pip window width[11:8]. these bits indicate the display width of the pip window. 1h address bit r/w description reset 0x2c8 7 - 0 r/w mpip frame horizontal position offset adjustment 2ch address bit r/w description reset 0x2c9 7 - 0 r/w mpip frame vertical position offset adjustment 2eh
TW8811 ? tft flat panel controller preliminary techwell, inc. 107 rev c 02/07/2008 0x2ca to 0x2ec ? mpip control registers address bit r/w description reset 0x2ca 7 - 0 r/w horizontal input cropping start[7:0]. these bits indicate the start point of the cropping window of the mpip data which is going to be written into memory. 10h address bit r/w description reset 0x2cb 7 - 0 r/w horizontal input cropping window width[7:0]. these bits indicate the width of the cropping window of the mpip data which is going to be written into memory. 60h address bit r/w description reset 7 r/w 1: down scaler pre-filter manual selection enable. 0: auto selection (default) 00 6 - 4 r/w horizontal input cropping window width[10:8]. these bits indicate the width of the cropping window of the mpip data which is going to be written into memory. 010 3 ? 2 r/w down scaler pre-filter manual selection. 0: no filter, 1: weak filter , 2: strong filter, 3: medium filter 00 0x2cc 1 - 0 r/w horizontal input cropping start[9:8]. these bits indicate the start point of the cropping window of the mpip data which is going to be written into memory. 00 address bit r/w description reset 0x2cd 7 - 0 r/w vertical input cropping start[7:0]. these bits indi cate the start point of the cropping window of the mpip data which is going to be written into memory. 02h address bit r/w description reset 0x2ce 7 - 0 r/w vertical input cropping window height[7:0]. these bits indicate the height of the cropping window of the mpip data which is going to be written into memory. e0h address bit r/w description reset 7 r/w vertical input cropping start[8]. 0 6 - 4 r/w vertical input cropping window height[10:8]. 000 3 - 2 r/w even field offset for the cropping window. 00 0x2cf 1 - 0 r/w odd field offset for the cropping window. 00 address bit r/w description reset 0x2d0 7 - 0 r/w mpip horizontal down scaling ratio [7:0]. 100h for no down scaling. 00h address bit r/w description reset 0x2d1 7 - 0 r/w mpip vertical down down scaling ratio [7:0]. 100h for no down scaling. 00h address bit r/w description reset 7 - 4 r/w mpip vertical down down scaling ratio [11:8]. 0001 0x2d2 3 - 0 r/w mpip horizontal down down scaling ratio [11:8]. 0001 address bit r/w description reset 0x2d3 7 - 0 r/w mpip window write buffer base address. it defines start address of mpip memory area 00h address bit r/w description reset 0x2d4 7 - 0 r/w mpip window write width[7:0]. these bits indicate the width of the single mpip sub-window. 30h address bit r/w description reset 0x2d5 7 - 0 r/w mpip window write height[7:0]. these bits indica te the height of the single mpip sub-window. 70h address bit r/w description reset 7 r/w 1 : mpip window write enable. when disabled read-out image will freeze.. 0 6 r/w write data color phase control. 0 5 r/w reserved 0 4 r/w reserved 0 3 r/w mpip window write height[8]. 0 0x2d6 2 - 0 r/w mpip window write width[10:8]. these bits indicate the width of the mpip window written into the memory. maximum width is 400h. 00
TW8811 ? tft flat panel controller preliminary techwell, inc. 108 rev c 02/07/2008 address bit r/w description reset 7 r/w mpip window read enable. 0 6 r/w 1: mpip write power down (live window will freeze), 0: normal 0 5 r/w mpip mode enable. 0 4 r/w reserved. 0 3 r/w mpip read buffer field polarity. 0 2 r/w 1: pixel doubling when up scaling, 0: normal. 0 1 r/w reserved. 0 0x2d7 0 r/w 1: force black, 0: normal. 0 address bit r/w description reset 0x2d8 7 - 0 r/w mpip horizontal up scaling ratio [7:0]. 800h for no up scaling. should not be changed. 00h address bit r/w description reset 0x2d9 7 - 0 r/w mpip vertical up scaling ratio [7:0]. 8 00h for no up scaling. should not be changed. 00h address bit r/w description reset 7 - 4 r/w mpip vertical up scaling ratio [11:8]. should not be changed. 1000 0x2da 3 - 0 r/w mpip horizontal up scaling ratio [11:8]. should not be changed. 1000 address bit r/w description reset 0x2db 7 - 0 r/w mpip image position base x start[7:0]. these bits indicate the origin of the mpip window. 20h address bit r/w description reset 0x2dc 7 - 0 r/w mpip image position base y start[7:0]. these bits indicate the origin of the mpip window. 2ch address bit r/w description reset 0x2dd 7 - 0 r/w pip vertical scaling offset. 80h address bit r/w description reset 7 ? 4 r/w mpip window position base y start offset. these bits indicate the base position of the mpip window. 0h 0x2de 3 - 0 r/w mpip window position base x start offset. these bits indicate the base position of the mpip window. 0h address bit r/w description reset 0x2df 7 ? 0 r/w mpip window width[7:0]. these bits indicate the display width of the combined mpip windows. 00h address bit r/w description reset 0x2e0 7 ? 0 r/w mpip window height[7:0]. these bits indicate the display height of the combined mpip windows. 00h address bit r/w description reset 7 r/w 1: mpip clock inverse, 0: normal 0 6 ? 4 r/w mpip window height[10:8]. these bits indicate th e display height of the combined mpip windows. 0h 0x2e1 3 ? 0 r/w mpip window width[11:8]. these bits indicate the display width of the combined mpip windows. 0h address bit r/w description reset 7 r/w mpip window color phase control for 16 to 24 conversion. 0 6 - 1 r/w reserved 00h 0x2e2 0 r/w 1 : mpip image memory initialization enable. (color is defined by 0x2e5). after initialization, should be return to 0 for normal operation. 0 address bit r/w description reset 0x2e3 7 - 0 r/w mpip window origin x [7:0] 00h address bit r/w description reset 0x2e4 7 - 0 r/w mpip window origin y [7:0] 00h address bit r/w description reset 0x2e5 7 - 0 r/w mpip image memory initialization color 24h
TW8811 ? tft flat panel controller preliminary techwell, inc. 109 rev c 02/07/2008 address bit r/w description reset 7 r/w pip overlay key color position for test. 0 6-5 r/w reserved 00 0x2e6 4 - 0 r/w alpha2 of pip alpha blending (main dimming) 10h : full main ? 00h : black 10h address bit r/w description reset 7 r/w reserved 0 6 - 4 r/w pip/mpip horizontal border width (0 dot ? 7 dots) 0h 3 r/w mpip window origin y [8] 0 0x2e7 1 - 0 r/w mpip window origin x [9:8] 0h address bit r/w description reset 7 - 4 r/w mpip window vertical spacing [3:0] 0h 0x2e8 3 - 0 r/w mpip window horizontal spacing [3:0] 0h address bit r/w description reset 7 - 6 r/w mpip maximum window number y [1:0]. it?s value plus 1 defines the column number of window array. 0h 5 - 4 r/w mpip maximum window number x [1:0]. it?s value plus 1 defines the row number of window array. 0h 3 - 2 r/w mpip active window number y [1:0]. it?s value plus 1 defines the column number of the sub- window which receives write image. 0h 0x2e9 1 - 0 r/w mpip active window number x [1:0]. it?s value pl us 1 defines the row number of the sub-window which receives write image. 0h address bit r/w description reset 7 r/w reserved 0 6 - 4 r/w pip/mpip vertical border width [2:0] (0 line ? 7 lines) 0h 3 - 2 r/w mpip highlight window number y [1:0]. it?s value plus 1 defines the column number of the sub- window which has highlight frame color defined by 0x2ec. 0h 0x2ea 1 - 0 r/w mpip highlight window number x [1:0]. it?s value pl us 1 defines the row number of the sub-window which has highlight frame color defined by 0x2ec. 0h address bit r/w description reset 0x2eb 7 - 0 r/w pip/mpip standard window frame color 1ch address bit r/w description reset 0x2ec 7 - 0 r/w mpip highlight window frame color e0h address bit r/w description reset 7 r/w pip data sampling control 1: ignore de 1 0x2ee 6 r/w pip data cropping 1: base on h/v sync 0: base on de 1 address bit r/w description reset 7 r/w 1: pip alpha blending enable, 0: disable 0 6 r/w 1: 565 mode (4:4:4 color space) for pip, 0: 888 mode (4:2:2 color space ) default 0 5 r/w 1: pip alpha blending key detection reverse 0 0x2ef 4 - 0 r/w alpha1 of pip alpha blending (main/sub mixing ratio), 10h : full pip ? 00h : full main 10h address bit r/w description reset 0x2f0 7 - 0 r/w red key color level for pip alpha blending 00h address bit r/w description reset 0x2f1 7 - 0 r/w green key color level for pip alpha blending 00h address bit r/w description reset 0x2f2 7 - 0 r/w blue key color level for pip alpha blending 00h address bit r/w description reset 0x2f3 7 - 0 r/w key color range 00h
TW8811 ? tft flat panel controller preliminary techwell, inc. 110 rev c 02/07/2008 0x2ed ? pip/mpip control registers address bit r/w description reset 7 r/w reserved 00 6 r/w reserved 0 5 r/w reserved 0 3 - 2 r/w reserved 00 1 r/w reserved 0 0x2ed 0 r/w reserved 0 address bit r/w description reset 7 r/w reserved 0 6 r/w 1: use dtv input de, 0: do not use input de, use input hs/vs instead 0 5 - 4 r/w reserved 0h 3 - 2 r/w pip input selection. 0 : decoder, 1 : analog rgb/yuv, 2 : dtv 0h 0x2ee 1 - 0 r/w mpip input selection. 0 : decoder, 1 : analog rgb/yuv, 2 : dtv 0h
TW8811 ? tft flat panel controller preliminary techwell, inc. 111 rev c 02/07/2008 0x2f4 to 0x2f8 ? power management registers address bit r/w description reset 0x2f4 7-0 r/w msb of an internal 23 bit divide down c ounter. the 27 mhz clock from pin#33 xtal27i is divided by this counter to serve as the clo ck for the power state transition timer. 0000 0000 address bit r/w description reset 7 r/w force the internal pclk to ?0?. 0 6 r/w clksel_fppwr 0 5-4 r show current power management state. these power states determine the states of pins #40 fppwc, #39 fpbias & fp interface signals which includes #55 fpvs, #56 fphs, #57 fpde, #53 fpclk and all data signals. fppwc fpbias fp interface signals 00: off ?0? ?0? ?0? 01: standby ?1? ?0? ?0? 10: suspend ?1? ?0? ?1? or ?0? 11: on ?1? ?1? ?1? or ?0? the transition between the power states does not occur right away. it takes place after the timer expiration by the corresponding timer counts defined in 0x275-0x277 00 3 r/w manual power sequencing contro l. when this bit is set, bits [2:0] control #39 fpbias, fp interface signals, and #40 fppwc directly. 0 2 r/w if bit 3 is ?0? and this bit is ?1?, this enable auto power sequencing. vsync loss & hsync loss ---> off vsync loss & hsync active ---> standby vsync active & hsync loss ---> suspend vsync active & hsync active ---> on 0 0x2f5 1-0 r/w power state steering. when these 2 bits are written, assuming both bit 3 and bit 2 are 0?s, and the current power state is different from the value written, the power state will be sequencing to the state that matches the value written. for example, current power state is 11. a 01 value is written. the power state will be steered to ?01? and stay in ?01. 00: off state, 01: standby, 10: suspend, 11: on state 00 address bit r/w description reset 7-4 r/w timer counts for suspend state to standby state transition 0000 0x2f6 3-0 r/w timer counts for on state to suspend state transition 0000 address bit r/w description reset 7-4 r/w timer counts for power off state to standby state transition 0000 0x2f7 3-0 r/w timer counts for standby state to power off state transition 0000 address bit r/w description reset 7-4 r/w timer counts for standby state to suspend sate transition 0000 0x2f8 3-0 r/w timer counts for suspend to on state transition 0000
TW8811 ? tft flat panel controller preliminary techwell, inc. 112 rev c 02/07/2008 timing controller configuration registers 0x300 ? output mode control register bit function r/w description reset 7 sig_off r/w lcd panel signals off control during power off 0 : disable 1 : all signals and data keep zero after gpio[0] was zero. (between back light off and lcd power off) 0 6 tcck_ph r/w tcclk phase control if reg0x300[ 0] set is high. (divide clock mode) 0 : no clock phase shift 1 : clock phase 90 degree shift *** it?s set reg0x270[3] (invert clock polarity) high and this bit set high also then tcclk is 270 degree shift. 0 5 roe_en r/w roe (row driver) output enable 0 : disable 1 : enable 1 4 -1 r/w reserved -- 0 div_ck r/w output mode selection 0 : one pixel data out per tcclk 1 : two pixel data out per tcclk (rising and falling both) 0 0x301 ? display control register bit function r/w description reset 7-4 r/w reserved --- 3 rev_en r/w pixel data reverse control 0 : data no reverse (don?t case tcrev signal) 1 : data reverse if tcrev signal is high period 0 2 r/w reserved --- 1-0 inv r/w inversion mode selection 2?b00 : disable 2?b01 : disable 2?b10 : line inversion 2?b11 : frame inversion 00 0x302 ? display direction control register bit function r/w description reset 7-4 r/w reserved --- 3-2 top_btm r/w top/bottom display direction select 2?b00 : top low active (normal) 2?b01 : top high active (normal) 2?b10 : bottom low active (flip) 2?b11 : bottom high active (flip) 01 1-0 lft_rht r/w left/right display direction select 2?b00 : left low active (normal) 2?b01 : left high active (normal) 2?b10 : right low active (mirror) 2?b11 : right high active (mirror) 01
TW8811 ? tft flat panel controller preliminary techwell, inc. 113 rev c 02/07/2008 0x303 ? control signal polarity selection register bit function r/w description reset 7-4 reserved ---- 3 roe_p r/w row driver output enable signal 0 : active low 1 : active high 1 2 rsp_p r/w row driver start pulse signal 0 : active low 1 : active high 1 1 clp_p r/w column driver latch pulse signal 0 : active low 1 : active high 1 0 csp_p r/w column driver start pulse signal 0 : active low 1 : active high 1 0x304 ? control signal generation method register bit function r/w description reset 7 pgm_sharp r/w 0 : sharp same polarity start point follow trsp pulse 1 : sharp same polarity start poi nt follow sharp_str register 6 sp_ctrl r/w unused output start pulse pin control 0 : zero 1: hi-z 5 pgm_rck r/w row driver clock signal 0 4 pgm_roe r/w row driver output enable signal 0 : this is generate during horizontal display enable. 1 : it?s generated that set tcon register address 0x32c though 0x32f. also, this is relative to vertical active register 0x30c though 0x30f. 0 3 pgm_rsp r/w row driver start pulse signal 0 : this signal immediately gener ate and then keep one horizontal period activation received from vertical active signal. 1 : it?s generated that set tcon register address 0x324 though 0x327. also, this is relative to vertical back porch register 0x279. 0 2 pgm_pol r/w 0 : this signal toggles when hsync toggle. 1: it?s generated that set tcon register 0x310 through 0x311 1 1 pgm_clp r/w column driver latch pulse signal 0 : this signal generate after horizon tal display enable done a every scan line. 1 : it?s generated that set tcon register address 0x312 though 0x315. 0 0 pgm_csp r/w column driver start pulse signal 0 : this signal generate after horizontal display enable. 1 : it?s generated that set tcon register address 0x31a though 0x31d. also, this is relative to horizontal back porch register 0x274. 0 0x305 ? inversion signal operating period register bit function r/w description reset 7-1 r/w reserved ---- 0 inv_sw r/w inversion signal (column driv er) working period selection 0 : inversion signal working within display enable period 1 : inversion signal working whol e(display enable and blanking time) period 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 114 rev c 02/07/2008 0x306 ? panel type select register bit function r/w description reset 7-2 r/w reserved --- 1 rev_inv r/w signal output selection 0 : tcinv signal output select 1 : tcrev output select 1 0 line_inv r/w analog panel data swapping 0 : no data inversion 1 : every line data inversion 0 0x30a ? special lcd module control register bit function r/w description reset 7-6 r/w reserved -- 5-4 rsp_width r/w row driver start pulse wi dth (period) selection 0 : one horizontal period 1 : two horizontal period 2 : three horizontal period 3 : four horizontal period 00 3-2 r/w reserved -- 1-0 company r/w lcd module company selection 2?b00 : lg-philips lcd module 2?b01 : sharp lcd module 2?b10, 2?b11 : other companies lcd module 10 0x30b ? revv(tcpolp) / revc(tcpoln) control registers bit function r/w description reset 7-0 revv_revc r/w revv_revc[7 :0] for sharp 4dh 0x30c ? vertical active start high register bit function r/w description reset 7-4 r/w reserved --- 3-0 v_st[11:8] r/w ver_ash[11:8] 0h 0x30d ? vertical active start low register bit function r/w description reset 7-0 v_st[7:0] r/w ver_asl[7:0] 06h 0x30e ? vertical active end high register bit function r/w description reset 7-4 r/w reserved --- 3-0 v_ed[11:8] r/w ver_aeh[11:8] 1h 0x30f ? vertical active end low register bit function r/w description reset 7-0 v_ed[7:0] r/w ver_ael[7:0] e2h
TW8811 ? tft flat panel controller preliminary techwell, inc. 115 rev c 02/07/2008 column driver chip control signals relative registers 0x310 ? polarity control high register bit function r/w description reset 7-4 r/w reserved --- 3-0 cp_sw[11:8] r/w programmable polarity period high[11:8] value. 2h 0x311 ? polarity control low register bit function r/w description reset 7-0 cp_sw[7:0] r/w programmable polarity period low[7:0] value. d0h 0x312 ? load/latch pulse start high register bit function r/w description reset 7-4 r/w reserved --- 3-0 clp_st[11:8] r/w lp_hsh[11:8] 2h 0x313 ? load/latch pulse start low register bit function r/w description reset 7-0 clp_st[7:0] r/w lp_hsl[7 :0] d0h 0x314 ? load/latch pulse width high register bit function r/w description reset 7-4 r/w reserved --- 3-0 clp_ed[11:8] r/w lp_heh[11:8] 0h 0x315 ? load/latch pulse width low register bit function r/w description reset 7-0 clp_ed[7:0] r/w lp_hel[7:0] 06h 0x31a ? column driver start pulse high register bit function r/w description reset 7-4 r/w reserved --- 3-0 csp_st[11:8] r/w sp_hsh[11:8] 0h 0x31b ? column driver start pulse low register bit function r/w description reset 7-0 csp_st[7:0] r/w sp_hsl[7 :0] c8h 0x31c ? column driver start pulse width high register bit function r/w description reset 7-4 r/w reserved --- 3-0 csp_ed[11:8] r/w sp_heh[11 :8] 0h 0x31d ? column driver start pulse width low register bit function r/w description reset 7-0 csp_ed[7:0] r/w sp_hel[7 :0] 01h
TW8811 ? tft flat panel controller preliminary techwell, inc. 116 rev c 02/07/2008 row driver chip control signals relative registers 0x320 ? clock start pulse high register bit function r/w description reset 7-4 r/w reserved --- 3-0 rck_st[11:8] r/w rck_hsh[11:8] 0 0x321 ? clock start pulse low register bit function r/w description reset 7-0 rck_st[7:0] r/w rck_hsl[7 :0] 00h 0x322 ? clock start pulse width high register bit function r/w description reset 7-4 r/w reserved --- 3-0 rck_ed[11:8] r/w rck_heh[11 :8] 2h 0x323 ? clock start pulse width low register bit function r/w description reset 7-0 rck_ed[7:0] r/w rck_hel[7 :0] 30h 0x324 ? row start pulse high register bit function r/w description reset 7-4 r/w reserved --- 3-0 rsp_st[11:8] r/w rsp_vsh[11:8] 0h 0x325 ? row start pulse low register bit function r/w description reset 7-0 rsp_st[7:0] r/w rsp_vsl[7 :0] 06h 0x326 ? row start pulse width high register bit function r/w description reset 7-4 r/w reserved --- 3-0 rsp_ed[11:8] r/w rsp_veh[11 :8] 0h 0x327 ? row start pulse width low register bit function r/w description reset 7-0 rsp_ed[7:0] r/w rsp_vel[7 :0] 01h 0x32c ? row output enable high register bit function r/w description reset 7-4 r/w reserved --- 3-0 roe_st[11:8] r/w roe_hsh[11:8] 0 0x32d ? row output enable low register bit function r/w description reset 7-0 roe_st[7:0] r/w roe_hsl[7 :0] 0ah 0x32e ? row output enable width high register bit function r/w description reset 7-4 r/w reserved --- 3-0 roe_ed[11:8] r/w roe_heh[11 :8] 0
TW8811 ? tft flat panel controller preliminary techwell, inc. 117 rev c 02/07/2008 0x32f ? row output enable width low register bit function r/w description reset 7-0 roe_ed[7:0] r/w roe_hel[7 :0] 36h 0x334 ? register bit function r/w description reset 7-4 r/w reserved 3-0 sharp_str_ h r/w sharp same polarity start point high bits 0h 0x335 ?register bit function r/w description reset 7-0 sharp_str_ l r/w sharp same polarity start point low bits 20h 0x336 ?register bit function r/w description reset 7-4 r/w reserved --- 3-0 sharp_end_ h r/w sharp same polarity end point high bits 1h 0x337 ?register bit function r/w description reset 7-0 sharp_end_ l r/w sharp same polarity end point low bits e2h 0x338 ?register bit function r/w description reset 7-6 r/w reserved --- 5 clpw r/w tclp direct mode pulse width c ontrol. { 1`b0 => 1 clk, 1?b1 => 2 clks } 0 4 csync_mod e r/w enable csync mode 0 3-2 clpsel r/w direct tcsp pulse adjust register 00 1-0 cspsel r/w direct tclp pulse adjust register 00 0x339 --register bit function r/w description reset 7-4 r/w reserved --- 3-0 pol_step r/w tcpol direct mode 16 step control 0h 0x3a0 to 0x3a0 -- pll control registers the frequency of the flat panel clock output (fpclk) pin c an be controlled by an internal frequency multiplier based on the video decoder clock source (xtal27i), or by an external oscillator connected to the pclk pin. when the internal frequency multiplier is being used, the frequency of the flat panel clock output signal is determined by the following formula.
TW8811 ? tft flat panel controller preliminary techwell, inc. 118 rev c 02/07/2008 address bit r/w description reset 7-5 r/w charge pump current control for pclk 0x3a0 4-0 r/w pclk oscillation fr equency calculation freq_p[19:15] pclk pll oscillation frequency = 108m hz * freq_p / 2 ^ 17 / 2^ post_p 40h address bit r/w description reset 0x3a1 7-0 r/w freq_p[14:7] 00h address bit r/w description reset 7-1 r/w freq_p[6:0] 0000000 0x3a2 0 r/w reserved 0 address bit r/w description reset 0x3a3 7-0 r/w it control pclk sp read spectrum modulation frequency. ssfreq_p[7:0] spread spectrum modulation freque ncy = 27mhz * ssfreq_p / 2^16 00h address bit r/w description reset 7-4 r/w this bit control pclk variance of spread spectrum. ssg_p[3:0] frequency deviation control for pclk : the max percentage of frequency deviation is given by following equation. dev = 2^8 * ssg_p / 2^ssd / 2^freq_p * 100 % 3-2 r/w pclk vco[1:0] 00 : 13.5 ~ 27mhz, 01 : 27 ~ 54 mhz 10 : 54 ~ 108mhz, 11 : 108 ~ 133mhz 0x3a4 1-0 r/w post_p: pclk post[1:0] 00h address bit r/w description reset 7-5 r/w charge pump current control for mclk 0x3a5 4-0 r/w mclk oscillation fr equency calculation freq_m[19:15] mclk pll oscillation frequency = 108mhz * freq_m / 2 ^ 17 / 2^ post_p 40h address bit r/w description reset 0x3a6 7-0 r/w freq_m[14:7] 00h address bit r/w description reset 7-1 r/w freq_m[6:0] 0000000 0x3a7 0 r/w reserved 0 address bit r/w description reset 0x3a8 7-0 r/w it control mclk sp read spectrum modulation frequency. ssfreq_m[7:0] spread spectrum modulation freque ncy = 27mhz * ssfreq_m / 2^16 00h address bit r/w description reset 7 r/w ss-pll output clock select. 0 : 27mhz xtal input 1 : pclk select 0 6 r/w ss-pll output clock select. 0 : 27mhz xtal input 1 : mclk select 0 5 r/w freq. synthesizer power down for pclk 0 : normal operation, 1 : off 0 4 r/w freq. synthesizer power down for mclk 0 : normal operation, 1 : off 0 3 r/w pll input select. 0 : 27mhz xtal 1 : pclk 0 0x3a9 2-0 r/w ss-pll gain divider for mclk, mdgain[2:0] 000
TW8811 ? tft flat panel controller preliminary techwell, inc. 119 rev c 02/07/2008 address bit r/w description reset 7-4 r/w this bit control mclk variance of spread spectrum. ssg_m[3:0] frequency deviation control for mclk : the max percentage of frequency deviation is given by following equation. dev = 2^8 * ssg_m / 2^ssd / 2^freq_m * 100 % 3-2 r/w mclk vco[1:0] 00 : 13.5 ~ 27mhz, 01 : 27 ~ 54 mhz 10 : 54 ~ 108mhz, 11 : 108 ~ 133mhz 0x3aa 1-0 r/w post_m : mclk post[1:0] 00 address bit r/w description reset 7-5 r/w ss-pll gain divider for pclk, pdgain[2:0] 0x3ab 4-0 r/w da_rgain address bit r/w description reset 7-5 r/w reserved 0x3ac 4-0 r/w da_ggain address bit r/w description reset 7-5 r/w reserved 0x3ad 4-0 r/w da_bgain address bit r/w description reset 7 r/w dac power down 0 6-5 r/w reserved for internal test. 0 4 r/w dac iref 0 0x3ae 3-0 r/w reserved 0h address bit r/w description reset 7-6 r/w reserved 0 0x3f0 5-0 r/w hswid, hsync widith. the unit of hwsid is one clock cycle. 10h address bit r/w description reset 0x3ff 7 - 6 r/w page register 00
TW8811 ? tft flat panel controller preliminary techwell, inc. 120 rev c 02/07/2008 copyright notice this manual is copyrighted by techwell, inc. do not r eproduce, transform to any other format, or send/transmit any part of this documentation without the express written permission of techwell, inc. trademark acknowledgment silicon image, the silicon image logo, panellink ? is a registered trademarks of silicon image, inc. vesa ? is a registered trademark of the video electronics standards association. all other trademarks are the property of their respective holders. disclaimer this document provides technical information for the us er. techwell, inc. reserves the right to modify the information in this document as necessary. the customer should make sure that they have the most recent data sheet version. techwell, inc. holds no responsibility for any errors that may appear in this document. customers should take appropriate action to ensure their use of the products does not infringe upon any patents. techwell, inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. life support policy techwell, inc. products are not authorized for use as critical components in life support devices or systems.
TW8811 ? tft flat panel controller preliminary techwell, inc. 121 rev c 02/07/2008 revision history date revision note 10/19/2007 revision b datasheet 01/21/2008 revision c datasheet -add rohs label -remove font base teltext osd feature, vbi slicer, scart rgb support -osd support dual window bitmap -pin 30, 31, 37 description updated -register 0x00d, 0x00e, 0x00f, 0x036, 0x037, 0x038[7] 0x1b3[1] remove -updated register 0x006[6][5], 0x01f, 0x102[4], 0x1b8, 0x1b9, 0x1c0, 0x1ce, 0x1f0[3:0],0x21f[2:1], 0x1cc[3:2] -add register 0x131~0x136, 0x2e6[7], 0x 2ee[7][6], 0x13a[5:4], 0x13d[7], 0x3f0[5:0] 02/07/2008 updated temperature spec

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