View DS1875T_7709617.PDF datasheet online --- IC-ON-LINE

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general description the ds1875 controls and monitors all functions for burst- mode transmitters, apd receivers, and video receivers. it also includes a power-supply controller for apd bias generation, and provides all sff-8472 diagnostic and monitoring functionality. the combined solution of the ds1875 and the max3643 laser driver provides apc loop, modulation current control, and eye safety func- tionality. ten adc channels monitor v cc , temperature (both internal signals), and eight external monitor inputs (mon1?on8) that can be used to meet transmitter, digital receiver, video receiver, and apd receiver-signal monitoring requirements. four total dac outputs are available. a pwm controller with feedback and compen- sation pins can be used to generate the bias for an apd or as a step-down converter. five i/o pins allow addi- tional monitoring and configuration. applications bpon, gpon, or epon optical triplexers sff, sfp, and sfp+ transceiver modules apd controller features ? meets all pon burst-timing requirements for burst-mode operation ? laser bias controlled by apc loop and temperature lookup table (lut) ? laser modulation controlled by temperature lut ? six total dacs: four external, two internal ? two 8-bit dacs, one of which is optionally controlled by mon4 voltage ? internal 8-bit dac controlled by a temperature- indexed lut ? pwm controller ? boost or buck mode ? boost mode: uses optional external components, up to 90v bias generation ? 131khz, 262khz, 525khz, or 1050khz selectable- switching frequency ? apd overcurrent protection using optional fast shutdown ? 10 analog monitor channels: temperature, v cc , eight monitors ? internal, factory-calibrated temperature sensor ? rssi with 29db electrical dynamic ? five i/o pins for additional control and monitoring functions, four of which are either digital i/o or analog monitors ? comprehensive fault-measurement system with maskable laser shutdown capability ? two-level password access to protect calibration data ? 120 bytes of password-1 protected memory ? 128 bytes of password-2 protected memory in main device address ? 256 additional bytes located at a0h slave address ? i 2 c-compatible interface for calibration and monitoring ? 2.85v to 3.9v operating voltage range ? -40? to +95? operating temperature range ? 38-pin tqfn (5mm x 7mm) package ds1875 ________________________________________________________________ maxim integrated products 1 top view tqfn (5mm 7mm 0.8mm) 13 14 15 16 17 18 19 mon5/d0 mon6/d1 mon7/d2 mon8/d3 mon1 mon2 mon4 38 37 36 35 34 33 32 123456789101112 n.c. n.c. n.c. v cc sw gnd gnd losi n.c. gnd v cc tx-d n.c. fetg n.c. tx-f scl sda ben 31 30 29 28 27 26 25 24 23 22 21 20 n.c. mon3n mon3p dac1 gnd m4dac fb bias mod comp bmd v cc + *ep *exposed pad. ds1875 pin configuration ordering information rev 1; 10/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. part temp range pin-package DS1875T+ -40c to +95c 38 tqfn-ep* DS1875T+t&r -40c to +95c 38 tqfn-ep* pon triplexer and sfp controller
ds1875 2 _______________________________________________________________________________________ absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 electrical characteristics (dac1 and m4dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 analog input characteristics (bmd, txp hi, txp lo, hbias) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 analog output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pwm characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 timing characteristics (control loop and quick trip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 analog voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 digital thermometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 nonvolatile memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 i 2 c timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 typical operating circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 bias control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 autodetect bias control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 open-loop bias control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 closed-loop bias control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 dc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 modulation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 bias and mod output during power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 bias and mod output as a function of transmit disable (tx-d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 apc and quick-trip shared comparator timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 monitors and fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 power-on analog (poa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 quick-trip monitors and alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 mon3 quick trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 adc monitors and alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 adc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 right-shifting adc result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 transmit fault (tx-f) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 safety shutdown (fetg) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 determining alarm causes using the i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table of contents pon triplexer and sfp controller
ds1875 _______________________________________________________________________________________ 3 die identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 low-voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 enhanced rssi monitoring (dual range functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 pwm controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 stability and compensation component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 dac1 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 m4dac output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 digital i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 i 2 c communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 i 2 c definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 i 2 c protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 shadowed eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 lower memory register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 00h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 01h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 02h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 03h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 04h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 05h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 06h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 07h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 08h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 auxiliary a0h memory register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 lower memory register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 00h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 01h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 02h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 03h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table 04h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table 05h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table 06h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 table 07h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 08h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table of contents (continued) pon triplexer and sfp controller
ds1875 pon triplexer and sfp controller 4 _______________________________________________________________________________________ auxiliary memory a0h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table of contents (continued) figure 1. power-up timing (ben is a long burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 2. tx-d timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 3. apc loop and quick-trip sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 4. m3qt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 5. adc timing with en5to8b = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 6. adc timing with en5to8b = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 7. tx-f timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 8. fetg/output disable timing (fault condition detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 9. see timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 10. rssi flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 11. pwm controller diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 12. pwm controller typical apd bias circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 13. pwm controller voltage output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 14. pwm controller current-sink output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 15. i 2 c timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 16. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 1. ds1875 acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 2. update rate timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 3. adc default monitor ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 4. tx-f as a function of tx-d and alarm sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 5. fetg, mod, and bias outputs as a function of tx-d and alarm sources . . . . . . . . . . . . . . . . . . . . . . . . .2 2 table 6. mon3 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7. mon3 hysteresis threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 list of figures list of tables
ds1875 stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on mon1?on8, ben, bmd, and tx-d pins relative to ground .................................-0.5v to (v cc + 0.5v)* voltage range on v cc , sda, scl, d0?3, and tx-f pins relative to ground...............-0.5v to 6v operating temperature range ...........................-40? to +95? programming temperature range .........................0? to +85? storage temperature range .............................-55? to +125? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units main supply voltage v cc (note 1) +2.85 +3.9 v high-level input voltage (sda, scl, ben) v ih:1 0.7 x v cc v cc + 0.3 v low-level input voltage (sda, scl, ben) v il:1 -0.3 0.3 x v cc v high-level input voltage (tx-d, losi, d0, d1, d2, d3) v ih:2 2.0 v cc + 0.3 v low-level input voltage (tx-d, losi, d0, d1, d2, d3) v il:2 -0.3 +0.8 v ac electrical characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units supply current i cc (notes 1, 2) 5.5 10 ma output leakage (sda, tx-f, d0, d1, d2, d3) i lo (note 2) 1 a i ol = 4ma 0.4 low-level output voltage (sda, tx-f, fetg, d0, d1, d2, d3) v ol i ol = 6ma 0.6 v high-level output voltage (fetg) v oh i oh = 4ma v cc - 0.4 v fetg before recall (note 3) 10 100 na input leakage current (scl, ben, tx-d, losi) i li:1 1 a digital power-on reset pod 1.0 2.2 v analog power-on reset poa 2.1 2.75 v * subject to not exceeding +6v. recommended operating conditions (t a = -40? to +95?, unless otherwise noted.) absolute maximum ratings pon triplexer and sfp controller _______________________________________________________________________________________ 5
ds1875 pon triplexer and sfp controller 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units dac output range 2.5 v dac output resolution 8 bits dac output integral nonlinearity -1 +1 lsb dac output differential nonlinearity -1 +1 lsb dac error t a = +25c -1.25 +1.25 %fs dac temperature drift -2 +2 %fs dac offset -12 +12 mv maximum load -500 +500 a maximum load capacitance 250 pf parameter symbol conditions min typ max units bmd, txp hi, txp lo full-scale voltage v apc (note 4) 2.5 v hbias full-scale voltage (note 5) 1.25 v bmd input resistance 35 50 65 k resolution 8 bits error t a = +25c (note 6) 2 %fs integral nonlinearity -1 +1 lsb differential nonlinearity -1 +1 lsb temperature drift -2.5 +2.5 %fs analog output characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units bias current i bias (note 1) 1.2 ma i bias shutdown current i bias:off 10 100 na voltage at i bias 0.7 1.2 1.4 v mod full-scale voltage v mod (note 5) 1.25 v mod output impedance (note 7) 3 k v mod error t a = +25c (note 8) -1.25 +1.25 %fs v mod integral nonlinearity -1 +1 lsb v mod differential nonlinearity -1 +1 lsb v mod temperature drift -2 +2 %fs analog input characteristics (bmd, txp hi, txp lo, hbias) (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) electrical characteristics (dac1 and m4dac) (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.)
ds1875 parameter symbol conditions min typ max units pwm-dac full-scale voltage v pwm-dac 1.25 v pwm-dac resolution 8 bits v pwm-dac full-scale voltage error t a = +25c 1.25 % v pwm-dac integral nonlinearity -1 1 lsb v pwm-dac differential nonlinearity -1 1 lsb v pwm-dac temperature drift -2 +2 %fs sw output impedance 20 sw frequenc y error f swer (note 9) -5 +7 % sw duty cycle d max 89 90 91 % error-amplifier source current -10 a error-amplifier sink current +10 a comp high-voltage clamp 2.1 v comp low-voltage clamp 0.8 v error-amplifier transconductance g m 425 s error-amplifier output impedance r ea 260 m fb pin capacitance 5 pf parameter symbol conditions min typ max units first bmd sample following ben t first (note 10) remaining updates during ben t update (note 10) ben high time t ben:high 400 ns ben low time t ben:low 96 ns output-enable time following poa t init 10 ms bias and mod turn-off delay t off 5 s bias and mod turn-on delay t on 5 s fetg turn-on delay t fetg:on 5 s fetg turn-off delay t fetg:off 5 s timing characteristics (control loop and quick trip) (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) pwm characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) pon triplexer and sfp controller _______________________________________________________________________________________ 7
ds1875 pon triplexer and sfp controller 8 _______________________________________________________________________________________ parameter symbol conditions min typ max units thermometer error t err -40c to +95c 3.0 c nonvolatile memory characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units at +85c (note 11) 50,000 eeprom write cycles at +25c (note 11) 200,000 parameter symbol conditions min typ max units adc resolution 13 bits input/supply accuracy (mon1Cmon8, v cc ) acc at factory setting 0.25 0.50 %fs update rate for temp, mon1Cmon4, and v cc t frame:1 78 95 ms update rate for mon5Cmon8 t frame:2 bit en5to8b is enabled in table 02h, register 89h 156 190 ms input/supply offset (mon1Cmon8, v cc ) v os (note 11) 0 5 lsb mon1Cmon8 2.5 v cc 6.5536 v factory setting mon3 fine full scales are user programmable 312.5 v digital thermometer (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) analog voltage monitoring (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.)
ds1875 note 1: all voltages are referenced to ground. current into ic is positive, and current out of the ic is negative. note 2: digital inputs are at rail. fetg is disconnected. sda = scl = v cc . sw, dac1, and m4dac are not loaded. note 3: see the safety shutdown (fetg) output section for details. note 4: eight ranges allow the full scale to change from 625mv to 2.5v. note 5: eight ranges allow the full scale to change from 312.5mv to 1.25v. note 6: this specification applies to the expected full-scale value for the selected range. see the comp ranging register description for available full-scale ranges. note 7: the output impedance of the ds1875 is proportional to its scale setting. for instance, if using the 1/2 scale, the output impedance would be approximately 1.56k . note 8: this specification applies to the expected full-scale value for the selected range. see the mod ranging register description for available full-scale ranges. note 9: the switching frequency is selectable between four values: 131.25khz, 262.5khz, 525khz, and 1050khz. note 10: see the apc and quick-trip shared comparator timing section for details. note 11: guaranteed by design. note 12: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c stan- dard mode. note 13: c b ?otal capacitance of one bus line in pf. note 14: eeprom write begins after a stop condition occurs. i 2 c timing specifications (v cc = +2.85v to +3.9v, t a = -40? to +95?, timing referenced to v il(max) and v ih(min) .) (see figure 15.) parameter symbol conditions min typ max units scl clock frequency f scl (note 12) 0 400 khz clock pulse-width low t low 1.3 s clock pulse-width high t high 0.6 s bus-free time between stop and start condition t buf 1.3 s start hold time t hd:sta 0.6 s start setup time t su:sta 0.6 s data in hold time t hd:dat 0 0.9 s data in setup time t su:dat 100 ns capacitive load for each bus line c b 400 pf rise time of both sda and scl signals t r (note 13) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 13) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 s eeprom write time t w (note 14) 20 ms pon triplexer and sfp controller _______________________________________________________________________________________ 9
ds1875 pon triplexer and sfp controller 10 ______________________________________________________________________________________ supply current vs. supply voltage ds1875 toc01 v cc (v) supply current (ma) 3.85 3.35 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 4.5 2.85 sda = scl = v cc +95 c +25 c -40 c supply current vs. temperature ds1875 toc02 temperature ( c) supply current (ma) 80 60 20 40 0 -20 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 4.5 -40 v cc = 3.9v v cc = 2.85v sda = scl = v cc supply current vs. temperature v cc = 3.3v, no bias current ds1875 toc03 temperature ( c) i cc (ma) 80 60 20 40 0 -20 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 6.4 -40 sw = 1050khz sw = 525khz sw = 262.5khz sw = 131.25khz supply current vs. temperature v cc = 5v, no bias current ds1875 toc04 temperature ( c) i cc (ma) 80 60 40 20 0 -20 7.6 7.8 8.0 8.2 8.4 8.6 8.8 7.4 -40 sw = 1050khz sw = 525khz sw = 262.5khz sw = 131.25khz dac1 and m4dac dnl ds1875 toc05 dac1 and m4dac position (dec) dac1 and m4dac dnl (lsb) 250 200 150 100 50 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 dac1 and m4dac inl ds1875 toc06 dac1 and m4dac position (dec) dac1 and m4dac inl (lsb) 250 200 150 100 50 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 dac1 and m4dac offset vs. v cc ds1875 toc07 v cc (v) dac1 and m4dac offset (mv) 3.85 3.65 3.45 3.25 3.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -0.05 2.85 t a = -40 c to +95 c load = -0.5ma to +0.5ma dac1 and m4dac offset variation vs. load current ds1875 toc08 load current (ma) dac1 and m4dac offset (mv) 0.3 0.1 -0.1 -0.3 -0.0008 -0.0006 -0.0004 -0.0002 0 0.0002 0.0004 0.0006 0.0008 0.0010 -0.0010 -0.5 0.5 v cc = 2.85v v cc = 3.6v v cc = 3.9v dac1 and m4dac output vs. load current ds1875 toc09 load current (ma) dac1 and m4dac output (v) 0.3 0.1 -0.3 -0.1 1.247 1.249 1.251 1.253 1.257 1.255 1.259 1.245 -0.5 0.5 output without offset v cc = 2.85v v cc = 3.9v typical operating characteristics (v cc = +2.85v to +3.9v, t a = +25?, unless otherwise noted.)
ds1875 typical operating characteristics (continued) (v cc = +2.85v to +3.9v, t a = +25?, unless otherwise noted.) calculated and desired % change in v mod vs. mod ranging ds1875 toc10 mod ranging value (dec) change in v mod (%) 007 006 004 005 002 003 001 10 20 30 40 50 60 70 80 90 100 0 000 calculated value desired value desired and calculated change in v bmd vs. comp ranging ds1875 toc11 comp ranging (dec) change in v bmd (%) 111 110 100 101 010 011 001 10 20 30 40 50 60 70 80 90 100 0 000 calculated value desired value mon1 to mon8 inl ds1875 toc12 mon1 to mon8 input voltage (v) mon1 to mon8 inl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 using factory-programmed full-scale value of 2.5v mon1 to mon8 dnl ds1875 toc13 mon1 to mon8 input voltage (v) mon1 to mon8 dnl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 using factory-programmed full-scale value of 2.5v v bmd inl vs. apc index ds1875 toc14 apc index (dec) v bmd inl (lsb) 250 200 150 100 50 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 v mod inl vs. mod index ds1875 toc15 mod index (dec) v mod inl (lsb) 250 200 150 100 50 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 fb voltage vs. temperature pwm dac = ffh ds1875 toc16 temperature ( c) v out (v) 80 60 40 20 0 -20 1.245 1.250 1.255 1.260 1.240 -40 v out vs. v cc v in = 3.3v ds1875 toc17 v cc (v) v out (v) 3.85 3.35 75.2 75.4 75.6 75.8 76.0 76.2 76.4 76.6 76.8 77.0 75.0 2.85 duty-cycle limit vs. temperature ds1875 toc18 temperature ( c) v out (v) 80 60 -20 0 20 40 89.25 89.50 89.75 90.00 90.25 90.50 90.75 91.00 89.00 -40 sw frequency 525khz 262.5khz 131.25khz 1050khz pon triplexer and sfp controller ______________________________________________________________________________________ 11
ds1875 pon triplexer and sfp controller 12 ______________________________________________________________________________________ pwm dac dnl ds1875 toc19 dac setting (dec) dac dnl (lsb) 224 192 32 64 96 128 160 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 256 pwm dac inl ds1875 toc20 dac setting (dec) dac inl (lsb) 224 192 32 64 96 128 160 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 256 m3qt dac dnl ds1875 toc21 dac setting (dec) dac dnl (lsb) 224 192 32 64 96 128 160 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 256 m3qt dac inl ds1875 toc22 dac setting (dec) dac inl (lsb) 224 192 32 64 96 128 160 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 256 sw current into bss123 fet frequency = 1050khz 50% duty cycle ds1875 toc23 100ns/div 0v 1v/div 0ma 10ma/div sw current sw pwm dac changing from 00h to 80h r comp = 24.3k , c comp = 220nf ds1875 toc24 5ms/div 0v 20v/div 0v 0v 10%/div 0% 200mv/div 200mv/div v out comp duty cycle fb switching waveforms v in = 3.3v, v out ~ 90v, i out ~ 1.25ma, c2 = 0.1 f ds1875 toc25 2 s/div 0v 5v/div 0v 0v 0ma 50v/div 100mv/div 100ma/div sw inductor voltage inductor current v out ripple (ac-coupled) typical operating characteristics (continued) (v cc = +2.85v to +3.9v, t a = +25?, unless otherwise noted.)
ds1875 pon triplexer and sfp controller ______________________________________________________________________________________ 13 pin description pin name function 1 ben burst-enable input. triggers the samples for the apc and quick-trip monitors. 2 sda i 2 c serial-data input/output 3 scl i 2 c serial-clock input 4 tx-f transmit-fault output 5, 7, 11, 20, 36, 37, 38 n.c. no connection 6 fetg fet gate output. signals an external n-channel or p-channel mosfet to enable/disable the lasers current. 8 tx-d transmit-disable input. disables analog outputs. 9, 31, 35 v cc power-supply input (2.85v to 3.9v) 10, 24, 32, 33 gnd ground connection 12 losi loss-of-signal input. open-collector buffer for external loss-of-signal input. this input is accessible in the status register through the i 2 c interface. 13 mon5/d0 external monitor input 5 or digital i/o 0. this signal is the open-collector output driver for in. it can also be controlled by the mux0 and out0 bits. the voltage level of this pin can be read at in0. in analog input mode, the voltage at this pin is digitized by the internal 13-bit analog-to- digital converter and can be read through the i 2 c interface. alarm and warning values can be assigned to interrupt the processor based on the adc result. 14, 15, 16 mon6/d1, mon7/d2, mon8/d3 external monitor inputs 6, 7, and 8 or digital i/o 1, 2, and 3. in digital mode, these open-collector outputs are controlled by the outx bits, and their voltage levels can be read at the inx bits. in analog input mode, the voltages at these pins are digitized by the internal 13-bit analog-to-digital converter and can be read through the i 2 c interface. alarm and warning values can be assigned to interrupt the processor based on the adc result. d2 is configurable as a quick-trip output for mon3. 17, 18, 19 mon1, mon2, mon4 external monitor input 1, 2, and 4. the voltage at these pins is digitized by the internal 13-bit analog-to-digital converter and can be read through the i 2 c interface. alarm and warning values can be assigned to interrupt the processor based on the adc result. 21, 22 mon3n, mon3p external monitor input 3. this is a differential input that is digitized by the internal 13-bit adc and can be read through the i 2 c interface. alarm and warning values can be assigned to interrupt the processor based on the adc result. when used as a single-ended input, connect mon3n to ground. 23 dac1 8-bit dac output. driven either by i 2 c interface or temperature-indexed lut. 25 m4dac 8-bit dac output for generating analog voltage. can be controlled by a lut indexed by the voltage applied to mon4. 26 fb converter feedback. input to error amplifier. the other input to the error amplifier is an 8-bit dac. the dac can be driven by a temperature-indexed lut. the output of the error amplifier is the input of the comparator used to create the pwm signal. 27 bias bias-current output. this 13-bit current output generates the bias current reference for the max3643. 28 mod modulation output voltage. this 8-bit voltage output has eight full-scale ranges from 1.25v to 0.3125v. this pin is connected to the max3643s vmset input to control the modulation current. 29 comp compensation for error amplifier in pwm controller 30 bmd back monitor diode input (feedback voltage, transmit power monitor) 34 sw pwm output. this is typically the switching node of a pwm converter. in conjunction with fb, a boost converter, buck converter, or analog 8-bit output can be created. ep exposed pad
ds1875 pon triplexer and sfp controller 14 ______________________________________________________________________________________ block diagram hbias quick-trip limit htxp quick-trip limit ltxp quick-trip limit apc set point from tracking-error table latch enable v cc mon[5:8] temp sensor i 2 c interface sample control 8-bit dac with scaling digital apc integrator 8-bit pwm-dac 13-bit dac analog mux mod lut tx-d input 8-bit dac with scaling pwm bias max quick trip table 08h bias ol lut temp indexed table 07h pwm voltage lut can be indexed by temp sensor interrupt mask interrupt latch interrupt mask interrupt latch power-on analog v cc > v poa nonmaskable interrupt 13-bit adc ds1875 memory organization sram reset digital limit comparator for adc results mux mux mux tx-d mon5 mux bmd ben mon3n mon3p mon2 mon1 mon4 scl sda ttl losi 0 1 ttl mon5/d0 los status/ d0 in d0 out ttl 0 1 mux0 ttl mon6/d1 d1 in d1 out ttl mon7/d2 d2 in d2 out mux2 inv m3qt m3qt ttl mon8/d3 d3 in d3 out gnd inv0 dac1 8-bit, 2.5v full scale i 2 c control dac1 fetg bias mod m4dac 8-bit, 2.5v full scale table 06h m4dac lut indexed by mon4 m4dac i 2 c control v cc v cc eeprom 256 bytes at a0h slave address tx-f table 02h (eeprom) configuration and calibration table 06h (eeprom) m4dac lut table 03h (eeprom) user memory table 07h (eeprom) pwm lut table 04h (eeprom) modulation lut table 08h (eeprom) bias ol lut main memory eeprom/sram adc configuration/results system status bits alarm/warning comparisons table 00h (eeprom) additional monitors table 01h (eeprom) user memory, alarm trap table 05h (eeprom) adc te lut sw comp fb mon6 mon7 mon8 ds1875
ds1875 typical operating circuit ben+ ben- dis in- in+ out- bias- bias+ out+ v cc tx-f tx-d scl sda losi d3 d0 mon[5:7] mon2 mon3 mon4 fetg m4dac d1 mon1 bmd 3.3v vmset modset vref imax gnd biasset benout bcmon vbset transmit power dac1 d2 mon8 voltage reference optional apd overload quick trip apd voltage monitor disable input receiver los open-drain los output fault output i 2 c communication receive power catv rf power v cc sw gnd additional digital i/o additional monitors catv receive power (current) 12v ftth catv tia rf detector gain control catv shutdown control current monitor fb 3.3v 3.3v r agc tia rosa apd comp mod bias ben ds1875 max3643 max4003 max4007 max3654 pon triplexer and sfp controller ______________________________________________________________________________________ 15
ds1875 pon triplexer and sfp controller 16 ______________________________________________________________________________________ detailed description the ds1875 integrates the control and monitoring func- tionality required to implement a pon system using maxim? max3643 compact burst-mode laser driver. the compact laser-driver solution offers a considerable cost benefit by integrating control and monitoring fea- tures in the low-power cmos process, while leaving only the high-speed portions to the laser driver. key components of the ds1875 are shown in the block diagram and described in subsequent sections. table 1 contains a list of acronyms used in this data sheet. bias control bias current is controlled by an apc loop. the apc loop uses digital techniques to overcome the difficulties associated with controlling burst-mode systems. autodetect bias control this is the default mode of operation. in autodetect bias control, transmit burst length is monitored. a ?hort burst?is declared when the burst is shorter than expected based on the sample rate setting in table 02h, register 88h. in the case that 32 consecutive short bursts are transmitted, the integrator is disabled and the bias dac is loaded from the bias lut (table 08h). any single burst of adequate burst length re-enables the apc integrator. open-loop bias control open-loop control is configured by setting fbol in table 02h, register c7h. in this mode, the bias lut (table 08h) is directly loaded to the bias dac output. the bias lut can be programmed in 2? increments over the 40? to +102? range. it is left-shifted so that the lut value is loaded to either the dac msb or the dac msb-1 (bit bolfs, table 02h, register 89h). closed-loop bias control the closed-loop control requires a burst length long enough to satisfy the sample rate settings in table 02h, register 88h (apc_sr[3:0]). closed-loop control is configured by setting fbcl in table 02h, register c7h. in this mode, the apc integrator is enabled, which con- trols the bias dac. the apc loop begins by loading the value from the bias lut (table 08h) indexed by the present tempera- ture conversion. the feedback for the apc loop is the monitor diode (bmd) current, which is converted to a voltage using an external resistor. the feedback volt- age is compared to an 8-bit scaleable voltage refer- ence, which determines the apc set point of the system. scaling of the reference voltage accommo- dates the wide range in photodiode sensitivities. this allows the application to take full advantage of the apc reference? resolution. the ds1875 has an lut to allow the apc set point to change as a function of temperature to compensate for te. the te lut (table 05h) has 36 entries that deter- mine the apc setting in 4? windows between -40? to +100?. ranging of the apc dac is possible by pro- gramming a single byte in table 02h, register 8dh. table 1. ds1875 acronyms acronym definition 10gepon 10-gigabit ethernet pon adc analog-to-digital converter agc automatic gain control apc automatic power control apd avalanche photodiode bm burst mode bpon broadband pon catv cable television epon ethernet pon er extinction ratio dac digital-to-analog converter ftth fiber-to-the-home fttx fiber-to-the-x gepon gigabit ethernet pon gpon gigabit pon los loss of signal lut lookup table te tracking error tia transimpedance amplifier rosa receiver optical subassembly rssi receive signal strength indicator pon passive optical network pwm pulse-width modulation sff small form factor sff-8472 document defining register map of sfps and sffs sfp small form factor pluggable sfp+ enhanced sfp tosa transmit optical subassembly
ds1875 dc operation when using autodetect mode or closed-loop mode, ben should be equal to v cc or long burst. in open-loop mode, ben should be ground or any burst length. modulation control the mod output is an 8-bit scaleable voltage output that interfaces with the max3643? vmset input. an external resistor to ground from the max3643? modset pin sets the maximum current that the voltage at the vmset input can produce for a given output range. this resistor value should be chosen to produce the maximum modulation current the laser type requires over temperature. then the mod output? scaling is used to calibrate the full-scale (fs) modulation output to a particular laser? requirements. this allows the application to take full advantage of the mod output? resolution. the modulation lut can be programmed in 2? increments over the -40? to +102? range. ranging of the mod dac is possible by programming a single byte in table 02h, register 8bh. bias and mod output during power-up on power-up the modulation and bias outputs remain off until v cc is above v poa , a temperature conversion has been completed, and, if the v cc adc alarm is enabled, a v cc conversion above the customer-defined v cc low alarm level must clear the v cc low alarm (t init ). once all these conditions (t init ) are satisfied, the mod output is enabled with the value determined by the temperature conversion and the modulation lut (table 04h). when the mod output is enabled, the bias output is turned on to a value equal to the temperature-indexed value in the bias lut (table 08h). next, the apc inte- grator is enabled, and single lsb steps are taken to tightly control the average power. if a fault is detected and tx-d is toggled to re-enable the outputs, the ds1875 powers up following a similar sequence to an initial power-up. the only difference is that the ds1875 already determined the present tem- perature, so the t init time is not required for the ds1875 to recall the apc and mod set points from eeprom. 12345678910111213 t init v poa v mod i bias v cc bias sample apc integrator on bias lut value figure 1. power-up timing (ben is a long burst) pon triplexer and sfp controller ______________________________________________________________________________________ 17
ds1875 pon triplexer and sfp controller 18 ______________________________________________________________________________________ bias and mod output as a function of transmit disable (tx-d) if the tx-d pin is asserted (logic 1) during normal oper- ation, the outputs are disabled within t off . when tx-d is deasserted (logic 0), the ds1875 turns on the mod output with the value associated with the present tem- perature and initializes the bias using the same search algorithm used at startup. when asserted, the soft tx-d bit (lower memory, register 6eh) offers a soft- ware control identical to the tx-d pin (see figure 2). apc and quick-trip shared comparator timing as shown in figure 3, the ds1875? input comparator is shared between the apc control loop and the three quick-trip alarms (txp hi, txp lo, and bias hi). the comparator polls the alarms in a multiplexed sequence. six of every eight comparator readings are used for apc loop-bias current control. the other two updates are used to check the htxp/ltxp (monitor diode volt- age) and the hbias (mon1) signals against the inter- nal apc and bias reference. if the last apc comparison was higher than the apc set point, it makes an htxp comparison, and if it is lower, it makes an ltxp comparison. depending on the results of the comparison, the corresponding alarms and warnings (txp hi, txp lo) are asserted or deasserted. the ds1875 has a programmable comparator sample time based on an internally generated clock to facilitate a wide variety of external filtering options suitable for burst-mode transmitters. the rising edge of ben trig- gers the sample to occur, and the update rate register (table 02h, register 88h) determines the sampling time. the first sample occurs (t first ) after the rising edge of ben. the internal clock is asynchronous to ben, caus- ing a ?0ns uncertainty regarding when the first sample will occur following ben. after the first sample occurs, subsequent samples occur on a regular interval, t rep . table 2 shows the sample rate options available. updates to the txp hi and txp lo quick-trip alarms do not occur during the ben low time. the bias hi quick trip can be sampled during the burst-low time. any * all codes greater than 1001b (1010b to 1111b) use the maximum sample time of code 1001b. ben apc quick-trip sample times hbias sample t first t rep htxp/ltxp sample apc sample apc sample apc sample apc sample apc sample apc sample apc sample figure 3. apc loop and quick-trip sample timing table 2. update rate timing apc_sr[3:0] minimum time from ben to first sample (t first ) 50ns (ns) repeated sample period following first sample (t rep ) (ns) 0000b 350 800 0001b 550 1200 0010b 750 1600 0011b 950 2000 0100b 1350 2800 0101b 1550 3200 0110b 1750 3600 0111b 2150 4400 1000b 2950 6000 1001b* 3150 6400 tx-d i bias v mod t off t on t on t off figure 2. tx-d timing
ds1875 quick-trip alarm that is detected by default remains active until a subsequent comparator sample shows the condition no longer exists. a second bias-current moni- tor (bias max) compares the ds1875? bias dac? code to a digital value stored in the max bias register. this comparison is made at every bias-current update to ensure that a high bias current is quickly detected. monitors and fault detection monitors monitoring functions on the ds1875 include a power-on analog (poa) v cc comparison, five quick-trip com- parators, and adc channels. this monitoring combined with the interrupt masks determine if the ds1875 shuts down its outputs and triggers the tx-f and fetg out- puts. all the monitoring levels and interrupt masks are user programmable with the exception of poa, which trips at a fixed range and is nonmaskable for safety reasons. power-on analog (poa) poa holds the ds1875 in reset until v cc is at a suitable level (v cc > v poa ) for the part to accurately measure with its adc and compare analog signals with its quick- trip monitors. because v cc cannot be measured by the adc when v cc is less than v poa , poa also asserts the v cc low alarm, which is cleared by a v cc adc conver- sion greater than the customer-programmable v cc low adc limit. this allows a programmable limit to ensure that the head room requirements of the transceiver are satisfied during slow power-up. the tx-f and fetg outputs do not latch until there is a conversion above the v cc low limit. the poa alarm is nonmaskable. the tx-f and fetg outputs are asserted when v cc is below v poa . see the low-voltage operation section for more information. five quick-trip monitors and alarms five quick-trip monitors are provided to detect potential laser safety issues. these monitor: 1) high bias current (hbias) 2) low transmit power (ltxp) 3) high transmit power (htxp) 4) max output current (bias max) 5) mon3 quick trip (m3qt) the high- and low-transmit power quick-trip registers (htxp and ltxp) set the thresholds used to compare against the bmd voltage to determine if the transmit power is within specification. the hbias quick trip com- pares the mon1 input (generally from the max3643 bias monitor output) against its threshold setting to determine if the present bias current is above specifica- tion. the bias max quick trip is a digital comparison that determines if the bias dac indicates that the bias current is above specification. i bias is not allowed to exceed the value set in the max bias register. when the ds1875 detects that the bias is at the limit, it sets the bias max status bit and clamps the bias current at the max bias level. in the closed-loop mode, if the recalled value from the bias lut is greater than max bias then, the update is not done and i bias reverts to the previous i bias value. the quick trips are routed to the tx-f and fetg outputs through interrupt masks to allow combinations of these alarms to be used to trigger these outputs. when fetg is triggered, the ds1875 also disables the mod and bias outputs. see the bias and mod output during power-up section for details. mon3 quick trip one additional quick trip is used to protect the apd from overcurrent. mon3p is used to monitor the current through the apd. when mon3p exceeds a threshold set by the m3qt dac register (table 02h, register c3h), the pwm is shut down by blocking sw pulses. the mon3 comparison is single-ended referenced to ground. in the case where mon3 is used differentially and not referenced to ground, this must be considered when setting the mon3 quick-trip threshold. additionally, the d2 pin can be driven either high or low as determined by inv m3qt and mux m3qt bits in lower memory, register 79h. an external switch con- trolled by pin d2 may be used to clamp the converter? output when mon3 quick trip occurs. this external switch discharges the output voltage much faster than allowing the load to discharge the rail. the mon3 quick-trip alarm can be latched by enabling m3qt len in table 02h, register 89h. the latch is reset by setting m3qt reset in lower memory, register 78h. a soft quick trip is performed by setting soft m3qt in lower memory, register 78h (see figure 4). adc monitors and alarms the adc monitors six channels that measure tempera- ture (internal temp sensor), v cc , and mon1?on4 using an analog multiplexer to measure them round robin with a single adc. each channel has a customer- programmable full-scale range and offset value that is factory programmed to default value (see table 3). additionally, mon1?on4 can right-shift results by up to 7 bits before the results are compared to alarm thresholds or read over the i 2 c bus. this allows cus- tomers with specified adc ranges to calibrate the adc full scale to a factor of 1/2 n their specified range to measure small signals. the ds1875 can then right-shift the results by n bits to maintain the bit weight of their specification. pon triplexer and sfp controller ______________________________________________________________________________________ 19
ds1875 pon triplexer and sfp controller 20 ______________________________________________________________________________________ the adc results (after right-shifting, if used) are com- pared to high and low alarm and warning thresholds after each conversion. the alarm values can be used to trigger the tx-f or fetg outputs. these adc thresholds are user programmable through the i 2 c interface, as well as masking registers that can be used to prevent the alarms from triggering the tx-f and fetg outputs. adc timing there are 10 analog channels that are digitized in a sequential fashion. the mon5?on8 channels are sampled depending on the state of the en5to8b bit in table 02h, register 89h. if the bit is programmed to logic 0, the adc cycles through temperature, v cc , and mon1?on4 (figure 5). if the bit is programmed to logic 1, all 10 channels are digitized, including chan- nels mon5?on8 (figure 6). in this mode (en5to8b = 0), each of mon5?on8 is sampled on alternate cycles, as shown in figure 5. the total time required to convert one set of channels is the sequential adc cycle time, t frame1 or t frame2 (see figure 6). table 3. adc default monitor ranges signal +fs signal +fs hex -fs signal -fs hex temperature (c) 127.996 7fff -128 8000 v cc (v) 6.5528 fff8 0 0000 mon1Cmon8 (v) 2.4997 fff8 0 0000 v cc mon1 mon2 mon3 mon4 mon5 mon6 temp v cc mon1 mon2 mon3 mon4 mon7 mon8 temp t frame2 t frame2 figure 6. adc timing with en5to8b = 1 temp v cc mon1 mon2 mon3 mon4 temp one adc cycle mon4 t frame1 figure 5. adc timing with en5to8b = 0 trip condition mclk (525khz) capture alarm m3qt alarm (unlatched) figure 4. m3qt timing
ds1875 right-shifting adc result if the weighting of the adc digital reading must con- form to a predetermined full-scale value defined by a standard? specification, then right-shifting can be used to adjust the predetermined full-scale analog measure- ment range while maintaining the weighting of the adc results. the ds1875? range is wide enough to cover all requirements; when the maximum input value is 1/2 the fs value, right-shifting can be used to obtain greater accuracy. for instance, the maximum voltage might be 1/8th the specified predetermined full-scale value, so only 1/8th the converter? range is used. an alternative is to calibrate the adc? full-scale range to 1/8th the readable predetermined full-scale value and use a right-shift value of 3. with this implementation, the resolution of the measurement is increased by a factor of 8, and because the result is digitally divided by 8 by right-shifting, the bit weight of the measurement still meets the standard? specification (i.e., sff-8472). the right-shift operation on the adc result is carried out based on the contents of right shift1/0 registers (table 02h, registers 8eh?fh). four analog channels, mon1?on4, have 3 bits each allocated to set the number of right-shifts. up to seven right-shift operations are allowed and are executed as a part of every con- version before the results are compared to the high and low alarm levels, or loaded into their corresponding measurement registers (table 01h, registers 62h?bh). this is true during the setup of internal cali- bration as well as during subsequent data conversions. transmit fault (tx-f) output the tx-f output has masking registers for the adc alarms and the qt alarms to select which comparisons cause it to assert. in addition, the fetg alarm is selec- table through the tx-f mask to cause tx-f to assert. all alarms, with the exception of fetg, only cause tx-f to remain active while the alarm condition persists. however, the tx-f latch bit can enable the tx-f output to remain active until it is cleared by the tx-f reset bit, tx-d, soft tx-d, or by power cycling the part. if the fetg output is configured to trigger tx-f, it indicates that the ds1875 is in shutdown and requires tx-d, soft tx-d, or cycling power to reset. only enabled alarms activate tx-f (see figure 7). table 4 shows tx-f as a function of tx-d and the alarm sources. table 4. tx-f as a function of tx-d and alarm sources v cc > v poa tx-d nonmasked tx-f alarm tx-f no x x 1 yes 0 0 0 yes 0 1 1 yes 1 x 0 tx-f latched operation tx-f nonlatched operation detection of tx-f fault tx-d or tx-f reset tx-f detection of tx-f fault tx-f figure 7. tx-f timing pon triplexer and sfp controller ______________________________________________________________________________________ 21
ds1875 pon triplexer and sfp controller 22 ______________________________________________________________________________________ safety shutdown (fetg) output the fetg output has masking registers (separate from tx-f) for the adc alarms and the qt alarms to select which comparisons cause it to assert. unlike tx-f, the fetg output is always latched. its output polarity is programmable to allow an external nmos or pmos to open during alarms to shut off the laser-diode current. if the fetg output triggers, indicating that the ds1875 is in shutdown, it requires tx-d, soft tx-d, or cycling power to be reset. under all conditions, when the ana- log outputs are reinitialized after being disabled, all the alarms with the exception of the v cc low adc alarm are cleared. the v cc low alarm must remain active to prevent the output from attempting to operate when inadequate v cc exists to operate the laser driver. once adequate v cc is present to clear the v cc low alarm, the outputs are enabled following the same sequence as the power-up sequence. as previously mentioned, the fetg is an output used to disable the laser current through a series nmos or pmos. this requires that the fetg output can sink or source current. because the ds1875 does not know if it should sink or source current before v cc exceeds v poa , which triggers the ee recall, this output is high impedance when v cc is below v poa (see the low- voltage operation section for details and diagram). the application circuit should use a pullup or pulldown resistor on this pin that pulls fetg to the alarm/shut- down state (high for a pmos, low for a nmos). once v cc is above v poa , the ds1875 pulls the fetg output to the state determined by the fetg dir bit (table 02h, register 89h). set fetg dir to 0 if an nmos is used and 1 if a pmos is used. determining alarm causes using the i 2 c interface to determine the cause of the tx-f or fetg alarm, the system processor can read the ds1875? alarm trap bytes (atb) through the i 2 c interface (table 01h, registers f8h?bh). the atb has a bit for each alarm. any time an alarm occurs, regardless of the mask bit? state, the ds1875 sets the corresponding bit in the atb. active atb bits remain set until written to 0s through the i 2 c interface. on power-up, the atb is 0s until alarms dictate otherwise. fetg causes additional alarms that make it difficult to determine the root cause of the problem. therefore, no updates are made to the atb when fetg occurs. i bias v mod detection of fetg fault t off t on t on t off tx-d t fetg:on fetg* *fetg dir = 0 t fetg:off figure 8. fetg/output disable timing (fault condition detected) table 5. fetg, mod, and bias outputs as a function of tx-d and alarm sources v cc > v poa tx-d nonmasked fetg alarm fetg mod and bias outputs yes 0 0 fetg dir enabled yes 0 1 fetg dir disabled yes 1 x fetg dir disabled
ds1875 die identification the ds1875 has an id hard-coded to its die. two regis- ters (table 02h, registers 86h?7h) are assigned for this feature. byte 86h reads 75h to identify the part as the ds1875; byte 87h reads the die revision. low-voltage operation the ds1875 contains two power-on reset (por) levels. the lower level is a digital por (v pod ) and the higher level is an analog por (v poa ). at startup, before the supply voltage rises above v poa , the outputs are dis- abled (fetg and bias outputs are high impedance, mod is low), all sram locations are low (including shadowed eeprom (see)), and all analog circuitry is disabled. when v cc reaches v poa , the see is recalled, and the analog circuitry is enabled. while v cc remains above v poa , the device is in its normal operat- ing state, and it responds based on its nonvolatile con- figuration. if during operation v cc falls below v poa but is still above v pod , the sram retains the see settings from the first see recall, but the device analog is shut down and the outputs are disabled. fetg is driven to its alarm state defined by the fetg dir bit (table 02h, register 89h). if the supply voltage recovers back above v poa , the device immediately resumes normal functioning. when the supply voltage falls below v pod , the device sram is placed in its default state and another see recall is required to reload the nonvolatile settings. the eeprom recall occurs the next time v cc exceeds v poa . figure 9 shows the sequence of events as the voltage varies. any time v cc is above v pod , the i 2 c interface can be used to determine if v cc is below the v poa level. this is accomplished by checking the rdyb bit in the status (lower memory, register 6eh) byte. rdyb is set when v cc is below v poa . when v cc rises above v poa , rdyb is timed (within 500?) to go to 0, at which point the part is fully functional. for all device addresses sourced from eeprom (table 02h, register 8ch), the default device address is a2h until v cc exceeds v poa , allowing the device address to be recalled from the eeprom. enhanced rssi monitoring (dual range functionality) the ds1875 offers a new feature to improve the accu- racy and range of mon3, which is most commonly used for monitoring rssi. this feature enables right- shifting (along with its gain and offset settings) when the input signal is below a set threshold (within the range that benefits using right-shifting) and then auto- matically disables right-shifting (recalling different gain and offset settings) when the input signal exceeds the threshold. also, to prevent ?hattering,?hysteresis pre- vents excessive switching between modes in addition to ensuring that continuity is maintained. dual range operation is enabled by default (factory programmed in eeprom). however, it can easily be disabled through the rssi_ff and rssi_fc bits. when dual range oper- ation is disabled, mon3 operates identically to the other mon channels, although featuring a differential input. v cc v poa v pod fetg see high impedance high impedance high impedance normal operation driven to fetg dir normal operation precharged to 0 precharged to 0 precharged to 0 recalled value recalled value driven to fetg dir normal operation driven to fetg dir see recall see recall figure 9. see timing pon triplexer and sfp controller ______________________________________________________________________________________ 23
ds1875 24 ______________________________________________________________________________________ dual-range functionality consists of two modes of opera- tion: fine mode and coarse mode. each mode is calibrat- ed for a unique transfer function, hence the term, dual range. table 6 highlights the registers related to mon3. fine mode is equivalent to the other mon channels. fine mode is calibrated using the gain, offset, and right-shift- ing registers at locations shown in table 6 and is ideal for relatively small analog input voltages. coarse mode is automatically switched to when the input exceeds the threshold (to be discussed in a subsequent paragraph). coarse mode is calibrated using different gain and offset registers, but lacks right-shifting (since coarse mode is only used on large input signals). the gain and offset registers for coarse mode are also shown in table 6. with the use of right-shifting, the fine mode full scale is programmed to (1/2n)th the coarse mode full scale. the ds1875 will now autorange to choose the range that gives the best resolution for the measurement. to elimi- nate chatter, 6.25% of hysteresis is applied when the input resides at the boundary of the two ranges. see figure 10. additional information for each of the registers can be found in the memory map section. dual range operation is transparent to the end user. the results of mon3 analog-to-digital conversions are still stored/reported in the same memory locations (68?9h, lower memory) regardless of whether the conversion was performed in fine mode or coarse mode. when the ds1875 is powered up, analog-to-digital con- versions begin in a round-robin fashion. every mon3 timeslice begins with a fine mode analog-to-digital con- version (using fine mode? gain, offset, and right-shift- ing settings). see the flowchart in figure 10. then, depending on whether the last mon3 timeslice resulted in a coarse-mode conversion and also depending on the value of the current fine conversion, decisions are made whether to use the current fine-mode conversion result or to make an additional conversion (within the same mon3 timeslice), using coarse mode (using coarse mode? gain and offset settings, and no right- shifting) and reporting the coarse-mode result. the flowchart also illustrates how hysteresis is implement- ed. the fine-mode conversion is compared to one of mon3 timeslice end of mon3 timeslice perform fine- mode conversion report fine conversion result report coarse conversion result did prior mon3 timeslice result in a coarse conversion? (last rssi = 1?) last rssi = 0 last rssi = 1 was current fine- mode conversion 93.75% of fs? perform coarse- mode conversion did current fine- mode conversion reach max? n y y y n n figure 10. rssi flowchart table 6. mon3 configuration registers register fine mode coarse mode mon3 fine scale 98hC99h, table 02h 9chC9dh, table 02h mon3 fine offset a8hCa9h, table 02h achCadh, table 02h right shift0/1 8ehC8fh, table 02h config (rssi_fc, rssi_ff bits) 89h, table 02h mon3 value 68hC69h, lower memory pon triplexer and sfp controller
ds1875 two thresholds. the actual threshold values are a func- tion of the number of right-shifts being used. table 7 shows the threshold values for each possible number of right-shifts. the rssi_ff and rssi_fc (table 02h, register 89h) bits are used to force fine-mode or coarse-mode con- versions, or to disable the dual-range functionality. dual-range functionality is enabled by default (both rssi_fc and rssi_ff are factory programmed to 0 in eeprom). it can be disabled by setting rssi_fc to 0 and rssi_ff to 1. these bits are also useful when cali- brating mon3. for additional information, see the memory map section. pwm controller the ds1875 has a pwm controller that, when used with external components, generates a low-noise, high-volt- age output to bias apds in optical receivers. the achievable boost voltage is determined by the external component selection. figure 12 shows a typical schematic. selection of switching frequency, external inductor, capacitors, resistor network, switching fet, and switch diode determine the performance of the dc-dc converter. the pwm controller can be config- ured in boost or buck mode. both modes require an external nmos or npn transistor. the ds1875 pwm controller consists of several sec- tions used to create a pwm signal to drive a dc-dc converter. figure 11 is a block diagram of the ds1875 pwm controller. following is a description of each block in the pwm controller and some guidelines for selecting components for the dc-dc converter. the pwm dac is used to set the desired output voltage of the dc-dc converter section. the feedback from the dc-dc converter is compared to the output from the pwm dac by an error amplifier. if the fb level is less table 7. mon3 hysteresis threshold values * this is the minimum reported coarse-mode conversion. no. of right- shifts fine mode (max) coarse mode (min*) 0 fff8h f000h 1 7ffch 7800h 2 3ffeh 3c00h 3 1fffh 1e00h 4 0fffh 0f00h 5 07ffh 0780h 6 03ffh 03c0h 7 01ffh 01e0h mux pwm dac 8-bit 0 to 1.25v 10 a manual i 2 c control pwm_fr[1:0] ramp 90% duty cycle osc sw comp m3qt 1.9v 1.0v fb pwm en pwm controller gate driver 90% max duty cycle pwm dac table 02h register feh pwm dac temperature- referenced lut table 07h voltage clamp high = 2.1v low = 0.8v error amplifier 10 a ds1875 figure 11. pwm controller diagram pon triplexer and sfp controller ______________________________________________________________________________________ 25
ds1875 pon triplexer and sfp controller 26 ______________________________________________________________________________________ than the pwm dac level, the error amplifier increases the level on the comp pin. the level on the comp pin is compared to the signal from the oscillator and ramp generator to set the duty cycle that is input to the gate driver and maximum duty-cycle limiting block. an increase on the comp pin increases the duty cycle. conversely, if fb is greater than the pwm dac, the level on comp is decreased, decreasing the duty cycle. the gate driver and maximum duty-cycle block is used to limit the maximum duty cycle of the pwm controller to 90%. this block also disables the pwm dri- ver if an m3qt has resulted from the apd current exceeding a desired limit. the output from the pwm dac is used to control the output voltage of the dc-dc converter. the values for the pwm dac are recalled from the table 07h, which is a temperature-indexed lut. the temperature-indexed value from the lut is written to the pwm dac register (table 02h, register feh), which updates the setting of the pwm dac. the pwm dac can also be operated in a manual mode by disabling the automatic updating from the lut. this is done by clearing the pwm en bit (table 02h, register 80h, bit 5). the pwm dac full- scale output is 1.25v with 8 bits of resolution. when designing the feedback for the dc-dc converter sec- tion, the user needs to make sure that the desired level applied to the fb pin is in this range. the comp pin is driven by the error amplifier compar- ing the pwm dac to the dc-dc converter feedback signal at the fb pin. the error amplifier can sink and source 10?. an external resistor and capacitor con- nected to the comp pin determine the rate of change the comp pin. the resistor provides an initial step when the current from the error amplifier changes. the capacitor determines how quickly the comp pin charges to the desired level. the comp pin has inter- nal voltage clamps that limit the voltage level to a mini- mum of 0.8v and a maximum of 2.1v. the oscillator and ramp generator create a ramped sig- nal. the frequency of this signal can be 131.25khz, 262.5khz, 525khz, or 1050khz and is set by the pwm_fr[1:0] bits (table 02h, register 88h, bits 5:4). the low level and high level for the ramped signal are approximately 1.0v and 1.9v, respectively. the ramped signal is compared to the voltage level on the comp pin to determine the duty cycle that is input to the gate driver and duty-cycle limiting block. when comp is clamped low at 0.8v, below the level of the ramped signal, the comparator outputs a 0% duty- cycle signal to the gate driver block. when comp is clamped at 2.1v, above the level of the ramped signal, the comparator outputs a 100% duty-cycle signal to the gate driver and duty-cycle limiting block. the duty- cycle liming block is used to limit the duty cycle of the pwm signal from the sw pin to 90%. the pwm controller is designed to protect expensive apds against adverse operating conditions while pro- viding optimal bias. the pwm controller monitors photo- diode current to protect apds under avalanche conditions using the mon3 quick trip. a voltage level that is proportional to the apd current can be input to the mon3 pin. when this voltage exceeds the level set by the m3qt dac (table 02h, register c3h), pulses from the pwm controller are blocked until the fault is cleared. the quick trip can also toggle the digital output d2. d2 can be connected to an external fet to quickly discharge the dc-dc converter filter capacitors. inductor selection optimum inductor selection depends on input voltage, output voltage, maximum output current, switching fre- quency, and inductor size. inductors are typically spec- ified by their inductance (l), peak current (ipk), and resistance (lr). the inductance value is given by: where: v in = dc-dc converter input voltage v out = output of dc-dc converter i out(max) = maximum output current delivered t = time period of switching frequency (seconds) d = duty cycle = estimated power conversion efficiency the equation for inductance factors in conversion effi- ciency. for inductor calculation purposes, an of 0.5 to 0.75 is usually suitable. for example, to obtain an output of 80v with a load cur- rent of 1.0ma from an input voltage of 5.0v using the maximum 90% duty cycle and frequency of 1050khz (t = 952ns), and assuming an efficiency of 0.5, the pre- vious equation yields an l of 120?, so a 100? induc- tor would be a suitable value. the peak inductor current is given by: i vdt l pk in = l vdt iv in out max out = 22 2 ()
ds1875 stability and compensation component selection the components connected to the comp pin (r comp and c comp ) introduce a pole and zero that are neces- sary for stable operation of the pwm controller (figure 12). the dominant pole, pole1, is formed by the output impedance of the error amplifier (r ea ) and c comp . the zero formed by the components on comp, zero1, is selected to cancel pole2 formed by the output filter cap c3 and output load r load . the additional pole, pole3, formed by r1 and c3 should be at least a decade past the crossover frequency to not affect sta- bility. the following formulas can be used to calculate the poles and zero for the application shown in figure 12. pole1 (dominant pole) = 1/(2 r ea c comp ) zero1 (compensation zero) = 1/(2 r comp c comp ) pole2 (output load pole) = pole3 (output filter pole) = 1/(2 r1 c3) the dc open-loop gain is given by: where: r ea = 260m g m = 425? r load = parallel combination of feedback network and load resistance v out = output of dc-dc converter v in = dc-dc converter input voltage v fb = feedback voltage at the fb pin t = time period of switching frequency (seconds) l = inductor value (henries) dac1 output the dac1 output has a full-scale 2.5v range with 8 bits of resolution, and is programmed through the i 2 c inter- face. the dac1 setting is nonvolatile and password-2 (pw2) protected. m4dac output the m4dac output has a full-scale 2.5v range with 8 bits of resolution, and is controlled by an lut indexed by the mon4 voltage. the m4dac lut (table 06h) is nonvolatile and pw2 protected. see the memory organization section for details. the recalled value is either 16-bit or 32-bit depending on bits dbl_sb and up_lowb in table 02h, register c7h. digital i/o pins five digital i/o pins are provided for additional monitor- ing and control. by default the losi pin is used to con- vert a standard comparator output for loss of signal (losi) to an open-collector output. this means the mux shown on the block diagram by default selects the losi pin as the source for the d0 output transistor. the level of the d0 pin can be read in the status byte (lower memory, register 6eh) as the los status bit. the los status bit reports back the logic level of the d0 pin, so an external pullup resistor must be provided for this pin to output a high level. the losi signal can be inverted before driving the open-drain output transistor using the xor gate provided. the mux los allows the d0 pin to be used identically to the d1, d2, and d3 pins. however, the mux setting (stored in the eeprom) does not take effect until v cc > v poa , allowing the eep- rom to recall. this requires the losi pin to be ground- ed for d0 to act identical to the d1, d2, and d3 pins. digital pins d1, d2, and d3 can be used as inputs or outputs. external pullup resistors must be provided to realize high-logic levels. the din byte indicates the logic levels of these input pins (lower memory, register 79h), and the open-drain outputs can be controlled using the dout byte (lower memory, register 78h). when v cc < v poa , these outputs are high impedance. once v cc v poa , the outputs go to the power-on default state stored in the dpu byte (table 02h, register c0h). the eeprom-determined default state of the pin can be modified with pw2 access. after the default state has been recalled, the sram registers controlling outputs can be modified without password access. this allows the outputs to be used to control serial interfaces without wearing out the default eeprom setting. d2 can be configured as the output of a quick-trip mon- itor for mon3. the main application is to quickly shut down the pwm converter and discharge the voltage created by the converter. this is shown in the typical application circuit. aol g r vv vv vv mea fb in out in out in = ? ? 085 2 2 . vv rt l out load ? ? ? ? ? ? 2 2 1 223 ? ? + () vv vv r cc out in out in load pon triplexer and sfp controller ______________________________________________________________________________________ 27
ds1875 pon triplexer and sfp controller 28 ______________________________________________________________________________________ sw current sink fb comp ds1875 figure 14. pwm controller current-sink output configuration sw voltage output fb comp ds1875 figure 13. pwm controller voltage output configuration comp d2 mon3 apd overload quick trip sw fb v in c1 q1 c2 r2 r3 rmon r4 l1 c comp r comp d1 r1 v out 3.3v c4 c3 tia rosa apd ds1875 max4007 figure 12. pwm controller typical apd bias circuit
ds1875 scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low figure 15. i 2 c timing diagram i 2 c communication i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device gener- ates scl clock pulses and start and stop condi- tions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac- tive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 15 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 15 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated start conditions are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a normal start condition. see figure 15 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold-time requirements (figure 15). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl dur- ing a bit read (figure 15). the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl- edge- ment (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a one dur- ing the 9th bit. timing for the ack and nack is identical to all other bit writes (figure 15). an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. pon triplexer and sfp controller ______________________________________________________________________________________ 29
ds1875 pon triplexer and sfp controller 30 ______________________________________________________________________________________ byte write: a byte write consists of 8 bits of infor- mation transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledge- ment from the slave to the master. the 8 bits trans- mitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information trans- fer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte sent immedi- ately following a st art condition. the slave address byte contains the slave address in the most signifi- cant 7 bits and the r/ w bit in the least significant bit. the ds1875 responds to two slave addresses. the auxiliary memory always responds to a fixed i 2 c slave address, a0h. the lower memory and tables 00h?8h respond to i 2 c slave addresses that can be configured to any value between 00h?eh using the device address byte (table 02h, register 8ch). the user also must set the asel bit (table 02h, register 89h) for this address to be active. by writ- ing the correct slave address with r/ w = 0, the mas- ter indicates it will write data to the slave. if r/ w = 1, the master reads data from the slave. if an incorrect slave address is written, the ds1875 assumes the master is communicating with another i 2 c device and ignores the communications until the next start condition is sent. if the main device? slave address is programmed to be a0h, access to the auxiliary memory is disabled. memory address: during an i 2 c write operation to the ds1875, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c protocol writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/w = 0), write the memory address, write the byte of data, and generate a stop condition. the master must read the slave? acknowledgement dur- ing all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start con- dition, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition. the ds1875 writes 1 to 8 bytes (one page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memo- ry address before each data byte is sent. the address counter limits the write to one 8-byte page (one row of the memory map). attempts to write to additional pages of memory without sending a stop condition between pages result in the address counter wrapping around to the beginning of the present row. example: a 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three ?onsecutive?addresses. the result is that address- es 06h and 07h contain 11h and 22h, respectively, and the third data byte, 33h, is written to address 00h. to prevent address wrapping from occurring, the master must send a stop condition at the end of the page, then wait for the bus-free or eeprom write time to elapse. then the master can generate a new start condition and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time a eeprom location is written, the ds1875 requires the eeprom write time (t w ) after the stop condition to write the con- tents of the page to eeprom. during the eeprom write time, the device does not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the ds1875, which allows the next page to be written as soon as the ds1875 is ready to receive the data. the alternative to acknowledge polling is to wait for a maximum period of t w to elapse before attempting to write again to the ds1875. eeprom write cycles: when eeprom writes occur to the memory, the ds1875 writes the whole eeprom memory page, even if only a single byte on the page was modified. writes that do not modify all 8 bytes on the page are allowed and do not cor- rupt the remaining bytes of memory on the same page. because the whole page is written, bytes that
ds1875 were not modified during the transaction are still subject to a write cycle. this can result in a whole page being worn out over time by writing a single byte repeatedly. writing a page one byte at a time wears the eeprom out eight times faster than writ- ing the entire page at once. the ds1875? eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case temperature. it can handle approxi- mately 10 times that many writes at room tempera- ture. writing to sram-shadowed eeprom memory with seeb = 1 does not count as a eeprom write cycle when evaluating the eeprom? estimated life- time. reading a single byte from a slave: unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the address pointer to a particular value. to do this, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. memory map memory organization the ds1875 features 10 separate memory tables that are internally organized into 8-byte rows. the lower memory is addressed from 00h to 7fh and contains alarm and warning thresholds, flags, masks, several control registers, password entry area (pwe), and the table select byte. table 00h contains conversion results for mon5 through mon8. table 01h primarily contains user eeprom (with pw1 level access) as well as some alarm and warning status bytes. table 02h is a multifunction space that contains config- uration registers, scaling and offset values, passwords, interrupt registers, as well as other miscellaneous con- trol bytes. table 03h is strictly user eeprom that is protected by a pw2-level password. table 04h contains a temperature-indexed lut for control of the modulation voltage. the modulation lut can be programmed in 2? increments over the -40? to +102? range. access to this register is protected by a pw2-level password. table 05h contains a temperature-indexed lut that allows the apc set point to change as a function of temperature to compensate for tracking error (te). the apc lut has 36 entries that determine the apc setting in 4? windows between -40? to 100?. access to this register is protected by a pw2-level password. table 06h contains a mon4-indexed lut for control of the m4dac voltage. the mon4 lut has 32 entries that are configurable to act as one 32-entry lut of two 16- byte luts. when configured as one 32-byte lut, each entry corresponds to an increment of 1/32 the full scale. when configured as two 16-byte luts, the first 16 bytes and the last 16 bytes each correspond to 1/16 full scale. either of the two sections is selected with a sep- arate configuration bit. access to this register is pro- tected by a pw2-level password. table 07h contains a temperature-indexed lut for control of the pwm reference voltage (integration of fb input). the pwm lut has 36 entries that determine the apc setting in 4? windows between -40? to +100?. access to this register is protected by a pw2-level password. table 08h contains a temperature-indexed lut for control of the bias current. the bias lut can be pro- grammed in 2? increments over the 40? to +102? range. access to this register is protected by a pw2- level password. auxiliary memory (device a0h) contains 256 bytes of ee memory accessible from address 00h?fh. it is selected with the device address of a0h. see the register descriptions section for a more com- plete detail of each byte? function, as well as for read/write permissions for each byte. pon triplexer and sfp controller ______________________________________________________________________________________ 31
ds1875 pon triplexer and sfp controller 32 ______________________________________________________________________________________ shadowed eeprom many nv memory locations (listed within the register descriptions section) are actually shadowed eeprom that are controlled by the seeb bit in table 02h, byte 80h. the ds1875 incorporates shadowed-eeprom memory locations for key memory addresses that can be written many times. by default the shadowed-eeprom bit, seeb, is not set and these locations act as ordinary eeprom. by setting seeb, these locations function like sram cells, which allow an infinite number of write cycles without concern of wearing out the eeprom. this also eliminates the requirement for the eeprom write time, t wr . because changes made with seeb dis- abled do not affect the eeprom, these changes are not retained through power cycles. the power-on value is the last value written with seeb enabled. this func- tion can be used to limit the number of eeprom writes during calibration or to change the monitor thresholds periodically during normal operation helping to reduce the number of times eeprom is written. the memory map description indicates which locations are shad- owed eeprom. atb misc. control bits eeprom ffh i 2 c slave address a0h (fixed) 00h ffh 80h f8h pw1 level access eeprom (120 bytes) table 01h auxiliary memory ffh f7h d7h f7h ffh 80h 89h no memory mon5?on8 conv table 00h 88h 80h f8h d8h configuration and control no memory table 02h ffh 80h pw2 level access eeprom (128 bytes) table 03h c7h 80h modulation lut table 04h a3h 80h apc te lut table 05h 9fh 80h m4dac lut table 06h dec 0 hex 0h dec 128 hex 80h 255 ffh 255 ffh a3h 80h pwm ref lut table 07h c7h 80h bias open-loop lut table 08h table select byte password entry (pwe) (7bh?h) pw2 level access eeprom (48 bytes) digital diagnostic functions digital diagnostic functions 7fh 7ah 5fh 2fh i 2 c slave address a2h (default) 00h 30h 60h lower memory figure 16. memory map
ds1875 this register map shows each byte/word (2 bytes) in terms of the row it is on in the memory. the first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. each subsequent byte on the row is one/two memory locations beyond the previous byte/word? address. a total of 8 bytes are present on each row. for more information about each of these bytes, see the corresponding register description. register descriptions lower memory register map lower memory word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00 <1> threshold 0 temp alarm hi temp alarm lo temp warn hi temp warn lo 08 <1> threshold 1 v cc alarm hi v cc alarm lo v cc warn hi v cc warn lo 10 <1> threshold 2 mon1 alarm hi mon1 alarm lo mon1 warn hi mon1 warn lo 18 <1> threshold 3 mon2 alarm hi mon2 alarm lo mon2 warn hi mon2 warn lo 20 <1> threshold 4 mon3 alarm hi mon3 alarm lo mon3 warn hi mon3 warn lo 28 <1> threshold 5 mon4 alarm hi mon4 alarm lo mon4 warn hi mon4 warn lo 30 <1> pw2 ee ee ee ee ee ee ee ee ee 38 <1> pw2 ee ee ee ee ee ee ee ee ee 40 <1> pw2 ee ee ee ee ee ee ee ee ee 48 <1> pw2 ee ee ee ee ee ee ee ee ee 50 <1> pw2 ee ee ee ee ee ee ee ee ee 58 <1> pw2 ee ee ee ee ee ee ee ee ee 60 <2> adc values 0 temp value v cc value mon1 value mon2 value 68 <0> adc values 1 <2> mon3 value <2> mon4 value <2> reserved <0> status <3> update 70 <2> alarm/ warn alarm 3 alarm 2 alarm 1 alarm 0 warn 3 warn 2 reserved reserved 78 <0> table select <5> dout <2> din <6> reserved <6> pwe msb <6> pwe lsb <5> tbl sel access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 pon triplexer and sfp controller ______________________________________________________________________________________ 33
ds1875 pon triplexer and sfp controller 34 ______________________________________________________________________________________ table 00h word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <2> adc values 2 mon5 value mon6 value mon7 value mon8 value 88Cff empty empty empty empty empty empty empty empty empty access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 00h register map
ds1875 table 01h (pw1) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <7> pw1 ee ee ee ee ee ee ee ee ee 88 <7> pw1 ee ee ee ee ee ee ee ee ee 90 <7> pw1 ee ee ee ee ee ee ee ee ee 98 <7> pw1 ee ee ee ee ee ee ee ee ee a0 <7> pw1 ee ee ee ee ee ee ee ee ee a8 <7> pw1 ee ee ee ee ee ee ee ee ee b0 <7> pw1 ee ee ee ee ee ee ee ee ee b8 <7> pw1 ee ee ee ee ee ee ee ee ee c0 <7> pw1 ee ee ee ee ee ee ee ee ee c8 <7> pw1 ee ee ee ee ee ee ee ee ee d0 <7> pw1 ee ee ee ee ee ee ee ee ee d8 <7> pw1 ee ee ee ee ee ee ee ee ee e0 <7> pw1 ee ee ee ee ee ee ee ee ee e8 <7> pw1 ee ee ee ee ee ee ee ee ee f0 <7> pw1 ee ee ee ee ee ee ee ee ee f8 <11> alarm trap alarm 3 alarm 2 alarm 1 alarm 0 warn 3 warn 2 reserved reserved table 01h register map access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 pon triplexer and sfp controller ______________________________________________________________________________________ 35
ds1875 pon triplexer and sfp controller 36 ______________________________________________________________________________________ table 02h (pw2) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <0> config 0 <8> mode <4> tindex <4> mod dac <4> apc dac <4> vindex <4> m4dac <10> device id <10> device ver 88 <8> config 1 sample rate config reserved mod ranging device address comp ranging rshift 1 rshift 0 90 <8> scale 0 reserved v cc scale mon1 scale mon2 scale 98 <8> scale 1 mon3 fine scale mon4 scale mon3 coarse scale reserved a0 <8> offset 0 reserved v cc offset mon1 offset mon2 offset a8 <8> offset 1 mon3 fine offset mon4 offset mon3 coarse offset internal temp offset * b0 <9> pwd value pw1 msw pw1 lsw pw2 msw pw2 lsw b8 <8> interrupt fetg enable 1 fetg enable 0 tx-f enable 1 tx-f enable 0 htxp ltxp hbias max bias c0 <8> cntl out dpu reserved reserved m3qt dac dac1 reserved reserved m4 lut cntl c8 <8> scale 2 mon5 scale mon6 scale mon7 scale mon8 scale d0 <8> offset 1 mon5 offset mon6 offset mon7 offset mon8 offset d8Cf7 empty empty empty empty empty empty empty empty empty f8 <0> man bias <4> man bias 1 <4> man bias 0 <4> man_ cntl <10> bias dac 1 <10> bias dac 0 bias ol pwm dac reserved table 02h register map access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 * the final result must be xored with bb40h before writing to this register.
ds1875 table 03h (pw2) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> pw2 ee ee ee ee ee ee ee ee ee 88 <8> pw2 ee ee ee ee ee ee ee ee ee 90 <8> pw2 ee ee ee ee ee ee ee ee ee 98 <8> pw2 ee ee ee ee ee ee ee ee ee a0 <8> pw2 ee ee ee ee ee ee ee ee ee a8 <8> pw2 ee ee ee ee ee ee ee ee ee b0 <8> pw2 ee ee ee ee ee ee ee ee ee b8 <8> pw2 ee ee ee ee ee ee ee ee ee c0 <8> pw2 ee ee ee ee ee ee ee ee ee c8 <8> pw2 ee ee ee ee ee ee ee ee ee d0 <8> pw2 ee ee ee ee ee ee ee ee ee d8 <8> pw2 ee ee ee ee ee ee ee ee ee e0 <8> pw2 ee ee ee ee ee ee ee ee ee e8 <8> pw2 ee ee ee ee ee ee ee ee ee f0 <8> pw2 ee ee ee ee ee ee ee ee ee f8 <8> pw2 ee ee ee ee ee ee ee ee ee table 03h register map access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 pon triplexer and sfp controller ______________________________________________________________________________________ 37
ds1875 pon triplexer and sfp controller 38 ______________________________________________________________________________________ table 04h (modulation lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut4 mod mod mod mod mod mod mod mod 88 <8> lut4 mod mod mod mod mod mod mod mod 90 <8> lut4 mod mod mod mod mod mod mod mod 98 <8> lut4 mod mod mod mod mod mod mod mod a0 <8> lut4 mod mod mod mod mod mod mod mod a8 <8> lut4 mod mod mod mod mod mod mod mod b0 <8> lut4 mod mod mod mod mod mod mod mod b8 <8> lut4 mod mod mod mod mod mod mod mod c0 <8> lut4 mod mod mod mod mod mod mod mod access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 05h (apc te lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 88 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 90 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 98 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref a0 <8> lut5 apc ref apc ref apc ref apc ref reserved reserved reserved reserved table 05h register map access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 04h register map
ds1875 table 06h (m4dac lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut6 m4dac m4dac m4dac m4dac m4dac m4dac m4dac m4dac 88 <8> lut6 m4dac m4dac m4dac m4dac m4dac m4dac m4dac m4dac 90 <8> lut6 m4dac m4dac m4dac m4dac m4dac m4dac m4dac m4dac 98 <8> lut6 m4dac m4dac m4dac m4dac m4dac m4dac m4dac m4dac access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 07h (pwm reference lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut7 pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref 88 <8> lut7 pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref 90 <8> lut7 pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref 98 <8> lut7 pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref pwm ref a0 <8> lut7 pwm ref pwm ref pwm ref pwm ref reserved reserved reserved reserved table 07h register map access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 06h register map pon triplexer and sfp controller ______________________________________________________________________________________ 39
ds1875 pon triplexer and sfp controller 40 ______________________________________________________________________________________ table 08h (bias open-loop lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut8 bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol 88 <8> lut8 bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol 90 <8> lut8 bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol 98 <8> lut8 bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol a0 <8> lut8 bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol a8 <8> lut8 bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol b0 <8> lut8 bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol b8 <8> lut8 bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol c0 <8> lut8 bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol bias_ol table 08h register map access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1
ds1875 auxiliary memory (a0h) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00 <5> aux ee ee ee ee ee ee ee ee ee 08 <5> aux ee ee ee ee ee ee ee ee ee 10 <5> aux ee ee ee ee ee ee ee ee ee 18 <5> aux ee ee ee ee ee ee ee ee ee 20 <5> aux ee ee ee ee ee ee ee ee ee 28 <5> aux ee ee ee ee ee ee ee ee ee 30 <5> aux ee ee ee ee ee ee ee ee ee 38 <5> aux ee ee ee ee ee ee ee ee ee 40 <5> aux ee ee ee ee ee ee ee ee ee 48 <5> aux ee ee ee ee ee ee ee ee ee 50 <5> aux ee ee ee ee ee ee ee ee ee 58 <5> aux ee ee ee ee ee ee ee ee ee 60 <5> aux ee ee ee ee ee ee ee ee ee 68 <5> aux ee ee ee ee ee ee ee ee ee 70 <5> aux ee ee ee ee ee ee ee ee ee 78 <5> aux ee ee ee ee ee ee ee ee ee 80 <5> aux ee ee ee ee ee ee ee ee ee 88 <5> aux ee ee ee ee ee ee ee ee ee 90 <5> aux ee ee ee ee ee ee ee ee ee 98 <5> aux ee ee ee ee ee ee ee ee ee a0 <5> aux ee ee ee ee ee ee ee ee ee a8 <5> aux ee ee ee ee ee ee ee ee ee b0 <5> aux ee ee ee ee ee ee ee ee ee b8 <5> aux ee ee ee ee ee ee ee ee ee c0 <5> aux ee ee ee ee ee ee ee ee ee c8 <5> aux ee ee ee ee ee ee ee ee ee d0 <5> aux ee ee ee ee ee ee ee ee ee d8 <5> aux ee ee ee ee ee ee ee ee ee e0 <5> aux ee ee ee ee ee ee ee ee ee e8 <5> aux ee ee ee ee ee ee ee ee ee f0 <5> aux ee ee ee ee ee ee ee ee ee f8 <5> aux ee ee ee ee ee ee ee ee ee auxiliary a0h memory register map access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1875 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 pon triplexer and sfp controller ______________________________________________________________________________________ 41
ds1875 pon triplexer and sfp controller 42 ______________________________________________________________________________________ lower memory, register 02h to 03h: temp alarm lo lower memory, register 06h to 07h: temp warn lo lower memory register descriptions lower memory, register 00h to 01h: temp alarm hi lower memory, register 04h to 05h: temp warn hi factory default 7fffh read access all write access pw2 memory type nonvolatile (see) 00h, 04h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 01h, 05h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 temperature measurement updates above this twos complement threshold set its corresponding alarm or warning bit. temperature measurement updates equal to or below this threshold clear its alarm or warning bit. factory default 8000h read access all write access pw2 memory type nonvolatile (see) 02h, 06h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 03h, 07h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 temperature measurement updates below this twos complement threshold set its corresponding alarm or warning bit. temperature measurement updates equal to or above this threshold clear its alarm or warning bit.
ds1875 lower memory, register 08h to 09h: v cc alarm hi lower memory, register 0ch to 0dh: v cc warn hi lower memory, register 10h to 11h: mon1 alarm hi lower memory, register 14h to 15h: mon1 warn hi lower memory, register 18h to 19h: mon2 alarm hi lower memory, register 1ch to 1dh: mon2 warn hi lower memory, register 20h to 21h: mon3 alarm hi lower memory, register 24h to 25h: mon3 warn hi lower memory, register 28h to 29h: mon4 alarm hi lower memory, register 2ch to 2dh: mon4 warn hi factory default ffffh read access all write access pw2 memory type nonvolatile (see) 08h, 0ch, 10h, 14h, 18h, 1ch, 20h, 24h, 28h, 2ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 09h, 0dh, 11h, 15h, 19h, 1dh, 21h, 25h, 29h, 2dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. voltage measurements equal to or below this threshold clear its alarm or warning bit. pon triplexer and sfp controller ______________________________________________________________________________________ 43
ds1875 pon triplexer and sfp controller 44 ______________________________________________________________________________________ factory default 0000h read access all write access pw2 memory type nonvolatile (see) 0ah, 0eh, 12h, 16h, 1ah, 1eh, 22h, 26h, 2ah, 2eh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0bh, 0fh, 13h, 17h, 1bh, 1fh, 23h, 27h, 2bh, 2fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. voltage measurements equal to or above this threshold clear its alarm or warning bit. lower memory, register 0ah to 0bh: v cc alarm lo lower memory, register 0eh to 0fh: v cc warn lo lower memory, register 12h to 13h: mon1 alarm lo lower memory, register 16h to 17h: mon1 warn lo lower memory, register 1ah to 1bh: mon2 alarm lo lower memory, register 1eh to 1fh: mon2 warn lo lower memory, register 22h to 23h: mon3 alarm lo lower memory, register 26h to 27h: mon3 warn lo lower memory, register 2ah to 2bh: mon4 alarm lo lower memory, register 2eh to 2fh: mon4 warn lo
ds1875 lower memory, register 30h to 5fh: pw2 ee factory default 00h read access all write access pw2 memory type nonvolatile (ee) 30h to 5fh ee ee ee ee ee ee ee ee bit 7 bit 0 pw2 level access-controlled eeprom. factory default 0000h read access all write access n/a memory type volatile 60h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 61h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 signed twos complement direct-to-temperature measurement. lower memory, register 60h to 61h: temp value pon triplexer and sfp controller ______________________________________________________________________________________ 45
ds1875 pon triplexer and sfp controller 46 ______________________________________________________________________________________ power-on value 0000h read access all write access n/a memory type volatile 62h, 64h, 66h, 68h, 6ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 63h, 65h, 67h, 69h, 6bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 left-justified unsigned voltage measurement. power-on value 00h read access all write access n/a memory type 6ch, 6dh 0 0 0 0 0 0 0 0 bit 7 bit 0 these registers are reserved. the value when read is 00h. lower memory, register 62h to 63h: v cc value lower memory, register 64h to 65h: mon1 value lower memory, register 66h to 67h: mon2 value lower memory, register 68h to 69h: mon3 value lower memory, register 6ah to 6bh: mon4 value lower memory, register 6ch to 6d: reserved
ds1875 lower memory, register 6eh: status power-on value x000 0 xxxb read access all write access see below memory type volatile write access n/a all n/a all all n/a n/a n/a 6eh fetg status soft fetg reserved tx-f reset soft tx-d tx-f status los status rdyb bit 7 bit 0 bit 7 fetg status: reflects the active state of fetg. the fetg dir bit in table 02h, register 89h defines the polarity of fetg. 0 = normal operation. bias and modulation outputs are enabled. 1 = the fetg output is active. bias and modulation outputs are disabled. bit 6 soft fetg: 0 = (default) 1 = forces the bias and modulation outputs to their off state and assert the fetg output. bit 5 reserved (default = 0) bit 4 tx-f reset: 0 = (default) 1 = resets the latch for the tx-f output. this bit is self-clearing after resetting tx-f. bit 3 soft tx-d: this bit allows a software control that is identical to the tx-d pin. see the bias and mod output as a function of transmit disable (tx-d) section for further information. its value is wired-ored with the logic value of the tx-d pin. 0 = internal tx-d signal is equal to the external tx-d pin. 1 = internal tx-d signal is high. bit 2 tx-f status: reflects the active state of the tx-f pin. 0 = tx-f pin is not active. 1 = tx-f pin is active. bit 1 los status: loss of signal. reflects the logic level of the losi input pin. 0 = losi is logic-low. 1 = losi is logic-high. bit 0 rdby: ready bar. 0 = v cc is above poa. 1 = v cc is below poa and/or too low to communicate over the i 2 c bus. pon triplexer and sfp controller ______________________________________________________________________________________ 47
ds1875 pon triplexer and sfp controller 48 ______________________________________________________________________________________ power-on value 00h read access all write access all + ds1875 hardware memory type volatile 6fh temp rdy vcc rdy mon1 rdy mon2 rdy mon3 rdy mon4 rdy mon5/7 rdy mon6/8 rdy bit 7 bit 0 update of completed conversions. at power-on, these bits are cleared and are set as each conversion is completed. these bits can be cleared so that a completion of a new conversion is verified. lower memory, register 6fh: update
ds1875 power-on value 10h read access all write access n/a memory type volatile 70h temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 bit 7 temp hi: high alarm status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 temp lo: low alarm status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 vcc hi: high alarm status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 vcc lo: low alarm status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit 3 mon1 hi: high alarm status for mon1 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 2 mon1 lo: low alarm status for mon1 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 1 mon2 hi: high alarm status for mon2 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 0 mon2 lo: low alarm status for mon2 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. lower memory, register 70h: alarm 3 pon triplexer and sfp controller ______________________________________________________________________________________ 49
ds1875 pon triplexer and sfp controller 50 ______________________________________________________________________________________ power-on value 00h read access all write access n/a memory type volatile 71h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit 7 bit 0 bit 7 mon3 hi: high alarm status for mon3 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 mon3 lo: low alarm status for mon3 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 mon4 hi: high alarm status for mon4 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 mon4 lo: low alarm status for mon4 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bits 3:0 reserved lower memory, register 71h: alarm 2
ds1875 lower memory, register 72h: alarm 1 power-on value 00h read access all write access n/a memory type volatile 72h reserved reserved reserved reserved bias hi reserved txp hi txp lo bit 7 bit 0 bits 7:4 reserved bit 3 bias hi: high alarm status bias; fast comparison. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bit 2 reserved bit 1 txp hi: high alarm status txp; fast comparison. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bit 0 txp lo: low alarm status txp; fast comparison. 0 = (default) last comparison was above threshold setting. 1 = last comparison was below threshold setting. lower memory, register 73h: alarm 0 power-on value 00h read access all write access n/a memory type volatile 73h m3qt hi reserved reserved reserved bias max reserved reserved reserved bit 7 bit 0 bit 7 m3qt hi: high alarm status for mon3; fast comparison. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bits 6:4 reserved bit 3 bias max: alarm status for maximum digital setting of bias. 0 = (default) the value for bias is equal to or below the max bias register. 1 = requested value for bias is greater than the max bias register. bits 2:0 reserved pon triplexer and sfp controller ______________________________________________________________________________________ 51
ds1875 pon triplexer and sfp controller 52 ______________________________________________________________________________________ lower memory, register 74h: warn 3 power-on value 10h read access all write access n/a memory type volatile 74h temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 bit 7 temp hi: high warning status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 temp lo: low warning status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 vcc hi: high warning status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 vcc lo: low warning status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit 3 mon1 hi: high warning status for mon1 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 2 mon1 lo: low warning status for mon1 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 1 mon2 hi: high warning status for mon2 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 0 mon2 lo: low warning status for mon2 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting.
ds1875 lower memory, register 75h: warn 2 power-on value 00h read access all write access n/a memory type volatile 75h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit 7 bit 0 bit 7 mon3 hi: high warning status for mon3 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 mon3 lo: low warning status for mon3 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 mon4 hi: high warning status for mon4 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 mon4 lo: low warning status for mon4 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bits 3:0 reserved lower memory register 76h to 77h: reserved memory power-on value 00h read access all write access n/a memory type these registers are reserved. the value when read is 00h. pon triplexer and sfp controller ______________________________________________________________________________________ 53
ds1875 pon triplexer and sfp controller 54 ______________________________________________________________________________________ lower memory, register 78h: dout power-on value recalled from table 02h, register c0h read access all write access all memory type volatile 78h m3qt reset soft m3qt reserved reserved d3 out d2 out d1 out d0 out bit 7 bit 0 bit 7 m3qt reset: resets the latch for m3qt. the pwm does not begin normal operation until the mon3 voltage is below m3qt, regardless of resetting the latch. 0 = (default) 1 = m3qt alarm is reset. bit 6 soft m3qt: software control for setting the m3qt alarm. the pwm output pulse sw is disabled. 0 = (default) internal signal is controlled by trip point comparison. 1 = m3qt alarm is set to 1. bits 5:4 reserved bit 3 d3 out: controls the output of the open-drain pin d3. 0 = output is held low. 1 = output is high impedance. bit 2 d2 out: controls the output of the open-drain pin d2. 0 = output is held low. 1 = output is high impedance. bit 1 d1 out: controls the output of the open-drain pin d1. 0 = output is held low. 1 = output is high impedance. bit 0 d0 out: controls the output of the open-drain pin d0. 0 = output is held low. 1 = output is high impedance. at power-on, these bits are defined by the value stored in the dpu byte (table 02h, register c0h). these bits define the value of the logic states of their corresponding output pins.
ds1875 lower memory, register 79h: din power-on value see description read access all write access n/a memory type volatile 79h inv m3qt mux m3qt inv los mux los d3 in d2 in d1 in d0 in bit 7 bit 0 bit 7 inv m3qt: status of inversion of m3qt (internal signal) to d2 pin. mux m3qt bit must be set to 1 or this bit does not affect the output. the value is controlled (or set) by the dpu byte. 1 = m3qt buffered to d2 is inverted. bit 6 mux m3qt: determines control of d2 pin. the value is controlled (or set) by the dpu byte. 0 = logic value of d2 is controlled by dout byte. 1 = logic value of d2 is controlled by m3qt (internal signal) and inv m3qt bit. bit 5 inv los: status of inversion of losi pin to d0 pin. mux los bit must be set to 1 or this bit does not effect the output. the value is controlled (or set) by the dpu byte. 1 = losi buffered d0 is inverted. bit 4 mux los: determines control of d0 pin. the value is controlled (or set) by the dpu byte. 0 = logic value of d0 is controlled by dout byte. 1 = logic value of d0 is controlled by losi pin and inv los bit. bit 3 d3 in: reflects the logic value of d3 pin. bit 2 d2 in: reflects the logic value of d2 pin. bit 1 d1 in: reflects the logic value of d1 pin. bit 0 d0 in: reflects the logic value of d0 pin. lower memory, register 7ah: reserved power-on value 00h read access all write access n/a memory type n/a this register is reserved. the value when read is 00h. pon triplexer and sfp controller ______________________________________________________________________________________ 55
ds1875 pon triplexer and sfp controller 56 ______________________________________________________________________________________ lower memory, register 7bh to 7eh: password entry (pwe) power-on value ffff ffffh read access n/a write access all memory type volatile 7bh 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 7ch 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 7dh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 7eh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 there are two passwords for the ds1875. each password is 4 bytes long. the lower level password (pw1) has all the access of a normal user plus those made available with pw1. the higher level password (pw2) has all the access of pw1 plus those made available with pw2. the values of the passwords reside in eeprom inside pw2 memory. at power-up, all pwe bits are set to 1. all reads at this location are 0. lower memory, register 7fh: table select (tbl sel) power-on value 00h read access all write access all memory type volatile 7fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the upper memory tables (table 00h to 08h) of the ds1875 are accessible by writing the desired table value in this register.
ds1875 table 00h register descriptions table 00h, register 80h to 81h: mon5 value table 00h, register 82h to 83h: mon6 value table 00h, register 84h to 85h: mon7 value table 00h, register 86h to 87h: mon8 value power-on value 0000h read access all write access n/a memory type volatile 80h, 82h, 84h, 86h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 81h, 83h, 85h, 87h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 left-justified unsigned voltage measurement. table 01h register descriptions table 01h, register 80h to f7h: pw1 eeprom power-on value 00h read access pw1 write access pw1 memory type nonvolatile (ee) 80h to f7h ee ee ee ee ee ee ee ee bit 7 bit 0 eeprom for pw1-level access. pon triplexer and sfp controller ______________________________________________________________________________________ 57
ds1875 pon triplexer and sfp controller 58 ______________________________________________________________________________________ table 01h, register f8h: alarm 3 power-on value 00h read access all write access pw1 memory type volatile f8h temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 layout is identical to alarm 3 in lower memory, register 70h with two exceptions. 1. vcc lo alarm is not set at power-on. 2. these bits are latched. they are cleared by power-down or a write with pw1 access. table 01h, register f9h: alarm 2 power-on value 00h read access all write access pw1 memory type volatile f9h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit 7 bit 0 layout is identical to alarm 2 in lower memory, register 71h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access.
ds1875 table 01h, register fah: alarm 1 power-on value 00h read access all write access pw1 memory type volatile fah reserved reserved reserved reserved bias hi reserved txp hi txp lo bit 7 bit 0 layout is identical to alarm 1 in lower memory, register 72h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access. table 01h, register fbh: alarm 0 power-on value 00h read access all write access pw1 memory type volatile fbh m3qt hi reserved reserved reserved bias max reserved reserved reserved bit 7 bit 0 layout is identical to alarm 0 in lower memory, register 73h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access table 01h, register fch: warn 3 power-on value 00h read access all write access pw1 memory type volatile fch temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 layout is identical to warn 3 in lower memory, register 74h with two exceptions. 1. vcc lo warning is not set at power-on. 2. these bits are latched. they are cleared by power-down or a write with pw1 access. pon triplexer and sfp controller ______________________________________________________________________________________ 59
ds1875 pon triplexer and sfp controller 60 ______________________________________________________________________________________ table 01h, register fdh: warn 2 power-on value 00h read access all write access pw1 memory type volatile fdh mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit 7 bit 0 layout is identical to warn 2 in lower memory, register 75h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access. table 01h, register feh to ffh: reserved power-on value 00h read access all write access pw1 memory type volatile these registers are reserved.
ds1875 table 02h register descriptions table 02h, register 80h: mode pon triplexer and sfp controller ______________________________________________________________________________________ 61 power-on value 3fh read access pw2 write access pw2 memory type volatile 80h seeb reserved pwm en m4dac en aen mod en apc en bias en bit 7 bit 0 bit 7 seeb: 0 = (default) enables eeprom writes to see bytes. 1 = disables eeprom writes to see bytes during configuration, so that the configuration of the part is not delayed by the ee cycle time. once the values are known, write this bit to a 0 and write the see locations again for data to be written to the eeprom. bit 6 reserved bit 5 pwm en: 0 = pwm dac is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the dac value for the pwm dac. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for pwm dac. bit 4 m4dac en: 0 = m4dac is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the dac value for m4dac. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for m4dac. bit 3 aen: 0 = the temperature-calculated index value tindex is writable by users and the updates of calculated indexes are disabled. this allows users to interactively test their modules by controlling the indexing for the luts. the recalled values from the luts appear in the dac registers after the next completion of a temperature conversion. bit 2 mod en: 0 = mod dac is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the dac value for modulation. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for modulation. bit 1 apc en: 0 = apc dac is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the dac value for apc reference. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for apc reference. bit 0 bias en: 0 = bias dac is controlled by the user and the apc is in manual mode. the bias dac value is written to the man bias register. all values that are written to man bias and are greater than the max bias register setting are not updated and set the bias max alarm bit. the bias dac register continues to reflect the value of the bias dac. this allows users to interactively test their modules by writing the dac value for bias. the output is updated with the new value at the end of the write cycle to the man bias register. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control for the apc feedback.
ds1875 pon triplexer and sfp controller 62 ______________________________________________________________________________________ table 02h, register 81h: temperature index (tindex) factory default 00h read access pw2 write access pw2 and aen = 0 memory type volatile 81h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 holds the calculated index based on the temperature measurement. this index is used for the address during lookup of tables 04h, 05h, 07h, and 08h. temperature measurements below -40c or above +102c are clamped to 00h and c7h, respectively. the calculation of tindex is as follows: tindex = temp _ value + 40 c 2 c + 80h for the temperature-indexed luts, the index used during the lookup function for each table is as follows: table 04h (mod) 1 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 tindex 0 table 05h (apc) 1 0 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 table 07h (pwm) 1 0 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 table 08h (bias) 1 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 tindex 0 table 02h, register 82h: mod dac factory default 00h read access pw2 write access pw2 and mod en = 0 memory type volatile 82h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for mod and recalled from table 04h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. v mod = full scale 255 mod dac
ds1875 table 02h, register 83h: apc dac factory default 00h read access pw2 write access pw2 and apc en = 0 memory type volatile 83h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for apc reference and recalled from table 05h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. v bmd = full scale 255 apc dac table 02h, register 84h: voltage index (vindex) factory default 00h read access pw2 write access pw2 and aen = 0 memory type volatile 84h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 holds the calculated index based on the mon4 voltage measurement. this index is used for the address during lookup of table 06h. m4dac lut is 32 bytes from address 80h to 9fh. the calculation of vindex is as follows: vindex = mon4 800h + 80h when configured as a single lut, all 32 bytes are used for lookup. when configured as a double lut, the first 16 bytes (80h to 8fh) form the lower lut and the last 16 bytes (90h to 9fh) form the upper lut. for the three different modes, the index used during the lookup function of table 06h is as follows: single 1 0 0 vindex 4 vindex 3 vindex 2 vindex 1 vindex 0 double/lower 1 0 0 0 vindex 4 vindex 3 vindex 2 vindex 1 double/upper 1 0 0 1 vindex 4 vindex 3 vindex 2 vindex 1 pon triplexer and sfp controller ______________________________________________________________________________________ 63
ds1875 pon triplexer and sfp controller 64 ______________________________________________________________________________________ table 02h, register 85h: m4dac factory default 00h read access pw2 write access pw2 and m4dac en = 0 memory type volatile 85h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for m4dac and recalled from table 06h at the adjusted memory address found in vindex. this register is updated at the end of the mon4 conversion. v m4dac = 2.5 256 (m4dac + 1) table 02h, register 86h: device id factory default 75h read access pw2 write access n/a memory type rom 86h 0 1 1 1 0 1 0 1 bit 7 bit 0 hardwired connections to show the device id. table 02h, register 87h: device ver factory default device version read access pw2 write access n/a memory type rom 87h device version bit 7 bit 0 hardwired connections to show device version.
ds1875 table 02h, register 88h: sample rate factory default 30h read access pw2 write access pw2 memory type nonvolatile (see) 88h see see pwm_fr 1 pwm_fr 0 apc_sr 3 apc_sr 2 apc_sr 1 apc_sr 0 bit 7 bit 0 bits 7:6 see bits 5:4 pwm_fr[1:0]: 2-bit frequency rate for the sw pulsed output used with pwm. when switching a lower to a higher frequency, disable the sw output by setting soft m3qt (byte 78h) to a 1 before changing pwm_fr. after changing pwm_fr, wait 200 periods of the new frequency before enabling the sw output. this delay allows for the internal signals to integrate and lock to the new frequency without creating a large duty cycle. 00b: 131.25khz 01b: 262.5khz 10b: 525khz 11b: 1050khz (default) bits 3:0 apc_sr[3:0]: 4-bit sample rate for comparison of apc control. apc_sr[3:0] minimum time from ben to first sample (t first ) 50ns (ns) repeated sample period following first sample (t rep ) (ns) 0000b 350 800 0001b 550 1200 0010b 750 1600 0011b 950 2000 0100b 1350 2800 0101b 1550 3200 0110b 1750 3600 0111b 2150 4400 1000b 2950 6000 1001b* 3150 6400 defines the sample rate for comparison of apc control. * all codes greater than 1001b (1010b to 1111b) use the maximum sample time of code 1001b. pon triplexer and sfp controller ______________________________________________________________________________________ 65
ds1875 pon triplexer and sfp controller 66 ______________________________________________________________________________________ table 02h, register 89h: config factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) 89h fetg dir tx-f len m3qt len asel bolfs rssi_fc rssi_ff en5to8b bit 7 bit 0 configure the memory location and the polarity of the digital outputs. bit 7 fetg dir: chooses the direction or polarity of the fetg output for normal operation. 0 = (default) under normal operation, fetg is pulled low. 1 = under normal operation, fetg is pulled high. bit 6 tx-f len: the tx-f output pin always reflects the wired-or of all tx-f enabled alarm states. this bit enables the latching of the alarm state for the tx-f output pin. 0 = (default) not latched. 1 = the alarm bits are latched until cleared by a tx-d transition or power-down. if the v cc alarm is enabled for either fetg or tx-f, then latching is disabled until after the first v cc measurement is made above the v cc alarm lo set point to allow for proper operation during slow power-on cycles. bit 5 m3qt len: this bit enables the latching of the alarm for the m3qt. 0 = (default) not latched. 1 = the alarm bit is latched until cleared by setting the m3qt reset bit (byte 78h). bit 4 asel: address select. 0 = (default) device address of a2h. 1 = device address is equal to the value found in the device address byte (table 02h, 8ch). bit 3 bolfs: bias open-loop full scale. 0 = (default) full scale is 600a. 1 = full scale is 1.2ma. bits 2:1 rssi_fc and rssi_ff: rssi force coarse and rssi force fine. control bits for rssi mode of operation on the mon3 conversion. 00b = (default) normal rssi mode of operation. 01b = the fine settings of scale and offset are used for mon3 conversions. 10b = the coarse settings of scale and offset are used for mon3 conversions. 11b = normal rssi mode of operation. bit 0 en5to8b: this bit enables mon5Cmon8 conversion (voltage of d0Cd3 pins). 0 = (default) temperature, v cc , and mon1Cmon8 conversions are enabled. 1 = temperature, v cc , and mon1Cmon4 conversions are enabled.
ds1875 table 02h, register 8ah: reserved factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) this register is reserved. table 02h, register 8bh: mod ranging factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) 8bh reserved reserved reserved reserved reserved mod 2 mod 1 mod 0 bit 7 bit 0 the lower nibble of this byte controls the full-scale range of the modulation dac bits 7:3 reserved (default = 0) bits 2:0 mod[2:0]: mod fs ranging: 3-bit value to select the fs output voltage for mod. default is 000b and creates a fs of 1.25v. mod[2:0] % of 1.25v fs voltage (v) 000b 100.00 1.250 001b 80.05 1.001 010b 66.75 0.834 011b 50.13 0.627 100b 40.15 0.502 101b 33.50 0.419 110b 28.74 0.359 111b 25.17 0.315 pon triplexer and sfp controller ______________________________________________________________________________________ 67
ds1875 pon triplexer and sfp controller 68 ______________________________________________________________________________________ table 02h, register 8ch: device address factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) 8ch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 this value becomes the i 2 c slave address for the main memory when the asel (table 02h, register 89h) bit is set. if a0h is programmed to this register, the auxiliary memory is disabled.
ds1875 table 02h, register 8dh: comp ranging factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) 8dh reserved bias 2 bias 1 bias 0 reserved apc 2 apc 1 apc 0 bit 7 bit 0 the upper nibble of this byte controls the full-scale range of the quick-trip monitoring for bias. the lower nibble of this byte controls the full-scale range for the quick-trip monitoring of the apc reference as well as the closed- loop monitoring of apc. bit 7 reserved (default = 0) bits 6:4 bias[2:0] bias full-scale ranging. 3-bit value to select the fs comparison voltage for bias found on mon1. default is 000b and creates a fs of 1.25v. bias[2:0] % of 1.25v fs voltage (v) 000b 100.00 1.250 001b 80.04 1.001 010b 66.73 0.834 011b 50.10 0.626 100b 40.11 0.501 101b 33.45 0.418 110b 28.69 0.359 111b 25.12 0.314 bit 3 reserved (default = 0) bits 2:0 apc[2:0] apc full-scale ranging. 3-bit value to select the fs comparison voltage for bmd with the apc. default is 000b and creates a fs of 2.5v. apc[2:0] % of 2.50v fs voltage (v) 000b 100.00 1.250 001b 80.04 1.001 010b 66.73 0.834 011b 50.10 0.626 100b 40.11 0.501 101b 33.45 0.418 110b 28.69 0.359 111b 25.12 0.314 pon triplexer and sfp controller ______________________________________________________________________________________ 69
ds1875 pon triplexer and sfp controller 70 ______________________________________________________________________________________ table 02h, register 8eh: right shift 1 (rshift 1 ) factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) 8eh reserved mon1 2 mon1 1 mon1 0 reserved mon2 2 mon2 1 mon2 0 bit 7 bit 0 allows for right-shifting the final answer of mon1 and mon2 voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. table 02h, register 8fh: right shift 0 (rshift 0 ) factory default 30h read access pw2 write access pw2 memory type nonvolatile (see) 8fh reserved mon3 2 mon3 1 mon3 0 reserved mon4 2 mon4 1 mon4 0 bit 7 bit 0 allows for right-shifting the final answer of mon3 and mon4 voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. table 02h, register 90h to 91h: reserved factory default 0000h read access pw2 write access pw2 memory type nonvolatile (see) these registers are reserved.
ds1875 table 02h, register 92h to 93h: v cc scale table 02h, register 94h to 95h: mon1 scale table 02h, register 96h to 97h: mon2 scale table 02h, register 98h to 99h: mon3 fine scale table 02h, register 9ah to 9bh: mon4 scale table 02h, register 9ch to 9dh: mon3 coarse scale factory calibrated read access pw2 write access pw2 memory type nonvolatile (see) 92h, 94h, 96h, 98h, 9ah, 9ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 93h, 95h, 97h, 99h, 9bh, 9dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 controls the scaling or gain of the fs voltage measurements. the factory-calibrated value produces an fs voltage of 6.5536v for v cc and 2.5v for mon1, mon2, mon3, and mon4. table 02h, register 9eh to a1h: reserved factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) these registers are reserved. pon triplexer and sfp controller ______________________________________________________________________________________ 71
ds1875 pon triplexer and sfp controller 72 ______________________________________________________________________________________ table 02h, register a2h to a3h: v cc offset table 02h, register a4h to a5h: mon1 offset table 02h, register a6h to a7h: mon2 offset table 02h, register a8h to a9h: mon3 fine offset table 02h, register aah to abh: mon4 offset table 02h, register ach to adh: mon3 coarse offset factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) a2h, a4h, a6h, a8h, aah, ach s s 2 15 2 14 2 13 2 12 2 11 2 10 a3h, a5h, a7h, a9h, abh, adh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 allows for offset control of these voltage measurements if desired. table 02h, register aeh to afh: internal temp offset factory calibrated read access pw2 write access pw2 memory type nonvolatile (see) aeh s 2 8 2 7 2 6 2 5 2 4 2 3 2 2 afh 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 bit 7 bit 0 allows for offset control of temperature measurement if desired. the final result must be xored with bb40h before writing to this register. factory calibration contains the desired value for a reading in degrees celsius.
ds1875 table 02h, register b0h to b3h: pw1 factory default ffff ffffh read access n/a write access pw2 memory type nonvolatile (see) b0h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b1h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b2h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwe value is compared against the value written to this location to enable pw1 access. at power-on, the pwe value is set to all 1s. thus, writing these bytes to all 1s grants pw1 access on power-on without writing the password entry. all reads of this register are 00h. table 02h, register b4h to b7h: pw2 factory default ffff ffffh read access n/a write access pw2 memory type nonvolatile (see) b4h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b5h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b6h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwe value is compared against the value written to this location to enable pw2 access. at power-on, the pwe value is set to all 1s. thus writing these bytes to all 1s grants pw2 access on power-on without writing the password entry. all reads of this register are 00h. pon triplexer and sfp controller ______________________________________________________________________________________ 73
ds1875 pon triplexer and sfp controller 74 ______________________________________________________________________________________ table 02h, register b8h: fetg enable 1 factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) b8h temp en vcc en mon1 en mon2 en mon3 en mon4 en reserved reserved bit 7 bit 0 configures the maskable interrupt for the fetg pin. bit 7 temp en: enables/disables active interrupts on the fetg pin due to temperature measurements outside the threshold limits. 0 = disable (default) 1 = enable bit 6 vcc en: enables/disables active interrupts on the fetg pin due to v cc measurements outside the threshold limits. 0 = disable (default) 1 = enable bit 5 mon1 en: enables/disables active interrupts on the fetg pin due to mon1 measurements outside the threshold limits. 0 = disable (default) 1 = enable bit 4 mon2 en: enables/disables active interrupts on the fetg pin due to mon2 measurements outside the threshold limits. 0 = disable (default) 1 = enable bit 3 mon3 en: enables/disables active interrupts on the fetg pin due to mon3 measurements outside the threshold limits. 0 = disable (default) 1 = enable bit 2 mon4 en: enables/disables active interrupts on the fetg pin due to mon4 measurements outside the threshold limits. 0 = disable (default) 1 = enable bits 1:0 reserved (default = 0)
ds1875 table 02h, register b9h: fetg enable 0 factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) b9h txp hi en txp lo en bias hi en bias max en reserved reserved reserved reserved bit 7 bit 0 configures the maskable interrupt for the fetg pin. bit 7 txp hi en: enables/disables active interrupts on the fetg pin due to txp fast comparisons above the threshold limit. 0 = disable (default) 1 = enable bit 6 txp lo en: enables/disables active interrupts on the fetg pin due to txp fast comparisons below the threshold limit. 0 = disable (default) 1 = enable bit 5 bias hi en: enables/disables active interrupts on the fetg pin due to bias fast comparisons above the threshold limit. 0 = disable. (default) 1 = enable bit 4 bias max en: enables/disables active interrupts on the fetg pin due to bias fast comparison s below the threshold limit. 0 = disable (default) 1 = enable bits 3:0 reserved (default = 0) pon triplexer and sfp controller ______________________________________________________________________________________ 75
ds1875 pon triplexer and sfp controller 76 ______________________________________________________________________________________ table 02h, register bah: tx-f enable 1 factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) bah temp en vcc en mon1 en mon2 en mon3 en mon4 en reserved reserved bit 7 bit 0 configures the maskable interrupt for the tx-f pin. bit 7 temp en: enables/disables active interrupts on the tx-f pin due to temperature measurements outside the threshold limits. 0 = disable (default) 1 = enable bit 6 vcc en: enables/disables active interrupts on the tx-f pin due to v cc measurements outside the threshold limits. 0 = disable (default) 1 = enable bit 5 mon1 en: enables/disables active interrupts on the tx-f pin due to mon1 measurements outside the threshold limits. 0 = disable (default) 1 = enable bit 4 mon2 en: enables/disables active interrupts on the tx-f pin due to mon2 measurements outside the threshold limits. 0 = disable (default) 1 = enable bit 3 mon3 en: enables/disables active interrupts on the tx-f pin due to mon3 measurements outside the threshold limits. 0 = disable (default) 1 = enable bit 2 mon4 en: enables/disables active interrupts on the tx-f pin due to mon4 measurements outside the threshold limits. 0 = disable (default) 1 = enable bits 2:0 reserved (default = 0)
ds1875 table 02h, register bbh: tx-f enable 0 factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) bbh txp hi en txp lo en bias hi en bias max en reserved reserved reserved fetg en bit 7 bit 0 configures the maskable interrupt for the tx-f pin. bit 7 txp hi en: enables/disables active interrupts on the tx-f pin due to txp fast comparisons above the threshold limit. 0 = disable (default) 1 = enable bit 6 txp lo en: enables/disables active interrupts on the tx-f pin due to txp fast comparisons below the threshold limit. 0 = disable (default) 1 = enable bit 5 bias hi en: enables/disables active interrupts on the tx-f pin due to bias fast comparison s above the threshold limit. 0 = disable (default) 1 = enable bit 4 bias max en: enables/disables active interrupts on the tx-f pin due to bias fast comparisons above the threshold limit. 0 = disable (default) 1 = enable bits 3:1 reserved (default = 0) bit 0 fetg en: 0 = normal fetg operation (default). 1 = enables fetg to act as an input to tx-f output. pon triplexer and sfp controller ______________________________________________________________________________________ 77
ds1875 pon triplexer and sfp controller 78 ______________________________________________________________________________________ table 02h, register bch: htxp factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) bch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast comparison dac threshold adjust for high txp. this value is added to the apc dac value recalled from table 04h. if the sum is greater than 0xff, 0xff is used. comparisons greater than v htxp , compared against v bmd , create a txp hi alarm. the same ranging applied to the apc dac should be used here. v htxp = full scale 255 htxp + apc dac () table 02h, register bdh: ltxp factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) bdh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast-comparison dac threshold adjust for low txp. this value is subtracted from the apc dac value recalled from table 04h. if the difference is less than 0x00, 0x00 is used. comparisons less than v ltxp , compared against v bmd , create a txp lo alarm. the same ranging applied to the apc dac should be used here. v ltxp = full scale 255 apc dac ltxp ()
ds1875 table 02h, register beh: hbias factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) beh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast-comparison dac setting for high bias. comparisons greater than v hbias , found on the mon1 pin, create a bias hi alarm. v hbias = full scale 255 hbias table 02h, register bfh: max bias factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) bfh 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 bit 7 bit 0 this value defines the maximum dac value allowed for the upper 8 bits of bias output during all operations. pon triplexer and sfp controller ______________________________________________________________________________________ 79
ds1875 pon triplexer and sfp controller 80 ______________________________________________________________________________________ table 02h, register c0h: dpu factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) c0h inv m3qt mux m3qt inv los mux los d3 cntl d2 cntl d1 cntl d0 cntl bit 7 bit 0 bit 7 inv m3qt: inverts the internal m3qt signal to output pin d2 if mux m3qt is set. if mux m3qt is not set, this bits value is a dont care. 0 = (default) noninverted m3qt to d2 pin. 1 = inverted m3qt to d2 pin. bit 6 mux m3qt: chooses the control for d2 output pin. 0 = (default) d2 is controlled by bit d2 in found in byte 79h. 1 = m3qt is buffered to d2 pin. bit 5 inv los: inverts the buffered input pin losi to output pin d0 if mux los is set. if mux los is not set, this bits value is a dont care. 0 = (default) noninverted losi to d0 pin. 1 = inverted losi to d0 pin. bit 4 mux los: chooses the control for d0 output pin. 0 = (default) do is controlled by bit d0 in found in byte 79h. 1 = losi is buffered to d0 pin. bit 3 d3 cntl: at power-on, this bits value is loaded into bit d3 out of byte 78h to control the output pin d3. 0 = (default) bit 2 d2 cntl: at power-on, this bits value is loaded into bit d2 out of byte 78h to control the output pin d2. 0 = (default) bit 1 d1 cntl: at power-on, this bits value is loaded into bit d1 out of byte 78h to control the output pin d1. 0 = (default) bit 0 d0 cntl: at power-on, this bits value is loaded into bit d0 out of byte 78h to control the output pin d0. 0 = (default) controls the power-on values for d3, d2, d1, and d0 output pins and mux and invertion of the losi pin.
ds1875 table 02h, register c1h to c2h: reserved factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) these registers are reserved. table 02h, register c3h: m3qt dac factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) c3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 register to control m3qt dac. v m3qt = 1.25 256 m3qt dac + 1 () table 02h, register c4h: dac1 factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) c4h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 register to control dac1. v daci = 2.5 256 dac1 + 1 () pon triplexer and sfp controller ______________________________________________________________________________________ 81
ds1875 pon triplexer and sfp controller 82 ______________________________________________________________________________________ table 02h, register c5h to c6h: reserved factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) these registers are reserved. table 02h, register c7h: m4 lut cntl factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) c7h reserved reserved reserved reserved fbol fbcl dbl_sb up_lowb bit 7 bit 0 bits 7:4 reserved (default = 000000b) bits 3:2 fbol and fbcl: force bias open loop and force bias closed loop. 00b = (default) normal operation. 10b = force control of i bias to be open loop regardless of duration of ben pulses. 01b = force control of i bias to be closed loop regardless of duration of ben pulses. 11b = same as 10b. when forcing open-loop mode, ben s hould be gr ound or at any burst length. bit 1 dbl_sb: chooses the size of lut for table 06h. 0 = (default) single lut of 32 bytes. 1 = double lut of 16 bytes. bit 0 up_lowb: determines which 16-byte lut is used if dbl_sb = 1. if dbl_sb = 0, the value of this bit is a dont care. 0 = (default) chooses the lower 16 bytes of table 06h (80h to 8fh). 1 = chooses the upper 16 bytes of table 06h (90h to 9fh). controls the size and location of lut functions for the mon4 measurement.
ds1875 table 02h, register c8h to c9h: mon5 scale table 02h, register cah to cbh: mon6 scale table 02h, register cch to cdh: mon7 scale table 02h, register ceh to cfh: mon8 scale factory calibrated read access pw2 write access pw2 memory type nonvolatile (see) c8h, cah, cch, ceh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 c9h, cbh, cdh, cfh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 controls the scaling or gain of the fs voltage measurements. the factory-calibrated value produces an fs voltage of 2.5v for mon5, mon6, mon7, and mon8. table 02h, register d0h to d1h: mon5 offset table 02h, register d2h to d3h: mon6 offset table 02h, register d4h to d5h: mon7 offset table 02h, register d6h to d7h: mon8 offset factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) d0h, d2h, d4h, d6h s s 2 15 2 14 2 13 2 12 2 11 2 10 d1h, d3h, d5h, d7h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 allows for offset control of these voltage measurements if desired. pon triplexer and sfp controller ______________________________________________________________________________________ 83
ds1875 pon triplexer and sfp controller 84 ______________________________________________________________________________________ table 02h, register d8h to f7h: empty table 02h, register f8h to f9h: man bias factory default 00h read access pw2 write access pw2 and bias en = 1 memory type volatile fah reserved reserved reserved reserved reserved reserved reserved man_clk bit 7 bit 0 when bias en (table 02h, register 80h) is written to 0, bit 0 of this byte controls the updates of the man bias value to the bias output. the values of man bias should be written with a separate write command. setting bit 0 to a 1 clocks the man bias value to the output dac. 1. write the man bias value with a write command. 2. set the man_clk bit to a 1 with a separate write command. 3. clear the man_clk bit to a 0 with a separate write command. table 02h, register fah: man_cntl factory default 00h read access pw2 write access pw2 and bias en = 1 memory type volatile f8h reserved reserved 2 12 2 11 2 10 2 9 2 8 2 7 f9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 when bias en (table 02h, register 80h) is written to 0, writes to these bytes control the bias dac.
ds1875 table 02h, register fbh to fch: bias dac factory default 8000h read access pw2 write access n/a memory type volatile fbh bol 0 2 12 2 11 2 10 2 9 2 8 2 7 fch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the bias open-loop bit (bol) reflects the status of the bias current-control loop. if it is 1, the loop is open and the ds1875 is controlling the bias output from the lut. if it is 0, the loop is closed and the bias output is controlled by active feedback from the bmd pin. the remaining bits are the digital value used for the bias output regardless of the value of ol. table 02h, register fdh: bias ol factory default 00h read access pw2 write access pw2 and apc en = 1 memory type volatile fdh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for bias at power-on and during open loop. it is recalled from table 08h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. the correct value depends on the value of bolfs (table 02h, register 89h, bit 3). if bolfs = 0, bias ol[7:0] = i bias [11:4]. if bolfs = 1, bias ol[7:0] = i bias [12:5]. pon triplexer and sfp controller ______________________________________________________________________________________ 85
ds1875 pon triplexer and sfp controller 86 ______________________________________________________________________________________ table 02h, register feh: pwm dac factory default 00h read access pw2 write access pw2 and pwm en = 0 memory type volatile feh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for pwm integration of the fb pin. it is recalled from table 07h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. v pwm = 1.25 256 (pwm dac + 1) table 02h, register ffh: reserved factory default 00h read access pw2 write access n/a memory type n/a this register is reserved.
ds1875 table 03h register descriptions table 03h, register 80h to ffh: pw2 eeprom factory default 00h read access pw2 write access pw2 memory type nonvolatile (ee) 80h to ffh ee ee ee ee ee ee ee ee bit 7 bit 0 pw2-protected eeprom. table 04h register descriptions table 04h, register 80h to c7h: modulation lut factory default 00h read access pw2 write access pw2 memory type nonvolatile (ee) 80h to c7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value for the modulation dac output. the modulation lut is a set of registers assigned to hold the temperature profile for the modulation dac. the values in this table combined with the mod bits in the mod ranging register (table 02h, register 8bh) determine the set point for the modulation voltage. the temperature measurement is used to index the lut (tindex, table 02h, register 81h) in 2c increments from -40c to +102c, starting at 80h in table 04h. register 80h defines the -40c to -38c mod output, register 81h defines the -38c to -36c mod output, and so on. values recalled from this eeprom memory table are written into the mod dac (table 02h, register 82h) location that holds the value until the next temperature conversion. the ds 1875 can be placed into a manual mode (mod en bit, table 02h, register 80h), where mod dac is directly controlled for calibration. if the temperature compensation functionality is not required, then program the entire table 04h, to the desired modulation setting. pon triplexer and sfp controller ______________________________________________________________________________________ 87
ds1875 pon triplexer and sfp controller 88 ______________________________________________________________________________________ table 05h register descriptions table 05h, register 80h to a3h: apc te lut factory default 00h read access pw2 write access pw2 memory type nonvolatile (ee) 80h to a3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the apc te lut is a set of registers assigned to hold the temperature profile for the apc reference dac. the values in this table combined with the apc bits in the comp ranging register (table 02h, register 8dh) determine the set point for the apc loop. the temperature measurement is used to index the lut (tindex, table 02h, register 81h) in 4c increments from -40c to +100c, starting at register 80h in table 05h. register 80h defines the -40c to -36c apc reference value, register 81h defines the -36c to -32c apc reference value, and so on. values recalled from this eeprom memory table are written into the apc dac (table 02h, register 83h) location that holds the value until the next temperature conversion. the ds1875 can be placed into a manual mode (apc en bit, table 02h, register 80h), where apc dac can be directly controlled for calibration. if te temperature compensation is not required by the application, program the entire lut to the desired apc set point. table 05h, register a4h to a7h: reserved factory default 00h read access pw2 write access pw2 memory type nonvolatile (ee) these registers are reserved.
ds1875 table 06h register descriptions table 06h, register 80h to 9fh: m4dac lut factory default 00h read access pw2 write access pw2 memory type nonvolatile (ee) 80h to 9fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the m4dac lut is set of registers assigned to hold the voltage profile for the m4dac. the values in this table determine the set point for the m4dac. the mon4 voltage measurement is used to index the lut (vindex, table 02h, register 84h), starting at register 80h in table 06h. values recalled from this eeprom memory table are written into the m4dac (table 02h, register 85h) location that holds the value until the next mon4 voltage conversion. the ds 1875 can be placed into a manual mode (m4dac en bit, table 02h, register 80h), where m4dac is directly controlled for calibration. if voltage compensation is not required by the application, program the entire lut to the desired m4dac set point. pon triplexer and sfp controller ______________________________________________________________________________________ 89
ds1875 pon triplexer and sfp controller 90 ______________________________________________________________________________________ table 07h register descriptions table 07h, register 80h to a3h: pwm reference lut factory default 00h read access pw2 write access pw2 memory type nonvolatile (ee) 80h to a3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwm reference lut is a set of registers assigned to hold the temperature profile for the pwm feedback. the values in this table determine the set point for the pwm loop. the temperature measurement is used to index the lut (tindex, table 02h, register 81h) in 4c increments from -40c to + 100c, starting at register 80h in table 07h. register 80h defines the -40c to -36c pwm reference value, register 81h defines the -36c to -32c pwm reference value, and so on. values recalled from this eeprom memory table are written into the pwm dac (table 02h, register feh) location that holds the value until the next temperature conversion. the ds1875 can be placed into a manual mode (pwm en bit, table 02h, register 80h), where pwm dac can be directly controlled for calibration. if temperature compensation is not required by the application, program the entire lut to the desired pwm set point. table 07h, register a4h to a7h: reserved factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) these registers are reserved.
ds1875 pon triplexer and sfp controller ______________________________________________________________________________________ 91 factory default 00h read access all write access all memory type nonvolatile (ee) 80h to c7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the bias open-loop lut is a set of registers assigned to hold the temperature profile for the bias ol dac. the values in this table determine the set point for the bias current. the temperature measurement is used to index the lut (tindex, table 02h, register 81h) in 2c increments from -40c to +102c, starting at 80h in table 08h. register 80h defines the -40c to -38c bias ol output, register 81h defines the -38c to -36c bias ol output, and so on. values recalled from this eeprom memory table are written into the bias ol (table 02h, register fdh) location that holds the value until the next temperature conversion. the ds1875 can be placed into a manual mode (bias en bit, table 02h, register 80h), where bias ol dac is directly controlled for calibration. if the temperature compensation functionality is not required, then program the entire table 08h to the desired bias ol setting. auxiliary memory a0h register descriptions auxiliary memory a0h, register 00h to ffh: eeprom factory default 00h read access all write access all memory type nonvolatile (ee) 80h to ffh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 accessible with the slave address a0h. package type package code document no. 38 tqfn-ep t3857+1 21-0172 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . table 08h register descriptions table 08h, register 80h to c7h: bias open-loop lut
ds1875 pon triplexer and sfp controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 92 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/08 initial release. 1 10/08 updated all instances of the operating voltage range from 5.5v to 3.9v on multiple pages. 1, 5C13

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