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intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet product features for a complete list of product features, see ?product features? on page 9 . typical applications intel xscale ? core three network processor engines pci interface two mii interfaces utopia-2 interface usb v 1.1 device controller two high-speed, serial interfaces sdram interface encryption/authentication high-speed uart console uart internal bus performance monitoring unit 16 gpios four internal timers packaging ?492-pin pbga ?commercial/extended temperature high-performance dsl modem high-performance cable modem residential gateway sme router network printers control plane integrated access device (iad) set-top box access points (802.11a/b/g) industrial controllers document number: 252479-004 june 2004
intel ? ixp42x product line and ixc1100 control plane processor 2 datasheet information in this document is provided in connection with intel r products. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty relating to sale and/or use of intel products, including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. intel products are not intended for use in medical, life saving , life sustaining, critical control or safety systems, or in nuc lear facility applications. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548-4725, or by visiting intel's website at http://www.intel.com . bunnypeople, celeron, chips, dialogic, etherexpress, etox, flas hfile, i386, i486, i960, icomp, instantip, intel, intel centrino , intel centrino logo, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, in telsx2, intel inside, intel insi de logo, intel netburst, intel netmerge, intel netstructure, intel singledriver, intel speedstep, intel strataflash, intel xeon, intel xscale, iplink, itanium, mcs, mmx, mmx logo, optimize r logo, overdrive, paragon, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, sound mark, the computer inside., th e journey inside, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? intel corporation 2004
datasheet 3 intel ? ixp42x product line and ixc1100 control plane processor contents contents 1.0 product features ...........................................................................................................................9 1.1 product line features ....................................................................................................... ... 9 1.2 processor features .......................................................................................................... ..12 1.3 about this document ......................................................................................................... .12 2.0 functional overview ...................................................................................................................14 2.1 functional units ............................................................................................................ ......17 2.1.1 network processor engines (npes) ......................................................................17 2.1.2 internal bus............................................................................................................18 2.1.2.1 north ahb..............................................................................................18 2.1.2.2 south ahb .............................................................................................19 2.1.2.3 apb bus.................................................................................................19 2.1.3 mii interfaces .........................................................................................................19 2.1.4 utopia 2 ..............................................................................................................20 2.1.5 usb interface ........................................................................................................20 2.1.6 pci controller ........................................................................................................20 2.1.7 sdram controller .................................................................................................20 2.1.8 expansion bus .......................................................................................................21 2.1.9 high-speed, serial interfaces ................................................................................21 2.1.10 high-speed and console uarts ..........................................................................22 2.1.11 gpio ..................................................................................................................... .22 2.1.12 internal bus performance monitoring unit (ibpmu) ..............................................22 2.1.13 interrupt controller .................................................................................................22 2.1.14 timers ................................................................................................................... .23 2.1.15 ahb queue manager ............................................................................................23 2.2 intel xscale ? core..............................................................................................................23 2.2.1 super pipeline .......................................................................................................24 2.2.2 branch target buffer (btb) ...................................................................................25 2.2.3 instruction memory management unit (immu) ......................................................26 2.2.4 data memory management unit (dmmu) .............................................................26 2.2.5 instruction cache (i-cache) ...................................................................................26 2.2.6 data cache (d-cache) ..........................................................................................27 2.2.7 mini-data cache ....................................................................................................27 2.2.8 fill buffer (fb) and pend buffer (pb).....................................................................28 2.2.9 write buffer (wb)...................................................................................................28 2.2.10 multiply-accumulate coprocessor (cp0) ...............................................................28 2.2.11 performance monitoring unit (pmu)......................................................................29 2.2.12 debug unit .............................................................................................................29 3.0 functional signal descriptions ..................................................................................................30 4.0 package and pinout information ................................................................................................42 4.1 package description ......................................................................................................... ..42 4.2 signal-pin descriptions..................................................................................................... ..45 4.3 package thermal specifications ........................................................................................73 4.3.1 commercial temperature ......................................................................................73 4.3.2 extended temperature ..........................................................................................73
intel ? ixp42x product line and ixc1100 control plane processor contents 4 datasheet 5.0 electrical specifications ............................................................................................................. 74 5.1 absolute maximum ratings ................................................................................................ 74 5.2 v ccpll1 , v ccpll2 , v ccoscp , v ccosc pin requirements .................................................. 74 5.2.1 v ccpll1 requirement ............................................................................................ 74 5.2.2 v ccpll2 requirement ............................................................................................ 75 5.2.3 v ccoscp requirement .......................................................................................... 75 5.2.4 v ccosc requirement ............................................................................................ 76 5.3 rcomp pin requirements................................................................................................. 77 5.4 dc specifications ........................................................................................................... .... 77 5.4.1 operating conditions ............................................................................................. 77 5.4.2 pci dc parameters ............................................................................................... 78 5.4.3 usb dc parameters.............................................................................................. 78 5.4.4 utopia-2 dc parameters .................................................................................... 79 5.4.5 mii dc parameters ................................................................................................ 79 5.4.6 mdio dc parameters............................................................................................ 80 5.4.7 sdram bus dc parameters................................................................................. 80 5.4.8 expansion bus dc parameters ............................................................................. 81 5.4.9 high-speed, serial interface 0 dc parameters..................................................... 81 5.4.10 high-speed, serial interface 1 dc parameters..................................................... 81 5.4.11 high-speed and console uart dc parameters .................................................. 82 5.4.12 gpio dc parameters ............................................................................................ 83 5.4.13 jtag dc parameters............................................................................................ 83 5.4.14 reset dc parameters............................................................................................ 83 5.5 ac specifications........................................................................................................... ..... 84 5.5.1 clock signal timings ............................................................................................. 84 5.5.1.1 processor clock timings ....................................................................... 84 5.5.1.2 pci clock timings ................................................................................. 86 5.5.1.3 mii clock timings .................................................................................. 86 5.5.1.4 utopia-2 clock timings....................................................................... 86 5.5.1.5 expansion bus clock timings ............................................................... 86 5.5.2 bus signal timings ................................................................................................ 87 5.5.2.1 pci ......................................................................................................... 87 5.5.2.2 usb interface......................................................................................... 88 5.5.2.3 utopia-2 .............................................................................................. 89 5.5.2.4 mii .......................................................................................................... 90 5.5.2.5 mdio...................................................................................................... 91 5.5.2.6 sdram bus........................................................................................... 92 5.5.2.7 expansion bus ....................................................................................... 93 5.5.2.8 high-speed, serial interfaces .............................................................. 107 5.5.2.9 jtag.................................................................................................... 109 5.5.3 reset timings...................................................................................................... 110 5.6 power sequence .............................................................................................................. 111 5.7 i cc and total average power ........................................................................................... 112 5.8 ordering information........................................................................................................ .112
datasheet 5 intel ? ixp42x product line and ixc1100 control plane processor contents figures 1 intel ? ixp425 network processor block diagram ......................................................................14 2 intel ? ixp422 network processor block diagram ......................................................................15 3 intel ? ixp421 network processor block diagram ......................................................................15 4 intel ? ixp420 network processor block diagram ......................................................................16 5 intel xscale ? core block diagram .............................................................................................24 6 492-pin lead pbga package ....................................................................................................4 2 7 package markings .............................................................................................................. ........43 8v ccpll1 power filtering diagram ...............................................................................................75 9v ccpll2 power filtering diagram ...............................................................................................75 10 v ccoscp power filtering diagram .............................................................................................76 11 v ccosc power filtering diagram ...............................................................................................76 12 rcomp pin external resistor requirements ............................................................................77 13 typical connection to a crystal .............................................................................................. ....85 14 typical connection to an oscillator .......................................................................................... ..85 15 pci output timing ............................................................................................................ ..........87 16 pci input timing ............................................................................................................. ............87 17 utopia-2 input timings....................................................................................................... ......89 18 utopia-2 output timings...................................................................................................... ....89 19 mii output timings ........................................................................................................... ..........90 20 mii input timings ............................................................................................................ ............90 21 mdio output timings .......................................................................................................... .......91 22 mdio input timings........................................................................................................... .........91 23 sdram input timings .......................................................................................................... ......92 24 sdram output timings ......................................................................................................... ....93 25 intel multiplexed mode....................................................................................................... .........93 26 intel simplex mode ........................................................................................................... ..........94 27 motorola* multiplexed mode ................................................................................................... ....95 28 motorola* simplex mode....................................................................................................... ......97 29 hpi ? 8 mode write accesses .................................................................................................. ..99 30 hpi-16 multiplex write mode .................................................................................................. ..101 31 hpi-16 multiplex read mode................................................................................................... .103 32 hpi-16 non-multiplex read mode ............................................................................................104 33 hpi-16 non-multiplex write mode ............................................................................................10 6 34 high-speed, serial timings ................................................................................................... ...107 35 boundary-scan general timings..............................................................................................10 9 36 boundary-scan reset timings .................................................................................................1 09 37 reset timings................................................................................................................ ...........110 38 power-up sequence timing ..................................................................................................... 112
intel ? ixp42x product line and ixc1100 control plane processor contents 6 datasheet tables 1 processor features ............................................................................................................ ........ 12 2 related documents ............................................................................................................. ....... 13 3 processor functions ........................................................................................................... ........ 17 4 signal type definitions ....................................................................................................... ........ 30 5 sdram interface............................................................................................................... ......... 31 6 pci controller ................................................................................................................ ............. 33 7 high-speed, serial interface 0 ................................................................................................ ... 34 8 high-speed, serial interface 1 ................................................................................................ ... 35 9 mii interfaces................................................................................................................ .............. 35 10 utopia-2 interface ........................................................................................................... ......... 37 11 expansion bus interface...................................................................................................... ....... 38 12 uart interfaces .............................................................................................................. ........... 39 13 usb interface ................................................................................................................ ............. 39 14 oscillator interface......................................................................................................... ............. 40 15 gpio interface............................................................................................................... ............. 40 16 jtag interface ............................................................................................................... ............ 40 17 system interface............................................................................................................. ............ 41 18 power interface .............................................................................................................. ............ 41 19 part numbers ................................................................................................................. ............ 43 20 ball map assignment for the intel ? ixp425 network processor................................................. 45 21 ball map assignment for the intel ? ixp422 network processor................................................. 52 22 ball map assignment for the intel ? ixp421 network processor................................................. 59 23 ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor ............................................................................. 66 24 operating conditions ......................................................................................................... ......... 77 25 pci dc parameters ............................................................................................................ ........ 78 26 usb v1.1 dc parameters....................................................................................................... .... 78 27 utopia-2 dc parameters ....................................................................................................... .. 79 28 mii dc parameters ............................................................................................................ ......... 79 29 mdio dc parameters ........................................................................................................... ..... 80 30 sdram bus dc parameters...................................................................................................... 80 31 expansion bus dc parameters .................................................................................................. 81 32 high-speed, serial interface 0 dc parameters.......................................................................... 81 33 high-speed, serial interface 1 dc parameters.......................................................................... 81 34 uart dc parameters ........................................................................................................... ..... 82 35 gpio dc parameters ........................................................................................................... ...... 83 36 jtag dc parameters........................................................................................................... ...... 83 37 pwron_reset _n dc parameters ........................................................................................... 83 38 device clock timings (oscillator reference) ............................................................................. 84 39 device clock timings (crystal reference) ................................................................................. 84 40 pci clock timings ............................................................................................................ .......... 86 41 mii clock timings ............................................................................................................ ........... 86 42 utopia-2 clock timings ....................................................................................................... .... 86 43 expansion bus clock timings .................................................................................................. .. 86 44 pci bus signal timings ....................................................................................................... ....... 88 45 utopia-2 input timings values ................................................................................................ 89 46 utopia-2 output timings values.............................................................................................. 8 9 47 mii output timings values .................................................................................................... ..... 90
datasheet 7 intel ? ixp42x product line and ixc1100 control plane processor contents 48 mii input timings values ..................................................................................................... .......90 49 mdio timings values.......................................................................................................... .......92 50 sdram input timings values ................................................................................................... .92 51 sdram output timings values .................................................................................................9 3 52 intel multiplexed mode values................................................................................................ ....94 53 intel simplex mode values .................................................................................................... .....95 54 motorola* multiplexed mode values ...........................................................................................9 6 55 motorola* simplex mode values................................................................................................ .98 56 hpi timing symbol description ................................................................................................ ..99 57 hpi ? 8 mode write accesses values ........................................................................................99 58 setup/hold timing values ..................................................................................................... ...100 59 hpi-16 multiplexed write accesses values..............................................................................101 60 hpi-16 multiplex read accesses values .................................................................................102 61 hpi-16 non-multiplex read accesses values..........................................................................104 62 hpi-16 non-multiplexed write accesses values......................................................................105 63 high-speed, serial timing values............................................................................................1 08 64 boundary-scan interface timings values ................................................................................109 65 reset timings table parameters .............................................................................................11 1 66 i cc and total average power ...................................................................................................112
intel ? ixp42x product line and ixc1100 control plane processor contents 8 datasheet revision history date revision description june 2004 004 updated intel ? product branding. change bars are ret ained from the previous release of this document (003). april 2004 003 incorporated specification changes , specification clarifications and document changes from the intel ? ixp4xx product line of network processors and ixc1100 control plane processor specification update (252702-003). may 2003 002 incorporated specification changes , specification clarifications and document changes from the intel ? ixp4xx product line of network processors specification update (252702-001). incorporated information for the intel ? ixc1100 control plane processor. february 2003 001 initial release of this document. document reissued, without ?confidential? marking.
intel ? ixp42x product line and ixc1100 control plane processor product features datasheet 9 1.0 product features 1.1 product line features table 1 on page 12 describes which features apply to the intel ? ixp42x product line of network processors and ixc1100 control plane processor. ? intel xscale ? core (compliant with arm * architecture) ? high-performance processor based on intel xscale ? microarchitecture ? seven/eight-stage intel ? super-pipelined risc technology ? management unit ? 32-entry, data memory management unit ? 32-entry, instruction memory management unit ? 32-kbyte, 32-way, set associative instruction cache ? 32-kbyte, 32-way, set associative data cache ? 2-kbyte, two-way, set associative mini-data cache ? 128-entry, branch target buffer ? eight-entry write buffer ? four-entry fill and pend buffers ? clock speeds: ?266mhz ?400mhz ?533mhz ?arm * version v5te compliant ?intel ? media processing technology multiply-accumulate coprocessor ? debug unit accessible through jtag port ? three network processor engines (npes) used to offload typical layer-2 networking functions such as: ? ethernet filtering ?atm saring ? hdlc ? pci interface ? 32-bit interface ? selectable clock ? 33-mhz clock output ? 0- to 66-mhz clock input ? pci local bus specification , rev. 2.2 compatible
intel ? ixp42x product line and ixc1100 control plane processor product features 10 datasheet ? pci arbiter supporting up to four external pci devices (four req/gnt pairs) ? host/option capable ? master/target capable ? two dma channels ? two mii interfaces ? 802.3 mii interfaces ? single mdio interface to control both mii interfaces ? utopia-2 interface ? eight-bit interface ? up to 33 mhz clock speed ? five transmit and five receive address lines ? usb v 1.1 device controller ? full-speed capable ? embedded transceiver ? 16 endpoints ? two high-speed, serial interfaces ?six-wire ? supports speeds up to 8.192 mhz ? supports connection to t1/e1 framers ? supports connection to codec/slics ? eight hdlc channels ? sdram interface ? 32-bit data ? 13-bit address ? 133 mhz ? up to eight open pages simultaneously maintained ? programmable auto-refresh ? programmable cas/data delay ? support for 8 mb, minimum, up to 256 mb maximum ? expansion interface ? 24-bit address ? 16-bit data ? eight programmable chip selects ? supports intel/motorola* microprocessors ? multiplexed-style bus cycles ? simplex-style bus cycles
intel ? ixp42x product line and ixc1100 control plane processor product features datasheet 11 ? encryption/authentication ?des ?des3 ? aes 128-bit and 256-bit ? dsp support for: ? texas instruments* dsps supporting hpi-8 bus cycles ? texas instruments dsps supporting hpi-16 bus cycles ? high-speed/console uarts ? 1,200 baud to 921 kbaud ? 16550 compliant ? 64-byte tx and rx fifos ? cts and rts modem control signals ? internal bus performance monitoring unit ? seven 27-bit event counters ? monitoring of internal bus occurrences and duration events ? 16 gpios ? four internal timers ? packaging ?492-pin pbga ? commercial temperature (0 to +70 c) ? extended temperature (-40 to +85 c)
intel ? ixp42x product line and ixc1100 control plane processor product features 12 datasheet 1.2 processor features 1.3 about this document this datasheet contains a functional overview of the intel ? ixp42x product line of network processors and ixc1100 control plane processor, as well as mechanical data (package signal locations and simulated thermal characteristics), targeted electrical speci fications, and some bus functional wave forms for the device. detailed functional descriptions ? other than parametric performance ? are published in the intel ? ixp42x product line of network processors and ixc1100 control plane processor developer?s manual . other related documents are shown in table 2 . table 1. processor features feature intel ? ixp425 network processor b0 step intel ? ixp422 network processor intel ? ixp421 network processor intel ? ixp420 network processor intel ? ixc1100 control plane processor processor speed (mhz) 266/400/533 266 266 266 1 /400/533 1. only the 266-mhz version of the intel ? ixp420 network processor supports extended temperature. 266/400/533 utopia 2 x x gpio xxxxx uart 0/1 xxxxx hss 0 x x hss 1 x x mii 0 xxxxx mii 1 x x x x usb xxxxx pci xxxxx expansion bus 16-bit, 66-mhz 16-bit, 66-mhz 16-bit, 66-mhz 16-bit, 66-mhz 16-bit, 66-mhz sdram 32-bit, 133-mhz 32-bit, 133-mhz 32-bit, 133-mhz 32-bit, 133-mhz 32-bit, 133-mhz aes / des / des3 x x multi-channel hdlc 8 8 sha-1 / md-5 x x commercial temperature xxxxx extended temperature xxx
intel ? ixp42x product line and ixc1100 control plane processor product features datasheet 13 table 2. related documents document title document # intel ? ixp42x product line of network processors and ixc1100 control plane processor specification update 252702 intel ? ixp42x product line of network processors and ixc1100 control plane processor developer?s manual 252480 intel ? ixp400 software specification update 273795 intel ? ixp400 software programmer?s guide 252539 intel ? ixp4xx product line programmer?s guide (version 1.1) 252539 intel ? xscale? core developer?s manual 273473 intel ? ixp4xx product line and intel ? ixc1100 processor hardware design guideline 252817 intel xscale ? microarchitecture technical summary ? pci local bus specification , rev. 2.2 ? universal serial bus specification , revision 1.1 ? pc133 sdram specification ?
intel ? ixp42x product line and ixc1100 control plane processor functional overview 14 datasheet 2.0 functional overview the intel ? ixp42x product line of network processors and ixc1100 control plane processor are compliant with the arm * version 5te instruction-set architecture (isa). the intel ? ixp42x product line and ixc1100 control plane processors are designed with intel state-of-the-art 0.18- production semiconductor process technology. this process technology ? along with the compactness of the intel xscale core, the ability to simultaneously process up to three integrated network processing engines (npes), and numer ous dedicated-function peripheral interfaces ? enables the ixp42x product line and ixc1100 cont rol plane processors to operate over a wide range of low-cost networking applications, with industry-leading performance. as indicated in figure 1 through figure 4 , the intel ? ixp42x product line and ixc1100 control plane processors combine many features with the intel xscale core to create a highly integrated processor applicable to lan/wan-based networking applications in addition to other embedded networking applications. this section briefly describes the main features of the product. for detailed functional descriptions, see the intel ? ixp42x product line of network processors and ixc1100 control plane processor developer?s manual . figure 1. intel ? ixp425 network processor block diagram b1563-02 media independent interface media independent interface uart 921kbaud timers interrupt controller usb controller gpio controller uart 921kbaud pmu (ahb) test logic unit 66 mhz advanced peripheral bus 133 mhz advanced high-performance bus queue status bus bridge bridge arbiter arbiter ethernet npe b ethernet mac sha-1/md5, des/3des, aes queue manager 8 kb sram pci controller exp bus controller sdram controller 8 - 256 mb intel xscale ? core 266/400/533 mhz 32 kb data cache 32 kb instruction cache 2 kb mini-data cache ethernet npe a ethernet mac wan/voice npe utopia (max 24 xdsl phys) aal, hss, hdlc 16 pins 32-bit utopia 2 hss-w hss-v 16-bit jtag 32-bit 133 mhz advanced high- performance bus
intel ? ixp42x product line and ixc1100 control plane processor functional overview datasheet 15 figure 2. intel ? ixp422 network processor block diagram figure 3. intel ? ixp421 network processor block diagram b1566-02 media independent interface media independent interface uart 921kbaud timers interrupt controller usb controller gpio controller uart 921kbaud pmu (ahb) test logic unit 66 mhz advanced peripheral bus 133 mhz advanced high-performance bus queue status bus bridge bridge arbiter arbiter ethernet npe b ethernet mac sha-1/md5, des, 3des, aes pci controller exp bus controller sdram controller 8 - 256 mb intel xscale ? core 266 mhz 32 kb data cache 32 kb instruction cache 2 kb mini-data cache ethernet npe a ethernet mac 16 pins 32-bit 16-bit jtag 32-bit 133 mhz advanced high- performance bus queue manager 8 kb sram b1565-02 media independent interface uart 921kbaud timers interrupt controller usb controller gpio controller uart 921kbaud pmu (ahb) test logic unit 66 mhz advanced peripheral bus 133 mhz advanced high-performance bus queue status bus bridge bridge arbiter arbiter ethernet npe a ethernet mac queue manager 8 kb sram pci controller exp bus controller sdram controller 8 - 256 mb intel xscale ? core 266 mhz 32 kb data cache 32 kb instruction cache 2 kb mini-data cache 16 pins 32-bit 16-bit jtag 32-bit 133 mhz advanced high- performance bus wan/voice npe utopia (max 4 xdsl phys) aal, hss utopia 2 hss-w hss-v
intel ? ixp42x product line and ixc1100 control plane processor functional overview 16 datasheet figure 4. intel ? ixp420 network processor block diagram b1564-02 media independent interface media independent interface uart 921kbaud timers interrupt controller usb controller gpio controller uart 921kbaud pmu (ahb) test logic unit 66 mhz advanced peripheral bus 133 mhz advanced high-performance bus queue status bus bridge bridge arbiter arbiter ethernet npe b ethernet mac queue manager 8 kb sram pci controller exp bus controller sdram controller 8 - 256 mb intel xscale ? core 266/400/533 mhz 32 kb data cache 32 kb instruction cache 2 kb mini-data cache ethernet npe a ethernet mac 16 pins 32-bit 16-bit jtag 32-bit 133 mhz advanced high- performance bus
intel ? ixp42x product line and ixc1100 control plane processor functional overview datasheet 17 2.1 functional units the following sections briefly describe the function al units and their interaction in the system. for more detailed information, refer to the intel ? ixp42x product line of network processors and ixc1100 control plane processor developer?s manual . unless otherwise specified, the functional descriptions apply to all processors in the ixp42x product line and ixc1100 control plane processors. refer to table 1 on page 12 and figure 1 on page 14 through figure 4 for specific information on supported interfaces 2.1.1 network processor engines (npes) the network processor engines (npes) are dedicated-function processors containing hardware coprocessors integrated into the ixp42x produc t line and ixc1100 control plane processors. the npes are used to off-load processing functions required by the intel xscale core. these npes are high-performance, hardware-multi-threaded processors with additional local-hardware-assist functionality used to off-loa d highly processor-intensive functions such as mii (mac), crc checking/generation, aal 2, aes, des, sha-1, and md5. all instruction code for the npes are stored locally with a dedicated instruction memory bus and dedicated data memory bus. these npes support processing of the dedicated peripherals that can include: ? a universal test and op eration phy interface for atm (utopia) 2 interface ? two high-speed serial (hss) interfaces ? two media-independent interfaces (mii) table 3 specifies which devices, in the ixp42x product line and ixc1100 control plane processors, have which of these capabilities. the npe core is a hardware-multi-threaded processor engine that is used to accelerate functions that are difficult to achieve high performance in a standard risc processor. each npe core is a 133-mhz processor core that has self-contained instruction memory and self-contained data memory that operate in parallel. table 3. processor functions device utopia hss mii 0 mii 1 aes / des / des3 multi-channel hdlc sha-1 / md-5 intel ? ixp425 network processor , b-step xxxx x 8 x intel ? ixp422 network processor xx x x intel ? ixp421 network processor xxx 8 intel ? ixp420 network processor xx intel ? ixc1100 control plane processor xx
intel ? ixp42x product line and ixc1100 control plane processor functional overview 18 datasheet in addition to having separate instruction/data memory and local-code store, the npe core supports hardware multi-threading with support for multiple contexts. the support of hardware multi-threading creates an efficient processor engine with minimal processor stalls due to the ability of the processor core to switch co ntexts in a single clock cycle, based on a prioritized/preemptive basis. the prioritized/preemptive nature of the context switching allows time-critical applications to be implemented in a low-latency fashion ? which is required when processing multi-media applications. the npe core also connects several hardware-bas ed coprocessors that are used to implement functions that are difficult for a processo r to implement. these functions include: these coprocessors are implemented in hard ware, enabling the copr ocessors and the npe processor core to operate in parallel. the combined forces of the hardware multi-thr eading, local-code store, independent instruction memory, independent data memory, and parallel processing allows the intel xscale core to be utilized for application purposes. the multi-processing capability of the peripheral interface functions allows unparalleled performance to be achieved by the application running on the intel xscale core. 2.1.2 internal bus the internal bus architecture of the ixp42x prod uct line and ixc1100 control plane processors is designed to allow parallel processing to occur and to isolate bus utilization, based on particular traffic patterns. the bus is segmented into three major buses: the north ahb, south ahb, and apb. 2.1.2.1 north ahb the north ahb is a 133.32-mhz, 32-bit bus that can be mastered by the npes. the targets of the north ahb can be the sdram or the ahb/ahb bridge. the ahb/ahb bridge allows the npes to access the peripherals and internal targets on the south ahb. data transfers by the npes on the north ahb to the south ahb are targeted predominately to the queue manager. transfers to the ahb/ahb bridge may be ?posted,? when writing, or ?split,? when reading. when a transaction is ?posted,? a master on the north ahb requests a write to a peripheral on the south ahb. if the ahb/ahb bridge has a free fifo location, the write request will be transferred from the master on the north ahb to the ahb/ahb bridge. the ahb/ahb bridge will complete the write on the south ahb, when it can obtain access to the peripheral on the south ahb. the north ahb is released to complete another transaction. when a transaction is ?split,? a master on the north ahb requests a read of a peripheral on the south ahb. if the ahb/ahb bridge has a free fifo location, the read request will be transferred from the master on the north ahb to the ahb/ahb bridge. the ahb/ahb bridge will complete the read on the south ahb, when it can obtain access to the peripheral on the south ahb. ? serialization/de-serialization ? crc checking/generation ? des/3des/aes ? sha-1 ? md5 ? hdlc bit stuffing/de-stuffing
intel ? ixp42x product line and ixc1100 control plane processor functional overview datasheet 19 once the ahb/ahb bridge has obtained the read in formation from the peripheral on the south ahb, the ahb/ahb bridge notifies the arbiter, on the north ahb, that the ahb/ahb bridge has the data for the master that re quested the ?split? transfer. the master on the north ahb ? that requested the split transfer ? will arbitrate for th e north ahb and transfer the read data from the ahb/ahb bridge. the north ahb is released to complete another transaction while the north ahb master ? that requested the ?split? tr ansfer ? waits for the data to arrive. these ?posting? and ?splitting? transfers allow control of the north ahb to be given to another master on the north ahb ? enabling the north ahb to achieve maximum efficiency. transfers to the ahb/ahb bridge are considered to be small and infrequent, relative to the traffic passed between the npes on the north ahb and the sdram. 2.1.2.2 south ahb the south ahb is a 133.32-mhz, 32-bit bus that can be mastered by the intel xscale ? core, pci controller, and the ahb/ahb bridge. the targets of the south ahb bus can be the sdram, pci interface, queue manager, expansion bus, or the apb/ahb bridge. accessing across the apb/ahb bridge allows inte rfacing to peripherals attached to the apb. 2.1.2.3 apb bus the apb bus is a 66.66-mhz (which is 2 * osc_in input pin.), 32-bit bus that can be mastered by the ahb/apb bridge only. the targets of the apb bus can be: the apb interface is also used as an alternate-path interface to the npes an d is used for npe code download and configuration. 2.1.3 mii interfaces two industry-standard, media-independent interface (mii) interfaces are integrated into most of the ixp42x product line and ixc1100 control plane processors with separate media-access controllers and independent network processing engines. (see table 3 on page 17 .) the independent npes and macs allow parallel pr ocessing of data traffic on the mii interfaces and off-loading of processing required by the intel xscale ? core. the ixp42x product line and ixc1100 control plane processors are comp liant with the ieee, 802.3 specification. in addition to two mii interfaces, the ixp42x product line and ixc1100 control plane processors include a single management data interface that is used to configure and control phy devices that are connected to the mii interface. ? high-speed uart interface ? console uart interface ? usb v 1.1 interface ? all npes ? internal bus performance monitoring unit (ibpmu) ? interrupt controller ? gpio ? timers
intel ? ixp42x product line and ixc1100 control plane processor functional overview 20 datasheet 2.1.4 utopia 2 the integrated, utopia-2 interface works with a network processing engine, for several of the ixp42x product line and ixc1100 control plane processors. (see table 3 on page 17 .) the utopia-2 interface supports a single- or a multiple-physical-interface configuration with cell-level or octet-level handshaking. the network processing engine handles segmentation and reassembly of atm cells, crc checking/generation , and transfer of data to/from memory. this allows parallel processing of data traffic on the utopia-2 interface, off-loading processor overhead required by the intel xscale ? core. the ixp42x product line and ixc1100 control pl ane processors are compliant with the atm forum , utopia level-2 specification , revision 1.0. 2.1.5 usb interface the integrated usb 1.1 interface is a device-on ly controller. the interface supports full-speed operation and 16 endpoints and includes an integrated transceiver. there are: ? six isochronous endpoints (three input and three output) ? one control endpoints ? three interrupt endpoints ? six bulk endpoints (three input and three output) 2.1.6 pci controller the ixp42x product line and ixc1100 control plane processors? pci controller is compatible with the pci local bus specification , rev. 2.2. the pci interface is 32-bit compatible bus and capable of operating as either a host or an option (i.e. not the host) for more information on pci controller support and configuration see the intel ? ixp42x product line of network processors and ixc1100 control plane processor developer?s manual 2.1.7 sdram controller the memory controller manages the interface to external sdram memory chips. the interface: ? operates at 133.32 mhz (which is 4 * osc_in input pin.) ? supports eight open pages simultaneously ? has two banks to support memory configurations from 8 mbyte to 256 mbyte the memory controller only supports 32-bit memory. if a x16 memory chip is used, a minimum of two memory chips would be required to facilitate the 32-bit interface required by the ixp42x product line and ixc1100 control plane processors. a maximum of four sdram memory chips may be attached to the processors. for more information on sdram support and configuration see the intel ? ixp42x product line of network processors and ixc1100 control plane processor developer?s manual .
intel ? ixp42x product line and ixc1100 control plane processor functional overview datasheet 21 the memory controller internally interfaces to the north ahb and south ahb with independent interfaces. this architecture allows sdram transf ers to be interleaved and pipelined to achieve maximum possible efficiency. the maximum burst size supported to the sdram in terface is eight 32-bit words. this burst size allows the best efficiency/fairness performan ce between accesses from the north ahb and the south ahb. 2.1.8 expansion bus the expansion interface allows easy and ? in most cases ? glue-less connection to peripheral devices. it also provides input information for device configuration after reset. some of the peripheral device types are flash, atm control in terfaces, and dsps used for voice applications. (some voice configurations can be supported by the hss interfaces and the intel xscale ? core, implementing voice-compression algorithms.) the expansion bus interface is a 16-bit interface th at allows an address range of 512 bytes to 16 mbytes, using 24 address lines for each of the eight independent chip selects. accesses to the expansion bus interface consists of five phases. each of the five phases can be lengthened or shortened by setting various configura tion registers on a per-chip-select basis. this feature allows the ixp42x product line and ixc1100 control plane processors to connect to a wide variety of peripheral devices with varying speeds. the expansion bus interface supports intel or motorola* microprocessor-style bus cycles. the bus cycles can be configured to be mu ltiplexed address/data cycles or separate address/data cycles for each of the eight chip-selects. additionally, chip selects 4 through 7 can be configured to support texas instruments hpi-8 or hpi-16 style accesses for dsps. the expansion bus interface is an asynchronous inte rface to externally connected chips. however, a clock must be supplied to the ixp42x product line and ixc1100 control plane processors? expansion bus interface for the interface to operate. this clock can be driven from gpio 15 or an external source. the maximum clock rate th at the expansion bus interface can accept is 66.66 mhz. at the de-assertion of reset, the 24-bit address bus is used to capture configuration information from the levels that are applied to the pins at this time. external pull-up/pull-down resistors are used to tie the signals to particular logic levels. (for additional details, see ?package and pinout information? on page 42 .) 2.1.9 high-speed, serial interfaces the high-speed, serial interfaces are six-signal inte rfaces that support serial transfer speeds from 512 khz to 8.192 mhz, for some models of the ixp42x product line and ixc1100 control plane processors. (see table 3 on page 17 .) each interface allows direct connection of up to four t1/e1 framers and codec/slics to the ixp42x product line and ixc1100 control plane pr ocessors. the high-speed, serial interfaces are capable of supporting various protocols, based on the implementation of the code developed for the network processor engine core. for a list of supported protocols, see the intel ? ixp400 software programmer?s guide .
intel ? ixp42x product line and ixc1100 control plane processor functional overview 22 datasheet 2.1.10 high-speed and console uarts the uart interfaces are 16550-compliant uarts w ith the exception of transmit and receive buffers. transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the 16550 uart specification. the interface can be configured to support sp eeds from 1,200 baud to 921 kbaud. the interface support configurations of: ? five, six, seven, or eight data-bit transfers ? one or two stop bits ? even, odd, or no parity the request-to-send (rts_n) and clear-to-send (c ts_n) modem control signals also are available with the interface for hardware flow control. 2.1.11 gpio there are 16 gpio pins supported by the ixp42x product line and ixc1100 control plane processors. gpio pins 0 through 13 can be configured to be general-purpose input or general-purpose output. additionally, gpio pins 0 through 12 can be configured to be an interrupt input. gpio pin 14 can be configured similar to gpio pin 13 or as a clock output. the output-clock configuration can be set at various speeds, up to 33.33 mhz, with various duty cycles. gpio pin 14 is configured as an input, upon reset. gpio pin 15 can be configured similar to gpio pin 13 or as a clock output. the output-clock configuration can be set at various speeds, up to 33.33 mhz, with various duty cycles. gpio pin 15 is configured as a clock output, upon reset. gp io pin 15 can be used to clock the expansion interface, after reset. 2.1.12 internal bus performance monitoring unit (ibpmu) the ixp42x product line and ixc1100 control plane processors consists of seven 27-bit counters that may be used to capture predefined durati ons or occurrence events on the north ahb, south ahb, or sdram controller page hits/misses. 2.1.13 interrupt controller the ixp42x product line and ixc1100 control plane processors consists of 32 interrupt sources to allow an extension of the intel xscale ? core fiq and irq interrupt sources. these sources can originate from some external gpio pins or internal peripheral interfaces. the interrupt controller can configure each interr upt source as an fiq, irq, or disabled. the interrupt sources tied to interrupt 0 to 7 can be prioritized. the remaining interrupts are prioritized in ascending order. for example, interrupt 8 has a high er priority than 9, 9 has a higher priority than 10, and 30 has a higher priority that 31.
intel ? ixp42x product line and ixc1100 control plane processor functional overview datasheet 23 2.1.14 timers the ixp42x product line and ixc1100 control plane processors consists of four internal timers operating at 66.66 mhz (which is 2 * osc_in input pin.) to allow task scheduling and prevent software lock-ups. the device has four 32-bit counters: 2.1.15 ahb queue manager the ahb queue manager (aqm) provides queue functionality for various internal blocks. it maintains the queues as circular buffers in an em bedded 8kb sram. it also implements the status flags and pointers required for each queue. the aqm manages 64 independent queues. each qu eue is configurable for buffer and entry size. additionally status flags are maintained for each queue. the aqm interfaces include an advanced high -performance bus (ahb) interface to the npes and intel xscale core (or any other ahb bus master ), a flag bus interface, an event bus (to the npe condition select logic) and two interrupts to the intel xscale core. the ahb interface is used for configuration of the aqm and provides access to queues, queue status and sram. individual queue status for queues 0-31 is communicated to the npes via the flag bus. combined queue status for queues 32-63 are communicated to the npes via the event bus. the two interrupts, one for queues 0-31 and one for queues 32-63, provide status interrupts to the intel xscale core. 2.2 intel xscale ? core the intel xscale ? core technology is compliant with the arm * version 5te instruction-set architecture (isa). the intel xscale core ? shown in figure 5 ? is designed with intel state-of-the-art, 0.18--production semiconductor process technology. this process technology enables the intel xscale core to operate over a wide speed and power range, producing industry-leading mw/mips performance. intel xscale core features include: ? seven/eight-stage super-pipeline promotes high-speed, efficient core performance ? 128-entry branch target buffer keeps pipeline fi lled with statistically correct branch choices ? 32-entry instruction memory-management unit for logical-to-physical address translation, access permissions, i-cache attributes ? 32-entry data-memory management unit for lo gical-to-physical address translation, access permissions, d-cache attributes ? 32-kbyte instruction cache can hold entire pr ograms, preventing core stalls caused by multi-cycle memory accesses ? 32-kbyte data cache reduces core stalls caused by multi-cycle memory accesses ? 2-kbyte mini-data cache for frequ ently changing data streams avoids ?thrashing? of the d-cache ? four-entry fill-and-pend buffers to promote core efficiency by allowing ?hit-under-miss? operation with data caches ? watch-dog timer ? timestamp timer ? two general-purpose timers
intel ? ixp42x product line and ixc1100 control plane processor functional overview 24 datasheet ? eight-entry write buffer allows the core to continue execution while data is written to memory ? multiple-accumulate coprocessor that can do two simultaneous, 16-bit, simd multiplies with 40-bit accumulation for efficient, high-quality media and signal processing ? performance monitoring unit (pmu) furnishing two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. this pmu is for the intel xscale core only. an additional pmu is supplied for monitoring of internal bus performance. ? jtag debug unit that uses hardware break points and 256-entry trace history buffer (for flow-change messages) to debug programs 2.2.1 super pipeline the super pipeline is composed of integer, multiply-accumulate (mac), and memory pipes. the integer pipe has seven stages: ? branch target buffer (btb)/fetch 1 ? fetch 2 ? decode ? register file/shift ? alu execute ? state execute figure 5. intel xscale ? core block diagram a9568-02 multiply accumulate execution core interrupt request instruction fiq coprocessor interface irq data address data system management debug/ pmu jtag south ahb bus data cache 32 kb mini-data cache 2 kb m m u instruction cache 32 kb m m u branch target cache
intel ? ixp42x product line and ixc1100 control plane processor functional overview datasheet 25 ? integer writeback the memory pipe has eight stages: ? the first five stages of the integer pipe (btb/fetch 1 through alu execute) . . . then finish with the following memory stages: ? data cache 1 ? data cache 2 ? data cache writeback the mac pipe has six to nine stages: ? the first four stages of the integer pipe (btb/fetch 1 through register file/ shift) . . . then finish with the following mac stages: ? mac 1 ? mac 2 ? mac 3 ? mac 4 ? data cache writeback the mac pipe supports a data-dependent early terminate where stages mac 2, mac 3, and/or mac 4 are bypassed. deep pipes promote high instruction execution ra tes only when a means exists to successfully predict the outcome of branch instructions. th e branch target buffer provides such a means. 2.2.2 branch target buffer (btb) each entry of the 128-entry btb contains the addr ess of a branch instruction, the target address associated with the branch instruction, and a pr evious history of the branch being taken or not taken. the history is recorded as one of four states: the btb can be enabled or disabled via coprocessor 15, register 1. when the address of the branch instruction hits in the btb and its history is strongly or weakly taken, the instruction at the branch target address is fetched. when its history is strongly or weakly not-taken, the next sequential instruction is fetched. in either case the history is updated. data associated with a branch instruction enters the btb the first time the branch is taken. this data enters the btb in a slot with a history of strongly not-taken (overwriting previous data when present). successfully predicted branches avoid any branch-latency penalties in the super pipeline. unsuccessfully predicted branches re sult in a four to five cycle bran ch-latency penalty in the super pipeline. ? strongly taken ? weakly taken ? weakly not taken ? strongly not taken
intel ? ixp42x product line and ixc1100 control plane processor functional overview 26 datasheet 2.2.3 instruction memory management unit (immu) for instruction pre-fetches, the immu controls logical-to-physical address translation, memory access permissions, memory-domain identifications, and attributes (governing operation of the instruction cache). the immu contains a 32-entry , fully associative inst ruction-translation, look-aside buffer (itlb) that has a round-robin replacement policy. itlb entries zero through 30 can be locked. when an instruction pre-fetch misses in the i tlb, the immu invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the itlb. the descriptor contains information for logical-to-physical address translation, memory-access permissions, memory-domain identifications, and attributes governing operation of the i-cache. the immu then continues the instruction pre-fetc h by using the address translation just entered into the itlb. when an instruction pre-fetch hits in the itlb, the immu continues the pre-fetch using the address translation already resident in the itlb. access permissions for each of up to 16 memory domains can be programmed. when an instruction pre-fetch is attempted to an area of memory in violation of access permissions, the attempt is aborted and a pre-fetch abort is sent to the core for exception processing. the immu and dmmu can be enabled or disabled together. 2.2.4 data memory management unit (dmmu) for data fetches, the dmmu controls logical-t o-physical address translation, memory-access permissions, memory-domain identifications, and attributes (governing operation of the data cache or mini-data cache and write buffer). the dmmu contains a 32-entry, fully associative data-translation, look-aside buffer (dtlb) th at has a round-robin replacement policy. dtlb entries 0 through 30 can be locked. when a data fetch misses in the dtlb, the d mmu invokes an automatic table-walk mechanism that fetches an associated descriptor from memo ry and loads it into the dtlb. the descriptor contains information for logical-to-physical address translation, memory-access permissions, memory-domain identifications, and attributes ( governing operation of the d-cache or mini-data cache and write buffer). the dmmu continues the data fetch by using the address translation just entered into the dtlb. when a data fetch hits in the dtlb, the dmmu continues the fetch using the address translation already resident in the dtlb. access permissions for each of up to 16 memory domains can be programmed. when a data fetch is attempted to an area of memory in violation of access permissions, the attempt is aborted and a data abort is sent to the core for exception processing. the immu and dmmu can be enabled or disabled together. 2.2.5 instruction cache (i-cache) the i-cache can contain high-use, multiple-code se gments or entire programs, allowing the core access to instructions at core frequencies. this prevents core stalls caused by multi-cycle accesses to external memory.
intel ? ixp42x product line and ixc1100 control plane processor functional overview datasheet 27 the 32-kbyte i-cache is 32-set/32-way associative, where each set contains 32 ways and each way contains a tag address, a cache line of instructions (eight 32-bit words and one parity bit per word), and a line-valid bit. for each of the 32 sets, 0 through 28 ways can be locked. unlocked ways are replaceable via a round-robin policy. the i-cache can be enabled or disa bled. attribute bits within the descriptors ? contained in the itlb of the immu ? provide some control over an enabled i-cache. when a needed line (eight 32-bit words) is not pr esent in the i-cache, the line is fetched (critical word first) from memory via a two-level, deep -fetch queue. the fetch queue allows the next instruction to be accessed from the i-cache, but on ly when its data operands do not depend on the execution results of the instruction being fetched via the queue. 2.2.6 data cache (d-cache) the d-cache can contain high-use data such as l ookup tables and filter coefficients, allowing the core access to data at core frequencies. this prevents core stalls caused by multi-cycle accesses to external memory. the 32-kbyte d-cache is 32-set/32-way associative, where each set contains 32 ways and each way contains a tag address, a cache line (32 bytes w ith one parity bit per byte) of data, two dirty bits (one for each of two eight-byte groupings in a line), and one valid bit. for each of the 32 sets, zero through 28 ways can be locked, unlocked, or used as local sram. unlocked ways are replaceable via a round-robin policy. the d-cache (together with the mini-data cache) can be enabled or disabled. attribute bits within the descriptors, contained in the dtlb of the dmmu, provide significant control over an enabled d-cache. these bits specify cache operating modes such as read and write allocate, write-back, write-through, and d-cache versus mini-data cache targeting. the d-cache (and mini-data cache) work with th e load buffer and pend buffer to provide ?hit-under-miss? capability that a llows the core to access other data in the cache after a ?miss? is encountered. the d-cache (and mini-data cache) wo rks in conjunction with the write buffer for data that is to be stored to memory. 2.2.7 mini-data cache the mini-data cache can c ontain frequently changing data str eams such as mpeg video, allowing the core access to data streams at core frequencies . this prevents core stalls caused by multi-cycle accesses to external memory. the mini-data cache relieves the d-cache of data ?thrashing? caused by frequently changing data streams. the 2-kbyte, mini-data cache is 32-set/two-way associative, where each set contains two ways and each way contains a tag address, a cache line (32 byt es with one parity bit per byte) of data, two dirty bits (one for each of two eight-byte groupi ngs in a line), and a valid bit. the mini-data cache uses a round-robin replacement policy, and cannot be locked. the mini-data cache (together with the d-cache) can be enabled or disabled. attribute bits contained within a coprocessor register specify operating modes write and/or read allocate, write-back, and write-through.
intel ? ixp42x product line and ixc1100 control plane processor functional overview 28 datasheet the mini-data cache (and d-cache) work with the load buffer and pend buffer to provide ?hit-under-miss? capability that allows the core to access other data in the cache after a ?miss? is encountered. the mini-data cache (and d-cache) works in conjunction with the write buffer for data that is to be stored to memory. 2.2.8 fill buffer (fb) and pend buffer (pb) the four-entry fill buffer (fb) works with the core to hold non-cacheable loads until the bus controller can act on them. the fb and the four-e ntry pend buffer (pb) work with the d-cache and mini-data cache to provide ?hit-under-miss? capability, allowing the core to seek other data in the caches while ?miss? data is being fetched from memory. the fb can contain up to four unique ?miss? addre sses (logical), allowing four ?misses? before the core is stalled. the pb holds up to four addr esses (logical) for additional ?misses? to those addresses that are already in the fb. a coprocessor register can specify draining of the fill and pend (write) buffers. 2.2.9 write buffer (wb) the write buffer (wb) holds data for storage to memory until the bus controller can act on it. the wb is eight entries deep, where each entry hold s 16 bytes. the wb is constantly enabled and accepts data from the core, d-cache, or mini-data cache. coprocessor 15, register 1 specifies whether wb coalescing is enabled or disabled. when coalescing is disabled, stores to memory occur in program order regardless of the attribute bits within the descriptors located in the dtlb. when coalescing is enab led, the attribute bits within the descriptors located in the dtlb are examined to determine when coalescing is enabled for the destination region of memory. when coalescing is enabled in both cp15, r1 and the dtlb, data entering the wb can coalesce with any of the eight entries (16 bytes) and be stored to the destination memory region, but possibly out of program order. stores to a memory region specified to be non- cacheable and non-bufferable by the attribute bits within the descriptors located in the dtlb causes the core to stall until the store completes. a coprocessor register can specify draining of the write buffer. 2.2.10 multiply-accumulate coprocessor (cp0) for efficient processing of high-quality, media-and-signal-processing algorithms, cp0 provides 40-bit accumulation of 16 x 16, dual-16 x 16 (simd), and 32 x 32 signed multiplies. special mar and mra instructions are implemented to move the 40-bit accumulator to two core-general registers (mar) and move two core-general regist ers to the 40-bit accumulator (mra). the 40-bit accumulator can be stored or loaded to or fro m d-cache, mini-data cache, or memory using two stc or ldc instructions. the 16 x 16 signed multiply-accumulates (miaxy) multiply either the high/high, low/low, high/low, or low/high 16 bits of a 32-bit core general register (multiplier) and another 32-bit core general register (multiplicand) to produce a full, 32-bit product that is sign-extended to 40 bits and added to the 40-bit accumulator. dual-signed, 16 x 16 (simd) multiply-accumulates (miaph) multiply the high/high and low/low 16-bits of a packed 32-bit, core-general register (multiplier) and another packed 32-bit, core-general register (multiplicand) to produce two 16-bits products that are both sign-extended to 40 bits and added to the 40-bit accumulator.
intel ? ixp42x product line and ixc1100 control plane processor functional overview datasheet 29 the 32 x 32 signed multiply-accumulates (mia) multiply a 32-bit, core-general register (multiplier) and another 32-bit, core-general re gister (multiplicand) to produce a 64-bit product where the 40 lsbs are added to the 40-bit accu mulator. the 16 x 32 versions of the 32 x 32 multiply-accumulate instructions complete in a single cycle. 2.2.11 performance monitoring unit (pmu) the performance monitoring unit contains two 32-bit, event counters and one 32-bit, clock counter. the event counters can be programmed to monitor i-cache hit rate, data caches hit rate, itlb hit rate, dtlb hit rate, pipeline stalls, btb prediction hit rate, and instruction execution count. 2.2.12 debug unit the debug unit is accessed through the jtag port. the industry-standard, ieee 1149.1 jtag port consists of a test access port (tap) controller, boundary-scan register, instruction and data registers, and dedicated signals tdi, tdo, tck, tms, and trst#. the debug unit ? when used with debugger application code running on a host system outside of the intel xscale core ? allows a program, running on the intel xscale core, to be debugged. it allows the debugger application code or a debug exception to stop program execution and redirect execution to a debug-handling routine. debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug breakpoint, exception vector trap, and trace buffer full breakpoint. once execution has stopped, the debugger application code can examine or modify the core?s state, coprocessor state, or memory. the debugger application code can then restart program execution. the debug unit has two hardware-instruction, break point registers; two hardware, data-breakpoint registers; and a hardware, data-breakpoint control register. the second data-breakpoint register can be alternatively used as a mask register for the first data-breakpoint register. a 256-entry trace buffer provides the ability to cap ture control flow messages or addresses. a jtag instruction (ldic) can be used to download a debug handler via the jtag port to the mini-instruction cache (the i-cache has a 2-kbyte, mini-instruction cache to hold a debug handler).
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions 30 datasheet 3.0 functional signal descriptions listed in the signal definition tables ? starting at table 5, ?sdram interface? on page 31 ? are pull-up an pull-down resistor recommendations that are required when the particular enabled interface is not being used in the application. thes e external resistor requirements are only needed if the particular model of intel ? ixp42x product line and ixc1100 control plane processors has the particular interface enabled and the interface is not required in the application. warning: all ixp42x product line and ixc1100 control plane processors i/o pins are not 5-v tolerant. disabled features, within the ixp42x product line and ixc1100 control plane processors, do not require external resistors as the processor will have internal pull-up or pull-down resistors enabled as part of the disabled interface. table 4 presents the legend for interpreting the type field in the other tables in this section of the document. to determine which interfaces are not enabled within the ixp42x product line and ixc1100 control plane processors, see table 1 on page 12 . table 4. signal type definitions symbol description i input pin only o output pin only i/o pin can be either an input or output od open drain pin pwr power pin gnd ground pin 1 driven to vcc 0 driven to vss x driven to unknown state id input is disabled h pulled up to vcc l pulled to vss pd pull-up disabled z output disabled vo a valid output level is driven, allowed states -- 1, 0, h, z vi need to drive a valid input level, allowed states - 1, 0, h, z pe pull-up enabled, equivalent to h tri output only/tristatable n/c no connect - pin must be connected as described
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions datasheet 31 this section?s other tables include: ? table 5 ? sdram interface signals ? table 6 ? pci controller signals ? table 7 ? high-speed, serial interface 0 signals ? table 8 ? high-speed, serial interface 1 signals ? table 9 ? mii interfaces signals ? table 10 ? utopia-2 interface signals ? table 11 ? expansion bus interface signals ? table 12 ? uart interfaces signals ? table 13 ? usb interface signals ? table 14 ? oscillator interface signals ? table 15 ? gpio interface signals ? table 16 ? jtag interface signals ? table 17 ? system interface signals ? table 18 ? power interface signals note: 1. the power on reset column of the tables indicate the state of the signals during the power on reset process 2. the reset column of the tables indicate the state of the signals during the reset. table 5. sdram interface (sheet 1 of 2) name power on reset ? reset ? type ? description sdm_addr[12:0] z 0 o sdram address: a0-a12 signals are output during the read/write commands and active commands to select a location in memory to act upon. sdm_data[31:0] z 1i/o sdram data: bidirectional data bus used to transfer data to and from the sdram sdm_clkout z 0o sdram clock: all sdram input signals are sampled on the rising edge of sdm_clkout. all output signals are driven with respect to the rising edge of sdm_clkout. sdm_ba[1:0] z 0o sdram bank address: sdm_ba0 and sdm_ba1 define the bank the current command is attempting to access. sdm_ras_n z 1 o sdram row address strobe/select (active low): along with sdm_cas_n, sdm_we_n, and sdm_cs_n signals determines the current command to be executed. sdm_cas_n z 1o sdram column address strobe/select (active low): along with sdm_ras_n, sdm_we_n, and sdm_cs_n signals determines the current command to be executed. sdm_cs_n[1:0] z 1o sdram chip select (active low): cs# enables the command decoder in the external sdram when logic low and disables the command decoder in the external sdram when logic high. sdm_we_n z 1o sdram write enable (active low): along with sdm_cas_n, sdm_ras_n, and sdm_cs_n signals determines the current command to be executed. ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions 32 datasheet sdm_cke z 1 o sdram clock enable: cke is driving high to activate the clock to an external sdram and driven low to de-activate the clk to an external sdram. sdm_dqm[3:0] z 0 o sdram data bus mask: dqm is used to byte select data during read/write access to an external sdram. table 5. sdram interface (sheet 2 of 2) name power on reset ? reset ? type ? description ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions datasheet 33 table 6. pci controller (sheet 1 of 2) name power on reset ? reset ? type ? description pci_ad[31:0] z z i/o pci address/data bus used to transfer address and bidirectional data to and from multiple pci devices. should be pulled low with a 10-k ? resistor when not being utilized in the system. pci_cbe_n[3:0] z z i/o pci command/byte enables is used as a command word during pci address cycles and as byte e nables for data cycles. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_par z z i/o pci parity used to check parity across the 32 bits of pci_ad and the four bits of pci_cbe_n. should be pulled low with a 10-k ? resistor when not being utilized in the system. pci_frame_n z z i/o pci cycle frame used to signify the beginning and duration of a transaction. the signal will be inactive prior to or during the final data phase of a given transaction. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_trdy_n z z i/o pci target ready informs that the target of the pci bus is ready to complete the current data phase of a given transaction. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_irdy_n z z i/o pci initiator ready informs the pci bus that the initiator is ready to complete the transaction. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_stop_n z z i/o pci stop indicates that the current target is requesting the current initiator to stop the current transaction. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_perr_n z z i/o pci parity error asserted when a pci parity error is detected ? between the pci_par and associated information on the pci_ad bus and pci_cbe_n ? during all pci transactions, except for special cycles. the agent receiving data will drive this signal. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_serr_n z z i/od pci system error asserted when a parity error occurs on special cycles or any other error that will cause the pci bus not to function properly. this signal can function as an input or an open drain output. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_devsel_n z z i/o pci device select: ? when used as an output, pci_devsel_n indicates that device has decoded that address as the target of the requested transaction. ? when used as an input, pci_devsel_n indicates if any device on the pci bus exists with the given address. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_idsel z z i pci initialization device select is a chip select during configuration reads and writes. should be pulled low with a 10-k ? resistor when not being utilized in the system. pci_req_n[3:1] z z i pci arbitration request: used by the internal pci arbiter to allow an agent to request the pci bus. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_req_n[0] z z i/o pci arbitration request: ? when configured as an input (pci arbiter enabled), the internal pci arbiter will allow an agent to request the pci bus. ? when configured as an output (pci arbiter disabled), the pin will be used to request access to the pci bus from an external arbiter. should be pulled high with a 10-k ? resistor, when the pci bus is not being utilized in the system. pci_gnt_n[3:1] z z o pci arbitration grant: generated by the internal pci arbiter to allow an agent to claim control of the pci bus. ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions 34 datasheet pci_gnt_n[0] z z i/o pci arbitration grant: ? when configured as an output (pci arbiter enabled), the internal pci arbiter to allow an agent to claim control of the pci bus. ? when configured as an input (pci arbiter disabled), the pin will be used to claim access of the pci bus from an external arbiter. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_inta_n z z o/d pci interrupt: used to request an interrupt. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_clkin z vi i pci clock: provides timing for all transactions on pci. all pci signals ? except inta#, intb#, intc#, and intd# ? are sampled on the rising edge of clk and timing parameters are defined with respect to this edge. the pci clock rate can operate at up to 66 mhz. should be pulled low with a 10-k ? resistor when not being utilized in the system. table 7. high-speed, serial interface 0 name power on reset ? reset ? type ? description hss_txframe0 z z i/o the high-speed serial (hss) transmit frame signal can be configured as an input or an output to allow an external source become synchronized with the transmitted data. often known as a frame sync signal. configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_txdata0 z z o/d transmit data out. open drain output. must be pulled high with a 10-k ? resistor to v ccp . hss_txclk0 z z i/o the high-speed serial (hss) transmit clock signal can be configured as an input or an output. the clock can be a frequency ranging from 512 khz to 8.192 mhz. used to clock out the transmitted data. configured as an input upon reset. frame sync and data can be selected to be generated on the rising or falling edge of the transmit clock. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_rxframe0 z z i/o the high-speed serial (hss) receive frame signal can be configured as an input or an output to allow an external source to become synchronized with the received data. often known as a frame sync signal. configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_rxdata0 z vi i receive data input. can be sampled on the rising or falling edge of the receive clock. should be pulled low through a 10-k ? resistor when not being utilized in the system. hss_rxclk0 z z i/o the high-speed serial (hss) receive clock signal can be configured as an input or an output. the clock can be from 512 khz to 8.192 mhz. used to sample the received data. configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. table 6. pci controller (sheet 2 of 2) name power on reset ? reset ? type ? description ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions datasheet 35 table 8. high-speed, serial interface 1 name power on reset ? reset ? type ? description hss_txframe1 z z i/o the high-speed serial (hss) transmit frame signal can be configured as an input or an output to allow an external source to be synchronized with the transmitted data. often known as a frame sync signal. configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_txdata1 z z o/d transmit data out. open drain output. must be pulled high with a 10-k ? resistor to v ccp . hss_txclk1 z z i/o the high-speed serial (hss) transmit clock signal can be configured as an input or an output. the clock can be a frequency ranging from 512 khz to 8.192 mhz. used to clock out the transmitted data. configured as an input upon reset. frame sync and data can be selected to be generated on the rising or falling edge of the transmit clock. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_rxframe1 z z i/o the high-speed serial (hss) receive frame signal can be configured as an input or an output to allow an external source to be synchronized with the received data. often known as a frame sync signal. configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_rxdata1 z vi i receive data input. can be sampled on the rising or falling edge of the receive clock. should be pulled low through a 10-k ? resistor when not being utilized in the system. hss_rxclk1 z z i/o the high-speed serial (hss) receive clock signal can be configured as an input or an output. the clock can be from 512 khz to 8.192 mhz. used to sample the received data. configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. ? for a legend of the type codes, see table 4 on page 30 . table 9. mii interfaces (sheet 1 of 2) name power on reset ? reset ? type ? description eth_txclk0 zvii externally supplied transmit clock. ? 25 mhz for 100-mbps operation ? 2.5 mhz for 10 mbps should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_txdata0[3:0] z0o transmit data bus to phy, asserted synchronously with respect to eth_txclk0. eth_txen0 z0o indicates that the phy is being presented with nibbles on the mii interface. asserted synchronously, with respect to eth_txclk0, at the first nibble of the preamble and remains asserted until all the nibbles of a frame are presented. eth_rxclk0 zvii externally supplied receive clock. ? 25 mhz for 100-mbps operation ? 2.5 mhz for 10 mbps should be pulled low through a 10-k ? resistor when not being utilized in the system. ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions 36 datasheet eth_rxdata0[3:0] zvii receive data bus from phy, data sampled synchronously with respect to eth_rxclk0 ? should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_rxdv0 zvii receive data valid, used to inform the mii interface that the ethernet phy is sending data. should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_col0 zvii asserted by the phy when a collision is detected by the phy. should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_crs0 zvii asserted by the phy when the transmit medium or receive medium is active. de-asserted when both the transmit and receive medium are idle. remains asserted throughout the duration of a collision condition. phy asserts crs asynchronously and de-asserts synchronously, with respect to eth_rxclk0. should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_mdio z z i/o management data output. provides the write data to both phy devices connected to each mii interface. should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_mdc zzo management data clock. management data interface clock is used to clock the mdio signal as an output and sample the mdio as an input. the eth_mdc is an input on power up and can be configured to be an output through an intel api as documented in the intel ? ixp400 software programmer?s guide . eth_txclk1 zvii externally supplied transmit clock. ? 25 mhz for 100-mbps operation ? 2.5 mhz for 10 mbps should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_txdata1[3:0] z0o transmit data bus to phy, asserted synchronously with respect to eth_txclk1. eth_txen1 z0o indicates that the phy is being presented with nibbles on the mii interface. asserted synchronously, with respect to eth_txclk1, at the first nibble of the preamble, and remains asserted until all the nibbles of a frame are presented. eth_rxclk1 zvii externally supplied receive clock. ? 25 mhz for 100-mbps operation ? 2.5 mhz for 10 mbps should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_rxdata1[3:0] zvii receive data bus from phy, data sampled synchronously, with respect to eth_rxclk1. ? should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_rxdv1 zvii receive data valid, used to inform the mii interface that the ethernet phy is sending data. should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_col1 zvii asserted by the phy when a collision is detected by the phy. ? should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_crs1 zvii asserted by the phy when the transmit medium or receive medium are active. de-asserted when both the transmit and receive medium are idle. remains asserted throughout the duration of collision condition. phy asserts crs asynchronously and de-asserts synchronously with respect to eth_rxclk1. should be pulled low through a 10-k ? resistor when not being utilized in the system. table 9. mii interfaces (sheet 2 of 2) name power on reset ? reset ? type ? description ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions datasheet 37 table 10. utopia-2 interface (sheet 1 of 2) name power on reset ? reset ? type ? description utp_op_clk z vi i utopia transmit clock input. also known as utp_tx_clk. this signal is used to synchronize all utopia-transmit outputs to the rising edge of the utp_op_clk. this signal should be pulled low through a 10-k ? resistor when not being utilized in the system. utp_op_fco z z o utopia flow control output signal. also known as the txenb_n signal. used to inform the selected phy that data is being transmitted to the phy. placing the phy?s address on the utp_op_addr ? and bringing utp_op_fco to logic 1, during the current clock ? followed by the utp_op_fco going to a logic 0, on the next clock cycle, selects which phy is active in mphy mode. in sphy configurations, utp_op_fco is used to inform the phy that the processor is ready to send data. utp_op_soc z z o start of cell. also known as tx_soc. active high signal is asserted when utp_op_data contains the first valid byte of a transmitted cell. utp_op_data[7:0] z z o utopia output data. also known as utp_tx_data. used to send data from the processor to an atm utopia-level-2-compliant phy. utp_op_addr[4:0] z vi o transmit phy address bus. used by the processor when operating in mphy mode to poll and select a single phy at any given time. utp_op_fci z vi i utopia output data flow control input: also known as the txfull/clav signal. used to inform the processor of the ability of each polled phy to receive a complete cell. for cell-level flow control in an mphy environment, txclav is an active high tri-stateable signal from the mphy to atm layer. the utp_op_fci, which is connected to multiple mphy devices, will see logic high generated by the phy, one clock after the given phy address is asserted ? when a full cell can be received by the phy. the utp_op_fci will see a logic low generated by the phy one clock cycle, after the phy address is asserted ? if a full cell cannot be received by the phy. this signal should be tied low through a 10-k ? resistor if not being used. utp_ip_clk z vi i utopia receive clock input. also known as utp_rx_clk. this signal is used to synchronize all utopia-received inputs to the rising edge of the utp_ip_clk. this signal should be pulled low through a 10-k ? resistor when not being utilized in the system. utp_ip_fci z vi i utopia input data flow control input signal. also known as rxempty/clav. used to inform the processor of the ability of each polled phy to send a complete cell. for cell-level flow control in an mphy environment, rxclav is an active high tri-stateable signal from the mphy to atm layer. the utp_ip_fci, which is connected to multiple mphy devices, will see logic high generated by the phy, one clock after the given phy address is asserted, when a full cell can be received by the phy. the utp_ip_fci will see a logic low generated by the phy, one clock cycle after the phy address is asserted if a full cell cannot be received by the phy. in sphy mode, this signal is used to indicate to the processor that the phy has an octet or cell available to be transferred to the processor . should be pulled low through a 10-k ? resistor when not being utilized in the system. utp_ip_soc z vi i start of cell. rx_soc active-high signal that is asserted when utp_ip_data contains the first valid byte of a transmitted cell. should be pulled low through a 10-k ? resistor when not being utilized in the system. ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions 38 datasheet utp_ip_data[7:0] z vi i utopia input data. also known as rx_data. used by to the processor to receive data from an atm utopia-level-2-compliant phy. should be pulled low through a 10-k ? resistor when not being utilized in the system. utp_ip_addr[4:0] z vi o receive phy address bus. used by the processor when operating in mphy mode to poll and select a single phy at any one given time. utp_ip_fco z z o utopia input data flow control output signal: also known as the rx_enb_n. in sphy configurations, utp_ip_fco is used to inform the phy that the processor is ready to accept data. in mphy configurations, utp_ip_fco is used to select which phy will drive the utp_rx_data and utp_rx_soc signals. the phy is selected by placing the phy?s address on the utp_ip_addr and bringing utp_op_fco to logic 1 during the current clock, followed by the utp_op_fco going to a logic 0 on the next clock cycle. table 11. expansion bus interface name power on reset ? reset ? type ? description ex_clk zzi input clock signal used to sample all expansion interface inputs and clock all expansion interface outputs. ex_ale z 0 o address-latch enable used for multiplexed address/data bus accesses. used in intel and motorola* multiplexed modes of operation. ex_addr[23:0] h h i/o expansion-bus address used as an output for data accesses over the expansion bus. also, used as an input during reset to capture device configuration. these signals have a weak pull-up resistor attached internally. based on the desired configuration, various address signals must be tied low in order for the device to operate in the desired mode. ex_wr_n z 1 o intel-mode write strobe / motorola-mode data strobe (exp_mot_ds_n) / ti*-mode data strobe (ti_hds1_n). ex_rd_n z 1 o intel-mode read strobe / motorola-mode read-not-write (expb_mot_rnw) / ti mode read-not-write (ti_hr_w_n). ex_cs_n[7:0] z 1 o external chip selects for expansion bus. ? chip selects 0 through 7 can be configured to support intel or motorola bus cycles. ? chip selects 4 through 7 can be configured to support ti hpi bus cycles. ex_data[15:0] z 0 i/o expansion-bus, bidirectional data ex_iowait_n h h i data ready/acknowledge from expansion-bus devices. expansion-bus access is halted when an external device sets ex_iowait_n to logic 0 and resume from the halted location once the external device sets ex_iowait_n to logic 1. this signal affects accesses that use ex_cs_n[7:0] when the chip select is configured in intel- or motorola-mode of operation. should be pulled high through a 10-k ? resistor when not being utilized in the system. ex_rdy[3:0] h h i hpi interface ready signals. can be configured to be active high or active low. these signals are used to halt accesses using chip selects 7 through 4 when the chip selects are configured to operate in hpi mode. there is one rdy signal per chip select. this signal only affects accesses that use ex_cs_n[7:4]. should be pulled low though a 10-k ? resistor when not being utilized in the system. ? for a legend of the type codes, see table 4 on page 30 . table 10. utopia-2 interface (sheet 2 of 2) name power on reset ? reset ? type ? description ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions datasheet 39 power table 12. uart interfaces name power on reset ? reset ? type ? description rxdata0 z vi i uart serial data input to high-speed uart pins. should be pulled low through a 10-k ? resistor when not being utilized in the system. txdata0 z vo o uart serial data output. the txd signal is set to the marking (logic 1) state upon a reset operation. high-speed serial uart pins. cts0_n h vi/pe i uart clear-to-send input to high-speed uart pins. when logic 0, this pin indicates that the modem or data set connected to the uart interface of the processor is ready to exchange data. the cts_n signal is a modem status input whose condition can be tested by the processor. should be pulled high through a 10-k ? resistor when not being utilized in the system. rts0_n h vo/pe o uart request-to-send output: when logic 0, this informs the modem or the data set connected to the uart interface of the processor that the uart is ready to exchange data. a reset sets the request to send signal to logic 1. loop-mode operation holds this signal in its inactive state (logic 1). high-speed uart pins. rxdata1 z vi i uart serial data input. should be pulled low through a 10-k ? resistor when not being utilized in the system. txdata1 z vo o uart serial data output. the txd signal is set to the marking (logic 1) state upon a reset operation. console uart pins. cts1_n h vi/pe i uart clear-to-send input to console uart pins. when logic 0, this pin indicates that the modem or data set connected to the uart interface of the processor is ready to exchange data. the cts_n signal is a modem status input whose condition can be tested by the processor. should be pulled high through a 10-k ? resistor when not being utilized in the system. rts1_n h vo/pe o uart request-to-send output: when logic 0, this informs the modem or the data set connected to the uart interface of the processor that the uart is ready to exchange data. a reset sets the request to send signal to logic 1. loop-mode operation holds this signal in its inactive state (logic 1). console uart pins. ? for a legend of the type codes, see table 4 on page 30 . table 13. usb interface name power on reset ? reset ? type ? description usb_dpos z z i/o positive signal of the differential usb receiver/driver. usb_dneg z z i/o negative signal of the differential usb receiver/driver. ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions 40 datasheet table 14. oscillator interface name power on reset ? reset ? type ? description osc_in i 33.33-mhz, sinusoidal crystal input signal. can be driven by an oscillator. osc_out o 33.33-mhz, sinusoidal crystal output signal. left disconnected when being driven by an oscillator. ? for a legend of the type codes, see table 4 on page 30 . table 15. gpio interface name power on reset ? reset ? type ? description gpio[12:0] z z i/o general purpose input/output pins. may be configured as an input or an output. as an input, each signal may be configured a processor interrupt. default after reset is to be configured as inputs. should be pulled low using a 10-k ? resistor when not being utilized in the system. gpio[13] z z i/o general purpose input/output pins. may be configured as an input or an output. default after reset is to be configured as inputs. should be pulled low using a 10-k ? resistor when not being utilized in the system. gpio[14] z z i/o can be configured similar to gpio pin 13 or as a clock output. configuration as an output clock can be set at various speeds of up to 33.33 mhz with various duty cycles. configured as an input, upon reset. should be pulled low though a 10-k ? resistor when not being utilized in the system. gpio[15] z clkout /vo i/o can be configured similar to gpio pin 13 or as a clock output. configuration as an output clock can be set at various speeds of up to 33.33 mhz with various duty cycles. configured as an output, upon reset. can be used to clock the expansion interface, after reset. should be pulled low though a 10-k ? resistor when not being utilized in the system. ? for a legend of the type codes, see table 4 on page 30 . table 16. jtag interface name power on reset ? reset ? type ? description jtg_tms h vi/pe i test mode select for the ieee 1149.1 jtag interface. jtg_tdi h vi/pe i input data for the ieee 1149.1 jtag interface. jtg_tdo z vo o output data for the ieee 1149.1 jtag interface. jtg_trst_n h vi/pe i used to reset the ieee 1149.1 jtag interface. the jtg_trst_n signal must be asserted (driven low) during power-up, otherwise the tap controller may not be initialized properly, and the processor may be locked. when the jtag interface is not being used, the signal must be pulled low using a 10-k ? resistor. jtg_tck z vi i used as the clock for the ieee 1149.1 jtag interface. ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor functional signal descriptions datasheet 41 table 17. system interface name power on reset ? reset ? type ? description bypass_clk z vi i used for test purposes only. must be pulled high for normal operation. scantestmode_n h vi/pe i used for test purposes only. must be pulled high for normal operation. reset_in_n 0 vi i used as a reset input to the device after power up conditions have been met. power up conditions include the power supplies reaching a safe stable condition and the pll achieving a locked state and the pwron_reset_n coming to an active state prior to the reset_in_n coming to an active state. pwron_reset_n 0 vi i signal used at power up to reset all internal logic to a known state after the pll has achieved a locked state. the pwron_reset_n input is a 1.3-v tolerant only. highz_n h vi/pe i used for test purposes only. must be pulled high for normal operation. pll_lock z vo o signal used to inform external reset logic that the internal pll has achieved a locked state. rcomp i signal used to control pci drive strength characteristics. drive strength is varied on pci address, data and control signals. pin requires a 34- ? +/- 1% tolerance resistor to ground. refer to figure 12 on page 77 ? for a legend of the type codes, see table 4 on page 30 . table 18. power interface name type ? description vcc i 1.3-v power supply input pins used for the internal logic. vccp i 3.3-v power supply input pins used for the peripheral (i/o) logic. vss ground power supply input pins used for both the 3.3-v and the 1.3-v power supplies. vccoscp i 3.3-v power supply input pins used for the peripheral (i/o) logic of the analog oscillator circuitry. require special power filtering circuitry. refer to figure 10 on page 76 vssoscp i ground input pins used for the peripheral (i/o) logic of the analog oscillator circuitry. used in conjunction with the vccoscp pins. requires special power filtering circuitry. refer to figure 10 on page 76 vccosc i 1.3-v power supply input pins used for the internal logic of the analog oscillator circuitry. requires special power filtering circuitry. refer to figure 11 on page 76 vssosc i ground power supply input pins used for the internal logic of the analog oscillator circuitry. used in conjunction with the vccosc pins. requires special power filtering circuitry. refer to figure 11 on page 76 vccpll1 i 1.3-v power supply input pins used for the internal logic of the analog phase lock-loop circuitry. requires special power filtering circuitry. refer to figure 8 on page 75 vccpll2 i 1.3-v power supply input pins used for the internal logic of the analog phase lock-loop circuitry. requires special power filtering circuitry. refer to figure 9 on page 75 ? for a legend of the type codes, see table 4 on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 42 datasheet 4.0 package and pinout information the intel ? ixp42x product line of network processors and ixc1100 control plane processor have a 492-ball, plastic ball grid array (pbga) package for commercial-temperature applications and a pin-for-pin, compatible 492-ball, plastic ball grid array with a drop-in heat spreader (h) for extended-temperature applications. 4.1 package description figure 6. 492-pin lead pbga package 1. all measurements are in millimeters (mm). 2. the size of the land pad at the interposer side (1) is 0.81 mm. 3. the size of the solder resist at the interposer side (2) is 0.66 mm. b1268-0 3 0.60 0.10 seating plane 30o 3 1.17 0.05 2.38 0.21 0.61 0.06 0.15 c 0.20 -c- side view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d e f g h j k l m n p r aa y w u t 23 22 21 20 19 18 17 16 24 25 26 v ab ac ad ae af pin #1 corner 1.27 1.63 ref 1.27 a c ? 0.30 b s ?1.0 3 places 2 + + 1.63 ref 0.90 0.60 ? s s + + + 22.00 ref 22.00 ref 35.00 0.20 35.00 0.20 30.00 0.25 pin 1 id 30.00 0.25 45o chamfer 4 places 0.127 a -b- -a- top view (1) (2)
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 43 figure 7. package markings note: see table 19 for specific on ?level 1 name.? table 19. part numbers (sheet 1 of 2) device stepping speed (mhz) part # intel ? ixp425 network processor b-0 533 fwixp425bd intel ? ixp425 network processor b-0 400 fwixp425bc intel ? ixp425 network processor b-0 266 fwixp425bb intel ? ixp425 network processor b-0 533 extended temperature gwixp425bdt intel ? ixp425 network processor b-0 400 extended temperature gwixp425bct intel ? ixp425 network processor b-0 266 extended temperature gwixp425bbt intel ? ixp422 network processor b-0 266 fwixp422bb intel ? ixp421 network processor b-0 266 fwixp421bb bsmc (atpo#, date code and coo) pin #1 (not a mark) i fwixp42 xbx intel m c 2002 level 1 name yww korea bsmc marking zone: 0.380? max. *
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 44 datasheet intel ? ixp420 network processor b-0 533 fwixp420bd intel ? ixp420 network processor b-0 400 fwixp420bc intel ? ixp420 network processor b-0 266 fwixp420bb intel ? ixp420 network processor b-0 266 extended temperature gwixp420bbt intel ? ixc1100 control plane processor b-0 533 fwixc1100bd intel ? ixc1100 control plane processor b-0 400 fwixc1100bc intel ? ixc1100 control plane processor b-0 266 fwixc1100bb intel ? ixc1100 control plane processor b-0 533 extended temperature gwixc1100bdt intel ? ixc1100 control plane processor b-0 400 extended temperature gwixc1100bct intel ? ixc1100 control plane processor b-0 266 extended temperature gwixc1100bbt table 19. part numbers (sheet 2 of 2) device stepping speed (mhz) part #
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 45 4.2 signal-pin descriptions in this section, separate ball-map-assignment tables are given for each model of the ixp42x product line and ixc1100 control plane processors. these tables include: device table # starting page intel ? ixp425 network processor 20 45 intel ? ixp422 network processor 21 52 intel ? ixp421 network processor 22 59 intel ? ixp420 network processor and intel ? ixc1100 control plane processor 23 66 table 20. ball map assignment for the intel ? ixp425 network processor (sheet 1 of 7) ball signal ball signal ball signal ball signal a1 pci_ad[27] b1 pci_ad[28] c1 pci_ad[26] d1 pci_ad[25] a2 pci_gnt_n[1] b2 vccp c2 pci_ad[30] d2 vss a3 pci_gnt_n[3] b3 pci_gnt_n[2] c3 vss d3 pci_ad[31] a4 sdm_data[19] b4 vccp c4 pci_inta_n d4 vcc a5 sdm_data[27] b5 sdm_data[28] c5 vss d5 pci_serr_n a6 sdm_data[26] b6 vccp c6 sdm_data[18] d6 vcc a7 sdm_data[25] b7 sdm_data[21] c7 vss d7 sdm_data[29] a8 sdm_data[23] b8 vss c8 vccp d8 sdm_data[20] a9 sdm_data[14] b9 sdm_data[0] c9 sdm_data[24] d9 vcc a10 sdm_data[13] b10 vccp c10 vss d10 sdm_data[15] a11 sdm_data[11] b11 sdm_data[12] c11 sdm_data[2] d11 sdm_data[1] a12 sdm_data[10] b12 vss c12 sdm_data[4] d12 vcc a13 sdm_data[6] b13 sdm_data[9] c13 vss d13 sdm_data[5] a14 sdm_data[8] b14 vccp c14 sdm_data[7] d14 vcc a15 sdm_dqm[1] b15 sdm_dqm[2] c15 sdm_dqm[3] d15 sdm_we_n a16 sdm_cs_n[0] b16 vss c16 vccp d16 sdm_cs_n[1] a17 sdm_clkout b17 sdm_cke c17 sdm_cas_n d17 sdm_ba[1] a18 sdm_ras_n b18 vccp c18 sdm_addr[11] d18 vcc a19 sdm_addr[12] b19 sdm_addr[10] c19 vss d19 sdm_addr[0] a20 sdm_addr[9] b20 vss c20 sdm_addr[6] d20 vss a21 sdm_addr[8] b21 sdm_addr[1] c21 sdm_addr[2] d21 vcc a22 sdm_addr[5] b22 vccp c22 vss d22 ex_ale a23 ex_rd_n b23 ex_iowait_n c23 ex_addr[0] d23 vcc a24 ex_addr[1] b24 vss c24 ex_addr[4] d24 ex_addr[6] a25 ex_addr[3] b25 vccp c25 ex_addr[7] d25 rcomp a26 ex_addr[5] b26 ex_addr[9] c26 ex_addr[13] d26 ex_addr[17] note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 46 datasheet e1 pci_ad[23] f1 pci_ad[20] g1 pci_ad[21] h1 pci_ad[16] e2 vccp f2 pci_idsel g2 vccp h2 pci_ad[18] e3 pci_req_n[2] f3 vcc g3 pci_ad[24] h3 vcc e4 vss f4 pci_req_n[0] g4 vss h4 pci_cbe_n[3] e5 pci_gnt_n[0] f5 vccp g5 pci_req_n[1] h5 vcc e6 sdm_data[16] f6 vcc g6 vss h6 pci_req_n[3] e7 vccp f7 sdm_data[31] e8 sdm_data[30] f8 vss e9 vss f9 sdm_data[17] e10 sdm_data[22] f10 vcc e11 vccp e12 sdm_data[3] e13 vss e14 sdm_dqm[0] e15 vccp e16 sdm_ba[0] e17 vss f17 vcc e18 sdm_addr[7] f18 sdm_addr[4] e19 vccp f19 vss e20 sdm_addr[3] f20 usb_dpos e21 usb_dneg f21 vcc g21 ex_addr[2] h21 vss e22 vccp f22 ex_wr_n g22 vss h22 ex_addr[11] e23 vss f23 vcc g23 ex_addr[12] h23 ex_addr[18] e24 ex_addr[10] f24 ex_addr[14] g24 vss h24 vccp e25 ex_addr[15] f25 vccp g25 ex_addr[20] h25 vss e26 ex_addr[19] f26 ex_addr[21] g26 ex_addr[22] h26 ex_cs_n[1] table 20. ball map assignment for the intel ? ixp425 network processor (sheet 2 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 47 j1 pci_clkin k1 pci_cbe_n[2] l1 pci_devsel_n m1 pci_cbe_n[1] j2 vccp k2 vss l2 vccp m2 pci_par j3 vss k3 pci_ad[17] l3 pci_stop_n m3 vss j4 pci_ad[22] k4 vccp l4 vcc m4 pci_irdy_n j5 vss k5 pci_ad[19] l5 pci_frame_n m5 vccp j6 pci_ad[29] k6 vcc l11 vss m11 vss l12 vss m12 vss l13 vss m13 vss l14 vss m14 vss l15 vss m15 vss l16 vss m16 vss j21 ex_addr[8] k21 vcc j22 ex_addr[16] k22 vss l22 vccp m22 ex_cs_n[5] j23 vcc k23 ex_cs_n[0] l23 vcc m23 ex_clk j24 ex_addr[23] k24 ex_cs_n[3] l24 ex_cs_n[6] m24 ex_data[2] j25 ex_cs_n[2] k25 vccp l25 ex_data[0] m25 vss j26 ex_cs_n[4] k26 ex_cs_n[7] l26 ex_data[1] m26 ex_data[3] table 20. ball map assignment for the intel ? ixp425 network processor (sheet 3 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 48 datasheet n1 pci_ad[11] p1 pci_cbe_n[0] r1 pci_ad[10] t1 pci_ad[6] n2 vccp p2 pci_ad[14] r2 vss t2 pci_trdy_n n3 vcc p3 pci_ad[13] r3 pci_ad[9] t3 vss n4 pci_perr_n p4 vss r4 vcc t4 pci_ad[2] n5 pci_ad[15] p5 pci_ad[12] r5 pci_ad[4] t5 vccp n11 vss p11 vss r11 vss t11 vss n12 vss p12 vss r12 vss t12 vss n13 vss p13 vss r13 vss t13 vss n14 vss p14 vss r14 vss t14 vss n15 vss p15 vss r15 vss t15 vss n16 vss p16 vss r16 vss t16 vss n22 vcc p22 ex_data[6] r22 vccp t22 ex_rdy_n[0] n23 vss p23 ex_data[7] r23 vcc t23 vss n24 vcc p24 ex_data[8] r24 ex_data[12] t24 ex_data[14] n25 ex_data[4] p25 vccp r25 ex_data[11] t25 vss n26 ex_data[5] p26 ex_data[9] r26 ex_data[10] t26 ex_data[13] table 20. ball map assignment for the intel ? ixp425 network processor (sheet 4 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 49 u1 pci_ad[8] v1 pci_ad[5] w1 pci_ad[1] y1 hss_txclk0 u2 vccp v2 vss w2 vccp y2 hss_rxclk0 u3 pci_ad[0] v3 pci_ad[3] w3 hss_rxframe0 y3 hss_txframe1 u4 pci_ad[7] v4 vcc w4 vss y4 vcc u5 hss_txdata0 v5 hss_txframe0 w5 hss_txclk1 y5 vccp u6 vcc v6 vss w6 hss_rxframe1 y6 eth_txen0 u21 vcc v21 gpio[6] w21 gpio[1] y21 rxdata1 u22 gpio[14] v22 gpio[9] w22 vccp y22 gpio[0] u23 ex_rdy_n[1] v23 vcc w23 gpio[8] y23 vcc u24 ex_rdy_n[2] v24 gpio[13] w24 vss y24 gpio[5] u25 gpio[15] v25 vccp w25 gpio[11] y25 vccp u26 ex_data[15] v26 ex_rdy_n[3] w26 gpio[12] y26 gpio[10] table 20. ball map assignment for the intel ? ixp425 network processor (sheet 5 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 50 datasheet aa1 hss_rxdata0 ab1 hss_txdata1 ac1 vss ad1 eth_txclk0 aa2 vccp ab2 hss_rxdata1 ac2 eth_txdata0[0] ad2 eth_rxdv0 aa3 vss ab3 eth_txdata0[3] ac3 vccp ad3 vss aa4 hss_rxclk1 ab4 eth_txdata0[1] ac4 vcc ad4 eth_crs0 aa5 eth_txdata0[2] ab5 vss ac5 eth_rxdata0[0] ad5 eth_mdc aa6 vcc ab6 eth_rxclk0 ac6 vss ad6 eth_txdata1[0] aa7 eth_rxdata0[1] ab7 vccp ac7 vcc ad7 eth_rxdata1[3] aa8 vss ab8 eth_txdata1[2] ac8 eth_rxdata1[2] ad8 eth_rxclk1 aa9 eth_txdata1[1] ab9 eth_rxdata1[1] ac9 vcc ad9 vss aa10 vcc ab10 vccp ac10 vcc ad10 vssoscp ab11 vccp ac11 vccoscp ad11 vccp ab12 vss ac12 vcc ad12 pll_lock ab13 utp_op_data[7] ac13 reset_in_n ad13 pwron_reset_n ab14 vccp ac14 vcc ad14 utp_op_data[4] ab15 utp_op_soc ac15 utp_op_data[1] ad15 utp_op_data[2] ab16 vss ac16 utp_op_fci ad16 vss aa17 vcc ab17 utp_ip_data[6] ac17 utp_op_addr[1] ad17 utp_op_addr[3] aa18 utp_ip_fci ab18 vccp ac18 vcc ad18 utp_ip_data[7] aa19 utp_ip_addr[0] ab19 utp_ip_clk ac19 utp_ip_data[2] ad19 vccp aa20 vss ab20 utp_ip_addr[1] ac20 utp_ip_soc ad20 utp_ip_data[1] aa21 vcc ab21 scantestmode_n ac21 vcc ad21 utp_ip_addr[4] aa22 txdata1 ab22 vccp ac22 jtg_trst_n ad22 vss aa23 vss ab23 cts0_n ac23 vcc ad23 jtg_tdo aa24 gpio[3] ab24 cts1_n ac24 rxdata0 ad24 vss aa25 vss ab25 vccp ac25 rts1_n ad25 txdata0 aa26 gpio[7] ab26 gpio[4] ac26 gpio[2] ad26 rts0_n table 20. ball map assignment for the intel ? ixp425 network processor (sheet 6 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 51 ae1 eth_rxdata0[3] af1 eth_rxdata0[2] ae2 vccp af2 eth_mdio ae3 eth_col0 af3 (reserved) ae4 eth_txen1 af4 eth_txdata1[3] ae5 vccp af5 eth_txclk1 ae6 eth_rxdv1 af6 eth_rxdata1[0] ae7 vss af7 eth_crs1 ae8 eth_col1 af8 vssosc ae9 vccp af9 osc_in ae10 vccpll1 af10 vssoscp ae11 vss af11 osc_out ae12 vccpll2 af12 vccosc ae13 vccp af13 bypass_clk ae14 utp_op_data[5] af14 utp_op_data[6] ae15 vss af15 utp_op_data[3] ae16 utp_op_fco af16 utp_op_data[0] ae17 vccp af17 utp_op_clk ae18 utp_op_addr[2] af18 utp_op_addr[4] ae19 vss af19 utp_op_addr[0] ae20 utp_ip_data[4] af20 utp_ip_data[5] ae21 vccp af21 utp_ip_data[3] ae22 utp_ip_fco af22 utp_ip_data[0] ae23 vccp af23 utp_ip_addr[3] ae24 jtg_tdi af24 utp_ip_addr[2] ae25 vccp af25 jtg_tms ae26 highz_n af26 jtg_tck table 20. ball map assignment for the intel ? ixp425 network processor (sheet 7 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 52 datasheet table 21. ball map assignment for the intel ? ixp422 network processor (sheet 1 of 7) ball signal ball signal ball signal ball signal a1 pci_ad[27] b1 pci_ad[28] c1 pci_ad[26] d1 pci_ad[25] a2 pci_gnt_n[1] b2 vccp c2 pci_ad[30] d2 vss a3 pci_gnt_n[3] b3 pci_gnt_n[2] c3 vss d3 pci_ad[31] a4 sdm_data[19] b4 vccp c4 pci_inta_n d4 vcc a5 sdm_data[27] b5 sdm_data[28] c5 vss d5 pci_serr_n a6 sdm_data[26] b6 vccp c6 sdm_data[18] d6 vcc a7 sdm_data[25] b7 sdm_data[21] c7 vss d7 sdm_data[29] a8 sdm_data[23] b8 vss c8 vccp d8 sdm_data[20] a9 sdm_data[14] b9 sdm_data[0] c9 sdm_data[24] d9 vcc a10 sdm_data[13] b10 vccp c10 vss d10 sdm_data[15] a11 sdm_data[11] b11 sdm_data[12] c11 sdm_data[2] d11 sdm_data[1] a12 sdm_data[10] b12 vss c12 sdm_data[4] d12 vcc a13 sdm_data[6] b13 sdm_data[9] c13 vss d13 sdm_data[5] a14 sdm_data[8] b14 vccp c14 sdm_data[7] d14 vcc a15 sdm_dqm[1] b15 sdm_dqm[2] c15 sdm_dqm[3] d15 sdm_we_n a16 sdm_cs_n[0] b16 vss c16 vccp d16 sdm_cs_n[1] a17 sdm_clkout b17 sdm_cke c17 sdm_cas_n d17 sdm_ba[1] a18 sdm_ras_n b18 vccp c18 sdm_addr[11] d18 vcc a19 sdm_addr[12] b19 sdm_addr[10] c19 vss d19 sdm_addr[0] a20 sdm_addr[9] b20 vss c20 sdm_addr[6] d20 vss a21 sdm_addr[8] b21 sdm_addr[1] c21 sdm_addr[2] d21 vcc a22 sdm_addr[5] b22 vccp c22 vss d22 ex_ale a23 ex_rd_n b23 ex_iowait_n c23 ex_addr[0] d23 vcc a24 ex_addr[1] b24 vss c24 ex_addr[4] d24 ex_addr[6] a25 ex_addr[3] b25 vccp c25 ex_addr[7] d25 rcomp a26 ex_addr[5] b26 ex_addr[9] c26 ex_addr[13] d26 ex_addr[17] note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 53 e1 pci_ad[23] f1 pci_ad[20] g1 pci_ad[21] h1 pci_ad[16] e2 vccp f2 pci_idsel g2 vccp h2 pci_ad[18] e3 pci_req_n[2] f3 vcc g3 pci_ad[24] h3 vcc e4 vss f4 pci_req_n[0] g4 vss h4 pci_cbe_n[3] e5 pci_gnt_n[0] f5 vccp g5 pci_req_n[1] h5 vcc e6 sdm_data[16] f6 vcc g6 vss h6 pci_req_n[3] e7 vccp f7 sdm_data[31] e8 sdm_data[30] f8 vss e9 vss f9 sdm_data[17] e10 sdm_data[22] f10 vcc e11 vccp e12 sdm_data[3] e13 vss e14 sdm_dqm[0] e15 vccp e16 sdm_ba[0] e17 vss f17 vcc e18 sdm_addr[7] f18 sdm_addr[4] e19 vccp f19 vss e20 sdm_addr[3] f20 usb_dpos e21 usb_dneg f21 vcc g21 ex_addr[2] h21 vss e22 vccp f22 ex_wr_n g22 vss h22 ex_addr[11] e23 vss f23 vcc g23 ex_addr[12] h23 ex_addr[18] e24 ex_addr[10] f24 ex_addr[14] g24 vss h24 vccp e25 ex_addr[15] f25 vccp g25 ex_addr[20] h25 vss e26 ex_addr[19] f26 ex_addr[21] g26 ex_addr[22] h26 ex_cs_n[1] table 21. ball map assignment for the intel ? ixp422 network processor (sheet 2 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 54 datasheet j1 pci_clkin k1 pci_cbe_n[2] l1 pci_devsel_n m1 pci_cbe_n[1] j2 vccp k2 vss l2 vccp m2 pci_par j3 vss k3 pci_ad[17] l3 pci_stop_n m3 vss j4 pci_ad[22] k4 vccp l4 vcc m4 pci_irdy_n j5 vss k5 pci_ad[19] l5 pci_frame_n m5 vccp j6 pci_ad[29] k6 vcc l11 vss m11 vss l12 vss m12 vss l13 vss m13 vss l14 vss m14 vss l15 vss m15 vss l16 vss m16 vss j21 ex_addr[8] k21 vcc j22 ex_addr[16] k22 vss l22 vccp m22 ex_cs_n[5] j23 vcc k23 ex_cs_n[0] l23 vcc m23 ex_clk j24 ex_addr[23] k24 ex_cs_n[3] l24 ex_cs_n[6] m24 ex_data[2] j25 ex_cs_n[2] k25 vccp l25 ex_data[0] m25 vss j26 ex_cs_n[4] k26 ex_cs_n[7] l26 ex_data[1] m26 ex_data[3] table 21. ball map assignment for the intel ? ixp422 network processor (sheet 3 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 55 n1 pci_ad[11] p1 pci_cbe_n[0] r1 pci_ad[10] t1 pci_ad[6] n2 vccp p2 pci_ad[14] r2 vss t2 pci_trdy_n n3 vcc p3 pci_ad[13] r3 pci_ad[9] t3 vss n4 pci_perr_n p4 vss r4 vcc t4 pci_ad[2] n5 pci_ad[15] p5 pci_ad[12] r5 pci_ad[4] t5 vccp n11 vss p11 vss r11 vss t11 vss n12 vss p12 vss r12 vss t12 vss n13 vss p13 vss r13 vss t13 vss n14 vss p14 vss r14 vss t14 vss n15 vss p15 vss r15 vss t15 vss n16 vss p16 vss r16 vss t16 vss n22 vcc p22 ex_data[6] r22 vccp t22 ex_rdy_n[0] n23 vss p23 ex_data[7] r23 vcc t23 vss n24 vcc p24 ex_data[8] r24 ex_data[12] t24 ex_data[14] n25 ex_data[4] p25 vccp r25 ex_data[11] t25 vss n26 ex_data[5] p26 ex_data[9] r26 ex_data[10] t26 ex_data[13] table 21. ball map assignment for the intel ? ixp422 network processor (sheet 4 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 56 datasheet u1 pci_ad[8] v1 pci_ad[5] w1 pci_ad[1] y1 n/c u2 vccp v2 vss w2 vccp y2 n/c u3 pci_ad[0] v3 pci_ad[3] w3 n/c y3 n/c u4 pci_ad[7] v4 vcc w4 vss y4 vcc u5 n/c v5 n/c w5 n/c y5 vccp u6 vcc v6 vss w6 n/c y6 eth_txen0 u21 vcc v21 gpio[6] w21 gpio[1] y21 rxdata1 u22 gpio[14] v22 gpio[9] w22 vccp y22 gpio[0] u23 ex_rdy_n[1] v23 vcc w23 gpio[8] y23 vcc u24 ex_rdy_n[2] v24 gpio[13] w24 vss y24 gpio[5] u25 gpio[15] v25 vccp w25 gpio[11] y25 vccp u26 ex_data[15] v26 ex_rdy_n[3] w26 gpio[12] y26 gpio[10] table 21. ball map assignment for the intel ? ixp422 network processor (sheet 5 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 57 aa1 n/c ab1 n/c ac1 vss ad1 eth_txclk0 aa2 vccp ab2 n/c ac2 eth_txdata0[0] ad2 eth_rxdv0 aa3 vss ab3 eth_txdata0[3] ac3 vccp ad3 vss aa4 n/c ab4 eth_txdata0[1] ac4 vcc ad4 eth_crs0 aa5 eth_txdata0[2] ab5 vss ac5 eth_rxdata0[0] ad5 eth_mdc aa6 vcc ab6 eth_rxclk0 ac6 vss ad6 eth_txdata1[0] aa7 eth_rxdata0[1] ab7 vccp ac7 vcc ad7 eth_rxdata1[3] aa8 vss ab8 eth_txdata1[2] ac8 eth_rxdata1[2] ad8 eth_rxclk1 aa9 eth_txdata1[1] ab9 eth_rxdata1[1] ac9 vcc ad9 vss aa10 vcc ab10 vccp ac10 vcc ad10 vssoscp ab11 vccp ac11 vccoscp ad11 vccp ab12 vss ac12 vcc ad12 pll_lock ab13 n/c ac13 reset_in_n ad13 pwron_reset_n ab14 vccp ac14 vcc ad14 n/c ab15 n/c ac15 n/c ad15 n/c ab16 vss ac16 n/c ad16 vss aa17 vcc ab17 n/c ac17 n/c ad17 n/c aa18 n/c ab18 vccp ac18 vcc ad18 n/c aa19 n/c ab19 n/c ac19 n/c ad19 vccp aa20 vss ab20 n/c ac20 n/c ad20 n/c aa21 vcc ab21 scantestmode_n ac21 vcc ad21 n/c aa22 txdata1 ab22 vccp ac22 jtg_trst_n ad22 vss aa23 vss ab23 cts0_n ac23 vcc ad23 jtg_tdo aa24 gpio[3] ab24 cts1_n ac24 rxdata0 ad24 vss aa25 vss ab25 vccp ac25 rts1_n ad25 txdata0 aa26 gpio[7] ab26 gpio[4] ac26 gpio[2] ad26 rts0_n table 21. ball map assignment for the intel ? ixp422 network processor (sheet 6 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 58 datasheet ae1 eth_rxdata0[3] af1 eth_rxdata0[2] ae2 vccp af2 eth_mdio ae3 eth_col0 af3 (reserved) ae4 eth_txen1 af4 eth_txdata1[3] ae5 vccp af5 eth_txclk1 ae6 eth_rxdv1 af6 eth_rxdata1[0] ae7 vss af7 eth_crs1 ae8 eth_col1 af8 vssosc ae9 vccp af9 osc_in ae10 vccpll1 af10 vssoscp ae11 vss af11 osc_out ae12 vccpll2 af12 vccosc ae13 vccp af13 bypass_clk ae14 n/c af14 n/c ae15 vss af15 n/c ae16 n/c af16 n/c ae17 vccp af17 n/c ae18 n/c af18 n/c ae19 vss af19 n/c ae20 n/c af20 n/c ae21 vccp af21 n/c ae22 n/c af22 n/c ae23 vccp af23 n/c ae24 jtg_tdi af24 n/c ae25 vccp af25 jtg_tms ae26 highz_n af26 jtg_tck table 21. ball map assignment for the intel ? ixp422 network processor (sheet 7 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 59 table 22. ball map assignment for the intel ? ixp421 network processor (sheet 1 of 7) ball signal ball signal ball signal ball signal a1 pci_ad[27] b1 pci_ad[28] c1 pci_ad[26] d1 pci_ad[25] a2 pci_gnt_n[1] b2 vccp c2 pci_ad[30] d2 vss a3 pci_gnt_n[3] b3 pci_gnt_n[2] c3 vss d3 pci_ad[31] a4 sdm_data[19] b4 vccp c4 pci_inta_n d4 vcc a5 sdm_data[27] b5 sdm_data[28] c5 vss d5 pci_serr_n a6 sdm_data[26] b6 vccp c6 sdm_data[18] d6 vcc a7 sdm_data[25] b7 sdm_data[21] c7 vss d7 sdm_data[29] a8 sdm_data[23] b8 vss c8 vccp d8 sdm_data[20] a9 sdm_data[14] b9 sdm_data[0] c9 sdm_data[24] d9 vcc a10 sdm_data[13] b10 vccp c10 vss d10 sdm_data[15] a11 sdm_data[11] b11 sdm_data[12] c11 sdm_data[2] d11 sdm_data[1] a12 sdm_data[10] b12 vss c12 sdm_data[4] d12 vcc a13 sdm_data[6] b13 sdm_data[9] c13 vss d13 sdm_data[5] a14 sdm_data[8] b14 vccp c14 sdm_data[7] d14 vcc a15 sdm_dqm[1] b15 sdm_dqm[2] c15 sdm_dqm[3] d15 sdm_we_n a16 sdm_cs_n[0] b16 vss c16 vccp d16 sdm_cs_n[1] a17 sdm_clkout b17 sdm_cke c17 sdm_cas_n d17 sdm_ba[1] a18 sdm_ras_n b18 vccp c18 sdm_addr[11] d18 vcc a19 sdm_addr[12] b19 sdm_addr[10] c19 vss d19 sdm_addr[0] a20 sdm_addr[9] b20 vss c20 sdm_addr[6] d20 vss a21 sdm_addr[8] b21 sdm_addr[1] c21 sdm_addr[2] d21 vcc a22 sdm_addr[5] b22 vccp c22 vss d22 ex_ale a23 ex_rd_n b23 ex_iowait_n c23 ex_addr[0] d23 vcc a24 ex_addr[1] b24 vss c24 ex_addr[4] d24 ex_addr[6] a25 ex_addr[3] b25 vccp c25 ex_addr[7] d25 rcomp a26 ex_addr[5] b26 ex_addr[9] c26 ex_addr[13] d26 ex_addr[17] note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 60 datasheet e1 pci_ad[23] f1 pci_ad[20] g1 pci_ad[21] h1 pci_ad[16] e2 vccp f2 pci_idsel g2 vccp h2 pci_ad[18] e3 pci_req_n[2] f3 vcc g3 pci_ad[24] h3 vcc e4 vss f4 pci_req_n[0] g4 vss h4 pci_cbe_n[3] e5 pci_gnt_n[0] f5 vccp g5 pci_req_n[1] h5 vcc e6 sdm_data[16] f6 vcc g6 vss h6 pci_req_n[3] e7 vccp f7 sdm_data[31] e8 sdm_data[30] f8 vss e9 vss f9 sdm_data[17] e10 sdm_data[22] f10 vcc e11 vccp e12 sdm_data[3] e13 vss e14 sdm_dqm[0] e15 vccp e16 sdm_ba[0] e17 vss f17 vcc e18 sdm_addr[7] f18 sdm_addr[4] e19 vccp f19 vss e20 sdm_addr[3] f20 usb_dpos e21 usb_dneg f21 vcc g21 ex_addr[2] h21 vss e22 vccp f22 ex_wr_n g22 vss h22 ex_addr[11] e23 vss f23 vcc g23 ex_addr[12] h23 ex_addr[18] e24 ex_addr[10] f24 ex_addr[14] g24 vss h24 vccp e25 ex_addr[15] f25 vccp g25 ex_addr[20] h25 vss e26 ex_addr[19] f26 ex_addr[21] g26 ex_addr[22] h26 ex_cs_n[1] table 22. ball map assignment for the intel ? ixp421 network processor (sheet 2 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 61 j1 pci_clkin k1 pci_cbe_n[2] l1 pci_devsel_n m1 pci_cbe_n[1] j2 vccp k2 vss l2 vccp m2 pci_par j3 vss k3 pci_ad[17] l3 pci_stop_n m3 vss j4 pci_ad[22] k4 vccp l4 vcc m4 pci_irdy_n j5 vss k5 pci_ad[19] l5 pci_frame_n m5 vccp j6 pci_ad[29] k6 vcc l11 vss m11 vss l12 vss m12 vss l13 vss m13 vss l14 vss m14 vss l15 vss m15 vss l16 vss m16 vss j21 ex_addr[8] k21 vcc j22 ex_addr[16] k22 vss l22 vccp m22 ex_cs_n[5] j23 vcc k23 ex_cs_n[0] l23 vcc m23 ex_clk j24 ex_addr[23] k24 ex_cs_n[3] l24 ex_cs_n[6] m24 ex_data[2] j25 ex_cs_n[2] k25 vccp l25 ex_data[0] m25 vss j26 ex_cs_n[4] k26 ex_cs_n[7] l26 ex_data[1] m26 ex_data[3] table 22. ball map assignment for the intel ? ixp421 network processor (sheet 3 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 62 datasheet n1 pci_ad[11] p1 pci_cbe_n[0] r1 pci_ad[10] t1 pci_ad[6] n2 vccp p2 pci_ad[14] r2 vss t2 pci_trdy_n n3 vcc p3 pci_ad[13] r3 pci_ad[9] t3 vss n4 pci_perr_n p4 vss r4 vcc t4 pci_ad[2] n5 pci_ad[15] p5 pci_ad[12] r5 pci_ad[4] t5 vccp n11 vss p11 vss r11 vss t11 vss n12 vss p12 vss r12 vss t12 vss n13 vss p13 vss r13 vss t13 vss n14 vss p14 vss r14 vss t14 vss n15 vss p15 vss r15 vss t15 vss n16 vss p16 vss r16 vss t16 vss n22 vcc p22 ex_data[6] r22 vccp t22 ex_rdy_n[0] n23 vss p23 ex_data[7] r23 vcc t23 vss n24 vcc p24 ex_data[8] r24 ex_data[12] t24 ex_data[14] n25 ex_data[4] p25 vccp r25 ex_data[11] t25 vss n26 ex_data[5] p26 ex_data[9] r26 ex_data[10] t26 ex_data[13] table 22. ball map assignment for the intel ? ixp421 network processor (sheet 4 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 63 u1 pci_ad[8] v1 pci_ad[5] w1 pci_ad[1] y1 hss_txclk0 u2 vccp v2 vss w2 vccp y2 hss_rxclk0 u3 pci_ad[0] v3 pci_ad[3] w3 hss_rxframe0 y3 hss_txframe1 u4 pci_ad[7] v4 vcc w4 vss y4 vcc u5 hss_txdata0 v5 hss_txframe0 w5 hss_txclk1 y5 vccp u6 vcc v6 vss w6 hss_rxframe1 y6 eth_txen0 u21 vcc v21 gpio[6] w21 gpio[1] y21 rxdata1 u22 gpio[14] v22 gpio[9] w22 vccp y22 gpio[0] u23 ex_rdy_n[1] v23 vcc w23 gpio[8] y23 vcc u24 ex_rdy_n[2] v24 gpio[13] w24 vss y24 gpio[5] u25 gpio[15] v25 vccp w25 gpio[11] y25 vccp u26 ex_data[15] v26 ex_rdy_n[3] w26 gpio[12] y26 gpio[10] table 22. ball map assignment for the intel ? ixp421 network processor (sheet 5 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 64 datasheet aa1 hss_rxdata0 ab1 hss_txdata1 ac1 vss ad1 eth_txclk0 aa2 vccp ab2 hss_rxdata1 ac2 eth_txdata0[0] ad2 eth_rxdv0 aa3 vss ab3 eth_txdata0[3] ac3 vccp ad3 vss aa4 hss_rxclk1 ab4 eth_txdata0[1] ac4 vcc ad4 eth_crs0 aa5 eth_txdata0[2] ab5 vss ac5 eth_rxdata0[0] ad5 eth_mdc aa6 vcc ab6 eth_rxclk0 ac6 vss ad6 n/c aa7 eth_rxdata0[1] ab7 vccp ac7 vcc ad7 n/c aa8 vss ab8 n/c ac8 n/c ad8 n/c aa9 n/c ab9 n/c ac9 vcc ad9 vss aa10 vcc ab10 vccp ac10 vcc ad10 vssoscp ab11 vccp ac11 vccoscp ad11 vccp ab12 vss ac12 vcc ad12 pll_lock ab13 utp_op_data[7] ac13 reset_in_n ad13 pwron_reset_n ab14 vccp ac14 vcc ad14 utp_op_data[4] ab15 utp_op_soc ac15 utp_op_data[1] ad15 utp_op_data[2] ab16 vss ac16 utp_op_fci ad16 vss aa17 vcc ab17 utp_ip_data[6] ac17 utp_op_addr[1] ad17 utp_op_addr[3] aa18 utp_ip_fci ab18 vccp ac18 vcc ad18 utp_ip_data[7] aa19 utp_ip_addr[0] ab19 utp_ip_clk ac19 utp_ip_data[2] ad19 vccp aa20 vss ab20 utp_ip_addr[1] ac20 utp_ip_soc ad20 utp_ip_data[1] aa21 vcc ab21 scantestmode_n ac21 vcc ad21 utp_ip_addr[4] aa22 txdata1 ab22 vccp ac22 jtg_trst_n ad22 vss aa23 vss ab23 cts0_n ac23 vcc ad23 jtg_tdo aa24 gpio[3] ab24 cts1_n ac24 rxdata0 ad24 vss aa25 vss ab25 vccp ac25 rts1_n ad25 txdata0 aa26 gpio[7] ab26 gpio[4] ac26 gpio[2] ad26 rts0_n table 22. ball map assignment for the intel ? ixp421 network processor (sheet 6 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 65 ae1 eth_rxdata0[3] af1 eth_rxdata0[2] ae2 vccp af2 eth_mdio ae3 eth_col0 af3 (reserved) ae4 n/c af4 n/c ae5 vccp af5 n/c ae6 n/c af6 n/c ae7 vss af7 n/c ae8 n/c af8 vssosc ae9 vccp af9 osc_in ae10 vccpll1 af10 vssoscp ae11 vss af11 osc_out ae12 vccpll2 af12 vccosc ae13 vccp af13 bypass_clk ae14 utp_op_data[5] af14 utp_op_data[6] ae15 vss af15 utp_op_data[3] ae16 utp_op_fco af16 utp_op_data[0] ae17 vccp af17 utp_op_clk ae18 utp_op_addr[2] af18 utp_op_addr[4] ae19 vss af19 utp_op_addr[0] ae20 utp_ip_data[4] af20 utp_ip_data[5] ae21 vccp af21 utp_ip_data[3] ae22 utp_ip_fco af22 utp_ip_data[0] ae23 vccp af23 utp_ip_addr[3] ae24 jtg_tdi af24 utp_ip_addr[2] ae25 vccp af25 jtg_tms ae26 highz_n af26 jtg_tck table 22. ball map assignment for the intel ? ixp421 network processor (sheet 7 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 66 datasheet table 23. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 1 of 7) ball signal ball signal ball signal ball signal a1 pci_ad[27] b1 pci_ad[28] c1 pci_ad[26] d1 pci_ad[25] a2 pci_gnt_n[1] b2 vccp c2 pci_ad[30] d2 vss a3 pci_gnt_n[3] b3 pci_gnt_n[2] c3 vss d3 pci_ad[31] a4 sdm_data[19] b4 vccp c4 pci_inta_n d4 vcc a5 sdm_data[27] b5 sdm_data[28] c5 vss d5 pci_serr_n a6 sdm_data[26] b6 vccp c6 sdm_data[18] d6 vcc a7 sdm_data[25] b7 sdm_data[21] c7 vss d7 sdm_data[29] a8 sdm_data[23] b8 vss c8 vccp d8 sdm_data[20] a9 sdm_data[14] b9 sdm_data[0] c9 sdm_data[24] d9 vcc a10 sdm_data[13] b10 vccp c10 vss d10 sdm_data[15] a11 sdm_data[11] b11 sdm_data[12] c11 sdm_data[2] d11 sdm_data[1] a12 sdm_data[10] b12 vss c12 sdm_data[4] d12 vcc a13 sdm_data[6] b13 sdm_data[9] c13 vss d13 sdm_data[5] a14 sdm_data[8] b14 vccp c14 sdm_data[7] d14 vcc a15 sdm_dqm[1] b15 sdm_dqm[2] c15 sdm_dqm[3] d15 sdm_we_n a16 sdm_cs_n[0] b16 vss c16 vccp d16 sdm_cs_n[1] a17 sdm_clkout b17 sdm_cke c17 sdm_cas_n d17 sdm_ba[1] a18 sdm_ras_n b18 vccp c18 sdm_addr[11] d18 vcc a19 sdm_addr[12] b19 sdm_addr[10] c19 vss d19 sdm_addr[0] a20 sdm_addr[9] b20 vss c20 sdm_addr[6] d20 vss a21 sdm_addr[8] b21 sdm_addr[1] c21 sdm_addr[2] d21 vcc a22 sdm_addr[5] b22 vccp c22 vss d22 ex_ale a23 ex_rd_n b23 ex_iowait_n c23 ex_addr[0] d23 vcc a24 ex_addr[1] b24 vss c24 ex_addr[4] d24 ex_addr[6] a25 ex_addr[3] b25 vccp c25 ex_addr[7] d25 rcomp a26 ex_addr[5] b26 ex_addr[9] c26 ex_addr[13] d26 ex_addr[17] note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 67 e1 pci_ad[23] f1 pci_ad[20] g1 pci_ad[21] h1 pci_ad[16] e2 vccp f2 pci_idsel g2 vccp h2 pci_ad[18] e3 pci_req_n[2] f3 vcc g3 pci_ad[24] h3 vcc e4 vss f4 pci_req_n[0] g4 vss h4 pci_cbe_n[3] e5 pci_gnt_n[0] f5 vccp g5 pci_req_n[1] h5 vcc e6 sdm_data[16] f6 vcc g6 vss h6 pci_req_n[3] e7 vccp f7 sdm_data[31] e8 sdm_data[30] f8 vss e9 vss f9 sdm_data[17] e10 sdm_data[22] f10 vcc e11 vccp e12 sdm_data[3] e13 vss e14 sdm_dqm[0] e15 vccp e16 sdm_ba[0] e17 vss f17 vcc e18 sdm_addr[7] f18 sdm_addr[4] e19 vccp f19 vss e20 sdm_addr[3] f20 usb_dpos e21 usb_dneg f21 vcc g21 ex_addr[2] h21 vss e22 vccp f22 ex_wr_n g22 vss h22 ex_addr[11] e23 vss f23 vcc g23 ex_addr[12] h23 ex_addr[18] e24 ex_addr[10] f24 ex_addr[14] g24 vss h24 vccp e25 ex_addr[15] f25 vccp g25 ex_addr[20] h25 vss e26 ex_addr[19] f26 ex_addr[21] g26 ex_addr[22] h26 ex_cs_n[1] table 23. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 2 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 68 datasheet j1 pci_clkin k1 pci_cbe_n[2] l1 pci_devsel_n m1 pci_cbe_n[1] j2 vccp k2 vss l2 vccp m2 pci_par j3 vss k3 pci_ad[17] l3 pci_stop_n m3 vss j4 pci_ad[22] k4 vccp l4 vcc m4 pci_irdy_n j5 vss k5 pci_ad[19] l5 pci_frame_n m5 vccp j6 pci_ad[29] k6 vcc l11 vss m11 vss l12 vss m12 vss l13 vss m13 vss l14 vss m14 vss l15 vss m15 vss l16 vss m16 vss j21 ex_addr[8] k21 vcc j22 ex_addr[16] k22 vss l22 vccp m22 ex_cs_n[5] j23 vcc k23 ex_cs_n[0] l23 vcc m23 ex_clk j24 ex_addr[23] k24 ex_cs_n[3] l24 ex_cs_n[6] m24 ex_data[2] j25 ex_cs_n[2] k25 vccp l25 ex_data[0] m25 vss j26 ex_cs_n[4] k26 ex_cs_n[7] l26 ex_data[1] m26 ex_data[3] table 23. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 3 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 69 n1 pci_ad[11] p1 pci_cbe_n[0] r1 pci_ad[10] t1 pci_ad[6] n2 vccp p2 pci_ad[14] r2 vss t2 pci_trdy_n n3 vcc p3 pci_ad[13] r3 pci_ad[9] t3 vss n4 pci_perr_n p4 vss r4 vcc t4 pci_ad[2] n5 pci_ad[15] p5 pci_ad[12] r5 pci_ad[4] t5 vccp n11 vss p11 vss r11 vss t11 vss n12 vss p12 vss r12 vss t12 vss n13 vss p13 vss r13 vss t13 vss n14 vss p14 vss r14 vss t14 vss n15 vss p15 vss r15 vss t15 vss n16 vss p16 vss r16 vss t16 vss n22 vcc p22 ex_data[6] r22 vccp t22 ex_rdy_n[0] n23 vss p23 ex_data[7] r23 vcc t23 vss n24 vcc p24 ex_data[8] r24 ex_data[12] t24 ex_data[14] n25 ex_data[4] p25 vccp r25 ex_data[11] t25 vss n26 ex_data[5] p26 ex_data[9] r26 ex_data[10] t26 ex_data[13] table 23. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 4 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 70 datasheet u1 pci_ad[8] v1 pci_ad[5] w1 pci_ad[1] y1 n/c u2 vccp v2 vss w2 vccp y2 n/c u3 pci_ad[0] v3 pci_ad[3] w3 n/c y3 n/c u4 pci_ad[7] v4 vcc w4 vss y4 vcc u5 n/c v5 n/c w5 n/c y5 vccp u6 vcc v6 vss w6 n/c y6 eth_txen0 u21 vcc v21 gpio[6] w21 gpio[1] y21 rxdata1 u22 gpio[14] v22 gpio[9] w22 vccp y22 gpio[0] u23 ex_rdy_n[1] v23 vcc w23 gpio[8] y23 vcc u24 ex_rdy_n[2] v24 gpio[13] w24 vss y24 gpio[5] u25 gpio[15] v25 vccp w25 gpio[11] y25 vccp u26 ex_data[15] v26 ex_rdy_n[3] w26 gpio[12] y26 gpio[10] table 23. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 5 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 71 aa1 n/c ab1 n/c ac1 vss ad1 eth_txclk0 aa2 vccp ab2 n/c ac2 eth_txdata0[0] ad2 eth_rxdv0 aa3 vss ab3 eth_txdata0[3] ac3 vccp ad3 vss aa4 n/c ab4 eth_txdata0[1] ac4 vcc ad4 eth_crs0 aa5 eth_txdata0[2] ab5 vss ac5 eth_rxdata0[0] ad5 eth_mdc aa6 vcc ab6 eth_rxclk0 ac6 vss ad6 eth_txdata1[0] aa7 eth_rxdata0[1] ab7 vccp ac7 vcc ad7 eth_rxdata1[3] aa8 vss ab8 eth_txdata1[2] ac8 eth_rxdata1[2] ad8 eth_rxclk1 aa9 eth_txdata1[1] ab9 eth_rxdata1[1] ac9 vcc ad9 vss aa10 vcc ab10 vccp ac10 vcc ad10 vssoscp ab11 vccp ac11 vccoscp ad11 vccp ab12 vss ac12 vcc ad12 pll_lock ab13 n/c ac13 reset_in_n ad13 pwron_reset_n ab14 vccp ac14 vcc ad14 n/c ab15 n/c ac15 n/c ad15 n/c ab16 vss ac16 n/c ad16 vss aa17 vcc ab17 n/c ac17 n/c ad17 n/c aa18 n/c ab18 vccp ac18 vcc ad18 n/c aa19 n/c ab19 n/c ac19 n/c ad19 vccp aa20 vss ab20 n/c ac20 n/c ad20 n/c aa21 vcc ab21 scantestmode_n ac21 vcc ad21 n/c aa22 txdata1 ab22 vccp ac22 jtg_trst_n ad22 vss aa23 vss ab23 cts0_n ac23 vcc ad23 jtg_tdo aa24 gpio[3] ab24 cts1_n ac24 rxdata0 ad24 vss aa25 vss ab25 vccp ac25 rts1_n ad25 txdata0 aa26 gpio[7] ab26 gpio[4] ac26 gpio[2] ad26 rts0_n table 23. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 6 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information 72 datasheet ae1 eth_rxdata0[3] af1 eth_rxdata0[2] ae2 vccp af2 eth_mdio ae3 eth_col0 af3 (reserved) ae4 eth_txen1 af4 eth_txdata1[3] ae5 vccp af5 eth_txclk1 ae6 eth_rxdv1 af6 eth_rxdata1[0] ae7 vss af7 eth_crs1 ae8 eth_col1 af8 vssosc ae9 vccp af9 osc_in ae10 vccpll1 af10 vssoscp ae11 vss af11 osc_out ae12 vccpll2 af12 vccosc ae13 vccp af13 bypass_clk ae14 n/c af14 n/c ae15 vss af15 n/c ae16 n/c af16 n/c ae17 vccp af17 n/c ae18 n/c af18 n/c ae19 vss af19 n/c ae20 n/c af20 n/c ae21 vccp af21 n/c ae22 n/c af22 n/c ae23 vccp af23 n/c ae24 jtg_tdi af24 n/c ae25 vccp af25 jtg_tms ae26 highz_n af26 jtg_tck table 23. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 7 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 30 .
intel ? ixp42x product line and ixc1100 control plane processor package and pinout information datasheet 73 4.3 package thermal specifications the thermal characterization parameter ? jt? is proportional to the temperature difference between the top, center of the p ackage and the junction temperature. this can be a useful value for verifying devi ce temperatures in an actual environment. by measuring the package of the device, the junction temperature can be estimated, if the thermal characterization parameter has been measured under similar conditions. the use of jt should not be confused with jc, which is the thermal resistance from the device junction to the external surface of the package or case nearest the die attachment ? as the case is held at a constant temperature. the case temperature can then be monitored to ma ke sure that the maximum junction temperature is not violated. examples are given in the following sections. note: for more information on jt, refer to the eia/jedec standard 51-2, section 4. 4.3.1 commercial temperature ?commercial? temperature range is defined in te rms of the ambient temperature range, which is specified as 0 c to 70 c. the maximum power (p) is 2.4 w and the maximum junction temperature (t j ) is 115 c. jt for commercial temperature is 0.89 c/w. using the preceding junction-temperature formul a, the commercial temperature for a 266-mhz part ? assuming a maximum power of 2 w ? would be: 4.3.2 extended temperature ?extended? temperature range is defined in term s of the ambient temperature range, which is specified as -40 c to 85 c. the maximum power (p) is 2.4 w and the maximum junction temperature (t j ) is 115 c. jt for extended temperature is 0.32 c/w. using the preceding junction-temperature formula, the extended temperature for a 533-mhz part ? assuming a maximum power of 2.4 w ? would be: case temperature = junction temperature - ( jt * power dissipation) t jc = t j - ( jt * power dissipation) t jc = 115 c - (0.89 * 2.0) t jc = 113.22 c t jc = 115 c - (0.32 * 2.4) t jc = 114.23 c
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 74 datasheet 5.0 electrical specifications 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximu m ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. 5.2 v ccpll1 , v ccpll2 , v ccoscp , v ccosc pin requirements to reduce voltage-supply noise on the analog sections of the intel ? ixp42x product line of network processors and ixc1100 control plane processor, the phase-lock loop circuits (v ccpll1 , v ccpll2 ) and oscillator circuit (v ccoscp , v ccosc ) require isolated voltage supplies. the filter circuits for each supply are shown in the following sections. 5.2.1 v ccpll1 requirement a parallel combination of a 10-nf capacitor ? for bypass ? and a 200-nf capacitor ? for a first-order filter with a cut-off frequency below 30 mhz ? must be connected to the v ccpll1 pin of the intel ? ixp42x product line and ixc1100 control plane processors. the ground of both capacitors should be connected to the nearest v ss supply pin. both capacitors should be located less than 0.5 inch away from the v ccpll1 pin and the associated v ss pin. in order to achieve the 200-nf capacitance, a paralle l combination of two 100-nf capacitors may be used as long as the capacitors are placed directly beside each other. parameter maximum rating ambient air temperature (extended) -40o c to 85o c ambient air temperature (commercial) 0o c to 70o c supply voltage core -0.3 v to 2.1v supply voltage i/o -0.3 v to 3.6v supply voltage oscillator (v ccosc ) -0.3 v to 2.1v supply voltage oscillator (v ccoscp ) -0.3 v to 3.6v supply voltage pll (v ccpll1 ) -0.3 v to 2.1v supply voltage pll (v ccpll2 ) -0.3 v to 2.1v voltage on any i/o ball -0.3 v to 3.6v storage temperature -55 o c to 125 o c
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 75 5.2.2 v ccpll2 requirement a parallel combination of a 10-nf capacitor ? for bypass ? and a 200-nf capacitor ? for a first-order filter with a cut-off frequency below 30 mhz ? must be connected to the v ccpll2 pin of the ixp42x product line and ixc1100 control plane processors. the ground of both capacitors should be connected to the nearest v ss supply pin. both capacitors should be located less than 0.5 inch away from the v ccpll2 pin and the associated v ss pin. in order to achieve the 200-nf capacitance, a para llel combination of two 100-nf capacitors may be used as long as the capacitors are placed directly beside each other. 5.2.3 v ccoscp requirement a single 170-nf capacitor must be connected between the v ccp_osc pin and v ssp_osc pin of the ixp42x product line and ixc1100 control plane processors. this capacitor value provides both bypass and filtering. when 170 nf is an inconvenient size, capacitor values between 150 nf to 200 nf could be used with little adverse effects, assuming that the eff ective series resistance of the 200-nf capacitor is under 50 m ? . in order to achieve a 200-nf capacitance, a parall el combination of two 100-nf capacitors may be used as long as the capacitors are placed directly beside each other. v ssp_osc consists of two pins, ad10 and af10. ensure that both pins are connected as shown in figure 10 . figure 8. v ccpll1 power filtering diagram 1.3 v intel ? ixp4xx product line / intel ? ixc1100 control plane processor 10 nf v ss v ccpll1 100 nf 100 nf v ss b1680-02 figure 9. v ccpll2 power filtering diagram intel ? ixp4xx product line / intel ? ixc1100 control plane processor 1.3 v 10 nf v ss v ccpll2 100 nf 100 nf v ss b1681-02
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 76 datasheet 5.2.4 v ccosc requirement a parallel combination of a 10-nf capacitor ? for bypass ? and a 200-nf capacitor ? for a first-order filter with a cut-off frequency below 33 mhz ? must be connected to both of the v ccosc pins of the ixp42x product line and ixc1100 control plane processors. the grounds of both capacitors should be connected to the v ssosc supply pin. both capacitors should be located less than 0.5 inch away from the v ccosc pin and the associated v ssosc pin. in order to achieve a 200-nf capacitance, a paralle l combination of two 100-nf capacitors may be used as long as the capacitors are placed directly beside each other. figure 10. v ccoscp power filtering diagram intel ? ixp4xx product line / intel ? ixc1100 control plane processor 3.3 v 170 nf v ss v ccoscp v ssoscp v ssoscp b1675-03 figure 11. v ccosc power filtering diagram intel ? ixp4xx product line / intel ? ixc1100 control plane processor 1.3 v 10 nf v ss 100 nf 100 nf b1676-02
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 77 5.3 rcomp pin requirements figure 12 shows the requirements for the rcomp pin. 5.4 dc specifications 5.4.1 operating conditions figure 12. rcomp pin external resistor requirements table 24. operating conditions symbol parameter min. typ. max. units notes v ccp voltage supplied to the i/o. 3.135 3.3 3.465 v v cc voltage supplied to the internal logic. 1.235 1.3 1.365 v v ccosc voltage supplied to the internal oscillator logic. 1.235 1.3 1.365 v v ccoscp voltage supplied to the oscillator i/o. 3.135 3.3 3.465 v v ccpll1 voltage supplied to the analog phase-lock loop. 1.235 1.3 1.365 v v ccpll2 voltage supplied to the analog phase-lock loop. 1.235 1.3 1.365 v intel ? ixp4xx product line / intel ? ixc1100 control plane processor v ss rcomp v ss 34 ? , + 1% b1672-01
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 78 datasheet 5.4.2 pci dc parameters notes: 1. input leakage currents include hi-z output leakage fo r all bidirectional buffers with tri-state outputs. 2. these values are typical values seen by the manufacturing process and are not tested. 3. for additional information, see the pci local bus specification , rev. 2.2. 5.4.3 usb dc parameters notes: 1. these values are typical values seen by the manufacturing process and are not tested. table 25. pci dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 0.5 v ccp v 3 v il input-low voltage 0.3 v ccp v 3 v oh output-high voltage i out = -500 a 0.9 v ccp v 3 v ol output-low voltage i out = 1500 a 0.1 v ccp v 3 i il input-leakage current 0 < v in < v ccp -10 10 a 1 , 3 c in input-pin capacitance 5 pf 2 , 3 c out i/o or output pin capacitance 5pf 2 , 3 c idsel idsel-pin capacitance 5 pf 2 , 3 l pin pin inductance 20 nh 2 , 3 table 26. usb v1.1 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.15 v v il input-low voltage 0.8 v v oh output-high voltage i out = -6.1 * v oh ma 2.8 v v ol output-low voltage iout = 6.1 * v oh ma 0.3 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 79 5.4.4 utopia-2 dc parameters notes: 1. input leakage currents include hi-z output leakage for all bidirectional buffers with tri-state outputs. 2. these values are typical values seen by the manufacturing process and are not tested. 5.4.5 mii dc parameters notes: 1. these values are typical values seen by the manufacturing process and are not tested. table 27. utopia-2 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -8 ma 2.4 v v ol output-low voltage i out = 8 ma 0.5 v i oh output current at high voltage v oh > 2.4 v -8 ma i ol output current at low voltage v ol < 0.5 v 8 ma i il input-leakage current 0 < v in < v ccp -10 10 a 1 c in input-pin capacitance 5 pf 2 c out i/o or output pin capacitance 5pf 2 table 28. mii dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v v ol output-low voltage i out = 4ma 0.4 v i oh output current at high voltage v oh > 2.4 v -8 ma i ol output current at low voltage v ol < 0.4 v 8 ma i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 80 datasheet 5.4.6 mdio dc parameters notes: 1. these values are typical values seen by the manufacturing process and are not tested. 5.4.7 sdram bus dc parameters notes: 1. v ih overshoot: v ih (max) = v ccp + 2 v for a pulse width < 3 ns, and the pulse width cannot be greater than one third of the cycle rate. 2. v il undershoot: v il (min) = -2 v for a pulse width < 3 ns cannot be exceeded. 3. these values are typical values seen by the manufacturing process and are not tested. table 29. mdio dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v v ol output-low voltage i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 c inmdio input-pin capacitance 5 pf 1 table 30. sdram bus dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v 1 v il input-low voltage 0.8 v 2 v oh output-high voltage i out = -4 ma 2.4 v v ol output-low voltage i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -5 5 a i ol output-leakage current 0 < v in < v ccp -5 5 a c inclk input-pin capacitance 4 pf 3 c io i/o-pin capacitance 5 pf 3
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 81 5.4.8 expansion bus dc parameters notes: 1. test conditions were a 70 pf load to ground. 2. these values are typical values seen by the manufacturing process and are not tested. 5.4.9 high-speed, serial interface 0 dc parameters notes: 1. these values are typical values seen by the manufacturing process and are not tested. 5.4.10 high-speed, serial interface 1 dc parameters notes: 1. these values are typical values seen by the manufacturing process and are not tested. table 31. expansion bus dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v 1 v ol output-low voltage i out = 4ma 0.4 v 1 i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 2 table 32. high-speed, serial interface 0 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -8 ma 2.4 v v ol output-low voltage i out = 8 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 table 33. high-speed, serial interface 1 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -8 ma 2.4 v v ol output-low voltage i out = 8 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 82 datasheet 5.4.11 high-speed and console uart dc parameters notes: 1. these values are typical values seen by the manufacturing process and are not tested. table 34. uart dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v v ol output-low voltage i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 83 5.4.12 gpio dc parameters 5.4.13 jtag dc parameters notes: 1. these values are typical values seen by the manufacturing process and are not tested. 5.4.14 reset dc parameters table 35. gpio dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage for gpio 0 to gpio 13 i out = -16 ma 2.4 v v ol output-low voltage for gpio 0 to gpio 13 i out = 16 ma 0.4 v v oh output-high voltage for gpio 14 and gpio 15 i out = -4 ma 2.4 v v ol output-low voltage for gpio 14 and gpio 15 i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf table 36. jtag dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v v ol output-low voltage i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 table 37. pwron_reset _n dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 1.0 1.3 v the input voltage must not exceed 1.3v or long-term reliability may be adversely affected. v il input-low voltage 0.3 v i il input leakage current 0 < v in < 1.3v -500 10 a c in input capacitance 1 pf simulated results.
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 84 datasheet 5.5 ac specifications 5.5.1 clock signal timings 5.5.1.1 processor clock timings notes: 1. this value could be an oscillator input or a series resonant frequency from a crystal. if used as an oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected. 2. use the component values recommended by the crystal manufacturer. 3. this parameter applies when driving the clock input with an oscillator. 4. the reference-clock input slope should not exceed more than 2.5 v/ns to ensure proper pll operation . table 38. device clock timings (oscillator reference) symbol parameter min. nom. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v t frequency clock frequency for ixp42x product line and ixc1100 control plane processors crystal or oscillator. 33.33 mhz 1 , 4 u frequency clock tolerance over -40o c to 85o c. -50 50 ppm c in pin capacitance of ixp42x product line and ixc1100 control plane processors ? inputs. 5pf c shunt c shunt is a crystal parameter sometimes referred to as the holder capacitance. 234pf c 1 load capacitance pf 2 c 2 load capacitance pf 2 t dc duty cycle 35 50 65 % 3 table 39. device clock timings (crystal reference) (sheet 1 of 2) symbol parameter min. nom. max. units notes v ih input-high voltage 1.9 v v il input-low voltage 1.6 v t frequency clock frequency for ixp42x product line and ixc1100 control plane processors crystal or oscillator. 33.33 mhz 1 , 4 u frequency clock tolerance over -40o c to 85o c. -50 50 ppm esr equivalent series resistance 60 ? c in pin capacitance of ixp42x product line and ixc1100 control plane processors ? inputs. 5pf c shunt c shunt is a crystal parameter sometimes referred to as the holder capacitance. 23 4pf
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 85 1. this value could be an oscillator input or a series re sonant frequency from a crystal. if used as an oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected. 2. use the component values recommended by the crystal manufacturer. 3. this parameter applies when driving the clock input with an oscillator. 4. the reference-clock input slope should not exceed more than 2.5 v/ns to ensure proper pll operation c 1 load capacitance pf 2 c 2 load capacitance pf 2 t dc duty cycle 35 50 65 % 3 table 39. device clock timings (crystal reference) (sheet 2 of 2) symbol parameter min. nom. max. units notes figure 13. typical connection to a crystal figure 14. typical connection to an oscillator xtal c 1 c 2 osc_in osc_out intel ? ixp4xx product line / intel ? ixc1100 control plane processor b1677-02 oscillator osc_in osc_out intel ? ixp4xx product line / intel ? ixc1100 control plane processor b1678-02
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 86 datasheet 5.5.1.2 pci clock timings 5.5.1.3 mii clock timings 5.5.1.4 utopia-2 clock timings notes: 1. the utopia interface can operate at a minimum frequency greater than 0hz 5.5.1.5 expansion bus clock timings table 40. pci clock timings symbol parameter 33 mhz 66 mhz units notes min. max. min. max. t periodpciclk clock period for pci clock 30 15 ns t clkhigh pci clock high time 11 6 ns t clklow pci clock low time 11 6 ns t rise/fall rise and fall time requirements for pci clock 22ns table 41. mii clock timings symbol parameter min. nom. max. units notes t period100mbit clock period for tx and rx ethernet clocks 25 25 mhz t period10mbit clock period for tx and rx ethernet clocks 2.5 2.5 mhz t duty duty cycle for tx and rx ethernet clocks 35 50 65 % t rise/fall rise and fall time requirements for tx and rx ethernet clocks 2ns table 42. utopia-2 clock timings symbol parameter min. nom. max. units notes t period clock period for tx and rx utopia-2 clocks 33 mhz 1 t duty duty cycle for tx and rx utopia-2 clocks 40 50 60 % 1 t rise/fall rise and fall time requirements for tx and rx utopia-2 clocks 2ns1 table 43. expansion bus clock timings symbol parameter min. nom. max. units notes t period clock period for expansion-bus clock 66 mhz t duty duty cycle for expansion-bus clock 40 50 60 % t rise/fall rise and fall time requirements for expansion-bus clock 2ns
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 87 5.5.2 bus signal timings the ac timing waveforms are shown in the following sections. 5.5.2.1 pci note: v hi = 0.6 v cc and v low = 0.2 v cc figure 15. pci output timing a9572-01 clk output delay t clk2out(b) v low v hi figure 16. pci input timing a9573-01 clk input inputs valid t hold t setup(b)
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 88 datasheet notes: 1. see the timing measurement conditions. 2. parts compliant to the 3.3 v signaling environment. 3. req# and gnt# are point-to-point signals and have di fferent output valid delay and input setup times than do bused signals. gnt# has a setup of 10 ns for 33 mhz and 5 ns for 66 mhz; req# has a setup of 12 ns for 33 mhz and 5 ns for 66 mhz. 4. rst# is asserted and de-asserted as ynchronously with respect to clk. 5. all pci outputs must be asynchronously driven to a tri-state value when rst# is active. 6. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. 7. timing was tested with a 70-pf capacitor to ground. 8. for additional information, see the pci local bus specification , rev. 2.2. 5.5.2.2 usb interface for timing parameters, see the usb 1.1 specification. the ixp42x product line and ixc1100 control plane processors? usb 1.1 interface is a device or function controller only. the ixp42x product line and ixc1100 control plane processo rs? usb v 1.1 interface cannot be line-powered. table 44. pci bus signal timings symbol parameter 33 mhz 66 mhz units notes min. max. min. max. t clk2outb clock to output for all bused signals. this is the pci_ad[31:0], pci_cbe_n [3:0], pci_par, pci_frame_n, pci_irdy_n, pci_trdy_n, pci_stop_n, pci_devsel_n, pci_perr_n, pci_serr_n 2111 6ns 1 , 2 , 5 , 7 , 8 t clk2out clock to output for all point-to-point signals. this is the pci_gnt_n and pci_req_n(0) only. 2121 6ns 1 , 2 , 5 , 7 , 8 t setupb input setup time for all bused signals. this is the pci_ad[31:0], pci_cbe_n [3:0], pci_par, pci_frame_n, pci_irdy_n, pci_trdy_n, pci_stop_n, pci_devsel_n, pci_perr_n, pci_serr_n 73ns 4 , 6 , 7 , 8 t setup input setup time for all point-to-point signals. this is the pci_req_n and pci_gnt_n(0) only. 10, 12 5 ns 4 , 7 , 8 t hold input hold time from clock. 0 0 ns 4 , 7 , 8 t rst-off reset active-to-output float delay 40 40 ns 5 , 6 , 7 , 8
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 89 5.5.2.3 utopia-2 notes: 1. timing was tested with a 70-pf capacitor to ground. figure 17. utopia-2 input timings table 45. utopia-2 input timings values symbol parameter min. max. units notes t setup input setup prior to rising edge of clock. inputs included in this timing are utp_ip_data[7:0], utp_ip_soc, and utp_ip_fci, and utp_op_fci. 8ns t hold input hold time after the rising edge of the clock. inputs included in this timing are utp_ip_data[7:0], utp_ip_soc, and utp_ip_fci, and utp_op_fci. 1ns figure 18. utopia-2 output timings table 46. utopia-2 output timings values symbol parameter min. max. units notes t clk2out rising edge of clock to signal output. outputs included in this timing are utp_ip_data[3:0], utp_op_soc, utp_op_fco, utp_ip_fco, utp_op_data[7:0], and utp_op_addr[3:0]. 17 ns 1 t holdout signal output hold time after the rising edge of the clock. outputs included in this timing are utp_ip_data[3:0], utp_op_soc, utp_op_fco, utp_ip_fco, utp_op_data[7:0], and utp_op_addr[3:0]. 1ns 1 a9578-01 thold tsetup clock signals a9579-01 tclk2out tholdout clock signals
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 90 datasheet 5.5.2.4 mii notes: 1. these values satisfy the mii specification requirement of 0 ns to 25 ns clock to output delay. notes: 1. these values satisfy the mii specification requirement of 10-ns setup and hold time. 2. timing tests were performed with a 70-pf capacitor to ground. figure 19. mii output timings table 47. mii output timings values symbol parameter min. max. units notes t 1 clock to output delay for eth_txdata and eth_txen. 017ns 1 t 2 eth_txdata and eth_txen hold time after eth_txclk. 2 ns a9580-01 eth_tx_clk eth_tx_data[7:0] eth_tx_en eth_crs t 1 t 2 figure 20. mii input timings table 48. mii input timings values symbol parameter min. max. units notes t 3 eth_rxdata and eth_rxdv setup time prior to rising edge of eth_rxclk 5.5 ns 1 , 2 t 4 eth_rxdata and eth_rxdv hold time after the rising edge of eth_rxclk 0 ns 1 , 2 a9581-01 eth_rx_clk eth_rx_data[7:0] eth_rx_dv eth_crs t 4 t 3
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 91 5.5.2.5 mdio figure 21. mdio output timings note: processor is sourcing mdio. figure 22. mdio input timings note: phy is sourcing mdio. a9582-02 eth_mdc eth_mdio t 1 t 2 a9583-02 eth_mdc eth_mdio t 3 t 5 t 4
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 92 datasheet note: 1. this parameter is not tested and is guaranteed by design. 5.5.2.6 sdram bus table 49. mdio timings values symbol parameter min. max. units notes t1 eth_mdio, clock to output timing with respect to rising edge of eth_mdc clock eth_mdc/2 + 10 ns ns t2 eth_mdio output hold timing after the rising edge of eth_mdc clock 10 ns t3 eth_mdio input setup prior to rising edge of eth_mdc clock 2 ns t4 eth_mdio hold time after the rising edge of eth_mdc clock 0 ns t5 eth_mdc clock period 125 500 ns 1 figure 23. sdram input timings table 50. sdram input timings values symbol parameter min. max. units notes t setup input setup prior to rising edge of clock. inputs included in this timing are sdm_dq[31:0] (during a read operation). 1.4 ns t hold input hold time after the rising edge of the clock. inputs included in this timing are sdm_dq[31:0] (during a read operation). 1.5 ns tsetu p thol d cloc k si g nals
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 93 notes: 1. timing test were performed with a 70-pf load to ground. 5.5.2.7 expansion bus figure 24. sdram output timings table 51. sdram output timings values symbol parameter min. max. units notes t clk2out rising edge of clock-to-s ignal output. outputs included in this timing are sdm_addr[12:0], sdm_ba[1:0], sdm_dqm[3:0], sdm_cke, sdm_we_n, sdm_cs_n[1:0], sdm_cas_n, sdm_ras_n, sdm_dq[31:0] (during a write operation). 5.5 ns 1 t holdout signal output hold time after the rising edge of the clock. outputs included in this timing are sdm_dq[31:0] (during a write operation). 1.5 ns 1 a9584-01 t clk2out t holdout data valid clock signals figure 25. intel multiplexed mode a9585-01 ex_clk ex_addr ex_data ex_rd_n ex_data ex_ale ex_wr_n ex_cs_n valid address t5 1-16 cycles t4 1-4 cycles t recov t ale2addrhold t rdsetup t rdhold t dval2valwrt t dhold2afterwr t3 1-16 cycles t2 1-4 cycles t1 2-5 cycles ale extended t alepulse t ale2valcs t wrpulse address output data address input data multiplexed address/data
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 94 datasheet notes: 1. the ex_ale signal is extended form 1 to 4 cycles based on the programming of the t1 timing parameter. the parameter tale2addrhold is fixed at 1 cycle. 2. setting the address phase parameter (t1) will adjust the duration that the address appears to the external device. 3. setting the data setup phase parameter (t2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data will be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion interface. 7. one cycle is the period of the expansion bus clock. 8. clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing tests were performed with a 70-pf capacitor to ground. table 52. intel multiplexed mode values symbol parameter min. max. units notes talepulse pulse width of ale (addr is valid at the rising edge of ale) 1 41 cycles 1 , 7 tale2addrhold valid address hold time after from falling edge of ale 1 1 cycles 1 , 2 , 7 tdval2valwrt write data valid prior to wr_n falling edge 1 4 cycles 3 , 7 twrpulse pulse width of the wr_n 1 16 cycles 4 , 7 tdholdafterwr valid data after the rising edge of wr_n 1 4 cycles 5 , 7 tale2valcs valid chip select after the falling edge of ale 1 4 cycles 7 trdsetup data valid required before the rising edge of rd_n 5.3 14.7 ns trdhold data hold required after the rising edge of rd_n 2 ns trecov time needed between successive accesses on expansion interface. 116cycles 6 figure 26. intel simplex mode a9586-01 ex_clk ex_addr ex_data ex_rd_n ex_data ex_wr_n valid address output data t5 1-16 cycles t4 1-4 cycles ex_cs_n t wrpulse t recov t addr2valcs t dval2valwrt input data t dhold2afterwr t3 1-16 cycles t2 1-4 cycles t1 1-4 cycles t rdsetup t rdhold
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 95 notes: 1. ex_ale is not valid in simplex mode of operation. 2. setting the address phase parameter (t1) will adjust the duration that the address appears to the external device. 3. setting the data setup phase parameter (t2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data will be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion interface. 7. one cycle is the period of the expansion bus clock. 8. clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing tests were performed with a 70-pf capacitor to ground. table 53. intel simplex mode values symbol parameter min. max. units notes t addr2valcs valid address to valid chip select 1 4 cycles 1 , 2 , 7 t dval2valwrt write data valid prior to expb_io_write_n falling edge 1 4 cycles 3 , 7 t wrpulse pulse width of the exp_io_write_n 1 16 cycles 4 , 7 t dholdafterwr valid data after the rising edge of expb_io_write_n 1 4 cycles 5 , 7 t rdsetup data valid required before the rising edge of exp_io_read_n 5.3 14.7 ns t rdhold data hold required after the rising edge of exp_io_read_n 2ns t recov time required between successive accesses on the expansion interface. 116cycles 6 figure 27. motorola* multiplexed mode a9587-01 ex_clk ex_addr ex_data ex_rd_n (exp_mot_rnw) ex_wr_n (exp_mot_ds_n) ex_data ex_ale valid address t5 1-16 cycles t4 1-4 cycles ex_cs_n t recov t ale2addrhold t dval2valds ex_wr_n (exp_mot_ds_n) ex_rd_n (exp_mot_rnw) t dhold2afterds t3 1-16 cycles t2 1-4 cycles t1 2-5 cycles ale extended t alepulse t ale2valcs t dspulse address output data address input data multiplexed address/data t rdsetup t rdhold
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 96 datasheet notes: 1. the ex_ale signal is extended form 1 to 4 cycles based on the programming of the t1 timing parameter. the parameter tale2addrhold is fixed at 1 cycle 2. setting the address phase parameter (t1) will adjust the duration that the address appears to the external device. 3. setting the data setup phase parameter (t2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data will be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion interface. 7. one cycle is the period of the expansion bus clock. 8. clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing tests were performed with a 70-pf capacitor to ground. table 54. motorola* multiplexed mode values symbol parameter min. max. units notes t alepulse pulse width of ale (addr is valid at the rising edge of ale) 1 4 cycles 1 , 7 t ale2addrhold valid address hold time after from falling edge of ale 1 1 cycles 1 , 2 , 7 t dval2valds write data valid prior to exp_mot_ds_n falling edge 1 4 cycles 3 , 7 t dspulse pulse width of the exp_mot_ds_n 1 16 cycles 4 , 7 t dholdafterds valid data after the rising edge of exp_mot_ds_n 1 4 cycles 5 , 7 t ale2valcs valid chip select after the falling edge of ale 1 4 cycles 7 t rdsetup data valid required before the rising edge of exp_mot_ds_n 5.3 14.7 ns t rdhold data hold required after the rising edge of exp_mot_ds_n 2 ns t recov time needed between successive accesses on expansion interface. 116cycles 6
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 97 figure 28. motorola* simplex mode a9588-01 ex_clk ex_addr ex_data ex_wr_n (exp_mot_ds_n) ex_rd_n (exp_mot_rnw) ex_data ex_rd_n (exp_mot_rnw) valid address output data t5 1-16 cycles t4 1-4 cycles ex_cs_n t dspulse t recov t ad2valcs t dval2valds input data t dhold2afterds t3 1-16 cycles t2 1-4 cycles t1 1-4 cycles ex_wr_n (exp_mot_ds_n) t rdsetup t rdhold
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 98 datasheet notes: 1. ex_ale is not valid in simplex mode of operation. 2. setting the address phase parameter (t1) will adjust the duration that the address appears to the external device. 3. setting the data setup phase parameter (t2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data will be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion interface. 7. one cycle is the period of the expansion bus clock. 8. clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing tests were performed with a 70-pf capacitor to ground. table 55. motorola* simplex mode values symbol parameter min. max. units note s t ad2valcs valid address to valid chip select 1 4 cycles 1 , 2 , 7 t dval2valds write data valid prior to exp_mot_ds_n falling edge 1 4 cycles 3 , 7 t dspulse pulse width of the exp_mot_ds_n 1 16 cycles 4 , 7 t dholdafterds valid data after the rising edge of exp_mot_ds_n 1 4 cycles 5 , 7 t rdsetup data valid required before the rising edge of exp_mot_ds_n 5.3 14.7 ns t rdhold data hold required after the rising edge of exp_mot_ds_n 2ns t recov time required between successive accesses on the expansion interface. 116cycles 6
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 99 figure 29. hpi ? 8 mode write accesses table 56. hpi timing symbol description state description min max unit notes t1 address timing 3 4 cycles 1, 5, 6 t2 setup/chip select timing 3 4 cycles 2, 6 t3 strobe timing 2 16 cycles 3, 5, 6 t4 hold timing 3 4 cycles 6 t5 recovery phase 2 17 cycles 6 table 57. hpi ? 8 mode write accesses values symbol parameter min. max. units notes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1, 5, 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5, 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2, 4, 5 t data_setup data valid prior to the rising edge of the hds1 data strobe. 4 5 cycles 3, 5, 6 t data_hold data valid after the rising edge of the hds1 data strobe. 4 36 cycles 3, 6 t recov time required between successive accesses on the expansion interface. 217cycles4, 6 ex_addr[2:1] (hcntl) ex_addr[0] (hbil) ex_rdy_n (hrdy) data ex_data (hdin) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) valid data valid ex_clk t1 t3 t4 t3 t2 t4 t5 t1 t2 t5 tadd_setup tcs2hds1val thds1_pulse tdata_setup tdata_hold trecov
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 100 datasheet notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp4xx product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de-active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp4xx product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse after the hrdy is de-active 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the access. the interfac e will not leave states t1 or t3 until hrdy is de-active 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground. notes: 1. the setup and hold timing values are for all modes. table 58. setup/hold timing values parameter min. max. units notes output valid. 15 ns 1 output hold 0 ns 1 input setup 3 ns 1 input hold. 2 ns 1
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 101 notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp4xx product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de-active. 2. the data setup phase parameter (t2) must be set to a mi nimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp4xx product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse after the hrdy is de-active 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the ac cess. the interface will not leave states t1 or t3 until hrdy is de-active 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground. table 59. hpi-16 multiplexed write accesses values symbol parameter min. max . units notes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1, 5, 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5, 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2, 4, 5 t data_setup data valid prior to the rising edge of the hds1 data strobe. 4 5 cycles 3, 5, 6 t data_hold data valid after the rising edge of the hds1 data strobe. 4 36 cycles 3, 6 t recov time required between successive accesses on the expansion interface. 217cycles4, 6 figure 30. hpi-16 multiplex write mode data valid data valid t1 t3 t4 t3 t2 t4 t1 t2 t5 ex_addr[2:1] (hcntl) ex_rdy_n (hrdy) ex_data (hdin) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) ex_clk tadd_setup thds1_pulse tcs2hds1val tdata_setup tdata_hold trecov
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 102 datasheet notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp4xx product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de-active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp4xx product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse after the hrdy is de-active 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the access. the interfac e will not leave states t1 or t3 until hrdy is de-active 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground. table 60. hpi-16 multiplex read accesses values symbol parameter min. max. units notes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1, 5, 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5, 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2, 4, 5 t data_setup data is valid from the time from of the falling edge of hds1_n to when the data is read. 4 5 cycles 3, 5, 6 t recov time required between successive accesses on the expansion interface. 2 17 cycles 4, 6
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 103 figure 31. hpi-16 multiplex read mode valid valid data valid data t1 t3 t4 t3 t2 t4 t5 t1 t2 t5 ex_addr[2:1] (hcntl) ex_rdy_n (hrdy) ex_data (hdout) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) ex_clk tadd_setup trecov thds1_pulse tdata_setup tcs2hds1val
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 104 datasheet notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp4xx product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de-active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp4xx product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse after the hrdy is de-active 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the access. the interfac e will not leave states t1 or t3 until hrdy is de-active 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground. table 61. hpi-16 non-multiplex read accesses values symbol parameter min. max. units notes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1, 5, 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5, 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2, 4, 5 t data_setup data is valid from the time from of the falling edge of hds1_n to when the data is read. 4 5 cycles 3, 5, 6 t recov time required between successive accesses on the expansion interface. 2 17 cycles 4, 6 figure 32. hpi-16 non-multiplex read mode valid valid data valid data valid t1 t3 t4 t3 t2 t1 t2 t5 ex_addr[23:0] (ha) ex_rdy_n (hrdy) ex_data (hdout) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) ex_clk tadd_setup tdata_setup thds1_pulse tcs2hds1val trecov
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 105 notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp4xx product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de-active. 2. the data setup phase parameter (t2) must be set to a mi nimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp4xx product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse after the hrdy is de-active 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the ac cess. the interface will not leave states t1 or t3 until hrdy is de-active 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground. table 62. hpi-16 non-multiplexed write accesses values symbol parameter min. max. units notes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1, 5, 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5, 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2, 4, 5 t data_setup data valid prior to the rising edge of the hds1 data strobe. 4 5 cycles 3, 5, 6 t data_hold data valid after the rising edge of the hds1 data strobe. 4 36 cycles 3, 6 t recov time required between successive accesses on the expansion interface. 217cycles4, 6
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 106 datasheet figure 33. hpi-16 non-multiplex write mode data valid data valid t1 t3 t4 t3 t2 t4 t1 t2 t5 _ addr[23:0] (ha) ex_rdy_n (hrdy) ex_data (hdin) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) ex_clk tadd_setup trecov thds1_pulse tcs2hds1val tdata_setup tdata_hold
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 107 5.5.2.7.1 ex_iowait_n the ex_iowait_n signal is available to be shared by devices attached to chip selects 0 through 7 and is used as required by slow devices. if the external device asserts ex_iowait_n during the strobe phase of a read transfer, the controller will hold in that phase until the ex_iowait_n goes false. at that time, the controller will immediately transition to the hold phase regardless of the setting of the programming parameter (t3) for the strobe phase. the ex_iowait_n signal only affects the interface du ring the strobe phase of a read transfer. if chip selects 4 through 7 are configured in hpi mode of operation, each chip select will have a corresponding hrdy signal called ex_rdy. the pola rity of the ready signal is programmable. chip select 4 corresponds to ex_rdy signal 0 and chip select 7 corresponds to ex_rdy signal 3. 5.5.2.8 high-speed, serial interfaces figure 34. high-speed, serial timings a9594-01 hss_txclk/ hss_rxclk 1 hss_(tx or rx)frame (positive edge) hss_(tx or rx)frame (negative edge) hss_ rxdata (positive edge) as inputs: valid data hss_ rxdata (negative edge) hss_(tx or rx)frame (positive edge) hss_(tx or rx)frame (negative edge) hss_ txdata (positive edge) hss_ txdata (negative edge) as outputs: valid data t1 t3 t4 valid data valid data t6 t5 t7 t8 t2 t9
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 108 datasheet notes: 1. hss_txclk and hss_rxclk may be coming from external independent sources or being driven by the ixp42x product line and ixc1100 control plane processors. the signals are shown to be synchronous for illustrative purposes and are not required to be synchronous. 2. applicable when the hss_rxframe and hss_txframe signals are being driven by an external source as inputs into the ixp42x product line and ixc1100 control plane processors. always applicable to hss_rxdata. 3. the hss_rxframe and hss_txframe can be configured to accept data on the rising or falling edge of the given reference clock. hss_rxframe and hss_rxdata signals are synchronous to hss_rxclk and hss_txframe and hss_txdata signals are synchronous to the hss_txclk. 4. applicable when the hss_rxframe and hss_txframe signals are being driven by the ixp42x product line and ixc1100 control plane processors to an external source. always applicable to hss_txdata. 5. the hss_txclk can be configured to be driven by an external source or be driven by the ixp42x product line and ixc1100 control plane processors. the slowest clock speed that can be accepted or driven is 512 khz. the maximum clock speed that can be accept ed or driven is 8.192 mhz. the clock duty cycle accepted will be 50/50 + 20%. 6. timing tests were performed with a 70-pf capacitor to ground and a 10-k ? pull-up resistor. for more information on the hss jitter specifications see the intel ? ixp42x product line of network processors and ixc1100 control plane processor developer?s manual table 63. high-speed, serial timing values symbol parameter min. max. units notes t1 setup time of hss_txframe, hss_rxframe, and hss_rxdata prior to the rising edge of clock 5ns 1 , 2 , 3 t2 hold time of hss_txframe, hss_rxframe, and hss_rxdata after the rising edge of clock 0ns 1 , 2 , 3 t3 setup time of hss_txframe, hss_rxframe, and hss_rxdata prior to the falling edge of clock 5ns 1 , 2 , 3 t4 hold time of hss_txframe, hss_rxframe, and hss_rxdata after the falling edge of clock 0ns 1 , 2 , 3 t5 rising edge of clock to output delay for hss_txframe, hss_rxframe, and hss_txdata 15 ns 1 , 4 t6 falling edge of clock to output delay for hss_txframe, hss_rxframe, and hss_txdata 15 ns 1 , 3 , 4 t7 output hold delay after rising edge of final clock for hss_txframe, hss_rxframe, and hss_txdata 0ns 1 , 3 , 4 t8 output hold delay after falling edge of final clock for hss_txframe, hss_rxframe, and hss_txdata 0ns 1 , 3 , 4 t9 hss_txclk period and hss_rxclk period 1/8.192 mhz 1/512 khz ns 5
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 109 5.5.2.9 jtag notes: 1. tests completed with a tbd pf load to ground on jtag_tdo. 2. jtag_tck may be stopped indefinitely in either the low or high phase. figure 35. boundary-scan general timings figure 36. boundary-scan reset timings table 64. boundary-scan interface timings values symbol parameter conditions min. typ. max. units notes t bscl jtag_tck low time 50 ns 2 t bsch jtag_tck high time 50 ns 2 t bsis jtag_tdi, jtag_tms setup time to rising edge of jtag_tck 10 ns t bsih jtag_tdi, jtag_tms hold time from rising edge of jtag_tck 10 ns t bsoh jtag_tdo hold time after falling edge of jtag_tck 1.5 ns 1 t bsod jtag_tdo clock to output from falling edge of jtag_tck 40 ns 1 t bsr jtag_trst_n reset period 30 ns t bsrs jtag_tms setup time to rising edge of jtag_trst_n 10 ns t bsrh jtag_tms hold time from rising edge of jtag_trst_n 10 ns b0416-01 t bsel t bsis t bsih t bsch jtg_tck jtg_tms, jtg_tdi jtg_tdo t bsoh t bsod a9597-01 t bsr t bsrs t bsrh jtg_trst_n jtg_tms
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 110 datasheet 5.5.3 reset timings figure 37. reset timings v ccp v cc pll_lock pwron_reset_n reset_in_n ex_addr[23:0] ex_addr[23:0]-pull up/down cfg settings to be captured cfg settings to be captured ixp4xx/ixc1100 drives outputs t release_pwron_rst_n t ex_addr_setup t release_rst_n t pll_lock t ex_addr_hold b1679-02
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications datasheet 111 notes: 1. t release_pwron_rst_n is the time required for the internal oscillator to reach stability. when an external oscillator is being used in place of a cr ystal, the 500-ms delay is not required. 2. the expansion bus address is c aptured as a derivative of the reset_in_n signal going high. when a programmable-logic device is used to drive the ex_add r signals instead of pull-dow ns, the signals must be active until pll_lock is active. 3. pll_lock is deasserted immediately when watchdog timer event occurs, or when reset_in_n is asserted, or when pwron_rst_n is asserted. pll_lock remains deasserted for ~24 ref_clocks after the watchdog reset is deasserted (internal to the chip). a ref clock time period is 1/clkin. 5.6 power sequence the 3.3-v i/o voltage (v ccp ) must be powered up 1 s before the core voltage (v cc ). the ixp42x product line and ixc1100 control plane processors? core voltage (v cc ) must never become stable prior to the 3.3-v i/o voltage (v ccp ). the v ccosc , v ccpll1 , and v ccpll2 voltages follow the v cc power-up pattern. the v ccoscp follows the v ccp power-up pattern. the value for t power_up must be at least 1 s. the t power_up timing parameter is measured from v ccp at 3.3 v and v cc at 1.3 v. there are no power-down requirements for the ixp42x product line and ixc1100 control plane processors. table 65. reset timings table parameters symbol parameter min. typ. max. units note t release_pwron_rst_n minimum time required to hold the pwron_rst_n at logic 0 state after stable power has been applied to the ixp42x product line and ixc1100 control plane processors. when using a crystal to drive the processors? system clock. (osc_in and osc_out) 500 ms 1 t release_reset_in_n minimum time required to hold the reset_in_n at logic 0 state after pwron_rst_n has been released to a logic 1 state. the reset_in_n signal must be held low when the pwron_rst_n signal is held low. 10 ns t pll_lock maximum time for pll_lock signal to drive to logic 1 after reset_in_n is driven to logic 1 state. the boot sequence does not occur until this period is complete. 10 s t ex_addr_setup minimum time for the ex_addr signals to drive the inputs prior to reset_in_n being driven to logic 1 state. this is used for sampling configuration information. 50 ns 2 t ex_addr_hold minimum/maximum time for the ex_addr signals to drive the inputs prior to pll_lock being driven to logic 1 state. this is used for sampling configuration information. 020ns 2 t warm_reset minimum time required to drive reset_in_n signal to logic 0 in order to cause a reset after the ixp42x product line and ixc1100 control plane processors has been in normal operation. the power must remain stable and the pwron_rst_n signal must remain stable. 500 ns
intel ? ixp42x product line and ixc1100 control plane processor electrical specifications 112 datasheet 5.7 i cc and total average power 5.8 ordering information for ordering information, please contact your local intel sales representative. figure 38. power-up sequence timing table 66. i cc and total average power speed symbol description typ.1 max. . 2unitsnotes 266 mhz i cc core supply current 0.70 0.95 a 1,2,3 i ccp i/o supply current 0.17 0.26 a 1,2,3 p total total average power 1.50 2.20 w 1,2,3 400 mhz i cc core supply current 0.75 1.05 a 1,2,3,4 i ccp i/o supply current 0.17 0.260 a 1,2,3 p total total average power 1.57 2.34 w 1,2,3 533 mhz i cc core supply current 0.82 1.15 a 1,2,3 i ccp i/o supply current 0.17 0.260 a 1,2,3 p total total average power 1.66 2.47 w 1,2,3 notes: 1. t ypical current i cc and i ccp are not tested. typical currents were measured on the intel ? ixdp425 / ixcdp1100 development platform at room temperature using typical sku silicon samples. a smartbits* tester was used in a router application running linux on the development board. two ethernet npes, and two ethernet controller pci cards were used in this router application. 2. typical case power supply voltages v cc =1.327v, v ccp = 3.363 v. 3. maximum voltages: v cc = 1.365 v, v ccp = 3.465 v, v ccosc = 1.365 v, v ccpll1 = 1.365 v, v ccpll2 = 1.365 v, maximum capacitive loading on all i/o pins of 50 pf. maximum i cc and i ccp specifications are tested and guaranteed. 4. the 400-mhz typical case core supply current is an approximation. b2263-01 1 2 3 4 v o l t s time v ccp v cc t power_up

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