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? semiconductor components industries, llc, 2013 september, 2013 ? rev. 0 1 publication order number: ncv7518/d ncv7518 flexmos hex low\side mosfet pre\driver the ncv7518 programmable six channel low-side mosfet pre-driver is one of a family of flexmos automotive grade products for driving logic-level mosfets. the product is controllable by a combination of serial spi and parallel inputs. the device offers 3.3 v/ 5 v compatible inputs and the serial output driver can be powered from either 3.3 v or 5 v. an internal power-on reset provides controlled power up. a reset input allows external re-initialization and an enable input allows all outputs and diagnostics to be simultaneously disabled. each channel independently monitors its external mosfet?s drain voltage for fault conditions. shorted load fault detection thresholds are fully programmable using an ex ternally programmed reference voltage and a combination of discrete internal ratio values. the ratio values are spi selectable and allow different detection thresholds for each channel. fault recovery operation for each channel is programmable and may be selected for latch-off or automatic retry. status information for each channel is 3-bit encoded by fault type and is available through spi communication. the flexmos family of products offers application scalability through choice of external mosfets. features ? 16-bit spi with parity and frame error detection ? 3.3 v/5 v compatible parallel and serial control inputs ? 3.3 v/5 v compatible serial output driver ? reset and enable inputs ? open-drain fault flag ? priority encoded diagnostics with latched unique fault type data ? shorted load, short to gnd ? open load with fast charge option ? on and off state pulsed mode diagnostics ? ratiometric diagnostic references and currents ? programmable ? shorted load fault detection thresholds ? fault recovery mode ? blanking timers ? wettable flanks pb-free packaging ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec-q100 qualified and ppap capable ? this is a pb-free device benefits ? scalable to load by choice of external mosfet device package shipping ? ordering information NCV7518MWTXG qfn32 (pb-free) 5,000 / tape & reel qfn32 mw suffix case 485cz marking diagram http://onsemi.com ncv7518 awlyyww 1 a = assembly location wl = wafer lot yy = year ww = work week = pb-free package ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. (*note: microdot may be in either location)
ncv7518 http://onsemi.com 2 driver vcc2 vss channel0 power on reset & bias control registers fault data spi 16 bit clock vss vss fault reference generator rst csb sclk si so driver vss iref iref ncv7518 hex mosfet pre-driver drn0 in0 in1 in2 in3 in4 in5 vcc2 gat0 drn1 gat1 channel1 drn ref disable parallel serial vcc2 rst enb vss vload fltref gnd fltb si sclk csb vcc1 enb so vdd fault detect rstb off ? state diagnostics generator por ref drn disable vreg 3v internal rail rail fault logic & refresh timer rail ? + oa vcc1 ref ref disable drn2 gat2 channel2 drn ref disable parallel serial vcc2 rst enb drn3 gat3 channel3 drn ref disable parallel serial vcc2 rst enb drn4 gat4 channel4 drn ref disable parallel serial vcc2 rst enb drn5 gat5 channel5 drn ref disable parallel serial vcc2 rst enb drn vss rst enb rst rst rst csb rst rst enb figure 1. block diagram
ncv7518 http://onsemi.com 3 drn0 vcc2 gat0 drn1 gat1 vload gat2 drn3 gat3 drn4 gat4 drn5 gat5 vss drn2 so gnd fltref vcc1 in0 in1 in2 in3 in4 in5 csb sclk si fltb vdd rstb cb2 cb1 un clamp ed load v load m +5v enb power-on reset +5v or +3.3v pa ra llel spi irq host controller rst r fpu cb 3 rx1 rx2 reverse battery & transient protection vbat r d0 * r d1 * r d2 * r d3 * r d4 * r d5 * r filt * optional r dx - see application guidelines figure 2. application diagram ncv7518
ncv7518 http://onsemi.com 4 p ackage pin description 32 pin qfn exposed pad package label description fltref analog fault detect threshold: 5 v compliant drn0 ? drn5 analog drain feedback gat0 ? gat5 analog gate drive: 5 v compliant rstb digital master reset input: 3.3 v/5 v (ttl) compatible enb digital master enable input: 3.3 v/5 v (ttl) compatible in0 ? in5 digital parallel input: 3.3 v/5 v (ttl) compatible csb digital chip select input: 3.3 v/5 v (ttl) compatible sclk digital shift clock input: 3.3 v/5 v (ttl) compatible si digital serial data input: 3.3 v/5 v (ttl) compatible so digital serial data output: 3.3 v/5 v compliant fltb digital open-drain output: 3.3 v/5 v compliant vload power supply ? diagnostic references and currents vcc1 power supply ? low power path gnd power return ? low power path ? device substrate vcc2 power supply ? gate drivers vdd power supply ? serial output driver vss power return ? vload, vcc2, vdd ep exposed pad ? connected to gnd ? device substrate figure 3. 32 pin qfn exposed pad pinout (top view) ncv7518
ncv7518 http://onsemi.com 5 maximum ratings (voltages are with respect to device substrate.) rating value unit dc supply ? v load ? 0.3 to 40 v dc supply ? v cc1 , v cc2 , v dd ? 0.3 to 5.8 v difference between v cc1 and v cc2 0.3 v difference between gnd (substrate) and v ss 0.3 v drain input clamp forward voltage transient ( 2 ms, 1% duty) 78 v drain input clamp forward current transient ( 2 ms, 1% duty) 10 ma drain input clamp energy repetitive ( 2 ms, 1% duty) 1.56 mj drain input clamp reverse current v drnx ? 1.0 v ? 50 ma input voltage (any input other than drain) ? 0.3 to 5.8 v output voltage (any output) ? 0.3 to 5.8 v junction temperature, t j ? 40 to 150 c storage temperature, t stg ? 65 to 150 c peak reflow soldering temperature: lead-free 60 to 150 seconds at 217 c (note 1) 260 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. see or download on semiconductor?s soldering and mounting techniques reference manual, solderrm/d. attributes characteristic value esd capability human body model per aec ? q100 ? 002 machine model per aec ? q100 ? 003 drain feedback pins (note 3) all other pins 4.0 kv 2.0 kv 200 v moisture sensitivity (note 2) msl3 package thermal resistance ? still-air junction-to-ambient, r ja junction-to-exposed pad, r jpad (note 4) (note 5) 95 c/w 46 c/w 3.2 c/w 2. see or download on semiconductor?s soldering and mounting techniques reference manual, solderrm/d. 3. with gnd & v ss pins tied together ? path between drain feedback pins and gnd, or between drain feedback pins. 4. based on jesd51 ? 3, 1.2 mm thick fr4, 2s0p pcb, 2 oz. signal, 20 thermal vias to 400 mm 2 spreader on bottom layer. 5. based on jesd51 ? 7, 1.2 mm thick fr4, 1s2p pcb, 2 oz. signal, 20 thermal vias to 80 x 80 mm 1 oz. internal spreader planes. recommended operating conditions symbol parameter min max unit v load diagnostic references and currents power supply voltage 7.5 18.0 v v drnx drain input feedback voltage ? 0.3 60 v v cc1 main power supply voltage 4.75 5.25 v v cc2 gate drivers power supply voltage v cc1 ? 0.3 v cc1 + 0.3 v v dd serial output driver power supply voltage 3.0 v cc1 v v fltref fault detect threshold reference voltage 0.35 2.75 v v in high logic high input voltage 2.0 v cc1 v v in low logic low input voltage 0 0.8 v t a ambient still-air operating temperature ? 40 125 c t reset startup delay at power-on reset (por) (note 6) 500 ? s 6. minimum wait time until device is ready to accept serial input data.
ncv7518 http://onsemi.com 6 parametric tables electrical characteristics (4.75 v v ccx 5.25 v, v dd = v ccx , 4.5 v v load 18 v, rstb = v ccx , enb = 0, ? 40 c t j 150 c, unless otherwise specified.) (note 7) characteristic symbol conditions min typ max unit v cc1 supply operating current ? v cc1 = 5.25 v, v fltref = 2.75 v i cc1a rstb = 0 ? 2.80 5.0 ma i cc1b enb = 0, rstb = v cc1 , v drnx =0 v, gat x drivers off ? 3.10 5.0 ma i cc1c enb = 0, rstb = v cc1 , gat x drivers on ? 2.80 5.0 ma power-on reset threshold por v cc1 rising 3.65 4.125 4.60 v power-on reset hysteresis porh 0.150 0.385 ? v v cc2 supply operating current i cc2 v cc2 = 5.25 v, enb = 0, rstb = v cc1 = 5.25 v v drnx = 0 v, gat x drivers off ? 2.80 5.0 ma v dd supply standby current i dd1 v dd = 5.25v, enb = 0, rstb = v cc1 = 5.25 v so = z ? 25.0 34.0 a operating current i dd2 v dd = 5.25v, enb = 0, rstb = v cc1 = 5.25 v so = h or l ? 625 850 a v load supply standby current v ldsby v load = 13.2 v, 0 v cc1 5.25, enb = rstb = v cc1 , t a 85 c ? ? 5.0 a operating current v ldop v load = 18 v, enb = 0, rstb = v cc1, v drnx = 0 v ? 11 15 ma digital i/o v in high v ihx rstb, enb, in x , si, sclk, csb 2.0 ? ? v v in low v ilx rstb, enb, in x , si, sclk, csb ? ? 0.8 v v in hysteresis in hy rstb, enb, in x , si, sclk, csb 100 330 500 mv input pullup resistance r pux enb, csb, v in = 0 v 50 125 200 k input pulldown resistance r pdx rstb, in x , si, sclk, v in = v cc1 50 125 200 k so low voltage v sol v dd = 3.0 v, i sink = 2 ma ? ? 0.4 v so high voltage v soh v dd = 3.0 v , i source = 2 ma v dd ? 0.6 ? ? v so output resistance r so output high or low ? 25 ? so tri-state leakage current so lkg csb = 3.0 v ? 5.0 ? 5.0 a fltb low voltage v fltb fltb active, i fltb = 1.25 ma ? ? 0.4 v fltb leakage current i fltlkg v fltb = v cc1 ? ? 10 a fault detection ? gatx on fltref input current i fltref 0 v v fltref 2.75 v ? 1.0 ? 1.0 a fltref input linear range v reflin (note 8) 0.35 ? 2.75 v fltref op-amp v cc1 psrr psrr (note 8) 30 ? ? db 7. min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. 8. guaranteed by design.
ncv7518 http://onsemi.com 7 electrical characteristics (continued) (4.75 v v ccx 5.25 v, v dd = v ccx , 4.5 v v load 18 v, rstb = v ccx , enb = 0, ? 40 c t j 150 c, unless otherwise specified.) (note 7) characteristic unit max typ min conditions symbol fault detection ? gatx on drn x shorted load threshold v fltref = 0.35v v 25 register r2.c[11:9] = 000 (default) 20 25 30 % v fltref v 40 register r2.c[11:9] = 001 35 40 45 v 50 register r2.c[11:9] = 010 45 50 55 v 60 register r2.c[11:9] = 011 55 60 65 v 70 register r2.c[11:9] = 100 65 70 75 v 80 register r2.c[11:9] = 101 75 80 85 v 90 register r2.c[11:9] = 110 85 90 95 v 100 register r2.c[11:9] = 111 95 100 105 drn x input leakage current id lkg 0 v v cc1 = v cc2 = v dd 5.25 v, rstb = 0 v, v drnx = 32 v t a 25 c ? 5.0 ? 1.0 ? ? 5.0 1.0 a drn x clamp voltage v cl i drnx = i cl(max) =10 ma; t ransien t ( 2 ms, 1% duty) 60 ? 78 v fault detection ? gatx off (7.5 v v load 18 v, register r3.d[11:0] = 1) drn x diagnostic current ? proportional to v load i sg short to gnd detection, v drnx = 43%v load ? 81 ? 60 ? 39 a / v i ol open load detection, v drnx = 61%v load 2.73 4.20 5.67 a / v i chg transient fast charge current, 0 < v drnx < v ctr , t < t bl(off) ? 270 ? 200 ? 130 a / v diagnostic current limit point v lim current clamped and no longer proportional to v load 20 ? ? v drn x fault threshold voltage v sg short to gnd detection 39.56 43 46.44 %v load v ol open load detection 56.12 61 65.88 %v load drn x off state bias voltage v ctr 46.92 51 55.08 %v load vload undervoltage threshold v lduv vload decreasing 4.1 6.3 7.5 v fault timers channel fault blanking timers (figure 6) t bl(on) v drnx = v load ; in x rising to fltb falling register r2.c[6:5] = 00 4.8 6 7.2 s register r2.c[6:5] = 01 9.6 12 14.4 register r2.c[6:5] = 10 (default) 19.2 24 28.8 register r2.c[6:5] = 11 28.8 48 57.6 t bl(off) v drnx = 0v; in x falling to fltb falling register r2.c[8:7] = 00 44 55 66 s register r2.c[8:7] = 01 65 81 97 register r2.c[8:7] = 10 (default) 130 162 195 register r2.c[8:7] = 11 260 325 390 channel fault filter timer (figure 7) t ff(on) t ff(off) 2.0 44 3.0 55 4.0 66 s global fault retry timer (figure 8) t fr register r0.m[5:0] = 1 6 8 10 ms timer clock f clk rstb = v cc1 ? 4.0 ? mhz 7. min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. 8. guaranteed by design.
ncv7518 http://onsemi.com 8 electrical characteristics (continued) (4.75 v v ccx 5.25 v, v dd = v ccx , 4.5 v v load 18 v, rstb = v ccx , enb = 0, ? 40 c t j 150 c, unless otherwise specified.) (note 7) characteristic unit max typ min conditions symbol gate driver outputs gat x output resistance r gatx output high or low 200 350 500 gat x high output current i gsrc v gatx = 0 v ? 26.25 ? ? 9.5 ma gat x low output current i gsnk v gatx = v cc2 9.5 ? 26.25 ma turn-on propagation delay t p(on) in x to gatx (figure 4) ? ? 1.0 s csb to gat x (figure 5) turn-off propagation delay t p(off) in x to gat x (figure 4) ? ? 1.0 s csb to gat x (figure 5) output rise time t r 20% to 80% of v cc2 , c load = 400 pf (figure 4, note 8) ? ? 277 ns output fall time t f 80% to 20% of v cc2 , c load = 400 pf (figure 4, note 8) ? ? 277 ns serial peripheral interface (figure 9) v ccx = 5.0 v, v dd = 3.3 v, f sclk = 4.0 mhz, c load = 200 pf so supply voltage v dd 3.3 v interface 3.0 3.3 3.6 v 5 v interface 4.5 5.0 5.5 v sclk clock period t sclk ? 250 ? ns maximum input capacitance c inx sl, sclk (note 8) ? ? 12 pf sclk high time t clkh sclk = 2.0 v to 2.0 v 125 ? ? ns sclk low time t clkl sclk = 0.8 v to 0.8 v 125 ? ? ns sl setup time t sisu sl = 0.8 v/2.0 v to sclk = 2.0 v (note 8) 25 ? ? ns sl hold time t sihd sclk = 2.0 v to sl = 0.8 v/2.0 v (note 8) 25 ? ? ns so rise time t sor (20% v so to 80% v dd ) c load = 200 pf (note 8) ? 25 50 ns so fall time t sof (80% v so to 20% v dd ) c load = 200 pf (note 8) ? ? 50 ns csb setup time t csbsu csb = 0.8 v to sclk = 2.0 v (note 8) 60 ? ? ns csb hold time t csbhd sclk = 0.8 v to csb = 2.0 v (note 8) 75 ? ? ns csb to so time t cs ? so csb = 0.8 v to so data valid (note 8) ? 65 125 ns so delay time so dly sclk = 0.8 v to so data valid (note 8) ? 65 125 ns transfer delay time cs dly csb rising edge to next falling edge (note 8) 1.6 ? ? s 7. min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. 8. guaranteed by design. in x gat x t p(off) 80% 20% t r 50% 50% t f t p(on) figure 4. gate driver timing diagram ? parallel input
ncv7518 http://onsemi.com 9 gat x t p(off) 50% csb 50% g x t p(on) figure 5. gate driver timing diagram ? serial input in x 50% drn x 50% fltb 50% t bl(on) t bl(off) figure 6. blanking timing diagram in x shorted load threshold drn x 50% fltb 50% t ff(on) t ff(off) open load threshold figure 7. filter timing diagram in x shorted load threshold (fltref) drn x t bl(on) t ff (on ) gat x t fr t fr t bl(on) t fr figure 8. fault retry timing diagram
ncv7518 http://onsemi.com 10 note: not defined but usually msb of data just received. csb setup csb sclk si so msb in lsb in msb out lsb out see note transfer delay 1 bits 14...1 bits 14...1 16 so delay si setup si hold csb hold so rise,fall 80% v dd 20% v dd csb to so valid figure 9. spi timing diagram detailed operating description general the ncv7518 is a six channel general-purpose low-side pre-driver for controlling and protecting n-type logic level mosfets. programmable fault detection and protection modes allow the device to accommodate a wide range of external mosfets and loads, providing flexible application solutions. separate power supply pins are provided for low and high current paths to improve analog accuracy and digital signal integrity. power up/down control an internal power-on reset (por) monitors v cc1 and causes all gat x outputs to be held low until sufficient voltage is available to allow proper control of the device. all internal registers are initialized to their defaults, status data is cleared, and the open-drain fault flag (fltb) is disabled. when v cc1 exceeds the por threshold, the device is initialized and ready to accept input data. when v cc1 falls below the por threshold during power down, fltb is disabled and all gat x outputs are driven and held low until v cc1 falls below about 1.5 v. rstb and enb inputs the active-low rstb input with a resistive pull-down allows device reset by an external signal. when rstb is brought low, all gat x outputs, the timer clock, the spi, and the fltb flag are disabled. all internal registers are initialized to their default states, status data is cleared, and the spi and fltb are enabled when rstb goes high. the active-low enb input with resistive pull-up provides a global enable. enb disables all gat x outputs and diagnostics, and resets the auto-retry timer when brought high. the spi is enabled, fault data is not cleared and registers remain as programmed. faulted outputs are re-enabled when enb goes low. spi communication the ncv7518 is a 16-bit slave device. communication between the host and the device may either be parallel via individual csb addressing or daisy-chained through other devices using a compatible spi protocol. the active-low csb chip select input has a pull-up resistor. the si and sclk inputs have pull-down resistors. the recommended idle state for sclk is low. the tri-state so line driver is powered via the v dd and the v ss pins, and can be supplied with either 3.3 v or 5 v. the device employs odd parity, and frame error detection that requires integer multiples of 16 sclk cycles during each csb high-low-high cycle (valid communication frame.) a parity or frame error does not affect the fltb flag. the host initiates communication when a selected device?s csb pin goes low. output data is simultaneously sent msb first from the so pin while input data is received msb first at the si pin under synchronous control of the master?s sclk signal while csb is held low (figure 10). output data changes on the falling edge of sclk and is guaranteed valid before the next rising edge of sclk. input data received must be valid before the rising edge of sclk.
ncv7518 http://onsemi.com 11 when csb goes low, frame error detection is initialized, output data is transferred to the spi, and the fltb flag is disabled and reset if previously set. if a valid frame has been received when csb goes high, the last multiple of 16 bits received is decoded into command data, and fltb is re-enabled. the fltb flag will be set if a fault is detected. if a frame or parity error is detected when csb goes high, new command data is ignored, and previous fault data remains latched and available for retrieval during the next valid frame. the fltb flag will be set if a fault (not a frame or parity error) is detected. the interaction between csb and fltb facilitates fault polling. when multiple ncv7518 devices are configured for parallel spi access with individual csb addressing, the device reporting a fault can be identified by pulsing each csb in turn. z z x x csb sclk si so 1 2 3 14 15 16 msb lsb b15 b14 b13 b12 ? b3 b2 b1 b0 ukn b15 b14 b13 b2 b1 b0 note: x=don?t care, z=tri ? state, ukn=unknown data 4 ? 13 b12 ? b3 figure 10. spi communication frame format serial data and register structure the 16-bit data received by the ncv7518 is decoded into a 3-bit address, a 12-bit data word, and an odd parity bit (figure 11). the upper three bits, beginning with the received msb, are fully decoded to address one of eight registers. the valid register addresses are shown in t able 1. the input command structure is shown in table 3. each register is later described in detail. b3 b2 b1 b0 msb lsb b7 b6 b5 b4 b11 b10 b9 b8 b15 b14 b13 b12 b3 b2 b1 b0 msb lsb b7 b6 b5 b4 b11 b10 b9 b8 b15 b14 b13 b12 d3 d2 d1 d0 d7 d6 d5 d4 d11 d10 d9 d8 a2 a1 a0 p d3 d2 d1 d0 d7 d6 d5 d4 d11 d10 d9 d8 a2 a1 a0 p address input data + parity address echo output data + parity figure 11. spi data format
ncv7518 http://onsemi.com 12 table 1. valid register addresses function type alias a2 a1 a0 gate & mode select w r0 0 0 0 diagnostic pulse w r1 0 0 1 diagnostic config 1 w r2 0 1 0 diagnostic config 2 w r3 0 1 1 status ch2:0 r r4 1 0 0 status ch5:3 r r5 1 0 1 revision info r r6 1 1 0 reserved test r7 1 1 1 the 16-bit data sent by the ncv7518 is an echo of the previously received 3-bit address with the remainder of the 12-bit data and parity bit formatted into one of four response types ? an echo of the previously received input data, the diagnostic status information, the device revision information, or a transmission error (table 2). the first response frame sent after reset (via por or rstb) is the device revision information. table 2. output response types echo response a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p address echo input data echo ? diagnostic status response 1 0 0 0 0 enb ch2 ch1 ch0 ch2 ch1 ch0 ch2 ch1 ch0 ? 1 0 1 0 0 enb ch5 ch4 ch3 ch5 ch4 ch3 ch5 ch4 ch3 ? st2 st1 st0 device revision response 1 1 0 0 0 0 0 0 0 d5 d4 d3 d2 d1 d0 ? die revision mask revision transmission error response 1 1 1 0 1 0 1 0 1 0 1 0 1 0 d0 p parity error 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 d0 p frame error 0 1
ncv7518 http://onsemi.com 13 table 3. input command structure overview alias 3-bit addr 12-bit command input data odd parity r0 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 0 0 0 m5 m4 m3 m2 m1 m0 g5 g4 g3 g2 g1 g0 ? gate & mode select 1 = auto retry default = latch off 1 = gatx on default = all off r1 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 0 0 1 f5 f4 f3 f2 f1 f0 n5 n4 n3 n2 n1 n 0 ? diagnostic pulse 1 = diagnostic off pulse default = 0 1 = diagnostic on pulse default = 0 r2 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 0 1 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 ? diagnostic config 1 %vfltref select tblank off tblank on not used channel select r3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 0 1 1 ch5 ch4 ch3 ch2 ch 1 ch 0 ch5 ch 4 ch 3 ch 2 ch 1 ch 0 ? diagnostic config 2 1 = enable fast charge default = disable 1 = enable diagnostic default = enable open load diagnostic enable/disable r4 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 1 0 0 x x x x x x x x x x x x ? diagnostic status ch2:ch0 return enb status; d[9] = 0 = enabled return ch2:ch0 status; default d[8:0] = 1 r5 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 1 0 1 x x x x x x x x x x x x ? diagnostic status ch5:ch3 return enb status; d[9] = 0 = enabled return ch5:ch3 status; default d[8:0] = 1 r6 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 1 1 0 x x x x x x x x x x x x ? revision information return revision information r7 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 1 1 1 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 ? reserved reserved for test mode gate & mode select ? register r0 each gat x output is turned on/off serially by programming its respective g x bit (t able 4). when parallel inputs in x = 0, setting r0.g x = 1 causes the selected gat x output to drive its external mosfet?s gate to v cc2 (on). setting r0.g x = 0 causes the selected gat x output to drive its external mosfet?s gate to v ss (off.) note that the actual state of the output depends on por, rstb, enb and shorted load fault states (shrt x ) as later defined by equation 1. default after reset is r0 . d[11:0] = 0 (all channels latch-off mode, all outputs off.) r0 is an echo type response register. the disable mode for shorted load (on-state) faults is controlled by each channel?s respective m x bit. setting r0 . m x = 0 causes the selected gat x output to latch-off when a fault is detected. setting r0.m x = 1 causes the selected gat x output to auto-retry when a fault is detected. recovery from latch-off is performed for all channels by disabling then re-enabling the device via the enb input. recovery for selected channels is performed by reading the status registers (r4, r5) for the faulted channels then executing a diagnostic on or off pulse for the desired channels.
ncv7518 http://onsemi.com 14 when auto-retry is selected, input changes for turn-on time are ignored while the retry timer is active. once active, the timer will run to completion of the programmed time. the output will follow the input at the end of the retry interval. the timer is reset when enb = 1 or when the mode is changed to latch-off. table 4. gate & mode select register r0 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 0 0 0 m5 m4 m3 m2 m1 m0 g5 g4 g3 g2 g1 g0 ? 1 = auto retry default = latch off 1 = gatx on default = all off diagnostic pulse select ? register r1 the ncv7518 has functionality to perform either on-state or off-state diagnostic pulses (table 5) the function is provided for applications having loads normally in a continuous on or off state. the diagnostic pulse function is available for both latch-off and auto-retry modes. the pulse executes for the selected channel(s) on low-high transition on csb. default after reset is r1 . d[11:0] = 0. r1 is an echo type response register. diagnostic pulses have priority and are not dependant on the input (in x , g x ) or the output (gat x ) states. the pulse does not execute if: enb =1 (device is disabled); both an on and off pulse is simultaneously requested for the same channel; an on or off pulse is requested and a scb (shorted load) diagnostic code is present for the selected channels; an on or off pulse is requested while a pulse is currently executing in the selected channels (i.e. a blanking timer is active); the selected channels are currently under auto-retry control (i.e. refresh timer is active). when r1.f x = 1, the diagnostic off pulse command is executed. the open load diagnostic is turned on if disabled (see diagnostic config 2 ? r3), the output changes state for the programmed t bl(off) blanking period, and the diagnostic status is latched if of higher priority than the previous status. ichg current is turned on if enabled via r3. the output assumes the currently commanded state at the end of the pulse. when r1.n x = 1, the diagnostic on pulse command is executed. the output changes state for the programmed t bl(on) blanking period, and the diagnostic status is latched if of higher priority than the previous status. the output assumes the currently commanded state at the end of the pulse. a flowchart for the diagnostic pulse is given in figure 16. table 5. diagnostic pulse select register r1 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 0 0 1 f5 f4 f3 f2 f1 f0 n5 n4 n3 n2 n1 n 0 ? 1 = diagnostic off pulse default = 0 1 = diagnostic on pulse default = 0 diagnostic config 1 ? register r2 the diagnostic config 1 register programs the turn-on/off blanking time and shorted load fault detection references for each channel (t able 6) bits r2 . c[2:0] select which channels receive the configuration data (table 7). bits r2 . c[8:5] select turn-on/off blanking time (table 8). bits r2 . c[11:9] select the fault reference (table 9). default after reset is indicated by ?(def)? in the tables. r2 is an echo type response register. if a blanking timer is currently running when the register is changed, the new value is accepted but will not take ef fect until the next activation of the timer. table 6. diagnostic config 1 register r2 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 0 1 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 ? %vfltref select tblank off tblank on not used channel select
ncv7518 http://onsemi.com 15 table 7. channel select c2 c1 c0 channel select 0 0 0 none 0 0 1 channel 0 0 1 0 channel 1 0 1 1 channel 2 1 0 0 channel 3 1 0 1 channel 4 1 1 0 channel 5 1 1 1 all (def) table 8. blanking time select c8 c7 c6 c5 c4 c3 tblank off tblank on x x 0 0 6 s 0 1 12 s 1 0 24 s (def) 1 1 48 s 0 0 55 s 0 1 81 s 1 0 162 s (def) 1 1 325 s table 9. fault reference select c11 c1 0 c9 %vfltref select 0 0 0 25 (def) 0 0 1 40 0 1 0 50 0 1 1 60 1 0 0 70 1 0 1 80 1 1 0 90 1 1 1 100 diagnostic config 2 ? register r3 off-state open load diagnostic currents for each channel can be enabled or disabled for led loads. short to gnd diagnostic is unaffected. fast charge current (ichg) can be enabled or disabled for capacitive loads. channels are selected by bit positions in the register (t able 10.) open load status (olf) information is suppressed when the diagnostic is turned off via r3. open load diagnostic and olf status is temporarily enabled when a diagnostic off pulse is executed via r1. default after reset is r3 . d[11:6] = 0 and r3 . d[5:0] = 1. r3 is an echo type response register.
ncv7518 http://onsemi.com 16 table 10. diagnostic config 2 register r3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 0 1 1 ch5 ch4 ch3 ch2 ch1 ch 0 ch5 ch4 ch3 ch2 ch1 ch 0 ? 1 = enable fast charge default = disable 1 = enable diagnostic default = enable open load diagnostic enable/disable diagnostic status registers ? register r4 & r5 diagnostic status and enb status information is returned when r4 or r5 is selected (table 11) diagnostic status information for each channel is 3-bit (st2:0) priority encoded (table 12). bit d[9] returns the state of the enb input e.g. d[9] = 0 when enb = 0 (enabled). default response after reset or spi read is d[8:0] = 1 (?diagnostic not complete?). table 11. diagnostic status registers a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p r4 1 0 0 x x x x x x x x x x x x ? si 1 0 0 0 0 enb ch2 ch1 ch0 ch2 ch1 ch0 ch2 ch1 ch0 ? so r5 1 0 1 x x x x x x x x x x x x ? si 1 0 1 0 0 enb ch5 ch4 ch3 ch5 ch4 ch3 ch5 ch4 ch3 ? so st2 st1 st0 table 12. diagnostic status encoding st2 st1 st0 status priority 0 0 0 invalid ? 0 0 1 scb ? short to battery 1 highest 0 1 0 scg ? short to ground 2 0 1 1 olf ? open load 3 (note) 1 0 0 diagnostic complete ? no fault 4 1 0 1 no scb fault ? on state 5 1 1 0 no scg/olf fault ? off state 6 1 1 1 diagnostic not complete (default) 7 lowest note: olf status report is suppressed when open load diagnostic is turned off via diagnostic config 2 ? register r3 status is latched for the currently higher priority fault and is not demoted if a fault of lower priority occurs. the status registers are reset to ?diagnostic not complete? after reading the registers, or by asserting a reset via rstb. status registers are not affected by enb. revision information ? register r6 device revision information is returned when r6 is selected (table 13). output bits d[11:6] are hard coded to 0, bits d[5:3] are hard coded with the die (silicon) revision, and bits d[2:0] are hard coded with the mask (interconnect) revision. the first response frame sent after reset is the device revision information. the revision encoding scheme is shown in table 14. mask revision may be incremented when an interconnect revision is made. die revision is incremented when a silicon revision is made. mask revision is reset to ?000? when a die revision is made. table 13. device revision information r6 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 1 1 0 x x x x x x x x x x x x ? si 1 1 0 0 0 0 0 0 0 d5 d4 d3 d2 d1 d0 ? so die rev mask rev
ncv7518 http://onsemi.com 17 table 14. device revision encoding d5 d4 d3 d2 d1 d0 die rev mask rev 0 0 0 a 0 0 0 0 0 0 1 b 0 0 1 1 0 1 0 c 0 1 0 2 0 1 1 d 0 1 1 3 1 0 0 e 1 0 0 4 1 0 1 f 1 0 1 5 1 1 0 g 1 1 0 6 1 1 1 h 1 1 1 7 reserved ? register r7 register r7 is reserved for factory test use. data sent to r7 is ignored. in normal operation, r7 is an echo type response register. in the event of a transmission error, r7 responds with either a parity or frame error on the next valid frame. table 15. test mode register r7 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p 1 1 1 x x x x x x x x x x x x ? si echo input data echo ? so parity err 0 1 0 1 0 1 0 1 0 1 0 1 0 so frame err 0 1 0 1 0 1 0 1 0 1 0 0 1 so gate driver control and enable each gat x output may be turned on by either its respective parallel in x input or the gate & mode select register bits r0.g[5:0] via spi communication. the device?s rstb reset and enb enable inputs can be used to implement global control functions, such as system reset, over-voltage or input override by a watchdog controller. the rstb input has an internal pull-down resistor and the enb input has an internal pull-up resistor. each parallel input has an internal pull-down resistor. parallel input is recommended when low frequency ( 10 khz) pwm operation of the outputs is desired. unused parallel inputs should be connected to gnd. when rstb is brought low, all gat x outputs, the timer clock, the spi, and the fltb flag are disabled. all internal registers are initialized to their default states, status data is cleared, and the spi and fltb are enabled when rstb goes high. enb disables all gat x outputs and diagnostics, and resets the auto-retry timer when brought high. the spi is enabled, fault data is not cleared and registers remain as programmed. faulted outputs are re-enabled when enb goes low. the in x input state and the g x register bit data are logically combined with the internal (active low) power-on reset signal (por), the rstb and enb input states, and the shorted load state (internal shrt x ) to control the corresponding gat x output such that: gat x por rstb enb shrt x in x g x (eq. 1) the gat x state truth table is given in table 16.
ncv7518 http://onsemi.com 18 table 16. gate driver truth table por rstb enb shrt x in x g x gat x 0 x x x x x l 1 0 x x x x l 1 1 1 x x x l 1 1 0 1 0 0 l 1 1 0 1 1 x h 1 1 0 1 x 1 h 1 1 0 0 x x l 1 1 0 1 x x g x l 1 1 1 0 1 0 g x g x 1 1 0 x x x 0 l gate drivers the non-inverting gat x drivers are symmetrical resistive switches (350 typ.) to the vcc2 and vss voltages. while the outputs are designed to provide symmetrical gate drive to an external mosfet, load current switching symmetry is dependent on the characteristics of the external mosfet and its load. figure 12 shows the gate driver block diagram. driver vcc2 vss filter timer latch off / auto re ? try drn x gat x fault detection stx[2:0] r2.c[4:3] blanking timer encoding logic en shrt x 350 r0.m[ x] rstb enb por diagnostic pulse en g x in x r1.f|n[x] r2.c[8:5] r2.c[11:9] vss r3.d[x,x+6] figure 12. gate driver channel blanking and filter timers blanking timers are used to allow drain feedback to stabilize after a channel is commanded to change states. filter timers are used to suppress glitches while a channel is in a stable state. a turn-on blanking timer is started when a channel is commanded on. drain feedback is sampled after t bl(on) . a turn-off blanking timer is started when a channel is commanded off. drain feedback is sampled after t bl(off) . a filter timer is started when a channel is in a stable state and a fault detection threshold associated with that state has been crossed. drain feedback is sampled after t ff(on|off) . a filter timer may also be started while a blanking timer is active, so the blanking interval could be extended by the filter time. each channel has independent blanking and filter timers. the parameters for the t ff(on|off) filter timer are the same for all channels. the turn-on/off blanking time for each channel can be selected via the diagnostic config 1 register bits r2 . c[8:5] (tables 6 and 8). if a blanking timer is currently running when the register is changed, the new value is accepted but will not take ef fect until the next activation of the timer. blanking timers for all channels are started when both rstb goes high and enb goes low, when rstb goes high while enb is low, when enb goes low while rstb is high, or by por. fault diagnostics and behavior each channel has independent fault diagnostics and employs blanking and filter timers to suppress false faults. an external mosfet is monitored for fault conditions by connecting its drain to a channel?s drn x feedback input through an optional external series resistor. shorted load (or short to v load ) faults can be detected when a driver is on. open load or short to gnd faults can be detected when a driver is off. on-state faults will initiate mosfet protection behavior, set the fltb flag and the respective channel?s status bits in
ncv7518 http://onsemi.com 19 the device?s status registers. off-state faults will simply set the fltb flag and the channel?s status bits. status information is retrieved by spi read of registers r4 and r5 (table 11). status information for each channel is 3-bit priority encoded (table 12). shorted load fault has priority over open load and short to gnd. short to gnd has priority over open load. priority ensures that the most severe fault data is available at the next spi read. status is latched for the currently higher priority fault and is not demoted if a fault of lower priority occurs. the status registers are reset to ?diagnostic not complete? after reading the registers, or by asserting a reset via rstb. status registers are not affected by enb. when either rstb is low or enb is high, diagnostics are disabled. when rstb is high and enb is low, open load diagnostics are enabled according to the state of the diagnostic config 2 register bits r3 . d[5:0] (table 10). diagnostic pulse mode the ncv7518 has functionality to perform either on-state or off-state diagnostic pulses (table 5). the function is provided for applications having loads normally in a continuous on or off state. the diagnostic pulse function is available for both latch-off and auto-retry modes. the pulse executes for the selected channel(s) on low-high transition on csb. diagnostic pulses have priority and are not dependant on the input (in x , g x ) or the output (gat x ) states. the pulse does not execute if: enb =1 (device is disabled); both an on and off pulse is simultaneously requested for the same channel; an on or off pulse is requested and a scb (shorted load) diagnostic code is present for the selected channels; an on or off pulse is requested while a pulse is currently executing in the selected channels (i.e. a blanking timer is active); the selected channels are currently under auto-retry control (i.e. refresh timer is active). when r1.f x = 1, the diagnostic off pulse command is executed. the open load diagnostic is turned on if disabled (see diagnostic config 2 ? r3), the output changes state for the programmed t bl(off) blanking period, and the diagnostic status is latched if of higher priority than the previous status. ichg current is turned on if enabled via r3. the output assumes the currently commanded state at the end of the pulse. when r1.n x = 1, the diagnostic on pulse command is executed. the output changes state for the programmed t bl(on) blanking period, and the diagnostic status is latched if of higher priority than the previous status. the output assumes the currently commanded state at the end of the pulse. a flowchart for the diagnostic pulse is given in figure 16. shorted load detection an external reference voltage applied to the fltref input serves as a common reference for all channels (figures 1 and 2). the fltref voltage should be within the range of 0.35 to 2.75 v and can be derived via a voltage divider between v cc1 and gnd. shorted load detection thresholds can be programmed via spi in eight increments that are ratiometric to the applied fltref voltage. separate thresholds can be selected for each channel via the diagnostic config 1 register bits r2 . c[11:9] (tables 6 and 9). a shorted load fault is detected when a channel?s drn x feedback is greater than its selected fault reference after either the turn-on blanking or the filter has timed out. shorted load fault disable and recovery shorted load fault disable mode for each channel is individually spi programmable via the device?s gate & mode select register bits r0 . m[5:0] (table 4). when latch-off mode (default) is selected, the corresponding gat x output is latched off upon detection of a fault. recovery from latch-off is performed for all channels by disabling then re-enabling the device via the enb input. recovery for selected channels is performed by reading the status registers (r4, r5) for the faulted channels then executing a diagnostic on or off pulse for the desired channels. when auto-retry mode is selected the corresponding gat x output is turned off upon detection of a fault for the duration of the fault retry time (t fr ). when auto-retry is selected, input changes for turn-on blanking time are ignored while the retry timer is active. once active, the timer will run to completion of the programmed time. the output will follow the input at the end of the retry interval. the timer is reset when enb = 1 or when the mode is changed to latch-off. the output is automatically turned back on (if still commanded on) when the retry time ends. the channel?s drn x feedback is re-sampled after the turn-on blanking time. the output will automatically be turned off if a fault is again detected. this behavior will continue for as long as the channel is commanded on and the fault persists. in either mode, a fault may exist at turn-on or may occur some time afterward. to be detected, the fault must exist longer than either t bl(on) at turn-on or longer than t ff(on) some time after turn-on. the length of time that a mosfet stays on during a shorted load fault is thus limited to either t bl(on) or t ff(on) . recovery retry time a global retry timer is used for auto-retry timing. the first faulted channel triggers the timer and the full retry time is guaranteed for that channel. an additional faulted channel may initially retry immediately after its turn-on blanking time, but subsequent retries will have the full retry time. if all channels become faulted, they will become synchronized to the global retry timer.
ncv7518 http://onsemi.com 20 open load and short to gnd detection a window comparator with references and bias currents proportional to v load is used to detect open load or short to gnd faults when a channel is off. each channel?s drn x feedback is compared to the references after either the turn-off blanking or the filter has timed out. figure 13 shows the drnx bias and fault detection zones. v ctr v sg v ol -i sg i ol 0 v drnx i drnx open load short to gnd no fault figure 13. drn x bias and fault detection zones no fault is detected if the feedback voltage at drn x is greater than the v ol open load reference. if the feedback is less than the v sg short to gnd reference, a short to gnd fault is detected. if the feedback is less than v ol and greater than v sg , an open load fault is detected. when either rstb is low or enb is high, diagnostics are disabled. when rstb is high and enb is low, off-state diagnostics are enabled according to the content of the diagnostic config 2 register bits r3 . d[11:0] (tables 10 and 17.) table 17. open load diagnostic control (ch0 shown) d6 d0 ichg current open load diagnostic x 0 off x 1 on (def) 0 x off (def) 1 x on figure 14 shows the simplified detection circuitry. bias currents i sg and i ol are applied to a bridge along with bias voltage v ctr . transient fast charge current i chg is supplied to help charge any capacitance present at the drnx node to suppress a false short to gnd fault. b ? + cmp2 i ol ? + cmp1 v ctr v ol vload a v ld (v cl ) drn x r dx r ld r sg v x i sg d1 d2 d3 d4 dz1 v sg v os r4 r3 r2 r1 ? + oa i chg d5 rstb vbat dx1 s4 s2 s1 s5 s3 control logic enb t bl(off) r3.d[6,0] c esd r1.d[6,0] figure 14. short to gnd/open-load detection the transient current is started when a channel?s turn-off blanking time is started and terminated either when the drnx voltage reaches v ctr or when the turn-off blanking time t bl(off) expires. v drnx will remain at v ctr if an open load truly exists, otherwise the capacitance can continue to charge via r ld. when a channel is off and v ld and r ld are present, r sg is absent, and v drnx >> v ctr , bias current i ol is supplied from v ld to ground through resistors r ld and optional r dx , and bridge diode d2. bias current i sg is supplied from v load to v ctr through d3. no fault is detected if the feedback voltage (v ld minus the total voltage drop caused by i ol and the resistance in the path) is greater than v ol . when r sg and either v ld or r ld are absent, the bridge will self-bias so that v drnx will settle to about v ctr . an open load fault can be detected since the feedback is between v sg and v ol . short to gnd detection can tolerate up to a 1.0 v offset (v os ) between the ncv7518?s gnd and the short. when r sg is present and v drnx << v ctr , bias current i sg is supplied from v load to v os through d1, and the r sg and optional r dx resistances. bias current i ol is supplied from v ctr to ground through d4. when v ld and r ld are present, a voltage divider between v ld and v os is formed by r ld and r sg . a ?soft? short to
ncv7518 http://onsemi.com 21 gnd may be detected in this case depending on the ratio of r ld and r sg and the values of r dx , v ld , and v os . optional r dx resistor is used when voltages greater than the 60 v minimum clamp voltage or down to ? 1 v are expected at the drnx inputs. note that the comparators see a voltage drop or rise due to the r dx resistance and the bias currents. this produces an error in the comparison of feedback voltage at the comparator inputs to the actual node voltage v x . several equations for choosing r dx and for predicting open load or short to gnd resistances, and a discussion of the dynamic behavior of the short to gnd/ open load diagnostic are provided in the ?application guidelines? section of this data sheet. fault flag (fltb) the open-drain active-low fault flag output can be used to provide immediate fault notification to a host controller. fault detection from all channels is logically ored to the flag (figure 15) the fltb outputs from several devices can be wire-ored to a common pull-up resistor connected to the controller?s 3.3 or 5 v v dd supply. when rstb and csb are high, and enb is low, the flag is set (low) when any channel detects any fault. the flag is reset (hi-z) and disabled during por, when either rstb or csb is low, or when enb is high. see table 18 for details. other channels fltb fault x por enb csb rstb figure 15. fltb flag logic the interaction between csb and fltb facilitates fault polling. when multiple ncv7518 devices are configured for parallel spi access with individual csb addressing, the device reporting a fault can be identified by pulsing each csb in turn. fault detection and capture each channel of the ncv7518 is capable of detecting shorted load faults when the channel is on, and short to ground or open load faults when the channel is off. each fault type is priority encoded into 3-bit per channel fault data (table 12.) shorted load fault data has priority over open load and short to gnd data. short to gnd data has priority over open load data. priority ensures that the most severe fault data is available at the next spi read. a drain feedback input for each channel compares the voltage at the drain of the channel?s external mosfet to several internal reference voltages. separate detection references are used to distinguish the three fault types. blanking and filter timers are used respectively to allow for output state transition settling and for glitch suppression. when enabled and configured, each channel?s drain feedback input is continuously compared to references appropriate to the channel?s input state to detect faults, but the comparison result is only latched at the end of either a blanking or filter timer event. blanking timers for all channels are started when both rstb goes high and enb goes low, when rstb goes high while enb is low, when enb goes low while rstb is high, or by por. a single channel?s blanking timer is triggered when its input state changes. if the comparison of the feedback to a reference indicates an abnormal condition when the blanking time ends, a fault has been detected and the fault data is latched into the channel?s status register. a channel?s filter timer is triggered when its drain feedback comparison state changes. if the change indicates an abnormal condition when the filter time ends, a fault has been detected and the fault data is latched into the channel?s status register. thus, a state change of the inputs (por, rstb, enb, in x or g x ) or a state change of an individual channel?s feedback (drn x ) comparison must occur for a timer to be triggered and a detected fault to be captured. fault capture, spi communication, and spi frame error detection the ncv7518 latches a fault when it is detected, and parity and frame error detection will not allow any register to accept data if an invalid frame occurred. the fault capture, parity, and frame error detection strategies combine to ensure that intermittent faults can be captured and identified, and that the device cannot be inadvertently re-programmed by a communication error. when a fault has been detected, status information is latched into a channel?s status register if of higher priority than current status, and the fltb flag is set. the register holds the status data and ignores subsequent lower priority status data for that channel. current status information is transferred from the selected status register into the spi shift register at the start of the spi frame following the read status request. this ensures that status updates continue during inter-frame latency between the status request and delivery. the fltb flag is reset when csb goes low. the selected status register is cleared when csb goes high at the end of the spi frame only if a valid frame has occurred; otherwise the register retains status information until a valid read frame occurs. the fltb flag will be set if a fault is still present. status registers and the fltb flag can also be cleared by toggling rstb h l h. a full i/o truth table is given in table 18. status priority encoding shorted load (scb) faults can be detected when a driver is on. open load (olf) or short to gnd (scg) faults can
ncv7518 http://onsemi.com 22 be detected when a driver is off. status memory is priority encoded in a 3-bit per driver format (table 12). status memory will be encoded ?diagnostic not complete? during a blanking period unless a fault of higher priority has previously been encoded. status memory will be encoded ?diagnostic not complete? (cleared) for the selected status register at the end of a valid spi frame. ?diagnostic complete ? no fault? will be encoded when both on-state and off-state diagnostics have been completed unless a fault of higher priority has previously been encoded. a diagnostic cycle may start from either an off-state or an on-state. when a diagnostic cycle starts from an off-state and no fault is detected, ?no scg/olf fault? will be encoded unless a fault of higher priority has previously been encoded. otherwise, ?olf? or ?scg? will be encoded unless a fault of higher priority has previously been encoded. if the cycle continues to an on-state and no fault is detected, ?diagnostic complete ? no fault? will be encoded. otherwise, ?scb? will be encoded. when a diagnostic cycle starts from an on-state and no fault is detected, ?no scb fault? will be encoded unless a fault of higher priority has previously been encoded. otherwise, ?scb? will be encoded. if the cycle continues to an off-state and no fault is detected, ?diagnostic complete ? no fault? will be encoded unless a fault of higher priority has previously been encoded. otherwise, ?olf? or ?scg? will be encoded unless a fault of higher priority has previously been encoded. status is latched for the currently higher priority fault and is not demoted if a fault of lower priority occurs. the status registers are reset to ?diagnostic not complete? after reading the registers, or by asserting a reset via rstb. status registers are not affected by enb. a statechart diagram of the diagnostic status encoding is given in figure 17 and additional clarification is given in ?appendix a ? diagnostic and protection behavior tutorial?. vload undervoltage detection undervoltage detection is used to suppress off-state diagnostics when vload falls below the specified vlduv operating voltage. this ensures that potentially incorrect diagnostic status is not captured. on-state diagnostics continue to operate normally and status information is updated appropriately for an off-to-on input transition during undervoltage. previous status information and fltb are unchanged when entering or leaving undervoltage. upon a read of the status registers during undervoltage, the status is changed to ?diagnostic not complete? and will remain as such for channels in an off-state during the entire undervoltage interval. status information and fltb are updated appropriately if a channel changes from off to on during the interval. when vload returns to its normal operating range, a channel?s t bl(off) blanking timer is started if the channel was in an off state. status information is updated appropriately after the t bl(off) blanking interval, or after the t ff(off) filter interval if the filter has been activated.
ncv7518 http://onsemi.com 23 on or off pulse request device enabled ? both on & off request ? scb code present ? currently executing* ? on pulse request ? *a blanking or refresh timer is currently running for the selected channel enable open load execute on pulse open load enabled ? execute off pulse disable open load* execute off pulse end end yes yes yes no yes yes * don?t disable if a spi access to r3.d[5:0] occurred during the pulse to enable the channel?s diagnostic. 3/11 /2010 figure 16. pulse mode diagnostic flowchart
ncv7518 http://onsemi.com 24 { if no scb and no scg/olf} diag not complete 111 no scg/olf 110 no scb 101 diag complete no faults 100 open load (olf) 011 short to gnd (scg) 010 shorted load (scb) 001 reset enb = 1 or vload uv and (inx and gx=0) read status or reset figure 17. diagnostic status encoding statechart
ncv7518 http://onsemi.com 25 table 18. i/o truth table inputs outputs* por rstb enb csb in x g x drn x gat x fltb st[2:0] comment 0 x x x x 0 x l z 111 por reset 1 0 x x x x x l z 111 rstb 1 1 1 x x g x x l z st[2:0] enb 1 1 0 0 x x 0 x l z 111 rstb reset 1 1 0 1 x x g x x l z st[2:0] enb disable 1 1 0 x 0 0 > v ol l z st[2:0] fltb reset 1 1 0 1 0 0 v sg < v < v ol l l 011 fltb set ? olf 1 1 0 1 0 0 0 v sg < v < v ol l l z 011 fltb reset 1 1 0 0 1 0 0 v sg < v < v ol l z l 011 fltb set 1 1 0 1 0 0 < v sg l l 010 fltb set ? scg 1 1 0 1 0 0 0 < v sg l l z 010 fltb reset 1 1 0 0 1 0 0 < v sg l z l 010 fltb set 1 1 0 x 1 x < v fltref h z st[2:0] fltb reset 1 1 0 1 1 x > v fltref l l 001 fltb set ? scb 1 1 0 1 0 1 x > v fltref l l z 001 fltb reset 1 1 0 0 1 1 x > v fltref l z l 001 fltb set 1 1 0 1 x 1 < v fltref h z st[2:0] fltb reset 1 1 0 1 x 1 > v fltref l l 001 fltb set ? scb 1 1 0 1 0 x 1 > v fltref l l z 001 fltb reset 1 1 0 0 1 x 1 > v fltref l z l 001 fltb set *output states after blanking and filter timers end and when channel is set to latch-off mode. application guidelines general unused drn x inputs should be connected to v load to prevent false open load faults. unused parallel inputs should be connected to gnd and unused reset or enable inputs should be connected to v cc1 or gnd respectively. the user?s software should be designed to ignore fault information for unused channels. for best shorted-load detection accuracy , the external mosfet source terminals should be star -connected and the ncv7518? s gnd pin, and the lower resistor in the fault reference voltage divider should be kelvin connected to the star (see figure 2). consideration of auto-retry fault recovery behavior is necessary from a power dissipation viewpoint (for both the ncv7518 and the mosfets) and also from an emi viewpoint. driver slew rate and turn-on/off symmetry can be adjusted externally to the ncv7518 in each channel?s gate circuit by the use of series resistors for slew control, or resistors and diodes for symmetry. any benefit of emi reduction by this method comes at the expense of increased switching losses in the mosfets. the channel fault blanking timers must be considered when choosing external components (mosfets, slew control resistors, etc.) to avoid false faults. component choices must ensure that gate circuit char ge/discharge times stay within the turn-on/turn-off blanking times. the ncv7518 does not have integral drain-gate flyback clamps. self-clamped mosfet products, such as on semiconductor?s nif9n05cl or ncv8440a devices, are recommended when driving unclamped inductive loads. this flexibility allows choice of mosfet clamp voltages suitable to each application.
ncv7518 http://onsemi.com 26 appendix a ? diagnostic and protection behavior tutorial the following tutorial can be used together with table 19 and the statechart of figure 17 to further understand how diagnostic status information is updated. initial conditions: ? vcc1 > v(por) and rstb = 1 ? digital core is disabled if these conditions are not valid ? vcc2 present and in specified range ? vload present and in specified range on-state diagnostic: ? scb ? short circuit to battery ? qualifiers: ? vfltref present and in specified range ? inx or gx = 1 and enb 1 0 ? enb = 0 and inx or gx 0 1 ? enb = 0 and on-state diagnostic pulse request ? blanking and/or filter timer ran till end ?diagnostic complete? off-state diagnostic: ? olf/scg ? open load fault / short circuit to gnd ? qualifiers: ? vload present and in specified range ? inx and gx = 0 and enb 1 0 ? enb = 0 and inx 1 0 and gx = 0 ? enb = 0 and inx = 0 and gx 1 0 ? enb = 0 and off-state diagnostic pulse request ? blanking and/or filter timer ran till end ?diagnostic complete? transition trigger events: ? diagnostic status can transition from one state to another by several trigger events: ? on and/or off state diagnostic completed ? spi read of the status register(s) ? recovery from vload undervoltage detected ? reset via por or rstb table 19. diagnostic state transitions entering state description entering criteria exiting criteria exiting state 001 [scb] ? short circuit to battery scb detected read 111 010 [scg] ? short circuit to ground scg detected scb detected read 001 111 011 [olf] ? open load failure olf detected scb detected scg detected read 001 010 111 100 diagnostic complete ? no fault off state no fault and on state no fault scb detected scg detected olf detected read 001 010 011 111 101 no scb detected on state no fault scb detected scg detected olf detected off state no fault read 001 010 011 100 111 110 no scg/olf detected off state no fault scb detected scg detected olf detected on state no fault read 001 010 011 100 111 111 diagnostic not complete read scb detected & enb = 0 scg detected & enb = 0, vload > vlduv olf detected & enb = 0, vload > vlduv on state no fault & enb = 0 off state no fault & enb = 0, vload > vlduv 001 010 011 101 110 diagnostic status and protection interactions the following figures are graphical representations of some interactions between diagnostics and protections. the following assumptions apply: ? enb = 0 ? spi response is shown in-frame ? actual ncv7518 response is one frame behind ? spi frames are always valid ? integer multiples of 16 sclk cycles ? no parity errors
ncv7518 http://onsemi.com 27 so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx fltref 0 vbat vol diag status blank timer filter timer 111 rstb 0 1 internal signals 101 vol vsg t bl(off ) t bl(on) 110 100 100 110 diag not complete no scb fault no fault no scg/olf fault start on normal cycle1 111 111 110 110 figure 18. normal start-up out of reset with input high ? diagnostics complete, no fault so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx fltref 0 vbat vol diag status blank timer filter timer 111 rstb 0 1 internal signals vol vsg t bl(off ) 110 110 110 diag not complete no scg/olf fault no scg/olf fault start on normal cycle 2 111 111 110 110 t bl(on ) truncated figure 19. normal start-up out of reset with input high, tbl(on) truncated ? scb not checked
ncv7518 http://onsemi.com 28 so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx vsg 0 vbat vol diag status blank timer filter timer 111 rstb 0 1 internal signals 110 vol 101 100 100 101 111 t bl(on ) t bl(off ) fltref diag not complete no scb fault no fault no scg/olf fault start off normal cycle 1 111 101 101 figure 20. normal start-up out of reset with input low ? diagnostics complete, no fault so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx vsg 0 vbat vol diag status blank timer filter timer 111 rstb 0 1 internal signals 101 vol 101 101 111 t bl(on ) t bl(off ) fltref diag not complete no scb fault no scb fault start off normal cycle 2 111 101 101 truncated figure 21. normal start-up out of reset with input low, tbl(off) truncated ? scg/olf not checked
ncv7518 http://onsemi.com 29 so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx fltref 0 vbat diag status blank timer filter timer 100 rstb 0 1 internal signals 001 101 001 100 diag not complete scb fault no fault t ff(on) no fault 111 vol no scb fault on pulse req 110 scb latch & clear 1 echo truncated t bl(off) don?t care t bl(on) t bl(on) vol vsg t bl(off) figure 22. scb latch-off & recovery ? read status & request on pulse so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx fltref 0 vbat diag status blank timer filter timer 100 rstb 0 1 internal signals 001 110 001 100 diag not complete scb fault no fault t ff(on) no fault 111 vol no scg/olf fault t bl(off) t bl(on) off pulse req don?t care scb latch & clear 2 vol vsg fltref echo 101 figure 23. scb latch-off & recovery ? read status & request off pulse
ncv7518 http://onsemi.com 30 so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx fltref 0 vbat diag status blank/ refresh timer filter timer 100 rstb 0 1 internal signals 001 001 001 diag not complete scb fault t ff(on) no fault 111 vol scb fault on/off pulse req ignored during retry don?t care retry 1 t bl(on) t fr echo t fr vol vsg t ff(on) figure 24. auto-retry timer started, inx went low during second retry ? retry timer runs to completion so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx fltref 0 vbat diag status blank/ refresh timer filter timer 100 rstb 0 1 internal signals 001 001 001 diag not complete scb fault t ff(on ) no fault 111 vol scb fault on/off pulse req ignored during retry don?t care retry 2 t bl(on ) t fr echo t fr vol vsg 001 not complete 111 110 no scg/olf figure 25. auto-retry timer started, inx went low during second retry ? retry timer runs to completion status read clears scb, allows off-state status update
ncv7518 http://onsemi.com 31 so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx vsg 0 vbat diag status blank timer filter timer rstb 0 1 internal signals 111 100 echo no scb fault 101 vol no fault t bl(off ) vol vsg t bl(on) on or off pulse req ignored during t bl(on|off) don?t care on pulse req echo fltref diag not complete 110 off blank started to allow drain to settle pulse 1 figure 26. normal on pulse request & second request ignored ? inx remains in low state at end of pulse so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx vsg 0 vbat diag status blank timer filter timer rstb 0 1 internal signals 111 101 echo no scb fault vol t bl(on ) on pulse req echo fltref diag not complete echo on pulse req t bl(on) t bl(off ) off pulse req echo t bl(on ) 110 100 no fault 111 status req 100 101 no scb fault blanking not re ? started on blank started to allow drain to settle pulse 2 on or off pulse req ignored figure 27. normal on pulse request & second request ignored ? inx state change during first pulse execution, normal off pulse request
ncv7518 http://onsemi.com 32 so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx vsg 0 vbat diag status blank timer filter timer rstb 0 1 internal signals 111 101 echo no scb fault vol t bl(on) on pulse req echo fltref diag not complete echo on pulse req t bl(on) t bl(off) on or off pulse req ignored echo t bl(on) 110 100 no fault 111 status req 100 101 no scb fault blanking not re ? started pulse 2a on or off pulse req ignored off blank started to allow drain to settle figure 28. normal on pulse request & second request ignored, normal on pulse request, inx state change during normal pulse executions so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx vsg 0 vbat diag status blank timer filter timer rstb 0 1 internal signals 111 101 echo no scb fault vol t bl(on ) don?t care on pulse req echo fltref diag not complete echo on pulse req t bl(on) t bl(off ) off pulse req echo 110 100 no fault 111 status req 100 110 no scg/olf fault pulse 3 on or off pulse req ignored on blank not started (off state) off blank not started (on state) figure 29. normal on pulse request & second request ignored, normal off pulse request, inx state change during normal pulse executions and goes low during off pulse
ncv7518 http://onsemi.com 33 so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx vsg 0 vbat vol diag status blank timer filter timer rstb 0 1 internal signals scb diag not complete fltref previous data t bl(on) t ff(on ) t ff(on) t< t ff(on) scb t bl(off ) vsg fltref on blank & filter & scb t bl(off ) vsg 111 111 no scg/olf fault figure 30. filter timer started during blank timer because of intermittent scb, re-started just before end of blank timer ? scb latch-off time extended so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 drnx fltref 0 vbat vol diag status blank timer filter timer rstb 0 1 internal signals olf no scb fault previous data t bl(off ) olf t bl(on ) off blank & filter & flt vsg t ff(off ) t ff(off ) t ff(off ) scg olf olf fltref 111 figure 31. filter timer started when falling through olf threshold during blank timer, re-started when falling through scg threshold, re-started when falling through olf threshold ? off-state diagnostic status acquisition time extended by filter timer
ncv7518 http://onsemi.com 34 so fltb inx 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 vload 0 vbat diag status blank timer filter timer vlduv 0 1 internal signals previous data valid on state data status vld uv t bl(on) read status t bl(off) drnx 0 vbat diagnostic not complete vlduv 1 111 valid on state data status read status figure 32. off-state diagnostic status is suppressed while in vload undervoltage ? on-state diagnostics remain functional so fltb inx 0 1 0 1 0 1 0 1 csb 0 1 0 1 0 1 vload 0 vbat diag status blank timer filter timer vlduv 0 1 internal signals previous data status vld uv read status t bl(off) drnx 0 vbat diagnostic not complete t bl(off) valid off state diagnostic vlduv 2 figure 33. off-state diagnostic starts when recovery from undervoltage occurs
ncv7518 http://onsemi.com 35 package dimensions case 485cz issue o seating 0.15 c (a3) a a1 b 1 32 32x l 32x bottom view top view side view d a b e 0.15 c pin one reference 0.10 c 0.08 c c e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 0.90 a1 ??? 0.05 a3 0.20 ref b 0.20 0.30 d 5.00 bsc d2 3.20 3.40 e 5.00 bsc 3.40 e2 3.20 e 0.50 bsc l 0.30 0.50 l1 ??? 0.15 plane soldering footprint note 4 e2 d2 note 3 detail a dimensions: millimeters 5.30 3.60 3.60 0.50 0.62 0.30 32x 32x pitch 5.30 pkg outline recommended 8 e/2 9 24 a m 0.10 b c m m a m 0.10 b c l1 detail a l alternate terminal constructions l detail b (0.15) (0.10) alternate construction l detail b on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncv7518/d flexmos is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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