View KT0801A_7734932.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KT0801A monolithic digital stereo fm transmitter radio-station-on-a-chip? ? features hardware and software compatible with kt0801 additional features to kt0801 increased transmission power support input clock and external crystal: 32.768khz, 7.6mhz, 15.2mhz input signal detection bass control professional grade performance: snr 60 db stereo separation > 40 db international compatible 76mhz ~ 108mhz ultra-low power consumption: < 17 ma operation current < 3 a standby current small form factor: 24-pin qfn simple interface: single power supply industry standard 2-wire i 2 c mcu interface compatible advanced digital audio signal processing: on-chip 20-bit ? audio adc on-chip dsp core on-chip 24db pga with optional 1db step automatic calibration against process and temperature on-chip ldo (low-drop-out) regulator: accommodates 1.6v ~ 3.6v supply programmable transmit level programmable pre-emphasis (50/75 s) pb-free and rohs compliant applications mp3 player cellular phone pda portable personal media player laptop computer wireless speaker rev. 1.0 information furnished by kt micro is believed to be accurate and reliable. however, no responsibility is assumed by kt micro for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent ri g hts of kt micro, inc.. figure 1: KT0801A system diagram ? general description KT0801A, our new generation of low cost monolithic digital fm transmitter, is designed to process high-fidelity stereo audio signal and transmit modulated fm signal over a short range. it?s based on the architecture of award- winning kt0801 and it?s also an upgrade of kt0801. the additional features added to KT0801A are increased transmission power up to 11 3 dbuv, support of 32.768 khz input clock and crystal, bass control and auto level detection. the KT0801A features dual 20-bit ? audio adcs, a high- fidelity digital stereo audio pr ocessor and a fully integrated radio frequency (rf) transmitter. an on-chip low-drop-out regulator (ldo) allows the chip to be integrated in a wide range of low-voltage battery-operated systems with power supply ranging from 1.6v to 3.6v. the KT0801A is configured as an i 2 c slave and programmed through the indust ry standard 2-wire mcu interface. . thanks to its high integration level, the KT0801A is mounted in a generic 24-pin qfn package. it only requires a single low-voltage supply. no external tuning is required that makes design-in effort minimum. kt micro inc., 22391 gilberto, suite d rancho santa margarita, ca 92688 tel: 949.713.4000 http://www.ktmicro.com.cn fax: 949.713.4004 copyright ? 2009, kt micro, inc. .
copyright ? 2009, kt micro, inc. 2 KT0801A ? operation condition table 1: operation condition parameter symbol operating condition min typ max units io/regulator supply iovdd relative to gnd 1.6 3.6 v operating temp t a ambient temperature -30 25 85 c note: 1. when ldo enabled, no external voltage should be applied to this 1.8v supply. z specifications and features table 2: fm transmitter functional parameters (unless otherwise noted ta = -30~85 o c, iovdd=1.6~3.6 v, f in = 1 khz) parameter symbol test/operating condition min nom max units fm frequency range f tx pin 19 76 108 mhz current consumption i vdd pin 1 with pa (power amp.) at default power mode - 10 17 ma standby current i stand pin 1 - 0.1 1 a signal to noise ratio snr v in = 0.7 v p-p , g in = 0 60 - db total harmonic distortion thd v in = 0.7 v p-p , g in = 0 0.3 % left/right channel balance bal v in = 0.7 v p-p , g in = 0 -0.2 - 0.2 db stereo separation 0 (l<->r) sep v in = 0.7 v p-p , g in = 0 40 - db sub carrier rejection ratio scr v in = 0.7 v p-p , g in = 0 - - -60 db input swing 1 v in single-ended input - 0.35 1.4 v rms pga range for audio input g in -12 0 12 db pga gain step for audio input g step 1 4 db required input common-mode voltage when dc-coupled v cm pin 4, 6 0 0.8 1.8 v power supply rejection 2 psrr iovdd = 1.9 ~ 3.6 v 40 - - db ground bounce rejection 2 gsrr iovdd = 1.9 ~ 3.6 v 40 - - db input resistance (audio input) r in pin 4, 6 120 150 180 k ? input capacitance (audio input) c in pin 4, 6 0.5 0.8 1.2 pf audio input frequency band f in pin 4, 6 20 - 15k hz transmit level v out 96 108 113 dbv channel step step - 50 khz pilot deviation 7.5 15 khz frequency response mono,-3db, f=60khz, 50/75 s pre-emphasis 30 15k hz sig_proc<1> = 1 - 50 - s pre-emphasis time constant t pre sig_proc<0> = 0 - 75 - s crystal/external clock clk dual-frequency setup 0.32768 7.6 15.2 mhz 2-wire i 2 c clock scl pin 17 0 100 400 khz high level input voltage v ih pin 3, 9, 10, 12, 13, 16, 17, 24 0.75 x iovdd - iovdd + 0.25 v low level input voltage v il pin 3, 9, 10, 12, 13, 16, 17, 24 - 0.25 - 0.25 x iovdd v notes: 0. measured with mpx signal 1. maximum is given on the condition of pga gain = -12db. 2. fin = 20 ~ 15k hz.
copyright ? 2009, kt micro, inc. 3 KT0801A ? package and pin list a 24-pin qfn package is used. the chip io pin-out is listed in table 3. table 3: KT0801A pin definition pin index name i/o type function 1 iovdd power 1.6~3.3v external logic iovdd or regulator high supply input. 2, 14, 18, 21 22 nc reserved. no connection is recommended. though these pin definitions are different from in kt0801, KT0801A can function in a kt0801 system without any pcb change. 3 hf digital input please refer to table 5 on page 12. 4 inl analog input left channel audio input. 5, 11, 15, 20, gnd ground ground. 6 inr analog input right channel audio input. 7 nc1 reserved. do not connect. 8 nc2 reserved. do not connect. 9 sw1 digital input control bit. chip enable, supply mode and clock source. 10 sw2 digital input control bit. chip enable, supply mode and clock source. 12 rstb digital input reset (active low). 13 addr digital input set the 4 th i2c address bit (msb being the 1 st bit). 16 sda digital i/o serial data i/o. 17 scl digital i/o serial clock input. 19 pa_out analog output fm rf output. 23 xi analog i/o crystal input. 24 xo/rclk analog i/o crystal input or external reference clock input. 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 13 24 23 22 21 20 19 iovdd nc hf inl gnd inr nc scl sda gnd nc addr pa_out gnd nc nc xi xo/clk top view rstb gnd sw2 sw1 nc2 nc1 figure 2: pin-out
copyright ? 2009, kt micro, inc. 4 KT0801A ? i 2 c compatible 2-wire serial interface general descriptions please note that during the power-up, rstb should be set to low first to reset the chip. the registers should not be accessed until 150 ms after rstb returns to high. the serial interface consists of a serial controller and registers. an internal address decoder transfers the content of the data into appropriate registers. both the write and read operations are supported according to the following protocol: write operations: byte write: the write operation is accomplished via a 3-byte sequence: serial address with write command register address register data a write operation requires an 8-bit register address following the device address word and acknowledgment. upon receipt of this address, the KT0801A will again respond with a ?0? and then clock in the 8-bit register data. following receipt of the 8-bit register data, the KT0801A will output a ?0? and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition (see figure 3). read operations: random read: the read operation is accomplished via a 4-byte sequence: serial address with write command register address serial address with read command register data once the device address and register address are clocked in and acknowledged by the KT0801A, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the KT0801A acknowledges the device address and serially clocks out the register data. the microcontroller does not respond with a ?0? but does generate a following stop condition (see figure 3). random register write procedure s 0 1 1 x 1 1 0 w a a ap 7 bit address register address data acknowledge acknowledge stop condition start condition write command acknowledge random register read procedure s 0 1 1 x 1 1 0 w a as0111110 r a a p 7 bit address register address 7 bit address data acknowledge acknowledge acknowledge start condition write command read condition no acknowledge stop condition
copyright ? 2009, kt micro, inc. 5 KT0801A figure 3: serial interface protocol current address read: the internal data register address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. once the device address with the read/write select bit set to ?1? is clocked in and acknowledged by the KT0801A, the current address data word is serially clocked out. the microcontroller does not respond with an input ?0? but does generate a following stop condition (see figure 4). current register read procedure s 0 1 1 x 1 1 0 r a a p 7 bit address data acknowledge stop condition start condition read command no acknowledge figure 4: serial interface protocol note: the x is the optional 4 th msb bit address code that is set by the addr pin (pin 13) and is provided to allow a dual-transmitter-single-controller configuration that will enable multi-channel surround sound applications. addr (pin 13) must be externally tied to ground or iovdd for low or high setup, respectively. the serial controller supports slave mode only. any register can be addressed randomly. the address of the slave in the first 7 bits and the 8th bit tells whether the master is receiving data from the slave or transmitting data to the slave. when addr is set to ?0? (i.e. tied to ground), the i 2 c write address is 0x6c and the read address is 0x6d. when addr is set to ?1? (i.e. tied to power), the i 2 c write address is 0x7c and the read address is 0x7d. slave mode protocol with reference to the clocking scheme shown in figure 5, the serial interface operates in the following manner: figure 5: serial interface slave mode protocol clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 6). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 7). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the KT0801A in a standby power mode (see figure 7). acknowledge: all addresses and data words are serially transmitted to and from the KT0801A in 8-
copyright ? 2009, kt micro, inc. 6 KT0801A bit words. the KT0801A sends a ?0? to acknowledge that it has received each word. this happens during the ninth clock cycle (see figure 8). figure 6: clock and data transitions figure 7: start and stop definition figure 8: acknowledge
copyright ? 2009, kt micro, inc. 7 KT0801A ? register bank the register bank stores channel frequency codes, calibration parameters, operation status, mode and power controls, which can be accessed by the internal digital controller, state machines and external micro controllers through the serial interface. all registers are 8 bits wide. control logics are active high unless specifically noted. register 7 6 5 4 3 2 1 0 0x00 chsel[8:1] 0x01 rfgain[1:0] pga[2:0] chsel[11:9] 0x02 chsel[0] rfgain[3] - - mute pltadj - phtcnst 0x04 mono pga_lsb[1:0] - bass[1:0] 0x0b - - pdpa - - - - - 0x0e - - - - - - pa_bias - 0x0f - - - pw_ok - slncid - - 0x10 - - - lmtlvl[1:0] - - pgamod 0x12 slncdis slncthl[2:0] slncthh[2:0] sw_mod 0x13 rfgain[2] - - - - pa_ctrl - - 0x14 slnctime[2:0] slnccnthigh[2:0] - - 0x16 - - - slnccntlow[2:0] note 1: only read/write the defined registers. don?t read/write any undefined address. note 2: shaded registers are used in kt0801. register 0x00 (address: 0x00, default value: 0x81) bit 7 6 5 4 3 2 1 0 KT0801A chsel[8:1] kt0801 chsel[7:0] as the minimum frequency step is changed from 100khz in kt0801 to 50khz in KT0801A. the 12 bits (reg0x1[2:0]; reg0x0[7:0]; reg0x2[7]) are required to select the fm transmission channel instead of 11 bits in kt0801. if a 100 khz step is wanted to be compatible with kt0801, set reg0x2[7] to 0 and thus no software change is needed from kt0801 to KT0801A to set the same fm frequency. register 0x01 (address: 0x01, default value: 0xc3) bit 7 6 5 4 3 2 1 0 KT0801A rfgain[1:0] pga[2:0] chsel[11:9] kt0801 rfgain[1:0] pga[2:0] chsel[10:8] bits type default label description 7:6 rw 11 rfgain[1:0] transmission range adjustment with rfgain[3] in reg 0x02[6] and rfgain[2] in reg 0x13[7] (see table 4 below) 5:3 rw 000 pga[2:0] pga gain control (see pga_lsb description, reg 0x04) 111: 12db 110: 8db 101: 4db 100: 0db 000: 0db 001: -4db 010: -8db 011: -12db
copyright ? 2009, kt micro, inc. 8 KT0801A bits type default label description 2:0 rw 011 chsel[11:9] fm channel selection[11:9] table 4: transmission power setting rfgain<3:0> rfout 0000 95.5 dbuv 0001 96.5 dbuv 0010 97.5 dbuv 0011 98.2 dbuv 0100 98.9 dbuv 0101 100 dbuv 0110 101.5 dbuv 0111 102.8 dbuv 1000 105.1 dbuv ( 107.2dbuv pa_bias=1) 1001 105.6 dbuv (108dbuv, pa_bias=1) 1010 106.2 dbuv (108.7dbuv, pa_bias=1) 1011 106.5 dbuv (109.5dbuv, pa_bias=1) 1100 107 dbuv (110.3dbuv, pa_bias=1) 1101 107.4 dbuv (111dbuv, pa_bias=1) 1110 107.7 dbuv (111.7dbuv, pa_bias=1) 1111 (default setting) 108 dbuv (112.5dbuv, pa_bias=1) register 0x02 (address: 0x02, default: 0x40) bit 7 6 5 4 3 2 1 0 KT0801A chsel[0] rfgain[3] - - mute pltadj - phtcnst kt0801 - - - - mute pltadj - phtcnst bits type default label description 7 rw 0 chsel[0] lsb o chsel, additional to kt0801 6 rw 1 rfgain[3] msb of rfgain 5:4 rw 00 reserved 3 rw 0 mute software mute 1: mute enabled 0: mute disabled 2 rw 0 pltadj pilot tone amplitude adjustment 1: amplitude high 0: amplitude low 1 rw 0 na reserved 0 rw 0 phtcnst pre-emphasis time-constant set 1: 50 s (europe, australia) 0: 75 s (usa, japan) register 0x04 (address: 0x04, default: 0x04) - new bit 7 6 5 4 3 2 1 0 KT0801A - mono pga_lsb[1:0] fdev[1:0] bass[1:0] kt0801 - - - - - bits type default label description 7 rw 0 reserved
copyright ? 2009, kt micro, inc. 9 KT0801A bits type default label description 6 rw 0 mono force mono 5:4 rw 00 pga_lsb[1:0] pga<2:0> pga_lsb<1:0> pga gain 111 11 12db 111 10 11 111 01 10 111 00 9 110 11 8 110 10 7 110 01 6 110 00 5 101 11 4 101 10 3 101 01 2 101 00 1 100 11 0 100 10 0 100 01 0 100 00 0 000 00 0 000 01 -1 000 10 -2 000 11 -3 001 00 -4 001 01 -5 001 10 -6 001 11 -7 010 00 -8 010 01 -9 010 10 -10 010 11 -11 011 00 -12 011 01 -13 011 10 -14 011 11 -15 3:2 rw 01 nc 1:0 rw 00 bass[1:0] bass boost control 00 = disable 01 = low 10 = med 11 = high register 0x0b (address: 0x0b, default: 0x00) - new bit 7 6 5 4 3 2 1 0 KT0801A - - pdpa - - - - - kt0801 - - - - - - - - bits type default label description 7 rw 0 reserved 6 rw 0 reserved 5 rw 0 pdpa power amplifier power down 4 rw 0 reserved 3 rw 0 reserved
copyright ? 2009, kt micro, inc. 10 KT0801A bits type default label description 1 rw 0 reserved 0 rw 0 reserved register 0x0e (address: 0x0e, default: 0x02) ? new bit 7 6 5 4 3 2 1 0 KT0801A - - - - - - pa_bias - kt0801 - - - - - - - - bits type default label description 7:2 rw 0x00 reserved 1 rw 1 pa_bias pa bias current enhancement. 0 rw 0 reserved register 0x0f (address: 0x0f, read only) ? new bit 7 6 5 4 3 2 1 0 KT0801A - - - pw_ok - slncid - - kt0801 - - - - - - - - bits type default label description 7 r na reserved 6 r na reserved 5 r na reserved 4 r na pw_ok power ok indicator 3 r na reserved 2 r na slncid 1 when silence is detected 1 r na reserved 0 r na reserved register 0x10 (address: 0x10, default: 0x08) ? new bit 7 6 5 4 3 2 1 0 KT0801A - - - lmtlvl[1:0] - - pgamod kt0801 - - - - - - - - bits type default label description 7:5 rw 000 reserved 4:3 rw 01 lmtlvl[1:0] internal audio limiter level control 00 = lowest level 01 = low level 10 = high level 11 = hjghest level 2:1 rw 00 reserved 0 rw 0 pgamod pga mode selection 0 = 4db step (compatible with kt0801) 1 = 1db step with pga_lsb[1:0 ] used register 0x12 (address: 0x12, default: 0x80) - new bit 7 6 5 4 3 2 1 0 KT0801A slncdis slncthl[2:0] slncthh[2:0] sw_mod kt0801 - - - - - - - -
copyright ? 2009, kt micro, inc. 11 KT0801A bits type default label description 7 rw 1 slncdis silence detection disable 0 : enable 1 : disable 6:4 rw 000 slncthl silence detection low threshold 000 : 0.25mv 001 : 0.5mv 010 : 1mv 011 : 2mv 100 : 4mv 101 : 8mv 110 : 16mv 111 : 32mv 3:1 rw 000 slncthh silence detection high threshold 000 : 0.5mv 001 : 1mv 010 : 2mv 011 : 4mv 100 : 8mv 101 : 16mv 110 : 32mv 111 : 64mv 0 rw 0 sw_mod switching channel mode selection. 0 = mute when changing channel 1 = pa off when changing channel register 0x13 (address: 0x13, default: 0x80) bit 7 6 5 4 3 2 1 0 KT0801A rfgain[2] - - pa_ctrl - - kt0801 pa_hi_pw - - - - - - - bits type default label description 7 rw 1 rfgain[2] pa (power amplifier) power (combined with reg 0x01[7:6] and reg 0x02[6])to set up transmission range) 6:3 rw 0000 reserved 2 rw 0 pa_ctrl power amplifier structure selection 0 = pa powered by internal power supply, kt0801 compatible 1 = pa powered by external power supply via external inductor note: when external inductor is used, this bit must be set to 1 immediately after the power ok indicator is set to 1. otherwise, the device may be damaged! 1:0 rw 00 reserved register 0x14 (address: 0x14, default 0x00) - new bit 7 6 5 4 3 2 1 0 KT0801A slnctime<2:0> slnccnthigh<2:0> - - kt0801 - - - - - - - - bits type default label description
copyright ? 2009, kt micro, inc. 12 KT0801A bits type default label description 7:5 rw 000 slnctime<2:0> silence detection low level and high level duration time 000 : 50ms 001 : 100ms 010 : 200ms 011 : 400ms 100 : 1s 101 : 2s 110 : 4s 111 : 8s 4:2 rw 000 slnccnthigh<2:0 > silence detection high level counter threshold 000 : 15 001 : 31 010 : 63 011 : 127 100 : 255 101 : 511 110 : 1023 111 : 2047 1 0 rw 00 reserved register 0x16 (address 0x1 6, default: 0x00) - new bit 7 6 5 4 3 2 1 0 KT0801A - - - slnccntlow[2:0] kt0801 - - - - - - - - bits type default label description 7:3 rw 0x0 reserved 2:0 rw 000 slnccntlow[2:0] silence low counter 000 : 1 001 : 2 010 : 4 011 : 8 100 : 16 101 : 32 110 : 64 111 : 128 chip enable and mode control there are 2 external pins sw1 and sw2 (pin 9 and 10) which enable chip and define the supply voltage level and clock source of the chip. the definition is shown below. table 5: pin sw vs. chip supply and clock source sw[1:2] hf chip mode 00 x disabled 11 0 xtal/external reference 7.6mhz 11 1 xtal/external referenc 15.2mhz 10 1 xtal/external reference 32768hz
copyright ? 2009, kt micro, inc. 13 KT0801A mute the fm transmitter can be muted by setting register mute to ?1? through i2c programming. silence detection bit name register location description slncdis reg 0x12[7] setting to 0 to enable the silence detection slnctime[2:0] reg 0x14[7:5] silence detection time window slncthl[2:0] reg 0x12[6:4] low threshold voltage of input signal for silence detection slncthh[2:0] reg 0x12[3:1] high threshold voltage of input signal for silence detection slnccntthl[2:0] reg 0x14[4:2] # of time when the input signal amplitude is lower than slncthl slnccntthh[2:0] reg 0x16[2:1] # of time when the input signal amplitude is higher than slncthh slncid reg 0x0f[2] (read only) set to 1 when silence is detected. the silence detection scheme is enabled by setting slncdis to 0. during the time defined by slntime[2:0], the chip will be muted when the number of time when the input amplitude is higher than the voltage defined by slncthl[2:0] is lower than slnccntthl[2:0]. the slncid bit is set to 1. when the input signal amplitude is higher than the voltage defined by slncthh[2:0] and the number of time when that happens is more than slnccntthh[2:0], the chip exits from the mute status and the slncid is cleared to 0. reset the global reset is issued after the rstb pin set to ?0? or automatic on-chip power-on reset. after a global reset, all registers are reset to the default value. ? typical application circuits the KT0801A can be integrated in a wide range of systems by requiring only a single power supply. though there are a few power and ground pins in kt0801 defined as nc in KT0801A, KT0801A can be a direct drop-in replacement of kt0801 if a customer chose not to take advantage of the additional features from KT0801A. figure 9 shows a configuration with zero external components. figure 10 shows a setup with an external inductor (fb)to boost the transmission power.
copyright ? 2009, kt micro, inc. 14 KT0801A figure 9: typical application configuration with a 3.3v supply figure 10: application that requires higher transmission power (>5dbm) KT0801A sda scl inl inr stereo audio line input nc gnd r s tb sw1 sw2 hf pa_out antenna 7.6mhz 33nf 33nf xi xo 3.3v iovdd optional mcu (3.3 v cmos logic) i 2 c por 1 1 0 KT0801A sda scl inl inr stereo audio line input nc gnd r s tb sw1 sw2 hf pa_out antenna 32khz xtal 33nf 33nf xi xo 3.3v iovdd 15 p f 15 p f optional mcu (3.3 v cmos logic) i 2 c por 1 0 1
copyright ? 2009, kt micro, inc. 15 KT0801A ? package outline (millimeters) symbols min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.20 0.25 0.30 c 0.19 0.20 0.25 d 3.95 4.00 4.05 d2 2.65 2.70 2.75 e 3.95 4.00 4.05 e2 2.65 2.70 2.75 e - 0.5 - l 0.30 0.40 0.50 y 0.00 - 0.076
copyright ? 2009, kt micro, inc. 16 KT0801A ? recommended pcb land pattern
copyright ? 2009, kt micro, inc. 17 KT0801A ? revision history v1.0 official release
copyright ? 2009, kt micro, inc. 18 KT0801A ? contact information kt micro inc. 22391 gilberto, suite d rancho santa margarita, ca 92688 usa tel: 949-713-4000 fax: 949-713-4004 email: sales@ktmicro.com ??? ?j 2 ??? 2 b 8 (100089) 8610-88891945 8610-88891977 ? sales@ktmicro.com ? http://www.ktmicro.com.cn

▲Up To Search▲

Price & Availability of KT0801A

	To Download KT0801A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .