 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1. general description th e lpc1 1e1x are an arm co rt ex-m 0 ba se d, lo w-cost 3 2 - b it m c u fa mily , d e sign ed for 8 / 1 6 - b it m i cr ocon tr olle r ap plication s , of fe rin g pe rfor man c e , lo w po we r , simple in str u cti on set a nd mem o ry a d d r essing toge th er with r edu c ed co de size comp ar ed to e x isting 8/16 -b it architectures. th e lpc1 1e1x ope ra te a t cpu fre q u encies of up to 50 mhz. the peripheral complement of the lpc11e1x includes up to 32 kb of flash memory, up to 10 kb of sram data memory and 4 kb eeprom, one fast-mode plus i 2 c-bus interface, one rs-485/eia-485 usart with support for synchronous mode and smart card interface, two ssp interfaces, fo ur general-purpose counter/timers, a 10-bit adc, and up to 54 general-purpose i/o pins. 2. features and benefit s ? system: ? arm co rtex- m 0 pr ocessor , r unn ing a t fre que ncies of u p to 50 mhz. ? arm co rtex- m 0 bu ilt- i n nested v e ct or ed inter r u p t co ntro ller ( n vic). ? non-mas k able interr up t (nm i) in pu t se lect a b l e fr om several input sources. ? sys t em tick timer . ? me mor y : ? up to 32 kb o n - c h i p flash pr ogr am m e mo ry . ? up to 4 kb on-chip eepr om dat a memory ; byte erasable an d byte programmable. ? up to 10 kb sram dat a memory . ? 1 6 kb bo ot rom in cludin g 32 -bit inte g e r d i vid e ro utine s an d po we r pr ofiles. ? in -sy ste m pr og ra m m in g (i sp) an d in -ap p lic atio n prog ra mmin g (iap) for flash an d eeprom via on-chip bo otloader sof t ware. ? deb ug op tions: ? standard jtag test interface for bsdl. ? serial wire debug. lpc11e1x 32-bit arm cortex-m0 microcontr oller; up to 32 kb flash; up to 10 kb sram and 4 kb eeprom; usart rev. 1 ? 20 february 2012 product data sheet www.datasheet.net/ datasheet pdf - http://www..co.kr/ http://
lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 2 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller ? digit al peripherals : ? up to 54 general-purpos e i/o (gpi o) pi ns with c o nfigurable pull-up/pull-down r e sisto r s, r epe ater mode , a nd op en -d rain mod e . ? up to 8 gpio pin s can b e se lected as e d ge and level sensitiv e interrupt sources. ? t w o gpi o gr ou p e d in te rr up t m o du le s e n a b l e an in te rr up t ba se d on a p r og ra mma ble p a ttern o f in put st ates o f a g r ou p of gpio pin s . ? high - cur r e n t so urce o u tput dr ive r ( 20 ma) o n on e pin. ? high - cur r e n t sin k dr iver ( 20 ma) on tru e ope n- dr ain pin s . ? fo ur g ene ra l-p u r pose cou n ter / time rs with a tot a l o f up to 8 cap t u r e in pu t s an d 13 m a t c h ou tp u t s. ? pr ogr amm able win dowe d w a tch d o g t i m e r ( w wdt) with a de dicated , inter n a l low - pow e r w a tchdog os cillator (wdo). ? ana l og p er i phe ra ls: ? 10-bit adc with input multip lexin g amo ng eig h t pins. ? ser i al inte rfaces: ? usar t with fr action al bau d ra te gen er ati on, internal fifo, a full modem control h and sh ake inter f ace, a n d sup p o r t for rs- 4 8 5 /9- b it m ode a n d synchr ono us mod e . usar t sup p o r t s a n asynchr ono us sm art card inter f a c e ( i so 781 6- 3) . ? t w o ssp controllers with fifo an d multi-protocol cap a bilities. ? i 2 c- bus in te rface supp or tin g the full i 2 c- bu s sp ecifica t io n and fa st-m ode plus with a dat a rate of up to 1 mbit/s with mult iple add re ss re co gnitio n and m onito r mod e . ? clo ck ge ne r a t i o n : ? cryst al oscillator with an op erating range of 1 m hz to 25 mhz (s ystem oscillator). ? 12 mhz high-frequenc y internal rc os cilla tor (irc ) that can optionally be used as a sys tem clock. ? internal low-power , low - frequency w a tc hd og osc illator (wdo) with programmable fr eq u e n cy ou tp ut . ? pll allows cpu operation up to the max i mum cpu rate w ith the sys tem os cillator o r th e irc as clo c k so ur ce s. ? clock output function with divi der that c a n refl ec t the cryst al oscillator , the main clock, the irc , or the watchdog os cillator . ? powe r co ntro l: ? in te gr at ed pmu ( p ow er m a na ge m e n t un it) to min i m i ze p o w e r co n s u m p tio n d u r i ng slee p, de ep- sleep , powe r- down , an d de ep p o wer - d o wn mod e s. ? powe r pr ofiles resid i ng in bo ot rom allo w op tim i ze d pe rfor man c e a n d m i nimized p o wer con s u m ption fo r an y given app lica t ion thr oug h on e sim p le fun c tion call . ? f o u r re du ce d po we r m o d e s : sle e p , de ep -s lee p , po we r- do wn , an d de ep power-down. ? pr ocesso r wa ke -u p fro m dee p -sle ep a n d power - do wn mo des via rese t, sele ct a b le gpio p i ns, or a wa tch dog in terr up t. ? pro c e s s o r wa ke -u p fr om d e e p po we r- do wn m o de u s in g on e sp ec ial f u n c t i on p i n. ? power-on reset (por). ? brownout detect with four separate thre sholds for interrup t and forced reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 3 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller ? uniq ue de vice ser i al nu mbe r for id en tification. ? sing le 3.3 v power su pp ly ( 1 .8 v to 3.6 v) . ? t emp er atur e ra nge ? 40 ? c to +85 ? c. ? available as lqfp64, lqfp 48, and hvqfn33 package. 3. applications 4. ordering information 4.1 o rdering options ? co ns um e r p e r ip he ra ls ? ha nd he ld sc an ne rs ? medical ? industrial cont rol t a bl e 1. o r de ri ng i n fo rma tio n type number package name description ve r s i o n l p c1 1e1 1 fhn 33/101 hvqf n33 p l a sti c thermal e nhan ced very thi n quad fla t p a ckag e ; n o l ead s; 33 terminal s; bod y 7 ? 7 ? 0.85 mm n/a l p c1 1e12 fbd4 8/201 lqf p 48 pl asti c lo w prof ile qu ad flat p a ckage; 48 le ads; b ody 7 ? 7 ? 1. 4 mm s o t 3 1 3 - 2 l p c1 1e13 fbd4 8/301 lqf p 48 pl asti c lo w prof ile qu ad flat p a ckage; 48 le ads; b ody 7 ? 7 ? 1. 4 mm s o t 3 1 3 - 2 l p c1 1e14 fhn 33/401 hvqf n33 p l a sti c thermal e nhan ced very thi n quad fla t p a ckag e ; n o l ead s; 33 terminal s; bod y 7 ? 7 ? 0.85 mm n/a l p c1 1e14 fbd4 8/401 lqf p 48 pl asti c lo w prof ile qu ad flat p a ckage; 48 le ads; b ody 7 ? 7 ? 1. 4 mm s o t 3 1 3 - 2 l p c1 1e14 fbd6 4/401 lqf p 64 pl asti c lo w prof ile qu ad flat p a ckage; 64 le ads; b ody 10 ? 10 ? 1.4 mm sot314-2 table 2. part ordering options part number flash eeprom sram i 2 c-bus fm+ usart ssp ad c channels gpi o lpc 1 1e1 1 f hn3 3/1 0 1 8 kb 5 12 b 4 kb 1 1 2 8 2 8 l p c1 1 e 1 2 f b d 4 8/ 20 1 1 6 kb 1 kb 6 kb 1 1 2 8 40 l p c1 1 e 1 3 f b d 4 8/ 30 1 2 4 kb 2 kb 8 kb 1 1 2 8 40 lpc 1 1e14 fhn3 3/401 32 kb 4 kb 1 0 kb 1 1 2 8 2 8 l p c1 1 e 1 4 f b d 4 8/ 40 1 3 2 kb 4 kb 10 k b 1 1 2 8 40 l p c1 1 e 1 4 f b d 6 4/ 40 1 3 2 kb 4 kb 10 k b 1 1 2 8 54 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 4 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 5. block diagram (1) not available o n hvqf n33 p ackages. (2) c t 16b0/1_cap1, c t 32b1_c a p 1 a v aila ble on the lqfp64 p a ckage only . ct3 2b 0 _cap1 av ailable on the lqfp64 and lqfp48 p a ckages only . fi g 1. blo c k d i a g ra m sram 4/6/8/10 kb arm cortex-m0 test/debug interface flash 8/16/24/32 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions reset swd, jtag lpc11e1x slave slave slave slave rom 16 kb slave ahb-lite bus gpio ports 0/1 clkout irc, wdo system oscillator por pll0 bod 10-bit adc usar t/ smartcard interface ad[7:0] rxd txd cts, rts, dtr sclk gpio interrupts 32-bit counter/timer 0 ct32b0_mat[3:0] ct32b0_cap[1:0] (2) 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap[1:0] (2) dcd, dsr (1) , ri (1) 16-bit counter/timer 1 windowed watchdog timer gpio group0 interrupts ct16b1_mat[1:0] 16-bit counter/timer 0 ct16b0_mat[2:0] ct16b0_cap[1:0] (2) ct16b1_cap[1:0] (2) gpio pins gpio pins gpio group1 interrupts gpio pins system bus ssp0 sck0, ssel0, miso0, mosi0 ssp1 sck1, ssel1, miso1, mosi1 i 2 c-bus iocon system control pmu scl, sda xt alin xt alout 002aag683 eeprom 512 b 1/2/4 kb www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 5 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 6. pinning information 6.1 p inning fi g 2. pin c o n f ig ura t io n ( h vq fn3 3 ) 002aag684 transparent top view pio0_8/miso0/ct16b0_mat0 pio0_20/ct16b1_cap0 pio0_2/ssel0/ct16b0_cap0 pio0_9/mosi0/ct16b0_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 xtalout pio0_22/ad6/ct16b1_mat1/miso1 xtalin tdi/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2 tms/pio0_12/ad1/ct32b1_cap0 reset/pio0_0 tdo/pio0_13/ad2/ct32b1_mat0 pio1_19/dtr/ssel1 trst/pio0_14/ad3/ct32b1_mat1 pio0_3 pio0_4/scl pio0_5/sda pio0_21/ct16b1_mat0/mosi1 pio1_23/ct16b1_mat1/ssel1 pio1_24/ct32b0_mat0 pio0_6/sck0 pio0_7/cts pio0_19/txd/ct32b0_mat1 pio0_18/rxd/ct32b0_mat0 pio0_17/rts/ct32b0_cap0/sclk v dd pio1_15/dcd/ct16b0_mat2/sck1 pio0_23/ad7 pio0_16/ad5/ct32b1_mat3/wakeup swdio/pio0_15/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss lpc1 1e1 1 lpc11e14 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 6 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller fi g 3. pin c on f ig ura t io n ( lqf p4 8) lpc1 1e12fbd48/201 lpc1 1e13fbd48/301 lpc11e14fbd48/401 pio1_25/ct32b0_mat1 pio1_13/dtr/ct16b0_mat0/txd pio1_19/dtr/ssel1 trst/pio0_14/ad3/ct32b1_mat1 reset/pio0_0 tdo/pio0_13/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 tms/pio0_12/ad1/ct32b1_cap0 v ss tdi/pio0_11/ad0/ct32b0_mat3 xtalin pio1_29/sck0/ct32b0_cap1 xtalout pio0_22/ad6/ct16b1_mat1/miso1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio0_20/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio1_26/ct32b0_mat2/rxd pio1_21/dcd/miso1 pio1_27/ct32b0_mat3/txd pio1_31 pio1_20/dsr/sck1 pio1_16/ri/ct16b0_cap0 pio0_3 pio0_19/txd/ct32b0_mat1 pio0_4/scl pio0_18/rxd/ct32b0_mat0 pio0_5/sda pio0_17/rts/ct32b0_cap0/sclk pio0_21/ct16b1_mat0/mosi1 v dd pio1_23/ct16b1_mat1/ssel1 pio1_15/dcd/ct16b0_mat2/sck1 n.c. pio0_23/ad7 n.c. v ss pio1_24/ct32b0_mat0 pio0_16/ad5/ct32b1_mat3/wakeup pio0_6/sck0 swdio/pio0_15/ad4/ct32b1_mat2 pio0_7/cts pio1_28/ct32b0_cap0/sclk pio1_22/ri/mosi1 pio1_14/dsr/ct16b0_mat1/rxd 002aag685 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 7 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller see table 3 for the full pin name. fig 4. pin configuration (lqfp64) lpc11e14fbd64/401 pio1_0 v dd pio1_25 pio1_13 pio1_19 trst/pio0_14 reset/pio0_0 tdo/pio0_13 pio0_1 tms/pio0_12 pio1_7 pio1_11 v ss tdi/pio0_11 xtalin pio1_29 xtalout pio0_22 v dd pio1_8 pio0_20 swclk/pio0_10 pio1_10 pio0_9 pio0_2 pio0_8 pio1_26 pio1_21 pio1_27 pio1_2 pio1_4 v dd pio1_1 pio1_6 pio1_20 pio1_16 pio0_3 pio0_19 pio0_4 pio0_18 pio0_5 pio0_17 pio0_21 pio1_12 pio1_17 v dd pio1_23 pio1_15 n.c. pio0_23 n.c. pio1_9 pio1_24 v ss pio1_18 pio0_16 pio0_6 swdio/pio0_15 pio0_7 pio1_22 pio1_28 pio1_3 pio1_5 pio1_14 002aag686 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 8 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 6.2 p in d escrip tion ta b l e 3 s h o w s all pin s a n d the i r as sig n e d dig i t a l or a n a lo g fu nc tion s in or de r of th e gpi o po r t n u m b er . t h e de fa ult fu n c tio n af t e r r e se t is lis ted f irst . all port pins have internal pu ll- up r e sis to r s en a b le d af t e r r e se t ex cep t fo r t h e t r u e op en - d r a in p i ns pio 0 _4 a n d pio0 _5. every port pin h a s a co rr espo ndin g iocon r e g i ster for pr ogr amm i ng th e d i git a l or ana log fun c tion , the p u ll- up/pu ll-d o wn config ura t i on, th e re pea ter , an d the op en- dr ain m ode s. th e usar t , cou n ter / time r , and ssp function s ar e availa ble o n mor e than o n e p o r t pin . t able 3. pin de scr ip tio n symbol hvqfn33 lqfp48 lqfp64 r eset st at e [1 ] type des c ription reset /p io0_0 2 3 4 [2] i; pu i reset ? externa l reset i nput with 20 ns glitch filter . a low - g o in g p u lse as short as 5 0 ns o n th is p i n reset s the de vice, cau s ing i/o port s an d perip heral s to t a ke o n th eir de fa ult st ates, an d processo r e x ecution to b egi n at add ress 0. thi s pi n also serves as th e debu g select inpu t. low le ve l select s the jt ag bou ndary scan. h i gh level sel e ct s the arm sw d debu g mo de. -i / o pio0_0 ? genera l purpo se d i git a l in put/output pin . pio0_1/clkout / c t 32 b0_mat2 34 5 [3] i; pu i / o pio0_1 ? genera l purpo se digi t a l i nput/outpu t pin . a low le ve l on this pin du ring reset st art s the isp co mman d ha ndle r . -o clkou t ? cl ockout pin. -o ct 32b0 _ ma t2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 81 0 1 3 [3 ] i; pu i / o pio0_2 ? genera l purpo se d i git a l in put/output pin . -i / o ssel0 ? slave select for ssp0. -i ct16b0 _ cap0 ? capture in put 0 for 16-b i t timer 0. pio0_3 9 1 4 1 9 [3] i; pu i / o pio0_3 ? genera l purpo se d i git a l in put/output pin . pio0_4/scl 1 0 1 5 2 0 [4] i; ia i /o pio0_4 ? genera l purpo se d i git a l in put/output pin (ope n-drai n). -i / o scl ? i 2 c-bus clock inp u t/o u tput (o pen-d r a i n). hig h-current sink onl y if i 2 c fast-mode plu s is sele cted i n the i/o co nfi guratio n re gister . pio0_5/sda 1 1 1 6 2 1 [4] i; ia i /o pio0_5 ? genera l purpo se d i git a l in put/output pin (ope n-drai n). -i / o sda ? i 2 c - bus dat a inp u t/ou tp ut (op en-dra i n). hig h-current sink onl y if i 2 c fast-mode plu s is sele cted i n the i/o co nfi guratio n re gister . pio0_6/sck0 1 5 22 29 [3 ] i; pu i / o pio0_6 ? genera l purpo se d i git a l in put/output pin . -i / o sck0 ? serial clock for ssp0. pio0_7/cts 1 6 23 30 [5] i; pu i/o pio0_7 ? general purpose digital input/output pin (high-current output driver). -i cts ? clear t o send input for usart. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 9 of 61 nxp semiconductors lpc1 1e1x 32-bit arm cortex-m0 microcontroller pio0_8/miso0/ c t 16 b0_ma t 0 1 7 27 36 [3] i; pu i / o pio0_8 ? genera l purpo se d i git a l in put/output pin . -i / o miso0 ? master in slave out for ssp0. -o ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ c t 16 b0_ma t 1 1 8 28 37 [3 ] i; pu i / o pio0_9 ? genera l purpo se d i git a l in put/output pin . -i / o mosi0 ? master out slave in for ssp0. -o ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/sck0/ c t 16 b0_ma t 2 1 9 29 38 [3 ] i; pu i swclk ? serial wire clock and test c l ock tck for jt ag in te rface. -i / o pio0_ 10 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o sck0 ? serial cloc k for ssp0. -o ct16b0_mat2 ? match output 2 for 16-bit timer 0. tdi/ pio0_1 1/ ad0/ c t 32 b0_ma t 3 2 1 32 42 [6 ] i; pu i tdi ? t e st dat a in f o r jt ag in te rface . -i / o pio0_1 1 ? gene ra l purpo se d igi t a l i nput/output pin . -i ad0 ? a/d con v e r te r , i npu t 0. -o ct32b0_mat3 ? match output 3 for 32-bit timer 0. tms/pio0_12/ad1/ c t 32 b1_cap0 2 2 33 44 [6 ] i; pu i tm s ? t e s t m o de select for jt ag interface. -i / o pio_12 ? general purpose digital input/output pin. -i ad1 ? a/d con v e rte r , i npu t 1. -i ct32b1 _ cap0 ? capture in put 0 for 32-b i t timer 1. t do / pi o0 _13 /ad2 / c t 32 b1_ma t 0 2 3 34 45 [6 ] i; pu o tdo ? t e s t dat a o u t f o r jt a g interface. -i / o pio0_ 13 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ad2 ? a/d con v e r te r , i npu t 2. -o ct32b1_mat0 ? match output 0 for 32-bit timer 1. trst /pio0 _14/ad3/ c t 32 b1_ma t 1 2 4 35 46 [6 ] i; pu i trst ? t e st reset for jt ag interface. -i / o pio0_ 14 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ad3 ? a/d con v e r te r , i npu t 3. -o ct32b1_mat1 ? match output 1 for 32-bit timer 1. sw dio/pio0_1 5/ad4/ c t 32 b1_ma t 2 2 5 39 52 [6 ] i; pu i / o swdio ? serial wi re debu g inpu t/ou tp ut. -i / o pio0_ 15 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ad4 ? a/d con v e r te r , i npu t 4. -o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio0_16 /ad5 / ct32b1_ma t 3/w akeup 2 6 40 53 [6 ] i; pu i / o pio0_ 16 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ad5 ? a/d con v e r te r , i npu t 5. -o ct 32b1 _ ma t3 ? ma t c h ou tp u t 3 fo r 3 2 - bi t ti me r 1 . -i wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. pull this pin high externally to enter deep power-down mode. pull this pin low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. t able 3. pin de scr ip tio n symbol hvqfn33 lq fp48 lq fp64 reset state [1] type description www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 10 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller pio0_17/rts / ct32b0_cap0/sclk 3 0 45 60 [3 ] i; pu i / o pio0_ 17 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o rts ? requ est t o sen d o u tput for usar t . -i ct32b0 _ cap0 ? capture in put 0 for 32-b i t timer 0. -i/o sclk ? serial clock input/output for usart in synchronous mode. pio0_18 /rxd / c t 32 b0_ma t 0 3 1 46 61 [3 ] i; pu i / o pio0_ 18 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i rxd ? re ceiver inp u t for usar t . u s e d in uar t isp mode . -o ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio0_19 /t xd/ c t 32 b0_ma t 1 3 2 47 62 [3 ] i; pu i / o pio0_ 19 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o tx d ? t r ansmitte r ou tp ut for usar t . use d in uar t isp mode . -o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio0_20 /ct 1 6 b 1_cap0 7 9 1 1 [3 ] i; pu i / o pio0_ 20 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio0_21 /ct 1 6 b 1_ma t 0 / mosi1 1 2 17 22 [3 ] i; pu i / o pio0_ 21 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o ct 16b1 _ ma t0 ? ma t c h ou tp u t 0 fo r 1 6 - bi t ti me r 1 . -i/o mosi1 ? master out slave in for ssp1. pio0_22 /ad6 / c t 16 b1_ma t 1 / miso1 2 0 30 40 [6 ] i; pu i / o pio0_ 22 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ad6 ? a/d con v e r te r , i npu t 6. -o ct 16b1 _ ma t1 ? ma t c h ou tp u t 1 fo r 1 6 - bi t ti me r 1 . -i/o miso1 ? master in slave out for ssp1. pio0_23 /ad7 2 7 42 56 [6 ] i; pu i / o pio0_ 23 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ad7 ? a/d converter, input 7. pio1_0/ct 32b1 _ ma t 0 - - 1 [3 ] i; pu i / o pio1_0 ? genera l purpo se d i git a l in put/output pin . -o ct32b1_mat0 ? match output 0 for 32-bit timer 1. pio1_1/ct 32b1 _ ma t 1 - - 17 [3 ] i; pu i / o pio1_1 ? genera l purpo se d i git a l in put/output pin . -o ct32b1_mat1 ? match output 1 for 32-bit timer 1. pio1_2/ct 32b1 _ ma t 2 - - 34 [3 ] i; pu i / o pio1_2 ? genera l purpo se d i git a l in put/output pin . -o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_3/ct 32b1 _ ma t 3 - - 50 [3 ] i; pu i / o pio1_3 ? genera l purpo se d i git a l in put/output pin . -o ct32b1_mat3 ? match output 3 for 32-bit timer 1. pio1_4/ct 32b1 _ cap0 - - 16 [3 ] i; pu i / o pio1_4 ? genera l purpo se d i git a l in put/output pin . -i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. pio1_5/ct 32b1 _ cap1 - - 32 [3 ] i; pu i / o pio1_5 ? genera l purpo se d i git a l in put/output pin . -i ct32b1_cap1 ? capture input 1 for 32-bit timer 1. pio1_6 - - 64 [3 ] i; pu i/o pio1_6 ? general purpose digital input/output pin. pio1_7 - - 6 [3 ] i; pu i/o pio1_7 ? general purpose digital input/output pin. t able 3. pin de scr ip tio n symbol hvqfn33 lq fp48 lq fp64 reset state [1] type description www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 11 of 61 nxp semiconductors lpc1 1e1x 32-bit arm cortex-m0 microcontroller pio1_8 - - 39 [3] i; pu i / o pio1_8 ? genera l purpo se d i git a l in put/output pin . pio1_9 - - 55 [3] i; pu i / o pio1_9 ? genera l purpo se d i git a l in put/output pin . pio1_10 - - 12 [3] i; pu i / o pio1_ 10 ? gene ral purp o se dig it a l inpu t/outpu t pi n. pio1_1 1 - - 4 3 [3] i; pu i / o pio1_1 1 ? gene ra l purpo se d igi t a l i nput/output pin . pio1_12 - - 59 [3] i; pu i / o pio1_ 12 ? gene ral purp o se dig it a l inpu t/outpu t pi n. pio1_13/dtr / ct16b0_mat0/txd -3 6 4 7 [3 ] i; pu i / o pio1_ 13 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o dtr ? dat a t e rmina l r eady ou tpu t for usar t . -o ct 16b0 _ ma t0 ? ma t c h ou tp u t 0 fo r 1 6 - bi t ti me r 0 . -o tx d ? t r ansmitte r ou tp ut for usar t . pio1_14/dsr / ct16b0_mat1/rxd -3 7 4 9 [3 ] i; pu i / o pio1_ 14 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i dsr ? da t a set read y i nput fo r usar t . -o ct 16b0 _ ma t1 ? ma t c h ou tp u t 1 fo r 1 6 - bi t ti me r 0 . -i rxd ? re ceiver inp u t for usar t . pio1_15/dcd / ct16b0_mat2/sck1 2 8 43 57 [3 ] i; pu i / o pio1_ 15 ? gene ral purp o se dig it a l inpu t/outpu t pi n. i dcd ? dat a c a rrier detect i nput fo r usar t . -o ct 16b0 _ ma t2 ? ma t c h ou tp u t 2 fo r 1 6 - bi t ti me r 0 . -i / o sck1 ? serial cloc k for ssp1. pio1_16/ri / ct16b0_cap0 -4 8 6 3 [3 ] i; pu i / o pio1_ 16 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ri ? rin g ind icator inpu t for usar t . -i ct16b0 _ cap0 ? capture in put 0 for 16-b i t timer 0. pio1_17 /ct 1 6 b 0_cap1/ rxd -- 2 3 [3 ] i; pu i / o pio1_ 17 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ct16b0 _ cap1 ? capture in put 1 for 16-b i t timer 0. -i rxd ? re ceiver inp u t for usar t . pio1_18 /ct 1 6 b 1_cap1/ txd -- 2 8 [3 ] i; pu i / o pio1_ 18 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ct16b1 _ cap1 ? capture in put 1 for 16-b i t timer 1. -o tx d ? t r ansmitte r ou tp ut for usar t . pio1_19/dtr /ssel1 1 2 3 [3] i; pu i / o pio1_ 19 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o dtr ? dat a t e rmina l r eady ou tpu t for usar t . -i / o ssel1 ? slave select for ssp1. pio1_20/dsr /sck1 - 13 18 [3] i; pu i / o pio1_ 20 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i dsr ? da t a set read y i nput fo r usar t . -i / o sck1 ? serial cloc k for ssp1. pio1_21/dcd /mi s o1 - 26 35 [3] i; pu i / o pio1_ 21 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i dcd ? dat a c a rrier detect i nput fo r usar t . -i / o miso1 ? master in slave out for ssp1. pio1_22/ri /mo s i1 - 3 8 5 1 [3] i; pu i / o pio1_ 22 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ri ? rin g ind icator inpu t for usar t . -i / o mosi1 ? master out slave in for ssp1. t able 3. pin de scr ip tio n symbol hvqfn33 lq fp48 lq fp64 r eset state [1] type description www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 12 of 61 nxp semiconductors lpc1 1e1x 32-bit arm cortex-m0 microcontroller [1] p in st ate at re set for default function: i = input; o = ou tput; pu = internal pull- up enabled; ia = inactive, no pull-up/dow n enabled; f = f l oating; if th e pins ar e not used, tie flo ating p i ns to gr ound or power to mi nimize po wer consumption. [2] see figure 28 for the reset pad configuration. reset functionality is not available in deep po wer- down mode. use the w a k e u p p i n to r eset th e chip and wake up from d eep power -dow n mode. an extern al pull-up r esistor is r equired on this pin for the deep pow er-d own mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 27 ). [4] i 2 c-bu s pins comp liant with the i 2 c-b us specification for i 2 c st andar d mode, i 2 c fa st- m ode, and i 2 c f ast- m ode plus. [5] 5 v tolerant pad providing digital i/o functions with configurable pull-up/pull-down resistors and configurable hysteresis ( see figure 27 ); includes high-current output driver. pio1_23 /ct 1 6 b 1_ma t 1 / ssel1 1 3 18 24 [3 ] i; pu i / o pio1_ 23 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o ct 16b1 _ ma t1 ? ma t c h ou tp u t 1 fo r 1 6 - bi t ti me r 1 . -i / o ssel1 ? slave select for ssp1. pio1_24 /ct 3 2 b 0_ma t 0 1 4 2 1 2 7 [3] i; pu i / o pio1_ 24 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o ct 32b0 _ ma t0 ? ma t c h ou tp u t 0 fo r 3 2 - bi t ti me r 0 . pio1_25 /ct 3 2 b 0_ma t 1 - 1 2 [3] i; pu i / o pio1_ 25 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o ct 32b0 _ ma t1 ? ma t c h ou tp u t 1 fo r 3 2 - bi t ti me r 0 . pio1_26 /ct 3 2 b 0_ma t 2 / rxd -1 1 1 4 [3 ] i; pu i / o pio1_ 26 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o ct 32b0 _ ma t2 ? ma t c h ou tp u t 2 fo r 3 2 - bi t ti me r 0 . -i rxd ? re ceiver inp u t for usar t . pio1_27 /ct 3 2 b 0_ma t 3 / txd -1 2 1 5 [3 ] i; pu i / o pio1_ 27 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -o ct 32b0 _ ma t3 ? ma t c h ou tp u t 3 fo r 3 2 - bi t ti me r 0 . -o tx d ? t r ansmitte r ou tp ut for usar t . pio1_28 /ct 3 2 b 0_cap0/ sclk -2 4 3 1 [3 ] i; pu i / o pio1_ 28 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i ct32b0 _ cap0 ? capture in put 0 for 32-b i t timer 0. -i / o sclk ? serial clock input/output for usart in synchronous mode. pio1_29 /sck0 / c t 32 b0_cap1 -3 1 4 1 [3 ] i; pu i / o pio1_ 29 ? gene ral purp o se dig it a l inpu t/outpu t pi n. -i / o sck0 ? serial cloc k for ssp0. -i ct32b0 _ cap1 ? capture in put 1 for 32-b i t timer 0. pio1_31 - 2 5 - [3] i; pu i / o pio1_ 31 ? gene ral purp o se dig it a l inpu t/outpu t pi n. n . c. - 1 9 2 5 f - n ot conn ecte d. n . c. - 2 0 2 6 f - n ot conn ecte d. xt alin 4 6 8 [7] - - inpu t to the o s ci llator circuit and in te rn al clock gen erator circui t s . inpu t volt ag e mu st not exceed 1 . 8 v . xt alout 5 7 9 [7] - - output from th e o scilla to r ampl ifier . v dd 6; 29 8; 44 10 ; 33 ; 48 ; 58 - - sup p ly vo lt age to th e internal re gula t o r , the e x tern al rail , an d the adc . also used a s the adc reference vol t a ge. v ss 33 5 ; 41 7; 54 - - gro und . t able 3. pin de scr ip tio n symbol hvqfn33 lq fp48 lq fp64 r eset state [1] type description www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 13 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller [6] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 27 ); includes digit a l input glitch filte r . [7] w hen the syste m oscillator is not used, connect xt alin a nd xt alout as fo llows: xt alin can be lef t floating or ca n be grou nde d (grounding is preferred to reduce susceptib ility to noise). leave xtalout floating. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 14 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 7. functional description 7.1 o n - chip flash programming memory th e lpc1 1e1x co nt ain 24 kb o r 32 kb on- chip flash pr og ra m m e mo ry . the flash can b e p r og ra mme d using in- s ystem pr ogr amm i ng ( i sp) o r in- a p p lication pr og ra mming (iap) via the on -chip boo t loa d e r sof t wa re . 7.2 e eprom th e lpc1 1e1x co nt ain 500 byte, 1 kb, 2 kb, or 4 kb o f o n - c h i p byte -e ra sa ble a nd byte-programmable eep rom dat a memory . the eeprom can be programmed using in- a pplica t io n prog ra mmin g (iap) via th e on -chip b oot loa der so f t wa re. 7.3 s ram th e lpc1 1e1x co nt ain a to t a l of 4 kb, 6 kb, 8 kb, or 1 0 kb on -chip st a t ic ram m e mo ry . 7.4 o n - chip rom th e on -chip rom con t ain s the b oot load er an d th e fo llo win g ap plic atio n pr og ra m m in g interfaces (api s): ? in -sy s te m pr o g r a m m i ng (is p ) an d i n - a pp lica tio n pr og ra m m i ng (iap ) su pp or t fo r fla s h ? iap support for eep rom ? powe r pr ofiles fo r configu r in g po we r consum ption a nd pll setting s ? 3 2 -b it in te ger divisi on ro utine s 7.5 m emory map the lpc11e1x incorporates several distinct memory regions, shown in the following figures. figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 mb in size and is divided to allow for up to 128 peripherals. the apb peripheral area is 512 kb in size and is divided to allow fo r up to 32 peripherals. each peripheral of either type is allocated 16 kb of space. this addressing scheme allows simplifying the address decoding for each peripheral. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 15 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 7.6 n ested v e ctored in te rrupt controller (nvic) th e neste d v e ctor ed inter r u p t con t r o lle r ( n vi c) is p a rt of the cortex-m0. the tight coupling to the cp u allows for lo w in terr up t la te ncy a n d e f ficien t p r oce s sing of la te ar riving in te rr upt s. 7.6 .1 fea tures ? con t r o ls syste m exception s a nd pe rip her al inte rr upt s. ? in the lpc1 1e1x, th e nvic sup p or t s 2 4 ve ct or ed in te rr up t s . fi g 5. lpc1 1 e 1 x memo ry ma p apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4004 c000 0x4005 8000 0x4005 c000 0x4006 0000 0x4006 4000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wwdt 32-bit counter/timer 0 32-bit counter/timer 1 adc usar t/smar t card pmu i 2 c-bus 20 - 21 reserved 10 - 13 reserved reserved reserved 25 - 31 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x1000 1800 0x1fff 0000 0x1fff 4000 0x2000 0000 0x5000 0000 0x5000 4000 0xffff ffff reserved reserved 2 kb sram (lpc1 1e14/401) reserved 0x4000 0000 0x4008 0000 apb peripherals gpio 0x2000 0800 6 kb sram (lpc1 1e12/201) 0x1000 1000 4 kb sram (lpc1 1e1 1/101) 0x1000 2000 8 kb sram (lpc1 1e13/301 lpc1 1e14/401) 0x1000 0000 lpc11e1x 0x0000 6000 24 kb on-chip flash (lpc1 1e13) 0x0000 4000 16 kb on-chip flash (lpc1 1e12) 0x0000 2000 8 kb on-chip flash (lpc1 1e1 1) 0x0000 8000 32 kb on-chip flash (lpc1 1e14) 16 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors 002aag688 reserved reserved ssp0 ssp1 16-bit counter/timer 1 16-bit counter/timer 0 iocon system control 19 gpio interrupts 22 23 gpio group0 int 24 gpio group1 int flash/eeprom controller 0xe000 0000 0xe010 0000 private peripheral bus www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 16 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller ? fo ur p r o g r a mma ble in te rr up t pr ior i ty leve ls, with hardw a re pr iority lev e l masking. ? sof t ware interr up t ge ne ra tio n . 7.6 .2 inte r rupt s ources each p e r i ph era l de vice h a s on e inte rr upt line conn ecte d to the nvic but can have se ve ra l in te rr upt flags. ind i vidua l in terr up t flag s can a l so r e p r ese n t m o re th an on e inter r u p t source. 7.7 i ocon block th e iocon b l ock a llows sele cte d pins of th e micro c o n tro ller to ha ve mor e th an o ne fun c tion . con f ig ur ation r egister s con t r o l the mu ltip lexer s to allo w con nection b e tween the p i n and th e on- chip pe rip h e r als. con nect p e r i ph era l s to the a ppr op ria t e p i ns b e for e activa tin g the pe rip h e r al a nd be fo re enabling any relat e d interrupt. . a c tivit y of a n y ena bled per iph e r a l fu nctio n that is n o t ma pp ed to a re lated p i n is tre a ted a s un de fin ed. 7.7 .1 fea tures ? pr ogr amm able pull- up , pu ll-d o wn, or r epe ater mod e . ? all gpio pin s ( e xce p t pio0_4 a n d pio0 _5) ar e pulle d up to 3 . 3 v (v dd = 3. 3 v) if th e i r p u ll-u p re sistor is en abl ed. ? pr ogr amm able p s eu do o pen -d ra in mod e . ? pr ogr amm able 10 ns glitch filter on p i ns pio0 _22 , pio0 _23 , an d pio0_ 1 1 to pio0_ 1 6 . th e glitch filter is tur ned o f f by defa u lt. ? pr ogr amm able hyster esis. ? pr ogr amm able inpu t inve rter . 7.8 g eneral-purpose input/output gpio t h e g p io r e g i ste r s co n tro l d e v ice p i n fu nct i on s tha t ar e no t co nn ec te d to a sp ec if ic p e rip h e r a l fun c tion . pin s can be dynam ica lly con f ig ur ed as inp u t s o r ou tp ut s. m u ltiple o u tput s ca n be set or cle a re d in on e write op er ation. l p c1 1e1 x use accele ra te d gpio fu nctions: ? gpio r egister s ar e a de dicated ahb p e rip h e r a l so t h at the f a s t est possible i/ o timing ca n be a c h i ev ed . ? entir e por t valu e can be wr itte n in on e instr u ction. any gpio pin p r o v id ing a d i git a l fun c tion ca n be p r og ra mme d to g e n e ra te an inte rr upt on a le ve l, a r i sin g or fa lling ed ge , or both. th e gpio blo c k co nsist s of thre e p a r t s: 1 . th e gpio po rt s. 2 . th e gpio pin in te rr up t blo c k to co ntro l e i gh t gpio pin s sele cted as p i n inter r u p t s . 3. two gpio group interrupt blocks to control two combined interrupts from all gpio pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 17 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 7.8 .1 fea tures ? gpio p i ns can be config ure d as inpu t o r ou tp ut b y sof t war e . ? all gpio pin s de fa ult to in pu t s with in terr up t d i sa bled a t r e set. ? pin r egister s a llow p i ns to b e se nsed a n d set individ ually . ? up to eigh t gpio p i ns ca n be sele cted fr om all gpio p i ns to cre a te an e dge - or lev e l-sens itive gpio interrupt reques t . ? an y p i n or p i ns in ea ch p o r t ca n t r ig ge r a po r t in te rr up t. 7.9 u s art th e lpc1 1e1x co nt ain one usar t . th e usar t includ es fu ll m ode m co ntro l, su p por t for synch r on ou s mo de, and a sm art car d inter f ace. t he rs-4 85/9- bit mod e a llo ws both sof t war e add re ss de te ctio n and a u toma tic add re ss de te ction using 9 - bit mod e . th e usar t uses a fraction al ba ud r a te gen er ator . s t a nda rd b aud r a tes such as 1 1 5 2 0 0 bd ca n be a c h i eved with any cryst al fr eq uen cy ab ove 2 m hz. 7.9 .1 fea tures ? m a x i mu m usar t da t a b i t r a t e of 3. 12 5 m bit /s. ? 16 b y t e re ce ive an d tr an sm it fi fo s. ? reg i ster location s confo rm to 16 c5 50 ind u stry st a nda rd . ? receiver fifo trigger point s at 1 b, 4 b, 8 b , and 14 b. ? built- i n fr action al bau d ra te gen er ator cove r i ng wid e ra nge o f ba ud r a tes with out a n eed for exte rn al cryst a ls o f p a r t icula r valu es. ? fractional divider for baud rate control, auto baud cap a bilities and fifo control me ch an ism tha t en ab les so f t war e flow co ntrol imp l eme n t a tio n . ? su pp or t for r s -4 85 /9 -b it mo d e . ? su pp or t for m o de m co nt ro l. ? su pp or t for s y nc hr on o u s m o d e . ? includ es sma r t ca rd in te rface . 7.10 ssp serial i/o controller th e ssp con t r o lle rs ope ra te o n a ssp , 4 - wir e ss i, or microwire bus. it can interact wit h mu ltip le ma ster s a nd slaves on the b u s. only a sin g le ma ster and a sin g le slave can communicate on the bu s during a given dat a transfer . the ssp support s full duplex transfers, w i th frames of 4 b it to 16 b i t o f da t a flowing fro m th e master to the slave a nd fro m th e slave to th e master . in pr actice , of ten only one of the s e dat a flo w s ca rr ies me an ingful da t a . 7.10 .1 fea tures ? maximum ssp speed of 25 mbit/s (master) or 4.17 mbit/s (slave) (in ss p mode) ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 18 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller ? synchr ono us se ria l com m un ica t ion ? ma ste r or slave o per ation ? 8-frame fifo s for both t r ans m it and rec e ive ? 4 - bit to 16- bit fr ame 7.1 1 i 2 c-bus serial i/o contr o ller th e lpc1 1e1x co nt ain one i 2 c - bus controller . th e i 2 c-bus i s bidirec t ional for inter-ic contro l using o n ly two wires: a seria l clo c k line ( s cl ) an d a ser i al da t a line ( s da) . ea ch d e vice is r e cogn ized by a un ique a d d r e s s and can ope ra te as either a r e ceiver -o nly de vice ( e .g., an l c d dr iver ) or a tra n smitter with the cap a bility to both receive and s e nd information (s uc h as me mory). t r ansmitters and/or r e ceiver s ca n o per ate in eithe r m a ster or sl a v e mo de, de pe ndin g o n whe t h e r th e chip ha s to initiate a dat a tr an sf er o r is o n ly ad d r e sse d. t h e i 2 c-bu s is a multi- master b u s, an d mo re tha n on e bus master co nne cte d to th e inte r fac e ca n be co n tro lle d the b u s . 7.1 1 .1 fea tures ? th e i 2 c-in te rface is an i 2 c- bus co mplia nt inter f a c e with op en- dr ain p i ns. th e i 2 c-bus in te rface supp or t s fa st- m od e plus wit h bit ra te s up to 1 m bit /s . ? easy to con f ig ur e as master , slave, or ma ste r /slave. ? pr ogr amm able clo c ks a llow ve rsatile r a te contr o l. ? bidir e ction a l dat a tr ansfer b e tween m a ste r s an d sla v e s . ? mu lti- ma ster bus (n o ce ntra l master) . ? ar bitra t io n betwee n sim u lt an eo usly tra n smit tin g ma ster s withou t cor r u p tion o f ser i al d a t a on th e bus. ? se ria l clo ck sy nc hr on iza tio n allo ws d e v i ce s with dif f er ent bit r a tes to comm unicate via o ne ser i al bus. ? ser i al clock synchr onizatio n ca n be use d as a h and shake me ch ani sm to suspen d an d resume serial transfer . ? th e i 2 c-b u s ca n be use d fo r test an d dia gno stic pur po se s. ? th e i 2 c-b u s co ntro ller sup por t s m u ltiple ad dr ess r e cog n ition a nd a bu s mo nitor m ode . 7.12 10-bit adc th e lpc1 1 e 1x con t ains one adc. it is a si ngle 1 0 - b it successive ap pr oximatio n adc with e i ght ch an nels. 7.12 .1 fea tures ? 10-bit successiv e approximat ion ad c. ? inp u t m u ltiplexin g amo ng 8 p i ns. ? powe r- down mo de . ? m e a s u r e m en t r a ng e 0 v to v dd . ? 10 - b it co nv er sio n tim e ? 2.44 ? s ( u p t o 40 0 ksa m ple s /s ). ? burst conversion mode for single or multiple inputs. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 19 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller ? optiona l co nver sio n on tra n sition of inp u t p i n or time r ma tch sign al. ? ind i vid ual r e sult reg i ste r s fo r ea ch adc ch ann el to red u ce inter r upt over hea d. 7.13 general purpose externa l event counter/timers th e lpc1 1e1x include two 32 -b it cou n ter / ti me rs a n d two 16 -bit coun te r/timer s . th e cou n ter / time r is d e sign ed to co un t cycles of t h e s ystem derived clock. it can optionally g ene ra te in te rr up t s or per for m o t her actio n s a t spe c ifie d tim e r valu es, ba sed on fo ur mat c h registers. each c o unt e r/timer also incl ud es on e cap t u r e inp u t to tr ap th e time r va lue whe n an in put sig n a l tra n sitions, option a lly gen er ating a n inter r u p t. 7.13 .1 fea tures ? a 32- bit/16 - bit timer / cou n ter with a pr og ra mma ble 32 -b it/16 - b i t p r escale r . ? co un te r or tim e r op er a tion . ? up to two cap t u r e cha n n e ls p e r time r , th at ca n t a ke a snap sho t of th e timer va lue whe n an in put sig n a l tra n sitions. a cap t u r e e v e n t ca n also ge ner ate an in terr up t. ? f o u r ma tc h re gis ter s pe r tim e r th a t a llow : ? co ntinuo us ope ra tio n with o p tion al inter r u p t g ene ra tio n on m a tch . ? s t op time r on m a tch with op tiona l in te rr up t ge ne ratio n . ? re se t timer on ma tch with option a l inter r u p t gen er ation . ? up to f o u r ex ter n al o u tp u t s co rr es po nd in g to m a t c h re gis te r s, wit h the f o llo win g cap a bilities: ? se t low o n match. ? se t hi gh o n mat c h. ? t o ggle o n match. ? do n o thing on ma tch. ? th e ti mer a nd p r escale r can be co nfigur ed to b e cle a r ed on a design a ted cap t ure ev en t. t h is fe at ur e pe r m it s ea sy p u lse - wid th m e as ur em e n t b y cle a r in g th e tim e r o n the leading edge of an input puls e and capt uring the timer value on the trailing edge. 7.14 system tick timer the arm cortex-m0 includes a system tick timer (systic k) that is inte nded to generate a de d i ca ted sy st ick exc e p tio n at a fi xe d time inter v al (typically 10 ms) . 7.15 w i nd owed w a tc hdog t i mer (wwdt) th e pu rpo s e of the wwdt is to pr event an u n re spons ive sys tem st ate. if sof t w a re fails to u pda te th e wa tchd og within a p r o g ra mma ble time wind o w , the wa tchd og r e set s th e micr ocontr o lle r 7.15 .1 fea tures ? inter n a lly r e set s ch ip if no t p e rio d ically re load ed d u r i ng the p r og ra mma ble time- o u t pe r i od . ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 20 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller ? optiona l wa rnin g inter r u p t ca n be g ene ra te d at a pro g r a mm able time b e for e watch dog time-out . ? sof t war e en able s the wwdt , but a ha rdwa re r e set or a watchd og re set/in te rr up t is r equ ire d to disable th e wwdt . ? in co rr ec t fe e d se qu en ce c a u s e s r e s e t o r in te rr up t, if en ab le d. ? flag to indicate watchdog reset. ? pr ogr amm able 24- bit tim e r with inter nal p r escale r . ? sele ct able time p e r i od fro m (t cy( wdcl k) ? 25 6 ? 4) to (t c y ( w dclk ) ? 2 24 ? 4) in multiples of t c y ( w dclk ) ? 4. ? th e w a tch dog clock ( w dclk) sour ce ca n b e se lecte d fr om the irc o r th e d e d i ca te d watchdog oscillator (wd o ). the clock s o ur c e selection provi des a wide range of p o tential timing ch oices of watchd og op er ation u nde r dif f er ent po we r cond itio ns. 7.16 clocking and power control 7.16 .1 inte gra t ed osc illators the lpc1 1e1x include three i ndependent os cillators: the system osc illator , the internal rc os cillator (irc ), and the watchdog oscillato r . eac h osc illator can be used for more tha n one pur po se a s r equ ire d in a p a r t icula r ap plication . following reset, the lpc1 1e1x o perates from the internal rc os cillator until sof t w a re switche s to a dif f er ent clock sou r ce. the ir c allo ws the system to op er ate with out any e x ter n a l cr yst a l an d the bo otloa der co de to op er ate at a kn own freq ue ncy . see figure 6 for an overview of the lpc11e1x clock generation. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 21 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 7.16 .1 .1 int e rna l rc o scilla t or th e irc ca n be use d as the clock so urce for the wdt , an d/or a s the clock tha t dr ives th e system pl l and th en the cpu. the nom inal irc freq ue ncy is 1 2 mhz. up on p o w e r - u p , an y c h ip re se t, or wa ke- u p f r o m d e e p po we r- do wn m o d e , th e l p c1 1e1 x u s e the irc a s the clock so urce . sof t war e can later switch to on e of th e othe r availa ble clock sources. 7.16 .1 .2 sys t e m o scilla t or the sy stem oscillator can be used as the c l oc k s o urc e for the cpu , w i th or without using the pll. the system oscillator operates at frequenc ies of 1 m hz to 25 mhz. this frequency can be b oosted to a hig h e r fr eq uen cy , up to the m a ximum cpu o per ating fr equ en cy , by th e sys tem pll. 7.16 .1 .3 w a t c h dog os cillat or the watc hdog osc illator can be used as a clock source that directly drives the c p u, the watchdog timer , or the clkout pin. the watc hdog osc illator nominal frequenc y is p r og ra mma ble betwee n 7 . 8 khz and 1.7 mhz. th e freq ue ncy sp re ad over p r oce s sing an d temp er atur e is ? 40 % (see a l so ta b l e 1 3 ). fi g 6. lpc1 1 e 1 x c l oc k i n g g e ne rati on bl oc k d i a g ra m watchdog oscillator irc oscillator system clock divider sysahbclkctrln (ahb clock enable) cpu, system control, pmu memories, peripheral clocks ssp0 peripheral clock divider ssp0 ssp1 peripheral clock divider ssp1 usar t peripheral clock divider uart wdt wdclksel (wdt clock select) watchdog oscillator irc oscillator system oscillator clkout pin clock divider clkout pin clkoutuen (clkout update enable) 002aag687 system clock system pll irc oscillator system oscillator watchdog oscillator mainclksel (main clock select) syspllclksel (system pll clock select) main clock irc oscillator n www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 22 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 7.16 .2 syste m pll th e pll a c cep t s a n inpu t clock fr equ ency in th e ra nge of 1 0 mhz to 25 m h z. t he inp u t frequency is multiplied up to a high frequency with a c u rren t controlled osc illator (cco). th e multip lier can b e an in te ger va lue fro m 1 to 32. the cco op er ates i n th e ra nge o f 1 5 6 m hz to 32 0 m hz. t o su pp or t this fr equ en cy ra nge , an add itio na l d i vid e r kee p s the cco with in it s fre que ncy r a n ge while the pl l is p r ovid ing the d e sire d outpu t fre q u ency . th e ou tp ut d i vider ca n be set to d i vid e by 2, 4 , 8 , or 16 to pr odu ce th e ou tp ut clock. t he pll o u tpu t fre que ncy m u st be lo wer tha n 100 mhz. si nce th e minim u m ou tp ut divider valu e is 2 , it is insur ed tha t the pll o u tpu t ha s a 5 0 % d u ty cycle . th e pll is tu rn ed of f a nd byp a ssed follo win g a ch ip re set. sof t war e ca n en able th e pll later . the p r og ra m mu st config ure and activa te the pll, wait fo r the pll to lock, an d then co nne ct to th e pll as a clock source. the pll s e t t ling t ime is 100 ? s. 7.16 .3 clock output the lpc1 1e1x feature a c l ock output function that routes the irc os c illator , the sy stem os cillator , the w a tchdog os cillator , or the main clock to an output pin. 7.16 .4 w ake -up proces s the lpc1 1e1x begin operation by using the 12 mh z ir c oscillator as the clock s o urc e at p o wer - up and whe n awaken ed fr om deep p o wer - d o wn mo de . t h is m e chan ism a llows chip operation to resume quickl y . if the applic ation uses the main osc illator or the pll, sof t ware must enable these c o mp onent s and wait for them to st abilize. only then can the sys tem us e the p l l and main os c illator as a clock source. 7.16 .5 power control th e lpc1 1e1x su ppo rt va rio u s power co ntro l fea t ure s . the r e a r e fo ur spe c ia l m ode s o f p r oce s sor power re duction: slee p mod e , dee p - s le ep m ode , power - down mo de, an d dee p powe r - down mo de . th e cpu clo c k ra te ca n also be con t r o lle d as nee de d by cha ngin g clock sou r ces, r e con f ig ur ing pll va lues, a n d / o r alter i ng the cpu clo c k divide r value. this power cont r o l m e chan ism allo ws a tra de- of f of po wer ve rsus p r o c e s sin g spe ed b a sed o n app lication r equ ire m en t s . in ad dition, a r egister is pr ovide d for shu t tin g down the clo cks to in div i du al on -c hip p e r ip he ra ls. t h is re g i ste r allo ws fin e - tu n in g of p o we r con s u m ption by elimin ating all dyna mic power use in any pe rip her als that ar e n o t re quir e d for the a pplicatio n. sele cte d p e r i phe ra ls ha ve th eir o w n c l oc k d i vid e r w h ic h pr ov ide s ev en b e tte r po we r contr o l. 7.16 .5 .1 power pro f ile s th e po we r consum ption in active a n d sle ep mo des ca n be o p timized for th e app lication thr o u gh simple cal l s to th e po we r pr ofile. the p o wer co nfigur ation r o u t in e configu r e s the l p c1 1e1 x for o ne of th e followin g power mod e s: ? de fa ult m o d e co rr es po nd in g to po we r co nf igu r a tio n af t e r r e se t. ? cpu performance mode co rresponding to optimiz e d processing cap a bility . ? ef ficie ncy mod e co rr espo ndin g to op tim i ze d bala n ce of cur r e n t con s u m ption a nd cpu p e rfor ma nce. ? l o w-cur r e n t m ode co rr espo ndin g to l o west po wer con s u m ption . in addition, the power profile includes routines to select the optimal pll settings for a given system clock and pll input clock. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 23 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 7.16 .5 .2 sleep mo de whe n sleep m ode is enter ed , the clock to the cor e is sto ppe d. re su mption fr om the slee p mo de d oes no t ne ed an y spe c ia l se que nce bu t r e - ena bling th e clo c k to th e arm cor e . in sle e p m o de , ex ecu tio n of in str u c tio ns is su sp en ded u n til either a re se t or inter r u p t o c cur s . per i ph era l fu nctio n s co ntinue ope ra tio n du ring sle ep m ode a nd can g ene ra te in te rr upt s to ca use the pr ocessor to r e sume e x ecution . slee p mod e elimin ates dynam ic po we r us ed b y t h e p r o c e s s o r it se lf, by m e m o ry sys te ms a n d r e la te d co ntr o ller s , an d by in te rn al buses. 7. 16 .5 .3 dee p -s le ep mode in deep -slee p mod e , th e lpc1 1 e 1x is in slee p- mod e and all per iph e r a l clo c ks and a ll clock sources are of f ex cept for t h e i rc. th e irc outp u t is disab l ed un less the irc is selec t ed as input t o t h e w a tc hdog timer . in addit ion all analog blocks are shut down and the flash is in st an d- by mo de. in de ep -slee p m ode , th e a p p lica t io n ca n kee p th e watchdo g os cillator and the bod circ uit running for s e lf-timed wake-up and bod protection. th e lpc1 1e1x ca n wa ke up fro m de ep- sleep mod e via r e set, se lecte d gpio pin s , or a watchdo g timer in terr up t. dee p - s le ep mo de saves po we r an d allows fo r shor t wake- u p time s. 7.16 .5 .4 power- down mo de in power - d o wn mo de, th e lpc1 1e1x is in slee p- mod e and all per iph e r a l clo c ks and a ll clock sources are of f ex cept for w a tchdog os cillator if selec t ed. in addition all analog b l ocks an d th e fla s h are sh ut d o wn. in po we r- do wn m ode , the a ppli c a t io n ca n keep th e bod circuit ru nnin g fo r bod pr otecti on. th e lpc1 1e1x ca n wa ke up fro m po wer - do wn mod e via r e set, se lecte d gpio pin s , or a watchdo g timer in terr up t. powe r- down mo de r e d u ces p o wer co nsump t io n comp ar ed to deep -slee p mo de at th e e x p ense o f lon ger wa ke -u p times. 7.16 .5 .5 dee p powe r -d own mod e in deep power-down mode, power is shut of f to the entire chip except for the w akeup p i n. t he lpc1 1e1x ca n wake up fro m de ep p o wer - d o wn mod e via th e w akeup pin. th e lpc1 1e1x ca n be p r e v e n ted fr om en te rin g deep p o wer - d o wn mo de by settin g a lock b i t in the pm u b l ock. lo ckin g ou t dee p po we r- down m ode ena ble s the a p p lica t io n to keep the watchd og timer or the bod r unn ing a t all times. when entering deep power-down mode, an external pull-up resistor is required on the wakeup pin to hold it high. pull the reset pin high to prevent it from floating while in deep power-down mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 24 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 7.16 .6 syste m control 7.16 .6 .1 res et reset has four sources on the lpc11e1x: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a sch m itt trig ge r in put p i n. asse rtion of chip re set by a n y sour ce, on ce the ope ra tin g volt a g e att a in s a us ab le lev e l, st a r t s th e irc a n d initialize s the flash contr o ller . a low - go ing pu lse as sho r t as 50 ns re se t s the p a r t . whe n th e inter n a l rese t is r e mo ved, th e pr oc essor b egin s e x e c u t in g at add re ss 0, wh ich is initially th e re se t vector m app ed fro m th e bo o t blo ck. at th at p o in t, all of th e pr oc es so r a nd pe rip her al r egister s ha ve bee n in itialized to p r e deter min ed valu es. in deep power-down mode, an external pull-up resistor is required on the reset pin . 7.16 .6 .2 brownout det ect ion th e lpc1 1e1x include s fou r levels for mo nitor i ng the volt a g e o n th e v dd pin. if this volt a ge falls belo w o ne of th e four se lecte d levels, th e bod a s se rt s an inter r u p t sig n a l to th e nvic . t h is s i gn al ca n be e n a b l ed fo r int e rrupt in the interrupt ena b l e r e g i st er in th e nvic to cause a cpu interrupt. alternatively , so f tw a r e can m o nit o r th e sign a l by re a d in g a d edicated st a t u s r egister . fo ur a d d i tio nal thr e sho l d levels ca n be sele cte d to cau s e a forc ed reset of the chip. 7.16 .6 .3 code s e c urity ( c o de read pro t e c t i on - crp) crp pro v ides dif f er ent le ve ls o f se cu rity in th e s yst em so th at ac ces s to the on-chip flash a nd use o f the ser i al wire deb u g ger (swd) and in -system pr og ram m ing ( i sp) ca n be re st rict ed . p r o g r a m m i ng a s p e c ific p a tt er n in to a ded icated flash location invokes crp . iap com m an ds a r e n o t af fe cted by the crp . in ad dition , isp en try via the pio0 _1 p i n ca n be d i sa ble d witho u t ena blin g crp . for det a ils, see the lpc1 1 e xx user man ual . th er e ar e th re e levels of co de read pr otection : 1. crp 1 d i sa b l es ac ce ss t o th e ch ip v i a th e s w d a n d allo ws p a rtia l f l ash u p d a te ( e xclu din g fla s h se ctor 0) u s in g a limited set of th e isp comma nd s. this mod e is u s e f u l when crp is r equ ire d an d flash fi e l d u pda te s are ne ede d b ut all sector s ca nno t b e era s ed. 2. crp 2 d i sa b l es ac ce ss t o th e ch ip v i a th e s w d a n d on ly a llo ws f u ll fla s h er a s e an d u pda te u s ing a r edu ce d set o f the isp co mman d s. 3. running an application with level crp3 selected , fully disables any access to the chip via the swd pins and the isp. this mode effectively disables isp override using pio0_1 pin as well. if necessary, the application must provide a flash update mechanism using iap calls or using a call to the reinvoke isp command to enable a flash update via the usart. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 25 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller in addition to the three crp lev e ls , sampli ng of pin pio0 _1 for valid user cod e ca n be d i sa bled . fo r de t a ils, see th e lpc1 1 e xx user m anu al . 7.16 .6 .4 apb int erf ace the apb peripherals are located on one apb bus. 7.16 .6 .5 ahbl i t e t h e ahbl ite con n e c t s th e cpu bu s of th e arm co rt ex -m 0 t o th e f l as h m e m o ry , t h e ma in st atic ram, and th e rom. 7. 16 .6 .6 ext er n al int er r upt i n p u t s all gpio pins can be level or edge s e nsitiv e interrupt input s. 7.17 emulation and debugging deb ug fun c tion s ar e inte gra t ed into the arm co rte x - m 0. ser i al wir e debu g fu ncti ons ar e sup por ted in a ddition to a st an da rd jt ag b o u nda ry scan . th e arm cor t ex-m 0 is con f ig ur ed to supp or t up to fou r brea kp oint s an d two watch poin t s. the reset pin select s between the jtag boundary scan (reset = low) and the arm swd debug (reset = high). t he arm swd de bug p o r t is d i sable d while the lp c1 1e1x is in reset. t o pe rfor m bo und ar y sca n testin g, fo llow the s e step s: 1 . er ase any user co de r e sidin g in fla s h . 2 . power up the part with the reset p i n pu lled high e x ter n a lly . 3. w ait for at least 250 ? s. 4. pull the reset pin low e x ter n a lly . 5 . per f or m b o u nda ry scan ope ra tio n s. 6 . once the boundary scan operations are completed, assert the trst p i n to en ab le th e swd d ebug mode, and release the reset pin (pull high). remark: the jtag interface cannot be used for debug purposes. c aution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 26 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 8. limiting values [1] t he following app lies t o the limiting values: a) t his prod uct includ es cir c ui tr y designed for the pro tection of it s in ternal dev ices from the damaging ef fect s of excessive st atic charge . nonetheless, it is suggested tha t conventional precautions be t aken to avoid applying gr eater th an the ra ted maximum. b) para meters are valid over opera t ing te mperatur e rang e unless other wise specifi ed. all volt ages are w i th r esp ect to v ss unless other wise n oted. [2] inclu ding volt age on output s in 3-st ate mode. [3] t he peak cur r ent is limited to 25 times the corre spond ing ma ximum curren t. [4] t he maximum non -oper ating stor age temper ature is dif fer ent t han the temperatu r e for required shelf life w hich can be dete r mi n ed based on r equired shelf lifetime. refer to the je dec spec (j-std -033b.1) for fur ther d et ails. [5] h uma n body model: equivalent to dischar gin g a 100 pf ca p acitor through a 1.5 k ? ser i es resi stor . t a ble 4. l i miting v a lues in accorda n ce with th e ab solute ma ximum rating system (iec 6013 4). [1] symbol parameter conditions min max unit v dd su ppl y volt ag e (co r e a nd exte rn al rail ) 1.8 3.6 v v i inpu t volt age 5 v tole rant i/o pi ns; on ly va lid w h en th e v dd supply volt age is presen t [2 ] ? 0.5 + 5.5 v i dd supply current per supply pin [3] -1 0 0 m a i ss ground current per ground pin [3] -1 0 0 m a i la tch i/ o la tch-u p cu rre nt ? (0.5v dd ) < v i < (1.5v dd ); t j < 12 5 ? c -1 0 0 m a t stg storage temperat ure non-operating [4] ? 65 + 150 ? c t j ( max ) ma xi mum ju nction tempera t ure - 1 5 0 ? c p t o t( p a ck ) tot a l po wer dissip a ti on (per p a ckage ) base d on p a ckag e he at tra n sfer , n o t d e v ic e po w e r co n s um pt io n -1 . 5 w v esd electrostatic discharge voltage human body model; all pins [5] ? 6500 +6500 v www.datasheet.net/ datasheet pdf - http://www..co.kr/ lpc11e1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 20 february 2012 27 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 9. static characteristics table 5. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) 1.8 3.3 3.6 v i dd supply current active mode; v dd =3.3v; t amb =25 ? c; code while(1){} executed from flash; system clock = 12 mhz [2] [3] [4] [5] [6] -2-ma system clock = 50 mhz [3] [4] [5] [6] [7] -7-ma sleep mode; v dd = 3.3 v; t amb =25 ? c; system clock = 12 mhz [2] [3] [4] [5] [6] -1-ma deep-sleep mode; v dd = 3.3 v; t amb =25 ? c [3] - 360 - ? a power-down mode; v dd =3.3v; t amb =25 ? c -2- ? a deep power-down mode; v dd =3.3v; t amb =25 ? c [8] - 220 - na standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled -0.510na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -0.510na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled -0.510na v i input voltage pin configured to provide a digital function [9] [10] [11] 0- 5.0v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage 2.0 v ? v dd ? 3.6 v; i oh = ? 4 ma v dd ? 0.4--v 1.8 v ? v dd < 2.0 v; i oh = ? 3 ma v dd ? 0.4--v v ol low-level output voltage 2.0 v ? v dd ? 3.6 v; i ol =4 ma --0.4v 1.8 v ? v dd < 2.0 v; i ol =3 ma --0.4v i oh high-level output current v oh =v dd ? 0.4 v; 2.0 v ? v dd ? 3.6 v ? 4--ma 1.8 v ? v dd < 2.0 v ? 3--ma www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 28 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller i ol low - le ve l output cu rrent v ol =0 . 4 v 2.0 v ? v dd ? 3.6 v 4--ma 1.8 v ? v dd < 2 . 0 v 3 --m a i ohs hi gh-level s h ort- cir cuit output current v oh =0v [1 2] -- ? 45 ma i ols low - le ve l short-ci rcu it output current v ol =v dd [1 2] --5 0 m a i pd pull - down curren t v i = 5 v 1 05 01 5 0 ? a i pu pull - up current v i =0v ; 2.0 v ? v dd ? 3.6 v ? 15 ? 50 ? 85 ? a 1.8 v ? v dd < 2. 0 v ? 10 ? 50 ? 85 ? a v dd lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 30 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller [1] t he adc is mo notonic, the r e ar e no missing codes. [2] t he dif f er entia l line arity er ror (e d ) is the dif fe r ence betwee n the actual step wid th and the ideal step wid th. see f i gur e 7 . [3] t he int egral non-linearity (e l( ad j) ) is the pe ak dif ference betw een the center of the st ep s of the actual and the ideal tran sfer cu rve af ter appropriate adjustment of gain and offset errors. see figure 7 . [4] t he of fset e rror (e o ) is t he absolute dif f ere nce be tween the str a ight line which fit s the actual cu rve and the str aight line which fit s the ideal curve. see figure 7 . [5] t he gain err or (e g ) is the re lative dif fer ence in per cen t between t he str aight line fitting the actual transfe r cur v e af ter r emoving of fset error, and the straight line which fits the ideal transfer curve. see figure 7 . [6] t he absolute erro r (e t ) is the maximum dif fer ence between th e cent er of the st ep s of th e actu al tr ansfer curve of the n on-calibr ated adc and the ideal transfer curve. see figure 7 . [7] t amb = 25 ? c ; maximum sampling f r equency f s = 400ks a mples/s and analog input cap a cit ance c ia = 1 p f . [8] input resist ance r i d epends on the sampling frequency fs: r i = 1 / (f s ? c ia ). t a ble 6. adc s t a t ic ch ara c teristics t amb = ? 40 ? c to +85 ? c unless otherwise specified; adc frequency 4.5 mhz, v dd = 2.5 v to 3.6 v. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dd v c ia a nal og inp ut cap acit ance - - 1 pf e d d i f f erential li nea rity error [1] [2] -- ? 1l s b e l(adj) integral non-linearity [3] -- ? 1.5 l sb e o offset error [4] -- ? 3.5 l sb e g gain error [5] --0 . 6 % e t absolute error [6] -- ? 4l s b r vsi vo lt a ge source in te rface res i st ance --4 0 k ? r i i nput resist ance [7] [8] --2 . 5 m ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 31 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller (1) e xample of an actual transfer cur v e. (2) t he ide al tr ansfer curve. (3) d if ferential linear ity err or ( e d ). (4) i nteg ral non-lin earity ( e l( ad j) ). (5) c en ter of a step of the actual t r ansfer curve. f i g 7 . adc c h ar acter is tics 002aaf426 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd ? v ss 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb = www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 32 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 9.1 b od st atic characteristics [1] inter rupt levels are selected by writing the le vel value to the bod co ntrol register bodct rl, see the lpc1 1exx user manual . 9.2 p ower consumption powe r me asur eme n t s in active , sle e p , a nd de ep- sleep mod e s wer e pe rfor me d un der the follow ing conditions (see the l p c1 1exx u s er ma nu al ): ? con f ig ur e all pin s as gpio with p u ll- up r e sisto r disab l ed in the iocon blo c k. ? con f ig ur e gpio pin s as outp u t s u s in g the gpion d ir re giste r s. ? w r ite 0 to all gpionda t a re gister s to dr ive th e outpu t s l o w . t a ble 7. bod s t a t ic ch ara c teristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th thresh old volt ag e i nterrupt level 0 a sserti o n - 1.65 - v de-assertion - 1.80 - v in te rru p t l e ve l 1 a sserti o n - 2.22 - v de-assertion - 2.35 - v in te rru p t l e ve l 2 a sserti o n - 2.52 - v de-assertion - 2.66 - v in te rru p t l e ve l 3 a sserti o n - 2.80 - v de-assertion - 2.90 - v re se t le vel 0 a sserti o n - 1.46 - v de-assertion - 1.63 - v re se t le vel 1 a sserti o n - 2.06 - v de-assertion - 2.15 - v re se t le vel 2 a sserti o n - 2.35 - v de-assertion - 2.43 - v re se t le vel 3 a sserti o n - 2.63 - v de-assertion - 2.71 - v www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 33 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v ; active mode entere d executing co de wh ile(1 ) { } from fla s h; inte rnal pull- up resistor s d i sable d; bod disabled; all per ip herals d i sabled in t he sys ah b c lkctr l regist er; all peripher al clocks disabled; low-curr ent mode. ( 1) s ystem oscillato r and syste m pll disabled; irc e nable d. ( 2) s ystem oscillato r and syste m pll enabled; irc disable d. fig 8. t y pical sup p l y cu rre nt ver sus r e gu lator s u p p ly volt ag e v dd in ac ti ve m o de conditions: v dd = 3.3 v ; active mode entere d executing co de wh ile(1 ) { } from fla s h; inte rnal pull- up resistor s d i sable d; bod disabled; all per ip herals d i sabled in t he sys ah b c lkctr l regist er; all peripher al clocks disabled; low-curr ent mode; usb _ dp and usb_dm p ulled low exte rnally . ( 1) s ystem oscillato r and syste m pll disabled; irc e nable d. ( 2) s ystem oscillato r and syste m pll enabled; irc disable d. fig 9. t y pical sup p l y cu rre nt ver sus te mpe ratur e in a c tiv e mod e v dd (v) 1.8 3.6 3.0 2.4 002aag749 3 6 9 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) temperature (c) -40 85 35 10 60 -15 002aag750 3 6 9 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 34 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v ; sle ep mode enter ed fr om flash; intern al pull-up r esistors disabled; bod disabled; al l peripherals disa bl ed in the sysa h b clkc tr l regi ster; all peripher al cl ocks di sabled; lo w-curr ent mode. ( 1) s ystem oscillato r and syste m pll disabled; irc e nable d. ( 2) s ystem oscillato r and syste m pll enabled; irc disable d. fig 10 . t y p ical sup p l y cu rre nt ver sus te mpe ratur e in slee p mod e conditions: b o d disabl e d ; al l oscill ators a nd analog blocks turned o f f in the pdsleepcfg register . fig 1 1 . t y p ical sup p l y cu rre nt ver sus te mpe ratur e in d eep -sleep mo d e 002aag751 temperature (c) -40 85 35 10 60 -15 1 3 2 4 i dd (ma) 0 12 mhz (1) 36 mhz (2) 48 mhz (2) 24 mhz (2) 002aag745 temperature (c) -40 85 35 10 60 -15 355 375 365 385 i dd (a) 345 v dd = 3.6 v v dd = 3.3 v v dd = 2.0 v v dd = 1.8 v www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 35 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 9.3 p eripheral power consumption th e sup p ly cu rr en t p e r per iph e r a l is me asur ed a s th e dif f er ence in supp ly cu rr ent b e twe e n the p e r i phe ra l b l ock e nab led a nd the p e ri phe ra l b l ock d i sa bled in th e sysahbclkcfg and pdr uncfg (for analog block s ) regis t ers. all other bloc ks are dis a bled in both r egister s a nd no co de is e x ecuted. me a s ure d on a typical samp le at t amb =2 5 ? c. unless noted otherwise, the s ystem oscillator an d pll are running in both measurement s. th e supp ly cur r e n t s a r e sho w n fo r system clock fr equ encie s of 12 mhz a n d 4 8 mhz. conditions: b o d disabl e d ; al l oscill ators a nd analog blocks turned o f f in the pdsleepcfg register . fig 12 . t y p ical sup p l y cu rre nt ver sus te mper atur e in powe r-down mode fig 13 . t y p ical sup p l y cu rre nt ver sus te mpe ratur e in d eep p o wer - d o wn mo de 002aag746 temperature (c) -40 85 35 10 60 -15 5 15 10 20 i dd (a) 0 v dd = 3.6 v , 3.3 v v dd = 2.0 v v dd = 1.8 v 002aag747 temperature (c) -40 85 35 10 60 -15 0.2 0.6 0.4 0.8 i dd (a) 0 v dd = 3.6 v v dd = 3.3 v v dd = 2.0 v v dd = 1.8 v www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 36 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller t a bl e 8. pow er co ns ump t io n fo r i n di vi du al a n al o g an d di gi t al b l ock s peripheral typical supply current in ma notes n/a 12 mhz 48 mhz irc 0 .2 7 - - system oscillator running; pll off; independent of main clock frequency. system os cillator at 12 mhz 0 . 2 2 - - i rc run n ing ; pll o f f; inde pen dent of ma in clock freq uency . w a tchdo g oscillator at 50 0 k hz/2 0 . 0 0 4 - - s ystem oscilla to r run n ing ; pll of f; i ndep end ent o f main clo ck frequ ency . bod 0 .0 51 - - i nd epe nden t of ma in clock freq uen cy . mai n pl l - 0.21 - - adc - 0.08 0.29 - cl kout - 0 .12 0 .47 m a i n clock divid ed by 4 in th e clkou t div re gister . ct 16b0 - 0.02 0.06 - ct 16b1 - 0.02 0.06 - ct 32b0 - 0.02 0.07 - ct 32b1 - 0.02 0.06 - gpio - 0 .23 0 .88 g pio pin s con f ig ured as ou tpu t s and se t to l o w . direction a nd pin st ate are maint a in ed if the gpio is disabled in the sysahbclkcfg re gister . io co nfi g - 0 .03 0 .10 - i2c - 0.04 0.13 - rom - 0.04 0.15 - spi0 - 0.12 0.45 - spi1 - 0.12 0.45 - uar t - 0 .22 0 .82 - wwdt - 0 .02 0 .06 main clock s e lect ed as clock source for the wdt . www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 37 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 9.4 e lectrical p i n characteristics conditions: v dd = 3.3 v ; on pin pio0_7. fig 14 . h igh- drive o u tp ut: t y p i cal h i gh-le vel ou tput vo lt a g e v oh ve rsu s high-leve l ou tpu t c u rr en t i oh . conditions: v dd = 3.3 v ; on pins pio0_ 4 and pio0_5. fi g 15 . i 2 c-bu s pi ns (h ig h cu rre n t s ink ): t y pi c a l lo w - le ve l ou tpu t c u rre n t i ol ver sus low - leve l o u tpu t volt age v ol i oh (ma) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ? 40 c v ol (v) 0 0.6 0.4 0.2 002aaf019 20 40 60 i ol (ma) 0 t = 85 c 25 c ? 40 c www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 38 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v ; st andar d port pins and pio0_7. fig 16 . t y p ical low - l eve l ou tpu t c u rr ent i ol versu s lo w -level ou tpu t vo lt age v ol conditions: v dd = 3.3 v ; st andar d port pins. fig 17 . t y p ical high-leve l ou tpu t v o lt a g e v oh v e rs us high-lev el o u tp ut sou r c e c u r r en t i oh v ol (v) 0 0.6 0.4 0.2 002aae991 5 10 15 i ol (ma) 0 t = 85 c 25 c ? 40 c i oh (ma) 0 24 16 8 002aae992 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ? 40 c www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 39 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v ; st andar d port pins. fig 18 . t y p ical pu ll-up cur r en t i pu ver su s in pu t v o lt a g e v i conditions: v dd = 3.3 v ; st andar d port pins. fig 19 . t y p ical pu ll-do w n cur r en t i pd ver sus in pu t vo lt a g e v i v i (v) 0 5 4 23 1 002aae988 ? 30 ? 50 ? 10 10 i pu ( a) ? 70 t = 85 c 25 c ? 40 c v i (v) 0 5 4 23 1 002aae989 40 20 60 80 i pd ( a) 0 t = 85 c 25 c ? 40 c www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 40 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 10. dynamic characteristics 10.1 f lash memory [1] n umber of pro gram/er ase cycles. [2] p rogr amming times are given for writing 256 bytes from ram to the flash. dat a must be w r itten to the flash in blocks of 256 bytes. 10.2 e xternal clock [1] p aramete r s are valid over operating temp e r atur e range u nless otherw i se specified. [2] t ypical ratings are not guarante ed. the va lues list ed are at room tempe r atur e (25 ? c), nominal supply vo lt ag es. t a ble 9. flas h ch arac teristics t amb = ? 40 ? c to + 8 5 ? c, unle s s othe rwise specifie d. symbol parameter conditions min typ max unit n en du en duran ce [1] 10000 100 0 00 - cycles t re t retentio n ti me pow ered 10 - - years unp owere d 20 - - years t er e r as e ti me se cto r or mu lt i p l e consecu t i v e se ctors 95 10 0 105 ms t pr og programming time [2] 0.95 1 1 .05 m s t a ble 10. eeprom characteristics t amb = ? 40 ? ct o+ 8 5 ? c; v dd = 2 .7 v t o 3 .6 v . ba sed on jedec nvm q uali f i c a t i on. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit f clk cl ock freq uency 2 00 375 4 0 0 k hz n en du endu rance 1 00 000 1 0 00 000 - cycles t re t re te ntion time p o were d 1 0 0 200 - y ears u npo wered 1 50 300 - y ears t er erase ti me 6 4 byte s - 1.8 - ms t pr og programmin g time 64 bytes - 1.1 - ms table 11. dynamic characteristic: external clock t amb = ? 40 ? c to +85 ? c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscil l ator freq uen cy 1 - 2 5 mhz t cy ( cl k) cloc k cycle time 40 - 1 000 ns t chcx cloc k high time t cy( clk) ? 0.4 - - n s t clcx cloc k low time t cy( clk) ? 0.4 - - n s t clch cloc k rise time - - 5 n s t chcl clock fall time - - 5 ns www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 41 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 10.3 i n t ernal o scillators [1] p aramete r s are valid over operating temp e r atur e range u nless otherw i se specified. [2] t ypical ratings are not guarante ed. the va lues list ed are at room tempe r atur e (25 ? c), nominal supply vo lt ag es. [1] t ypical ratings are not guarante ed. the va lues list ed are at nom ina l supply volt ages. fig 20 . e xter nal clock timing (with a n amp l itu d e o f at least v i( rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 t a ble 12. dyn a mic ch ar a c teristics: ir c t amb = ? ? ? ? ? symbol parameter conditions min typ [2] max unit f osc ( rc) i n te rnal rc oscil l ator frequ ency - 1 1. 88 1 2 12 .1 2 m h z conditions: freq uency valu es ar e typical values. 12 mhz ? 1 % accur acy is gu aranteed for 2.7 v ? v dd ? 3.6 v and t amb = ? 40 ? c to +85 ? c. v ariations betw een p art s may cause t he ir c to fall out side the 12 mhz ? 1 % accuracy specification for volt ages below 2.7 v . fig 21 . i ntern a l rc osc i llator freq u e nc y ver sus temp er atur e t a ble 13. dyn a mic ch arac terist ics: w a tch d o g os cillato r symbol pa rame te r conditions min typ [1] max un it f os c(in t) i n ternal osci llator frequ ency divsel = 0x1f , freqs el = 0x1 in the wdtoscctrl register; [2] [3] -7.8-khz divsel = 0x00, freqsel = 0xf in t h e wd t o sc ct r l re gi st er [2 ] [3] - 1700 - khz 002aaf403 11.95 12.05 12.15 f (mhz) 11.85 temperature ( c) ? 40 85 35 10 60 ? 15 vdd = 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v 2.0 v www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 42 of 61 nxp semiconductors lpc1 1e1x 32-bit arm cortex-m0 microcontroller [2] t he typical fr equency spr ead over pr ocessing and temper ature ( t am b = ? 40 ? c t o +8 5 ? c) is ? 40 % . [3] s ee the lpc1 1exx user manu al. 10.4 i /o pins [1] a ppli e s to st andard port p i ns and reset pin. 10.5 i 2 c-bus [1] s ee the i 2 c- bus specification um1020 4 for det ails. [2] p ara m eters are valid over opera t ing te m peratur e rang e unle s s other wise specified. [3] thd ;da t is the dat a h old time that is measured fr om the fa lling edg e of scl; app lies t o dat a in tran smission and the a c knowl edge. [4] a device must internally pr ovide a h old time of at least 300 n s for the sda sign al ( w ith respect to the v ih (min) o f the scl sign al) to br idge the undefined r egion of the falling edge of scl. [5] c b = tot a l cap a cit a n c e of one bus line in pf . [6] t he maximum t f for the s d a and scl bus lines is s pecif ied at 300 ns. the maximum fall time for the sda o utput st ag e t f is specified at 250 n s . t his allow s series prote c tion re sistor s to be connected in between th e sda and the scl pins and th e sda/scl bus lines without exceeding the maximu m specified t f . t a ble 14. dyn a mic ch ara c teristics: i/o p i n s [1 ] t amb = ? 40 ? c to + 8 5 ? c; 3.0 v ? v dd ? 3.6 v . symbol parameter conditions min typ max unit t r rise ti me pin con f ig ured as outpu t 3 .0 - 5 .0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 15. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit f scl scl cloc k frequency s t and ard-mode 0 1 00 khz fa st-m od e 0 40 0 k h z f a st-mo de plus 0 1 mhz t f fall time [4 ] [5] [6] [7] of both sda and scl si gnal s standard-mode -3 0 0 n s f a st-mo d e 2 0 + 0.1 ? c b 30 0 ns f a st-mo de plus - 1 20 n s t lo w low pe ri od of the scl cloc k s t andard-mode 4 . 7 - ? s fast-m ode 1 .3 - ? s f a st-mo de plus 0 . 5 - ? s t hi gh hi gh p eriod of th e scl cloc k s t andard-mode 4 . 0 - ? s fast-m ode 0 .6 - ? s f a st-mo de plus 0 . 26 - ? s t hd; da t da t a ho ld time [3 ] [4] [8] s t and ard-mode 0 - ? s fast-m ode 0 - ? s f a st-mo de plus 0 - ? s t su;d a t da t a set-up time [9 ] [10] s t and ard-mode 2 5 0 - n s fast-m ode 1 00 - n s f a st-mo de plus 5 0 - n s www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 43 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller [7] in f ast -mode plus, fall time is specified the same for bot h output st ag e and bus timing. if se r i es resistor s are used, desig ners should allow for this when c onside r in g bus timing. [8] t he maxi mum t hd ; d a t could be 3.45 ? s and 0.9 ? s for s t andar d-mode a nd fast-mo de but must be less than t he maximum of t vd ;d a t or t vd ;a ck by a transit ion time (see um10204 ) . t his maximum must only be met if th e device does not stretch the low per iod (t low ) of the scl signal. if the clock str etch es the scl, the dat a must be va lid by the set-up time befor e it release s the clock. [9] tsu;d a t is the dat a set-up time tha t is measured w i th respec t t o the rising ed ge of scl; app lies to dat a in tran smission and the ackn owle dge. [10] a fa st- m ode i 2 c-bus device can be used in a s t andar d-mode i 2 c- bus syste m but the r equir ement t su ;d a t = 25 0 ns mu st the n be met. t his will automatically be the case if the device does not stretch the low period of the scl signa l. if such a device does stre t c h the low per iod of the scl sig nal, it must output t he next dat a bit to t he sda lin e t r( max) + t su ;d a t = 1000 + 250 = 12 50 ns (a ccording to the s t andar d-mode i 2 c- bus specification) befor e the scl line is r eleased. al so the acknow ledg e timing must meet this set- up time. fi g 22 . i 2 c-bu s pi ns c lo c k t imin g 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 44 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 10.6 s sp interface [1] t cy(clk) = (s spclkdiv ? (1 + scr ) ? cpsdvsr) / f ma in . t he cl oc k cy cl e ti me deri v ed fr om the spi bit rate t cy(clk) is a function of the main clock freq uency f ma in , the spi peripheral cl ock divi der (ssp c l kdiv), the spi sc r p aramete r (specified i n the ssp0cr0 reg i ster), and t he spi cpsdvsr p ar ameter ( s pe cified in th e sp i clock pr escale register). [2] t amb = ? 40 ? c to 85 ? c. [3] t cy(clk) = 12 ? t cy(pclk ) . [4] t amb = 25 ? c ; for nor mal volt age supply range: v dd = 3.3 v . t a ble 16 . dy n am ic ch ar acter istics o f spi p i ns in spi mo de symbol parameter conditions min typ max unit spi master (in spi mode) t cy( clk) clock c ycle time full-duplex mode [1] 50 - - ns whe n only tra n smitti ng [1] 40 ns t ds dat a set-u p ti me in spi mod e 2.4 v ? v dd ? 3.6 v [2] 15 - - ns 2.0 v ? v dd < 2. 4 v [2] 20 ns 1.8 v ? v dd < 2. 0 v [2] 24 - - ns t dh dat a hol d time in spi mod e [2] 0- - n s t v( q) dat a outpu t valid time in spi mod e [2] -- 1 0 n s t h( q) dat a outpu t hol d time in spi mod e [2] 0- - n s spi slave (in spi mo de) t cy( pclk) pclk cycl e time 20 - - n s t ds dat a set-u p ti me in spi mod e [3] [4] 0- - n s t dh dat a hol d time in spi mod e [3] [4] 3 ? t cy ( p c l k ) + 4 - - n s t v( q) dat a outpu t valid time in spi mod e [3] [4] -- 3 ? t cy (pcl k) + 1 1 n s t h( q) dat a outpu t hol d time in spi mod e [3] [4] -- 2 ? t cy(pclk) + 5 ns www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 45 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller fig 23. ssp master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 46 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller fig 24. ssp slave timing in s pi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) d a t a v alid d a t a v alid cpha = 1 cpha = 0 002aae830 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 47 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 1 1 . application information 1 1 .1 xt al input the input volt age to the on-chip oscillators is limited to 1.8 v . if the os cillator is driven by a clock in slave mo de , it is re co mme nde d that th e inpu t b e cou pled th ro ug h a cap acitor wi th c i = 1 00 pf . t o lim it the in put vo lt ag e to the sp ecifie d ra ng e, cho o se an a d d i tio nal cap a citor t o ground c g which a t ten u a t e s the inpu t vol t age by a facto r c i /(c i + c g ). in slav e mo de , a min i mum o f 20 0 mv(rms) is ne ede d. in s l av e mo d e , co u p le t h e inp u t c l ock s i gn al wit h a ca p a cito r o f 1 0 0 pf ( fig u r e 25 ), with an a m plitud e betwee n 200 mv(rms) a nd 10 00 m v ( r m s ) . t h is s i gn al co rr esp o n d s to a squ a r e wa ve sig nal with a sig n a l swing o f be twee n 28 0 mv and 1 . 4 v . th e xt alout pin in this co nfigu r a t io n ca n be le f t u n conn ected. external components and models used in oscillation mode are shown in figure 26 and in ta b l e 1 7 and ta b l e 1 8 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (l, c l and r s represent the fundamental frequency). capacitance c p in figure 26 represents the parallel package capacitance and must not be larger than 7 pf . parameters f osc , c l , r s and c p are supplied by the crystal manufacturer. fig 25 . s la ve mo de o p er ation o f th e on -chip o scillato r lpc1xxx xt alin c i 100 pf c g 002aae788 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 48 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 1 1 .2 xt al printed-circ uit bo ard (pcb) layout g u idelines follow thes e guidelin es fo r p c b la yo ut : ? connect the cryst al on the pcb as c los e as pos s ible to the oscilla tor input and output pin s of th e ch ip. ? t a ke car e th at th e load ca p a citor s c x1 , c x2 , an d c x3 in case o f thir d over to ne cryst al u s e h a ve a commo n gr ou nd pla n e . fig 26 . o s c illato r mod es an d mo dels: os cillation m o d e of op era t io n an d exter na l cry s t a l mo del use d for c x1 /c x2 eva lu ation t a ble 17. rec o mme nd ed v alu es fo r c x1 /c x2 in os cillation m o d e (c rys t a l an d exte rna l compone n t s p a r a me te rs) low fre q uenc y mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s exter n al lo ad cap acitor s c x1 , c x2 1 m hz - 5 m h z 10 pf < 300 ? 18 pf , 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf , 57 pf 5 m hz - 10 mhz 10 pf < 300 ? 18 pf , 18 pf 20 pf < 200 ? 39 pf , 39 pf 30 pf < 100 ? 57 pf , 57 pf 10 mhz - 1 5 mh z 10 pf < 160 ? 18 pf , 18 pf 20 pf < 60 ? 39 pf , 39 pf 15 mhz - 2 0 mh z 10 pf < 80 ? 18 pf , 18 pf t a ble 18. rec o mme nd ed v alu es fo r c x1 /c x2 in os cillation m o d e (c rys t a l an d exte rna l compone n t s p a r a me te rs) hi gh freq uen cy mo de fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s exter n al lo ad cap acitor s c x1 , c x2 15 mhz - 2 0 mh z 10 pf < 180 ? 18 pf , 18 pf 20 pf < 100 ? 39 pf , 39 pf 20 mhz - 2 5 mh z 10 pf < 160 ? 18 pf , 18 pf 20 pf < 80 ? 39 pf, 39 pf 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xt al = c l c p r s l www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 49 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller ? con nect th e exte rn al co mpo n e n t s to the g r o und p l ain . ? t o keep p a rasitics an d the no ise co uple d in via th e pcb as small as possible , kee p lo op s as small as possible . ? choo se sma ller va lues of c x1 an d c x2 if p a rasit ics of the pcb layout increase. 1 1 .3 s t andard i/o p a d configuration figure 27 sho w s th e po ssib le pin mo des for st an dar d i/o p i ns with a nalo g inp u t fun c tio n : ? digit al output driver ? digit al input: pull-up enabled/disabled ? digit a l in pu t: pull-d o wn en ab led/disa bled ? digit a l in pu t: re pea ter mo de e nab led / d i sa bled ? ana l og in put fi g 27 . s t a nda rd i/o p a d c o nfi gu r a t io n pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input 002aaf695 pin configured as digital output driver pin configured as digital input pin configured as analog input 10 ns rc glitch filter www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 50 of 61 nxp semiconductors lpc1 1e1x 32-bit arm cortex-m0 microcontroller 1 1 .4 reset p a d con f iguration 1 1 .5 adc u sage notes th e following guid e line s sho w h o w to incr ease the p e r f o r m ance of the adc in a n o isy en vir o n m en t be yo nd t h e ad c s p ecific ations lis ted in ta b l e 6 : ? th e adc inp u t tr ace must b e shor t a nd a s close as possible to the l p c1 1e1 x chip. ? shield the a dc input trac es fro m fa st switchin g digit a l sig nals an d noisy power supply lines. ? th e adc a nd the dig i t a l cor e shar e the sa me p o wer su pply . th er efor e, filter the p o wer sup p ly lin e ad equ ately . ? to improve the adc performance in a noisy environment, put the device in sleep mode during the adc conversion. fig 28 . res et p a d co n f ig ura t io n v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 51 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 12. package outline f i g 2 9 . p ac kag e ou tline hvqfn 33 (7 x 7 x 0 . 8 5 mm) references outline version european projection issue date iec jedec jeita - - - hvqfn33_po 09-03-17 09-03-23 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 0.65 4.55 0.75 0.60 0.45 0.1 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm a 1 b 0.35 0.28 0.23 cd (1) d h e (1) e h 4.85 4.70 4.55 ee 1 e 2 4.55 lv 0.1 w 0.05 y 0.08 y 1 0 2.5 5 mm scale terminal 1 index area b a d e c y c y 1 x detail x a 1 a c b e 2 e 1 e e a c b v c w terminal 1 index area d h e h l 9 16 32 33 25 17 24 8 1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 52 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller f i g 3 0. p ac kag e ou tline l q f p 48 (sot 313 -2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 53 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller f i g 3 1. p ac kag e ou tline l q f p 64 (sot 314 -2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 54 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 13. soldering f i g 3 2. re f lo w so ld erin g for the h v qfn 33 (7x7 ) p a cka ge footprint information for reflow soldering of hvqfn33 package 001aao134 occupied area solder land solder resist solder land plus solder paste solder paste deposit dimensions in mm remark: stencil thickness: 0.125 mm e = 0.65 evia = 4.25 owdtot = 5.10 oa pid = 7.25 p a+oa oid = 8.20 oa 0.20 sr chamfer (4) 0.45 dm evia = 1.05 w = 0.30 cu evia = 4.25 evia = 2.40 lbe = 5.80 cu lbd = 5.80 cu pie = 7.25 p a+oa lae = 7.95 cu lad = 7.95 cu oie = 8.20 oa owetot = 5.10 oa ehs = 4.85 cu dhs = 4.85 cu 4.55 sr 4.55 sr b-side (a-side fully covered) number of vias: 20 solder resist covered via 0.30 ph 0.60 sr cover 0.60 cu sehtot = 2.70 sp sdhtot = 2.70 sp gape = 0.70 sp spe = 1.00 sp 0.45 dm spd = 1.00 sp gapd = 0.70 sp www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 55 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller f i g 3 3. re f lo w so ld erin g for the l q f p 48 p a cka ge sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ay by p1 d2 (8 ) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 56 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller f i g 3 4. re f lo w so ld erin g for the l q f p 64 p a cka ge sot314-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp64 package ax bx gx gy hy hx ay by p1 p2 d2 (8 ) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 13.300 13.300 10.300 10.300 p1 0.500 p2 0.560 0.280 c 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 57 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 14. abbreviations t a ble 19. ab bre v iatio n s acronym de scr ip tio n a/d a na log - to-di g it al adc a na log - to-di g it al con v erte r ahb a dva n ced hig h-performan c e bu s apb adva nced perip heral bus bod b rown ou t detection bsdl b ou nda ry scan descrip ti on lan gua ge gpio gene ral purpose inpu t/outp ut jt a g joint t e st ac tion group pll p ha se-locked l oop rc re sisto r -c ap acitor spi seri al periph eral interfa c e ssi seri al synchron ous in terface ssp synchr onous serial port t a p t est ac cess port usart universal synchronous asynchronous receiver/transmitter www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 58 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 15. revision history t a b le 2 0 . r ev is i on hi st ory document id release date data sheet status change notice su pe rsed es lpc11e1x v.1 20120220 product data sheet - - www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 59 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller 16. legal information 16.1 dat a sheet st atus [1 ] p le ase con s ul t t h e mo st r e cent ly iss ued do cum e n t b e fo r e i n i t i a ti ng or co mp l e ti ng a de sig n . [2 ] t h e te r m ? sh o r t d a t a sh ee t? is e xplaine d i n secti o n ?de finition s?. [3 ] t h e pr od uct st a tus o f de vice ( s ) d e scr i bed i n th is d o cu me nt m a y h a ve cha nge d si nce thi s d o cum e nt w a s p u b l i s h e d a n d ma y di f fe r in case of mu ltip le de vice s. t h e lat e s t pr od uc t s t a t us i nf or m ati on i s a v ai l abl e on th e i ntern et at u r l htt p :// w w w .nxp .com . 16.2 definitions dr a f t ? the do c u m e nt is a draf t versi on onl y . the cont ent is st ill unde r int e rn al review and subje c t to f o rmal ap proval, which m a y re su lt in modif i cat i ons or add itio ns. nxp se miconduct o rs does not g i ve a n y rep resent a t io ns o r wa rrant ies as t o t he accu racy or compl e te ness o f inf o rma tio n in c l u ded her ein and shall hav e no liab ilit y fo r t he consequ ences o f use of such inf o rmat i on . short dat a sheet ? a shor t dat a she et is an extr act fr om a f ull da t a sh eet wit h t he same pr oduct t y pe numbe r(s) and t i t l e. a shor t dat a sh eet is int end ed for qu ick r efe rence only an d shou ld no t b e rel i ed u pon to cont ain det ailed and fu ll inf ormat i on. for det a iled and f ull inf orma tio n se e t he re levant f ull da t a sheet , which is availab l e on requ est vi a the lo c a l nx p semicond ucto rs sale s of fi ce . in case of a ny in co nsist en c y or conf lict wit h t he shor t dat a she et, th e fu ll dat a shee t shall pre v a il. p r o d u ct sp ec if i c a t io n ? the inf orma tio n and dat a p r ovide d i n a p r oduct dat a she et shal l d efi ne the spe c if icat ion of the pr oduct a s agr eed be tween nxp se mico nduct ors and it s cu st omer , u n less nx p s e micond uctor s an d custome r have explicit ly ag reed ot her wis e i n wri t in g. i n no event h owever , shall an ag reemen t be valid in which t he nxp semi co nduct ors p r odu ct is dee med to of f er fu nctio ns and quali t ies beyon d t hos e descri bed in th e pro duct da t a sh eet . 16.3 disclaimers li mi te d wa rr a n ty an d li a b il it y ? i nf ormat i on in th is documen t is bel ieved to be accurat e and re liabl e. however , nxp s emicondu ct ors doe s not give any rep resent a t io ns o r wa rrant ies, e x p ressed or implie d, as to t he accuracy or completen e ss of such informa tio n a nd shall have no lia bility for the consequ ences o f use of such inf o rmat i on . nxp se mico nduct ors t akes no respo n sibilit y f o r t he c o nt ent in t h is documen t if pr ovided by an inf o rmat i on source out si de of nxp s emicondu ct ors. in n o e v e nt shall nxp s emicond uctor s be lia ble fo r a ny in dire ct , in cid ent a l , pun itive, spe c i a l or consequ ent ial damag es (inclu ding - wit hou t limit a t io n - lost prof it s , lost savings, business int e rrupt ion, cost s related t o the remov a l or rep l acement of an y pro duct s o r rework ch arge s) whe t he r or not such dama ges a r e based on t ort ( i ncludi ng negli gence) , warra nty , bre ach of cont ract or an y ot her le gal th eory . not with s t andin g a n y d a mages th at cust omer might incur fo r any r eason what soe v e r , nxp semi co nduct ors? ag greg at e and cumulat i ve l i abil i ty t oward s custome r for t he pro duct s d escr i bed he rein shall be li mite d i n a c cor dance wit h t he t e rms a nd condit i on s of comme rcial sale of nxp s e micondu ct or s. ri ght to m ake c h a n ge s ? nx p semicon ducto rs re s e rves t he rig ht t o ma k e chang es t o inf o rmat i on pu blished in t his documen t, i ncludin g wit ho ut limit a t io n sp ecificat ion s an d p r odu ct descript i ons, a t any time a nd with out not ice. this documen t super sed e s a nd repla c e s all inf o rma tio n sup p lied pr ior to t he pu blicat ion her eof . s u i t a b il it y f o r us e ? nxp s e micond uctor s pro ducts are not designe d, aut hori z e d o r w a rran t ed t o be suit ab le fo r u s e in li fe suppo rt , lif e-crit ical or sa fe ty-crit i cal syst ems or e quipme n t, nor in app licat ions where f a ilur e or malf unct i on of an nx p s emicond uctor s pro duct can rea s o nabl y be expe ct ed to result in per sonal inju ry , d eat h or seve re prop ert y or envi ronme nt al damag e. nxp s e micondu c t ors and it s suppl iers a c cep t no lia bilit y f o r inclusion an d/ or use o f nxp se mico nduct o rs prod uct s in such equ ipment or appl ica t io ns and t her efo r e such inclu s io n and /or use is at t he cu st omer ? s own risk. app l ic ati o ns ? a ppli c a t ions t hat a r e describe d h erei n f or any of t hese prod uct s ar e for il lustra tive pu rpos es only . nxp se mico nduct o rs makes no repr esent a t io n o r wa rran t y tha t such a pplication s will be suit a b le for the specifi ed use w i tho ut f urt her t esti ng or modif i cat i on. custome rs ar e responsib le for t he desig n a nd ope rat i on of t hei r a pplicat ion s and pr oduct s using nxp s emicondu ct or s pro duct s, and nxp semi conduct ors acce pt s no liabi lity fo r any a s sist a n ce wit h app licati ons o r cu st omer pr oduct design . it is cust omer ? s sol e r e sponsib ilit y t o d e t e rmine whe t he r t h e nxp semicon ducto rs p r odu ct is sui t able a nd f i t f or t he custome r ? s a pplicat ion s an d prod uct s pl anne d, as well as f o r t he plan ned app licati on and use of cu st ome r ? s t h ird p a rt y cust omer( s ) . custo mers sho u ld pro v id e appro p ria t e design an d o pera t in g saf eg uard s t o min i mize the r i sks asso cia t e d wit h t heir appl ica t ions a nd prod uct s. nxp semicon duct o rs d oes n o t accept any liabil i ty rela ted t o any def ault , damag e, cost s o r probl em wh ich is based on a n y weakne ss or def aul t in th e cu st ome r ? s ap plicat ions or prod uct s , or t he appl ica t io n o r use b y custo m er ? s th ird p a rt y custo mer(s). c u st omer is respo n sible f o r doing a ll n e cessa ry te st ing f o r th e cu st omer ? s app lic at ions and pro duct s u s i ng nxp semicon ducto rs p r oduct s in orde r to av oid a de fau l t of the ap plicat ions and th e p r odu ct s or of t he ap plicat ion or use by cu st omer ? s t hird p art y cu st ome r(s). nxp d oes n ot accept a n y liab ilit y in t h is r e sp ec t. li mi ting v a l ues ? s t ress above one or mo re limit ing values (as def ined in th e a b solut e maximum rati ngs s y s t em of i e c 6013 4) will c a use p e rman ent damag e t o the device. li miti ng va lues are stre ss rat i ngs onl y and (prope r) oper ati on of t he device at t hese or an y ot her cond iti ons a bove th ose g i ven in th e re co mm e nded o perat ing con dit ions se ct ion (if presen t) or t he chara c t e rist ics sect ions of t h is d o cument is no t warra nte d . const a nt or repe ate d exposure t o limit ing values will perma nent ly and irre v e rsibly af f e ct th e q uality a nd relia bility o f th e device. t e rms a n d condi tions o f comm ercial s a le ? n x p semic onduc tors prod uct s ar e so ld su bject t o the g ener a l t er m s and cond iti ons o f commercial sa le, a s pub lished at ht tp :/ /www .n xp .c om / p ro file /t er m s , unle s s ot herwise agre ed in a va lid writ ten in dividua l a gree m ent . in case an ind i vidual agre ement is conclud ed only th e t er m s and cond iti ons o f t he respect i ve agre ement sh all appl y . nxp s emicondu ct ors her eby e x p r essly ob ject s t o appl yin g the cust omer ? s gene ral te rms an d con dit ions with re gard t o th e purcha s e of nxp semicon duct o rs p r odu ct s by cu st omer . no offe r to sel l or l i ce nse ? not h ing i n th is documen t may be int e rpr e t ed or co nstr ued a s an of f er t o sel l pro duct s t hat is ope n for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] defi niti on obje ct ive [sho rt] dat a shee t d evelop ment this d ocument con t ain s dat a fro m t he obj ecti ve specif icati on fo r p roduct d e velop ment . preli minary [sho rt] dat a shee t q ua lif ica t io n t his d o cument con t ain s dat a fro m t he pre liminar y specif icat ion. product [short] data sheet production this document contains the product specification. www.datasheet.net/ datasheet pdf - http://www..co.kr/ lp c1 1e 1x al l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 2. al l r i ght s r e se r v ed. product data sheet rev. 1 ? 20 february 2012 60 of 61 nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller export con t r ol ? t h is do cu ment a s well as the it em(s) de scrib ed here i n may b e su bject t o export co ntr ol regu lat i ons. expo rt migh t req uire a pri or aut hor izati on fro m compe t e nt au tho r it ies. non - autom o tive qual i fied p r oduct s ? unl e ss t h is d a t a sheet expressly st at es th at thi s spe c i f ic nxp semicon duct ors prod uct i s a uto mot i ve qual ifi ed, th e p roduct is n o t suit a b le for aut omo t ive use. it i s neit her qua lif ied nor test ed in accorda n ce wit h aut omot ive te st ing o r a pplicat ion re quire ment s. nx p semi co nduct o rs a c cep t s n o l i abili ty for in cl usion and/ or use of non -aut omot ive qual ifie d produ ct s in au tomo tive equ ipmen t or app licati ons. in t he even t th at custo m er uses t he pro duct f o r desig n-in and u s e in aut omot ive app licat ions t o aut omot ive s pecif ica t io ns and st an dard s , custome r (a) shal l u s e t he pro duct wit hout n x p semicon ducto rs? wa rrant y o f t he pro duct f o r su ch a u to moti ve ap plicat ions, u s e a nd sp ecifi c a t io ns, and (b ) whene ve r cust omer uses the p r odu ct for au to m o tive ap plicat ions beyond nxp semicon ductors? s p ecification s such use sh all be so lely at custo m er ? s own risk, and (c) custo mer ful l y ind e mnif ies nxp semicon duct o rs f o r an y liabi lity , da mages or f ailed p r odu ct cl aims r esult ing f r om custome r design an d use of t he prod uct f or aut omot ive a pp licat ion s be yo nd nxp semicon duct o rs? st anda rd warra nty and nxp s emicondu ct ors? pro duct specif icat ions. 16.4 t r ademarks noti ce : all r efe renced b r ands, prod uc t name s , service names and t rad emarks are t he prop ert y of the i r respect i ve o w ners. i 2 c-bus ? logo is a trademark of nxp b.v. 17. cont act information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com www.datasheet.net/ datasheet pdf - http://www..co.kr/ nxp semiconductors lpc11e1x 32-bit arm cortex-m0 microcontroller ? nxp b . v . 20 12 . a l l r i g h t s re se rv ed. for m o r e i n for m a t i o n , plea se visit: htt p :// w ww.n x p.co m for sale s of fice a d d r e sses, plea se se nd an ema i l t o : s a lesa ddre sses@ nxp . com date of release: 20 february 2012 document identifier: lpc11e1x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. content s 1 g e n e ral descrip t io n . . . . . . . . . . . . . . . . . . . . . . 1 2 f e atu r es and b e n e fit s . . . . . . . . . . . . . . . . . . . . 1 3 ap pli c ati o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 o r d e ri ng in formatio n . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 blo c k diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pi nn ing i n fo rmatio n . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin descr iption . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 f u n c ti on al d e scripti on . . . . . . . . . . . . . . . . . . 14 7.1 on-chip flash pr ogramming memory . . . . . . . 14 7.2 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5 memory m a p . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 ne sted v e ctored interrupt control l er (n vic) . 1 5 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6.2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 io con block . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.8 gener a l-purpos e input /output gpio . . . . . . . 16 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.9 usar t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.10 ssp s e rial i/o c o ntroller . . . . . . . . . . . . . . . . . 17 7.10. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 1 i 2 c-bus serial i/ o contr o ller . . . . . . . . . . . . . . 18 7.1 1 . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.12 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.12. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.13 gene ra l purpo se e x te rn al even t counter/ timers . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.13. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.14 system tick t i mer . . . . . . . . . . . . . . . . . . . . . . 19 7.15 w i ndo wed w a tchdog t i me r (w wdt ) . . . . . . 1 9 7.15. 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.16 clocking and power cont rol . . . . . . . . . . . . . . 20 7.16. 1 integrated osc i llators . . . . . . . . . . . . . . . . . . . 20 7.16. 1 . 1 internal rc os cillator . . . . . . . . . . . . . . . . . . . 21 7.16.1 . 2 system oscillator . . . . . . . . . . . . . . . . . . . . . . 21 7.16 .1 .3 w a tchdo g oscilla to r . . . . . . . . . . . . . . . . . . . . 2 1 7.16. 2 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16. 3 clock out p ut . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16.4 w a ke-up process . . . . . . . . . . . . . . . . . . . . . . 22 7.16. 5 power cont rol . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16. 5 . 1 power pr of iles . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16. 5 . 2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7. 16. 5 . 3 deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 23 7. 16. 5 . 4 power-down mode . . . . . . . . . . . . . . . . . . . . . 23 7. 16. 5 . 5 deep power-down mode . . . . . . . . . . . . . . . . 23 7. 16. 6 system contro l . . . . . . . . . . . . . . . . . . . . . . . . 24 7. 16. 6 . 1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 . 1 6 .6 .2 brow nout detection . . . . . . . . . . . . . . . . . . . . 24 7 . 1 6 .6 .3 co de security (code re ad protecti on - c rp) 24 7.16.6.4 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 25 7. 16. 6 . 5 ahblit e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7. 16 . 6 . 6 exte rn al in te rr upt input s . . . . . . . . . . . . . . . . . 25 7. 17 emulat ion and debugging . . . . . . . . . . . . . . . 25 8 li miti ng val u es . . . . . . . . . . . . . . . . . . . . . . . . 26 9 s t atic characteristics . . . . . . . . . . . . . . . . . . . 27 9. 1 bod s t atic characteristics . . . . . . . . . . . . . . . 32 9. 2 power consumption . . . . . . . . . . . . . . . . . . . 32 9. 3 per i pher a l power cons umpt ion . . . . . . . . . . . 35 9. 4 elect rical pin charact e rist ics . . . . . . . . . . . . . . 37 1 0 dyn a mic ch ara c teristics . . . . . . . . . . . . . . . . . 40 10.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 40 1 0 .3 interna l oscilla to rs . . . . . . . . . . . . . . . . . . . . . 41 10.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.5 i 2 c- bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.6 ssp interface . . . . . . . . . . . . . . . . . . . . . . . . . 44 1 1 app l i c ation in format i on . . . . . . . . . . . . . . . . . 47 1 1 . 1 xt al input . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1 1 .2 xt al pri n ted-circui t board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . 48 1 1 .3 s t anda rd i/o p a d co nfigura t io n . . . . . . . . . . . 49 1 1 . 4 reset p a d configur at ion . . . . . . . . . . . . . . . . . 50 1 1 . 5 adc usage notes . . . . . . . . . . . . . . . . . . . . . . 50 12 package out lin e . . . . . . . . . . . . . . . . . . . . . . . . 51 13 so lderin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14 abb r eviati ons . . . . . . . . . . . . . . . . . . . . . . . . . 57 15 revi si on hi story . . . . . . . . . . . . . . . . . . . . . . . 58 16 leg a l in fo rmatio n . . . . . . . . . . . . . . . . . . . . . . 59 16.1 dat a sheet st atus . . . . . . . . . . . . . . . . . . . . . . 59 16.2 def i nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.4 t r ademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17 con t act in formatio n . . . . . . . . . . . . . . . . . . . . 60 18 con t ent s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 www.datasheet.net/ datasheet pdf - http://www..co.kr/ |
Price & Availability of LPC11E12
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |