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this is information on a product in full production. april 2014 docid18093 rev 4 1/23 54ac164245 rad-hard 16-bit transceiver 3.3 v to 5 v bidirectional level shifter datasheet - production data features ? fully compatible with 54acs164245 ? dual supply bidirectional level shifter ? extended voltage range from 2.3 v to 5.5 v ? separated enable pin for 3-state output ? schmidt-triggered i/os: 100 mv hysteresis ? internal 26 limiting resistor on each i/o ? high speed: tpd = 8 ns maximum ? fail safe ? cold spare ? hermetic package ? 100 krad (si) at any mil1019 dose rate ? sel immune to 110mev.cm 2 /mg let ions ? rha qml-v qualified description the 54ac164245 is a rad-hard advanced high- speed cmos, schmitt trigger 16-bit bidirectional multi-purpose transceiver with 3-state outputs and cold sparing. designed for use as an interface between a 5 v bus and a 3.3 v bus in mixed 5 v/3.3 v supply systems, it achieves high-speed operation while maintaining the cmos low-power dissipation. all pins have cold spare buffers to change them to high impedance when v dd is tied to ground. this ic is intended for two-way asynchronous communication between the data buses. the direction of the data transmission is determined by the ndir inputs. the a port interfaces with the 3.3 v bus but can also operate at 2.3 v. the b port operates with the 5 v bus. ceramic flat-48 the upper metallic lid is not electrically connected to any pins, nor to the ic die inside the package table 1. device summary order codes smd pin quality level p ackage lead finish m ass eppl temp. range rhfac164245k1 - engineering model flat-48 gold 1.50 g - -55 c to 125 c rhrac164245k01v 5962r9858008vyc qml-v flight yes www.st.com
contents 54ac164245 2/23 docid18093 rev 4 contents 1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 cold spare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 absolute maximum ratings and operating c onditions . . . . . . . . . . . . . 6 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 radiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 ceramic flat-48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 other information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 data code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
docid18093 rev 4 3/23 54ac164245 functional description 23 1 functional description figure 1. logic diagram 9sruw 9sruw 9sruw 9sruw $0 ',5 $ $ $ $ $ $ $ $ % % % % % % % % $ $ $ $ $ $ $ $ % % % % % % % % ',5 2( 2( table 2. function table enable, oex direction, dirx operation l l b data to a bus h a data to b bus hx isolation
functional description 54ac164245 4/23 docid18093 rev 4 1.1 cold spare the 54ac164245 features a co ld spare input and output buffer. in high reliability applications, cold sparing enables a redundant device to be tied to the data bus with its power supply at 0 v (v dd = v ss , v dd - v ss = 0 v) without affecting the bus signals or injecting current from the i/os to the power supplies. cold sparing also allows redundant devices to be kept unpowered so that they can be switched on only when required. power consumption is therefore reduced by switching off the redundant circuit. this has no impact on the application. cold sparing is achieved by implementing a high impedance between i/os and v dd . the esd protection is ensured th rough a non-conventional dedicated structure. 1.2 power-up during power-up, all outputs are forced to high impedance. the high-impedance state is maintained approximately until v dd is high, thus avoiding any transient and erroneous signals during power-up. 1.3 pin connections figure 2. pin connections $0y
docid18093 rev 4 5/23 54ac164245 functional description 23 table 3. pin descriptions pin number symbol name and function 1 dir1 direction control inputs 2, 3, 5, 6, 8, 9, 11, 12 1b1 to 1b8 si de b inputs or 3-state outputs (5 v port) 4,10, 15, 21, 28, 34, 39, 45 v ss reference voltage to ground 7, 18 v dd1 supply voltage (5 v) 13, 14, 16, 17, 19, 20, 22, 23 2b1 to 2b8 side b inputs or 3-state outputs (5 v port) 24 dir2 direction control inputs 25 ng2 output enable inputs (active low) 31, 42 v dd2 supply voltage (3.3 v) 47, 46, 44, 43, 41, 40, 38, 37 1a1 to 1a8 side a inputs or 3-state outputs (3.3 v port) 36, 35, 33, 32, 30, 29, 27, 26 2a1 to 2a8 side a inputs or 3-state outputs (3.3 v port) 48 ng1 output enable inputs (active low)
absolute maximum ratings and operating conditions 54ac164245 6/23 docid18093 rev 4 2 absolute maximum ratings and operating conditions absolute maximum ratings are those values be yond which damage to the device may occur. functional operation under these conditions is not implied. stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maxi mum levels may degrade perfo rmance and affect reliability. unless otherwise noted, all voltages are referenced to v ss . the limits for the parameters specified in table 4 apply over the full specified v dd range and case temperature range of -55c to +125c. table 4. absolute maximum ratings symbol parameter value unit v dd1 5 v supply voltage (1) 1. v dd1 (5 v) may remain disconnected. -0.3 to +6.0 v v dd2 3 v supply voltage v ia dc input voltage range port a -0.3 to v dd1 +0.3 v v ib dc input voltage range port b v oa dc output voltage range port a v ob dc output voltage range port b i ia dc input currents port a, anyone input 10 ma i ib dc input currents port b, anyone input t stg storage temperature range -65 to +150 c t l lead temperature (10 s) 300 t j junction temperature range 175 r thja thermal resistance junction to ambient (2) flat package, 48 pins 2. short-circuits can cause exce ssive heating and destructive diss ipation. values are typical. tbd c/w r thjc thermal resistance junction to case (2) flat package, 48 pins esd hbm: human body model (3) 3. human body model: a 100 pf capacit or is charged to the specified voltage, then discharged through a 1.5 k resistor between two pins of the device. this is done for all couples of connected pin combinations while the other pins are floating. 2kv
docid18093 rev 4 7/23 54ac164245 absolute maximum ra tings and operating conditions 23 in table 5 , unless otherwise noted, all voltages are referenced to v ss . table 5. operating conditions symbol parameter value unit v dd1 supply voltage 4.5 to 5.5 or 2.3 to 3.6 v v dd2 2.3 to 3.6 or 4.5 to 5.5 v i input voltage 0 to v dd1 v o output voltage t op operating temperature -55 to +125 c d t / d v input rise and fall time v cc = 3.0, 4.5 or 5.5 (1) 1. derates system propagation del ays by difference in rise time to switch point for t r or t f > 1 ns/v. 0 to 8 ns / v
electrical characteristics 54ac164245 8/23 docid18093 rev 4 3 electrical characteristics in table 6 , t op = -55 c to 125c, v dd1 = 4.5 v to 5.5 v, v dd2 = 2.7 v to 3.6 v, unless otherwise specified. each input/output, as applicable, is tested at the specified temperature, for the specified limits, to the tests specified in table ia from the smd 5962-98580 dla agency spec. non-designated output terminals are high level logic, low level logic or open, except for all i dd tests, where the output terminals are open. when performing these tests, the current meter must be placed in the circui t such that all current flows through the meter. table 6. dc specifications symbol parameter port voltage test condition (v dd ) (1) limits unit min. max. v t+ schmitt trigger positive going threshold port a 3.3 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v 0.7 v dd2 v 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 4.5 and 5.5 v schmitt trigger positive going threshold port b 3.3 v v dd2 = 2.7 and 3.6 v v dd1 = 2.7 and 3.6 v 0.7 v dd1 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v v t- schmitt trigger positive going threshold port a 3.3 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v 0.3 v dd2 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 4.5 and 5.5 v schmitt trigger positive going threshold port b 3.3 v v dd1 = 2.7 and 3.6 v v dd2 = 2.7 and 3.6 v 0.3 v dd1 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v v h schmitt trigger range of hysteresis port a 3.3 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v 0.4 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 4.5 and 5.5 v 0.6 schmitt trigger range of hysteresis port b 3.3 v v dd1 = 2.7 and 3.6 v v dd2 = 2.7 and 3.6 v 0.4 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v 0.6
docid18093 rev 4 9/23 54ac164245 electrical characteristics 23 i ih input current high port a (for input under test v i = v dd2 other inputs, v i = v dd2 or v ss ) 3.3 v v dd1 = 5.5 v v dd2 = 3.6 v 3 a 5.0 v v dd1 = 5.5 v v dd2 = 5.5 v input current high port b (for input under test v i = v dd1 other inputs, v i = v dd1 or v ss ) 3.3 v v dd1 = 3.6 v v dd2 = 3.6 v 5.0 v v dd1 = 5.5 v v dd2 = 3.6 v i il input current low port a (for input under test v i =v ss other inputs, v i = v dd2 or v ss 3.3 v v dd1 = 5.5 v v dd2 = 3.6 v -1 5 v v dd1 = 5.5 v v dd2 = 5.5 v input current low port b (for input under test v i =v ss other inputs, v i = v dd1 or v ss 3.3 v v dd1 = 3.6 v v dd2 = 3.6 v 5 v v dd1 = 5.5 v v dd2 = 3.6 v i cs input current cold spare mode port a = port b = 5.5 v = v i dirn = 5.5 v, oen = 5.5 v v dd1 = 0 v -1 5 input current cold spare mode port a = port b = 5.5 v = v i dirn = 0v, oen = 5.5 v v dd1 = 0 v input current cold spare mode port a = port b = 5.5 v = v i dirn = 5.5 v, oen = 0 v v dd1 = 0 v input current cold spare mode port a = port b = 5.5 v = v i dirn = 0 v , oen = 0 v v dd1 = 0 v v ol1 low level output voltage port a, i ol = 8 ma for all inputs affecting output under test, v i = v dd2 or v ss 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v 0.5 v 5 v v dd1 = 4.5 v v dd2 = 4.5 v 0.4 low level output voltage port b, i ol = 8 ma for all inputs affecting output under test, v i = v dd1 or v ss 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v 0.5 5 v v dd1 = 4.5 v v dd2 = 2.7 v 0.4 table 6. dc specifications (continued) symbol parameter port voltage test condition (v dd ) (1) limits unit min. max.
electrical characteristics 54ac164245 10/23 docid18093 rev 4 v ol2 low level output voltage 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v 0.2 v port a, i ol = 100 a for all inputs affecting output under test, v i = v dd2 or v ss 5 v v dd1 = 4.5 v v dd2 = 4.5 v low level output voltage 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v port b, i ol = 100 a for all inputs affecting output under test, v i =v dd1 or v ss 5 v v dd1 = 4.5 v v dd2 = 2.7 v v oh1 high level output voltage port a, i oh = -8 ma for all inputs affecting output under test , v i = v dd2 or v ss 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v v dd2 -0.9 5 v v dd1 = 4.5 v v dd2 = 4.5 v v dd2 -0.7 high level output voltage port b , i oh = -8 ma for all inputs affecting output under test, v i = v dd1 or v ss 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v v dd1 -0.9 5 v v dd1 = 4.5 v v dd2 = 2.7 v v dd1 -0.7 v oh2 high level output voltage port a, i oh = - 100 a for all inputs affecting output under test, v i = v dd2 or v ss 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v v dd2 -0.2 5 v v dd1 = 4.5 v v dd2 = 4.5 v high level output voltage port b , i oh = - 100 a for all inputs affecting output under test, v i = v dd1 or v ss 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v v dd1 -0.2 5 v v dd1 = 4.5 v v dd2 = 2.7 v i ol (2) output current (sink) port a, v i = v ss 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v v ol = 0.5 v 8.0 ma 5 v v dd1 = 4.5 v v dd2 = 4.5 v v ol = 0.4 v output current (sink) port b, v i = v ss 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v v ol = 0.5 v 5 v v dd1 = 4.5 v v dd2 = 2.7 v v ol = 0.4 v table 6. dc specifications (continued) symbol parameter port voltage test condition (v dd ) (1) limits unit min. max.
docid18093 rev 4 11/23 54ac164245 electrical characteristics 23 i oh (4) output current (source) port a, v i = v dd2 or v ss 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v v oh = v dd2 -0.9 v -8.0 ma 5 v v dd1 = 4.5 v v dd2 = 4.5 v v oh = v dd2 -0.7 v output current (source) port b, v i = v dd2 or v ss 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v v oh = v dd2 -0.9 v 5 v v dd1 = 4.5 v v dd2 = 2.7 v v oh = v dd2 - 0.7 v i ozh three-state output leakage current high port a, for input under test, v i = v dd2 other inputs, v o = v dd2 v i =v dd2 or v ss 3.3 v v dd1 = 5.5 v v dd2 = 3.6 v 3.0 a v dd1 = 5.5 v v dd2 = 5.5 v three-state output leakage current high port b, for input under test, v i = v dd1 other inputs, v o = v dd1 v i = v dd1 or v ss 3.3 v v dd1 = 3.6 v v dd2 = 3.6 v 5 v v dd1 = 5.5 v v dd2 = 3.6 v i ozl three-state output leakage current low port a, for input under test, v i = v ss other inputs, v o = v ss v i = v dd2 or v ss 3.3 v v dd1 = 5.5 v v dd2 = 3.6 v -1.0 5 v v dd1 = 5.5 v v dd2 = 5.5 v three-state output leakage current low port b, for input under test , v i = v ss other inputs, v o = v ss v i = v dd1 or v ss 3.3 v v dd1 = 3.6 v v dd2 = 3.6 v 5 v v dd1 = 5.5 v v dd2 = 3.6 v i os (3) (3) short circuit output current port a, v o = v dd2 or v ss 3.3 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v -100 100 ma 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v -200 200 short circuit output current port b, v o = v dd1 or v ss 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.6 v -100 100 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v -200 200 table 6. dc specifications (continued) symbol parameter port voltage test condition (v dd ) (1) limits unit min. max.
electrical characteristics 54ac164245 12/23 docid18093 rev 4 p d (3) (4) (5) power dissipation, port a, c l = 50 pf per switching output 3.3 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 1.5 mw/ mhz 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 2.0 power dissipation, port b, c l = 50 pf per switching output 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.6 v 1.5 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 2.0 i ddq quiescent supply current port a, v i = v dd2 or v ss 5 v v dd1 = 5.5 v v dd2 = 5.5 v at 25c 10 a v dd1 = 5.5 v v dd2 = 5.5 v at -55 to 125 c 100 quiescent supply current port b, v i = v dd1 or v ss 5 v v dd1 = 5.5 v v dd2 = 5.5 v at 25 c 10 v dd1 = 5.5 v v dd2 = 5.5 v at -55 to 125 c 100 c i input capacitance f = 1 mhz v dd1 = v dd2 = 0 v 15 pf c o output capacitance f = 1 mhz v dd1 = v dd2 = 0 v (6) functional test v ih = 0.7 v dd , v il = 0.3 v dd v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v l h 1. this device requires both vdd1 and vdd2 power supplies for operation. the power supply is indicated and followed by the voltage to which the power supply is set to the given test. 2. this parameter is supplied as a des ign limit but not guaranteed or tested. 3. no more than one output should be shorted at a time for a maximum duration of one second. 4. power does not include power contributi on of any cmos output sink current. 5. power dissipation specified per switching output. 6. tests must be performed in sequence and include attribute dat a only. functional tests shoul d include the truth table and other logic patterns used for fault detection. the test vectors us ed to verify the truth table must, at minimum, test all the functions of each input and output. all pos sible input to output logic patterns per function should be guaranteed, if not tested, to the function table, table 2 . functional tests are performed in sequence as approved by the qualifying activity on qualified devices. functional tests are c onducted in accordance with mil-std-883 with the following input test conditions: vih = v ih (min + 20%, -0%); v il = v il (max + 0%, -50%), as specif ied herein, for ttl, cmos, or schmitt compatible inputs. devices are guaranteed to v ih(min) and v il(max) . table 6. dc specifications (continued) symbol parameter port voltage test condition (v dd ) (1) limits unit min. max.
docid18093 rev 4 13/23 54ac164245 electrical characteristics 23 in table 7 , data are guaranteed by design but not tested. table 7. ac electrical characteristics symbol parameter port voltage test condition (v dd ) limits unit min. max. t plh propagation delay time, data to bus (active low) c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 =2.7 to 3.6 v 1.0 20 ns propagation delay time, data to bus (active low) c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.6 v v dd2 = 2.7 to 3.6 v port a = port b = 5 v v dd1 =4.5 to 5.5 v v dd2 =4.5 to 5.5 v 15 t phl propagation delay time, data to bus (active high) c l = 50 pf port a = 3.3v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 20 propagation delay time, data to bus (active high) c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.6 v v dd2 = 2.7 to 3.6 v port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 15 t pzl propagation delay time, output enable, oen to bus (active low), c l = 50 pf port a = 3.3 v port b = 5v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 18 propagation delay time, output enable, oen to bus (active low), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.6 v v dd2 = 2.7 to 3.6 v 18 port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 12 t pzh propagation delay time, output enable, oen to bus (active high), c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 18 propagation delay time, output enable, oen to bus (active high), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.6 v v dd2 = 2.7 to 3.6 v port a = port b = 5 v v dd1 = 4.5 to 5.5v v dd2 = 4.5 to 5.5v 12 t plz propagation delay time, output disable, oen to bus (low impedance), c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 20 propagation delay time, output disable, oen to bus (low impedance), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.6 v v dd2 = 2.7 to 3.6 v port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 15 t phz propagation delay time, output disable, oen to bus (high impedance), c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.3 v 18 propagation delay time, output disable, oen to bus (high impedance), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.3 v port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 12
electrical characteristics 54ac164245 14/23 docid18093 rev 4 t pzl (1) propagation delay time, output enable, dirn to bus (active low), c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.3 v 1.0 18 ns propagation delay time, output enable, dirn to bus (active low), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.3 v port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 12 t pzh (1) propagation delay time, output enable, dirn to bus (active high), c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.3 v 18 propagation delay time, output enable, dirn to bus (active high), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.3 v port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 12 t plz (1) propagation delay time, output disable, dirn to bus (low impedance), c l =50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.3 v 20 propagation delay time, output disable, dirn to bus (low impedance), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.3 v port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 15 t phz (1) propagation delay time, output disable, dirn to bus (high impedance), c l = 50 pf port a = 3.3 v port b = 5.0 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.3 v 20 propagation delay time, output disable, dirn to bus (high impedance), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.3 v port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 15 table 7. ac electrical char acteristics (continued) symbol parameter port voltage test condition (v dd ) limits unit min. max.
docid18093 rev 4 15/23 54ac164245 radiations 23 4 radiations total dose (mil1019 dose rate): all parameters are post-irradiation guaranteed by wafer-lot acceptance (after dose, all guaranteed electrical parameters are tested on a sample of units of each wafer lot). all parameters provided in table 6 and table 7 apply to both pre- and post-irradiation. the 54ac164245 is a pure cmos product. irradiation is performed at high dose rates. heavy ions: the behavior of the product when submitted to heavy ions is guaranteed by qualification and is not tested in production. heavy-ion trials are performed on qualification lots only. table 8. radiations type features value unit tid total ionizing dose high dose rate (50 - 300 rad/sec) up to: 100 k rad heavy ions sel immune (at 125 c) up to: 110 mev.cm2/mg seu immune up to: 64
test circuit 54ac164245 16/23 docid18093 rev 4 5 test circuit figure 3. test circuit 1. c l = 50 pf or equivalent (includes jig and probe capacitance), r t = z out of pulse generator (typically 50 ), v ref = 0.5 v dd . i src is set to -1.0 ma and i snk is set to 1.0 ma for t phl and t plh measurements. input signal from pulse generator: v i = 0.0 v to v dd ; f = 10 mhz; t r = 1.0 v/ns "0.3 v/ns; t f = 1.0 v/ns "0.3 v/ns; tr and tf are measured from 0.1 v dd to 0.9 v dd and from 0.9 v dd to 0.1 v dd respectively. figure 4. waveform 1: propagation delay $0y 38/6( *(1(5$725 '87 9 && , 61. 9 5() 5 7 & / ' ' ' ' , 65& $0y ,1387 287387 w u w i w 3+/ w 3/+ 9 '' *1' 9 2+ 9 2/
docid18093 rev 4 17/23 54ac164245 test circuit 23 figure 5. waveform 2: enable and disabl e times (port a = port b, 5 v operation) figure 6. waveform 3: enable and disable times (port a = port b, 3.3 v operation) $0y ,1387 287387 w 3=+ w 3=/ 9 '' 9 '' 9 287387 w 3/= w 3+= 9 '' 9 9 '' 9 '' 9 '' 9 '' 9 '' 9 9 '' $0y ,1387 287387 w 3=+ w 3=/ 9 '' 9 '' 9 287387 w 3/= w 3+= 9 '' 9 9 '' 9 '' 9 '' 9 '' 9 '' 9 9 ''
test circuit 54ac164245 18/23 docid18093 rev 4 figure 7. waveform 4: enable and disable times (port a = 3.3 v, port b = 5 v) $0y ,1387 287387 w 3=+ w 3=/ 9 '' 9 '' 9 287387 w 3/= w 3+= 9 '' 9 9 '' 9 '' 9 '' 9 '' 9 '' 9 9 '' 287387 w 3=+ w 3=/ 9 '' 287387 w 3/= w 3+= 9 '' 9 9 '' 9 '' 9 '' 9 '' 9 '' 9 9 ''
docid18093 rev 4 19/23 54ac164245 package information 23 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark.
package information 54ac164245 20/23 docid18093 rev 4 6.1 ceramic flat-48 p ackage information figure 8. ceramic flat-48 pa ckage mechanical drawing 1. the upper metallic lid is not elec trically connected to any pins, nor to the ic die inside the package. connecting any unused pins or the metal lid to ground or to the power supply will not affect the electrical characteristics. table 9. ceramic flat-48 package mechanical data dim mm inches typ min max typ min max a 2.47 2.18 2.72 0.097 0.086 0.107 b 0.254 0.20 0.30 0.010 0.008 0.012 c 0.15 0.12 0.18 0.006 0.005 0.007 d 15.75 15.57 15.92 0.620 0.613 0.627 e 9.65 9.52 9.78 0.380 0.375 0.385 e2 6.35 6.22 6.48 0.250 0.245 0.255 e3 1.65 1.52 1.78 0.065 0.060 0.070 e 0.635 0.025 f0.20 0.008 l 8.38 6.85 9.40 0.330 0.270 0.370 q 0.79 0.66 0.92 0.031 0.026 0.036 s1 0.43 0.25 0.61 0.017 0.010 0.024
docid18093 rev 4 21/23 54ac164245 ordering information 23 7 ordering information 8 other information 8.1 data code the date code is structured as shown below: ? em xyywwz ? qml-v yywwz where: table 10. order codes order code description temperature range package marking packing rhfac164245k1 engineering model -55 c to 125 c flat-48 rhfac164245k1 conductive strip pack rhrac164245k01v qml-v flight 5962r9858008vyc xyywwz assembly location (em only) 3: rennes (france) last two digits of year week digits lot index in the week
revision history 54ac164245 22/23 docid18093 rev 4 8.2 documentation 9 revision history table 11. documentation provided for escc flight quality level documentation engineering model - qml-v flight certificate of conformance qci (1) (groups a, b, c, d, and e) screening electrical data precap report pind (2) test sem (3) inspection report x-ray report 1. qci = quality conformance inspection 2. pind = particle impact noise detection 3. sem = scanning electron microscope table 12. document revision history date revision changes 23-sep-2011 1 initial release. 06-apr-2012 2 added pin 4 description to table 3: pin descriptions . 29-aug-2013 3 minor changes to layout features : removed ?bus hold? table 1: device summary : updated order codes, quality level, and eppl data. table 10: order codes : updated order codes and description data. added section 8: othe r information 28-apr-2014 4 table 11: documentation provided for escc flight : removed documentation for engineering model (there is none). updated disclaimer
docid18093 rev 4 23/23 54ac164245 23 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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