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1. general description the uja1162 is a ?self-supplied? high -speed can transceiver integrating an iso 11898-2/5 compliant hs-can transceiver and an internal 5 v can supply. the only supply input is a battery connection. the uj a1162 can be operated in a very low-current sleep mode with local and bus wake-up capability. 2. features and benefits 2.1 general ? self-supplied high-speed can transceiver ? iso 11898-2 and iso 11898-5 compliant ? autonomous bus biasing according to iso 11898-6 ? fully integrated 5 v supply (v buf ) for the can transmitter/receiver ? vio input allows for direct interfac ing with 3.3 v to 5 v microcontrollers ? bus connections are truly floating when power to pin bat is off 2.2 designed for automotive applications ? ? 8 kv electrostatic discharge (esd) protection, according to the human body model (hbm) on the can bus pins ? ? 6 kv esd protection, according to iec 61000-4-2 on the can bus pins and on pins bat and wake ? can bus pins short-circuit proof to ? 58 v ? battery and can bus pins are protected against automotive transients according to iso 7637-3 ? very low quiescent current in sleep mode ? leadless hvson14 package (3 mm ? 4.5 mm) with improved automated optical inspection (aoi) capability ? dark green product (halogen free and rest riction of hazardous substances (rohs) compliant) 2.3 integrated supply voltage for the can transceiver (v buf ) ? 5 v nominal output; ? 2 % accuracy ? undervoltage detection at 90 % of nominal value ? excellent response with a 4.7 ? f ceramic output load capacitor ? turned off in sleep mode uja1162 self-supplied high-speed can transceiver with sleep mode rev. 1 ? 26 september 2013 product data sheet
uja1162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 26 september 2013 2 of 28 nxp semiconductors uja1162 self-supplied high-speed can transceiver with sleep mode 2.4 power management ? sleep mode featuring very low supply current ? remote wake-up capability via standard can wake-up pattern ? local wake-up capability via the wake pin ? entire node can be powered down via the inhibit output, inh 2.5 system control and diagnostic features ? mode control via slpn pin ? overtemperature shutdown ? transmit data (txd) dominant time-out function 3. ordering information table 1. ordering information type number package name description version UJA1162TK hvson14 plastic thermal enhanced very thin small outline package; no leads; 14 terminals; body 3 ? 4.5 ? 0.85 mm sot1086-2 uja1162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 26 september 2013 3 of 28 nxp semiconductors uja1162 self-supplied high-speed can transceiver with sleep mode 4. block diagram fig 1. block diagram of uja1162 uja1162 015aaa300 hs-can canh canl txd rxd 13 12 4 1 gnd 2 slpn mode control 14 5 v hs-can supply (v buf ) buf 3 vio 5 can transmitter status cts 6 bat inh inh 7 10 wake wake-up 9 uja1162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 26 september 2013 4 of 28 nxp semiconductors uja1162 self-supplied high-speed can transceiver with sleep mode 5. pinning information 5.1 pinning 5.2 pin description [1] hvson14 package die supply grou nd is connected to both the gnd pi n and the exposed center pad. the gnd pin must be soldered to board ground. for enhanc ed thermal and electrical performance, it is recommended to also solder the exposed center pad to board ground. fig 2. pin configuration diagram terminal 1 index area 015aaa302 uja1162 txd 1 gnd 2 3 rxd 4 5 cts 6 inh slpn canh canl i.c. bat wake i.c. 7 14 13 12 11 10 9 8 transparent top view buf vio table 2. pin description symbol pin description txd 1 transmit data input gnd 2 [1] ground buf 3 5 v transceiver supply voltage rxd 4 receive data output; reads out data from the bus lines vio 5 supply voltage for i/o level adaptor cts 6 can transmitter status inh 7 inhibit output for switching external voltage regulators i.c. 8 internally connected; should be left floating or connected to gnd wake 9 local wake-up input bat 10 battery supply voltage i.c. 11 internally connected; should be left floating or connected to gnd canl 12 low-level can bus line canh 13 high-level can bus line slpn 14 sleep mode control input (active low) uja1162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 26 september 2013 5 of 28 nxp semiconductors uja1162 self-supplied high-speed can transceiver with sleep mode 6. functional description the uja1162 is a self-supplied high-speed can transceiver incorporating a 5 v can supply. a variety of fail-safe and diagnostic features offer enhanc ed system reliability and advanced power management. 6.1 system controller the system controller is a state machine that manages register configuration and controls the internal functions of the uja1162. uja1 162 operating modes and state transitions are illustrated in figure 3 . these modes are discussed in more detail in the following sections. 6.1.1 operating modes the uja1162 supports five operating modes: normal, standby, sleep, overtemp and off. 6.1.1.1 normal mode normal mode is the active operating mode. in this mode, the uja1162 is fully operational. normal mode can be selected from standby and sleep (via standby) modes by setting pin slpn high, provided v io >v uvd(vio) . the uja1162 exits normal mode: ? if the microcontroller selects standby mode by setting pin slpn low ? if the uja1162 detects an undervoltage on vio, causing the uja1162 to switch to standby mode ? if the chip temperature rises above t th(act)otp , causing the uja1162 to switch to overtemp mode ? if the battery supply voltage drops below v th(det)poff , causing the uja1162 to switch to off mode all pending wake-up events (power-on, can bus wake-up, local wake-up via the wake pin) are cleared when the uja1162 enters normal mode. uja1162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 26 september 2013 6 of 28 nxp semiconductors uja1162 self-supplied high-speed can transceiver with sleep mode 6.1.1.2 standby mode standby mode is a transitional mode betwee n normal and sleep modes. the transceiver is unable to transmit or receive data in standby mode, but pin inh is active. the receiver monitors bus activity for a wake-up request in standby mode. the bus pins are biased at gnd level (via r i(cm) ) when the bus is inactive for t > t to(silence) and at approximately 2.5 v when there is activity on the bus (autonomous biasing). wake-up can be triggered remotely via a standard wake-up pattern on the can bus (see section 6.3.2 ) or locally via the wake pin. pin rxd is forced low when a bus or local wake-up event is detected. the uja1162 switches to standby mode: ? from normal mode if pin slpn goes low or and undervoltage is detected on vio ? from sleep mode in the event of a local or remote wake-up event or if slpn = high (with a valid voltage on vio) (1) slpn = high is only possible in sleep mode if a valid v io supply voltage is connected fig 3. uja1162 system controller state diagram 1 2 5 0 $ / 6 7 $ 1 ' % < d d d 6 / 3 1 + , * + 2 5 z d n h x s h y h q w 6 / ( ( 3 q r r y h u w h p s h u d w x u h h y h q w 2 9 ( 5 7 ( 0 3 s r z h u r q 2 ) ) i u r p d q \ p r g h 9 % $ 7 x q g h u y r o w d j h h y h q w r y h u w h p s h u d w x u h h y h q w 6 / 3 1 / 2 : 2 5 9 , 2 9 x y g 9 , 2 6 / 3 1 + , * + 9 , 2 ! 9 x y g 9 , 2 6 / 3 1 / 2 : i r u w ! w v o h h s q r z d n h x s s h q g l q j 9 , 2 ! 9 x y g 9 , 2 2 5 9 , 2 9 x y g 9 , 2 i r u w ! w x y 9 , 2 uja1162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 26 september 2013 7 of 28 nxp semiconductors uja1162 self-supplied high-speed can transceiver with sleep mode 6.1.1.3 sleep mode sleep mode is the uja1162?s power saving mode. in sleep mode, the transceiver behaves like in standby mode with the exception that pin inh is set floating. voltage regulators controlled by this pin will be s witched off, and the current into pin bat will be reduced to a minimum. a high level on slpn (provided a valid voltage is present on vio), a local wake-up via the wake pin or a remote can bus wake-up will cause the uja1162 to wake up from sleep mode and switch to standby mode. pin rxd is forced low when a local wake-up via wake or a remote bu s wake-up is detected. the uja1162 can be set to sleep mode by holding pin slpn low for t > t sleep (provided there are no wake-up events pending). if one or more wake-up events is pending, the uja1162 will remain in standby mode. the uja1162 mu st be switched to normal mode to clear pending wake-up events. the uja1162 will also be forc ed to sleep mode if an undervoltage la sting longer than t d(uvd-slp) is detected on vio (v io uja1162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 26 september 2013 9 of 28 nxp semiconductors uja1162 self-supplied high-speed can transceiver with sleep mode is no activity on the bus for t > t to(silence) (can offline mode). this is useful when the node is disabled due to a malfunction in the micr ocontroller. the transceiver ensures that the can bus is correctly biased to avoid distur bing ongoing communication between other nodes. the autonomous can bias voltage is derived directly from v bat . 6.3.1 can operating modes the integrated can transceiver supports three operating modes: active, offline and offline bias (see figure 5 ). the can transceiver operating mode depends on the uja1162 operating mode and the output voltage on pin buf. 6.3.1.1 can active mode in can active mode, the transceiver can transmit and receive data via canh and canl. the differential receiver converts the analog data on the bus lines into digital data, which is output on pin rxd. the transmitter conv erts digital data generated by the can controller (input on pin txd) into analog signals suitable for transmission over the canh and canl bus lines. the can transceiver is in active mode when: ? the uja1162 is in normal mode (slpn = 1) and ? v buf > v uvd(buf) and ? v io > v uvd(vio) in can active mode, the can bias voltage is derived from v buf . if v buf falls below v uvd(buf) , the uja1162 exits can active mode and enters can offline bias mode with autonomous can voltage biasing via pin bat. if pin txd is low when the transceiver swit ches to can active mode (uja1162 in normal mode; v buf and v io ok), the transmitter and receiv er will remain disabled until txd goes high. this prevents network traffic being blocked for t to(dom)txd (i.e. while the txd dominant time-out timer is running; see section 6.7.1 ) every time the transceiver enters active mode, if the txd pin is clamped permanently low. 6.3.1.2 can offline and offline bias modes in can offline mode, the transceiver monitors the can bus for a wake-up event. canh and canl are biased to gnd. can offline bias mode is the same as can offline mode, with the exception that the can bus is biased to 2.5 v. this mode is activa ted automatically when activity is detected on the can bus while the transceiver is in can offline mode. the tran sceiver will return to can offline mode if the can bus is silent (no can bus edges) for longer than t to(silence) . the can transceiver will switch from can ac tive mode to can offline bias mode if: ? the uja1162 switches to standby/sleep mode while the can bus had been inactive for less than t to(silence) or ? v buf < v uvd(buf) or v io < v uvd(vio) the can transceiver will switch directly from can active mode to can offline mode if: ? the uja1162 switches to standby/sleep mode after the can bus had been inactive for more than t to(silence) uja1162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 26 september 2013 10 of 28 nxp semiconductors uja1162 self-supplied high-speed can transceiver with sleep mode the can transceiver switches from can of fline bias mode to can offline mode: ? when the uja1162 is in standby/sleep mode and ? no activity has been detected on the bus for t > t to(silence) the can transceiver switches from can off line mode to can offline bias mode if: ? a wake-up event is detected on the can bus or ? the uja1162 switches to normal mode while v buf < v uvd(buf) or v io < v uvd(vio) 6.3.1.3 can off the can transceiver is switched off comple tely with the bus lines floating when: ? the uja1162 switches to off or overtemp mode or ? v bat falls below the can receiver undervoltage detection threshold, v uvd(can) it will be switched on again on ente ring can offline mode when v bat rises above the undervoltage release threshold and the uja1162 is no longer in off/overtemp mode. 6.3.2 can standard wake-up the uja1162 monitors the bus for a wake-up pattern when the can transceiver is in offline mode. a filter at the receiver input prevents unwanted wake-up events occurring due to automotive transients or emi. a dominant-recessive-dominant wake-up pattern must be transmitted on the can bus within the wake-up timeout time (t to(wake) ) to pass the wake-up filter and trigger a wake-up event (see figure 4 ; note that additional pulses may occur between the recessive/dominant phases). the recessive and dominant phases must last at least t wake(busrec) and t wake(busdom) , respectively. pin rxd is driven low when a valid can wake-up pattern is detected on the bus. fig 4. can wake-up timing t dom t wake(busdom) recessive t rec t wake(busrec) t dom t wake(busdom) dominant dominant 015aaa267 t wake < t to(wake) can wake-up uja1162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 26 september 2013 11 of 28 nxp semiconductors uja1162 self-supplied high-speed can transceiver with sleep mode 6.4 wake pin in standby and sleep modes, a local wake-up event is triggered by a low-to-high or a high-to-low transition on the wake pin. in app lications that don?t ma ke use of the local wake-up facility, the wake pin should be c onnected to gnd for opt imal emi performance. 6.5 vio supply pin pin vio should be connected to the microcontrolle r supply voltage. this will cause the signal levels on txd, rxd, slpn and cts to be adjusted to the i/o levels of the microcontroller, enabling direct interfacing without the need for glue logic. fig 5. can transceiver state machine & |