note: for detailed information on purchasing options, contact your local allegro field applications engineer or sales representative. allegro microsystems, inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no respon- sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. recommended substitutions: dabic-5 32-bit serial input latched sink drivers a6832 for existing customer transition, and for new customers or new appli- cations, contact allegro sales. date of status change: november 1, 2010 deadline for receipt of last time buy orders: april 30, 2011 this part is in production but has been determined to be last time buy. this classification indicates that the product is obsolete and notice has been given. sale of this device is currently restricted to existing customer applications. the device should not be purchased for new design applications because of obsolescence in the near future. samples are no longer available. last time buy
? thermal printheads ? multiplexed led displays ? incandescent lamps 12 13 14 15 16 17 10 11 9 8 7 27 26 25 24 23 22 21 28 20 19 18 35 34 33 32 31 36 37 38 39 29 2 1 44 43 42 3 4 5 6 40 41 30 description intended originally to drive thermal printheads, the a6832 has been optimized for low output-saturation voltage, high-speed operation, and pin configurations that are the most convenient for the tight space requirements of high-resolution printheads. these integrated circuits can also be used to drive multiplexed led displays or incandescent lamps at up to 125 ma peak current. the combination of bipolar and mos technologies gives the a6832 arrays an interface flexibility beyond the reach of standard buffers and power driver circuits. the devices each have 32 bipolar npn open-collector saturated drivers, a cmos data latch for each of the drivers, two 16-bit cmos shift registers, and cmos control circuitry. the high- speed cmos shift registers and latches allow operation with most microprocessor-based systems. use of these drivers with ttl may require input pull-up resistors to ensure an input logic high. mos serial data outputs permit cascading for interface applications requiring additional drive lines. the a6832 is supplied in a 44-lead plastic leaded chip carrier, for surface-mount applications requiring minimum area. these devices are lead (pb) free, with 100% matte tin plated leadframes. 26185.110g features and benefits ? 3.3 to 5 v logic supply range ? to 10 mhz data input rate ? schmitt trigger inputs for improved noise immunity ? low-power cmos logic and latches ? 40 v current sink outputs ? low saturation voltage ? ?40c operation available dabic-5 32-bit serial input latched sink drivers package: 44-pin plcc (suffix ep) applications: functional block diagram not to scale a6832 32-bit s hift r e gis te r latches clock serial data in strobe output enable v dd serial data out mos bipolar out out out out out out 1 2 3 30 31 32 ground
dabic-5 32-bit serial-input latched sink drivers a6832 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating unit logic supply voltage v dd 7v input voltage range v in caution: cmos devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges. ?0.3 to v dd + 0.3 v output voltage v out 40 v continuous output current i out 125 ma package power dissipation p d see allowable power dissipation chart. ? ? operating ambient temperature t a range e ?40 to 85 oc range s ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number packing operating temperature ( oc) package a6832eeptr-t 450 pieces per reel ?20 to 85 44-pin plcc A6832SEPTR-T 450 pieces per reel ?40 to +85 50 75 100 125 15 0 package power dissipation (w) ambient temperature ( o c ) 25 4.0 3.0 3.5 0.5 0 2.5 2.0 1.5 1.0 4.5 a6832ep, r = 54 c/w ja a6832ep, r = 30 c/w ja allowable power dissipation, p d * *additional thermal information is available on the allegro web site.
dabic-5 32-bit serial-input latched sink drivers a6832 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 unless otherwise noted: t a = 25c, logic supply operating voltage v dd = 3.0 v to 5.5 v characteristic symbol test conditions v dd = 3.3 v v dd = 5 v units min. typ. max. min. typ. max. output leakage current i cex v out = 40 v ? ? 10 ? ? 10 a collector?emitter saturation voltage v ce(sat) i out = 50 ma ? ? 275 ? ? 275 mv i out = 100 ma ? ? 550 ? ? 550 mv input voltage v in(1) 2.2 ? ? 3.3 ? ? v v in(0) ? ? 1.1 ? ? 1.7 v input current i in(1) v in = v dd ? < 0.01 1.0 ? < 0.01 1.0 a i in(0) v in = 0 v ? < ?0.01 ?1.0 ? < ?0.01 ?1.0 a serial data output voltage v out(1) i out = ?200 a 2.8 3.05 ? 4.5 4.75 ? v v out(0) i out = 200 a ? 0.15 0.3 ? 0.15 0.3 v maximum clock fre- quency 2 f c 10 ? ? 10 ? ? mhz logic supply current i dd(1) one output on, i out = 100 ma ? ? 6.0 ? ? 6.0 ma i dd(0) all outputs off ? ? 100 ? ? 100 a output enable-to-output delay t dis(bq) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s t en(bq) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s strobe-to-output delay t p(sth-ql) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s t p(sth-qh) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s output fall time t f v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s output rise time t r v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s clock-to-serial data out delay t p(ch-sqx) i out = 200 a ? 50 ? ? 50 ? ns 1 positive (negative) current is de ned as conventional current going into (coming out of) the speci ed device pin. 2 operation at a clock frequency greater than the speci ed minimum value is possible but not warran teed. l = low logic level h = high logic level x = irrelevant p = present state r = previous state serial shift register contents serial latch contents output output contents data clock data strobe enable input input i 1 i 2 i 3 ... i n-1 i n output input i 1 i 2 i 3 ... i n-1 i n input i 1 i 2 i 3 ... i n-1 i n hhr 1 r 2 ... r n-2 r n-1 r n-1 llr 1 r 2 ... r n-2 r n-1 r n-1 xr 1 r 2 r 3 ... r n-1 r n r n xxx...x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n hp 1 p 2 p 3 ... p n-1 p n hp 1 p 2 p 3 ... p n-1 p n x x x ... x x l h h h ... h h truth table
dabic-5 32-bit serial-input latched sink drivers a6832 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing requirements and speci cations (logic levels are v dd and ground) clock serial data in strobe output enable out n 50% serial data out data data 10% 90% 50% 50% 50% c a b d e high = all outputs enabled p(s t h-q l) t p(c h-s q x ) t data p(s t h-q h) t output enable out n data 10% 50% dis (b q) t en(bq) t low = all outputs blanked (disabled) r t f t 50% 90% note: timing is representative of a 10 mhz clock. higher speeds may be attainable; operation at high temperatures will reduce the speci ed maximum clock frequency. s erial data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the clock input pulse. on succeeding clock pulses, the registers shift data information towards the serial data output. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is transferred to the respective latch when the strobe is high (serial-to-parallel conversion). the latches will continue to accept new data as long as the strobe is held high. applications where the latches are bypassed (strobe tied high) will require that the output enable input be low during serial data entry. when the output enable input is low, the output sink drivers are disabled (off). the information stored in the latches is not affected by the output enable input. with the output enable input high, the outputs are controlled by the state of their respective latches. key description symbol time (ns) a data active time before clock pulse (data set-up time) t su(d) 25 b data active time after clock pulse (data hold time) t h(d) 25 c clock pulse width t w(ch) 50 d time between clock activation and strobe t su(c) 100 e strobe pulse width t w(sth) 50
dabic-5 32-bit serial-input latched sink drivers a6832 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 1 4 5 6 18 19 20 21 22 23 24 25 26 27 28 40 41 42 43 44 2 3 7 8 9 10 11 12 13 14 15 16 17 out nc strobe 1 ground serial data in logic supply clock serial data out output enable nc out 32 38 39 37 36 35 34 33 32 31 30 29 out 31 out 21 nc out 13 out 16 nc out 17 o ut 20 nc v dd 32 shift register latches shift register latches out 12 out 2 pin-out diagram typical input circuit typical output driver in v dd out v dd
dabic-5 32-bit serial-input latched sink drivers a6832 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ep, 44-pin plcc for the latest version of this document, visit our website: www.allegromicro.com copyright ?2003-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. 2144 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area for reference only (reference jedec ms-018 ac) dimensions in millimeters c seating plane 0.51 4.57 max 16.59 0.08 16.59 0.08 7.75 0.36 7.75 0.36 7.75 0.36 7.75 0.36 c 0.10 44x 0.74 0.08 17.53 0.13 17.53 0.13 1.27 0.43 0.10
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