View NT5DS128M4BT-6K_7863088.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 1 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. features ? ddr 512m bit, die b, based on 110nm design rules ? double data rate architecture: two data transfers per clock cycle ? bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and is center- aligned with data for writes ? differential clock inputs (ck and ck ) ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs trans itions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? burst lengths: 2, 4, or 8 ? cas latency: 2 / 2.5 (6k & 75b), 2.5 / 3 (6k & 5t) ? auto precharge option for each burst access ? auto refresh and self refresh modes ?7.8 s maximum average periodic refresh interval ? 2.5v (sstl_2 compatible) i/o ?v dd = v ddq = 2.5v 0.2v (6k & 75b) ?v dd = v ddq = 2.6v 0.1v (5t) description nt5ds128m4bf, nt5ds128m4bt, nt5ds128m4bg, nt5ds128m4bs, nt5ds64m8bf, nt5ds64m8bt, nt5ds64m8bg, nt5ds64m8bs, nt5ds32m16bf nt5ds32m16bt, nt5ds32m16bg and nt5ds32m16bs are die b of 512mb sdram devices based using ddr inter- face. they are all based on nanya?s 110 nm design process. the 512mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. it is internally configured as a quad-bank dram. the 512mb ddr sdram uses a double-data-rate architec- ture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512mb ddr sdram effectively consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one- half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge- aligned with data for reads and center-aligned with data for writes. the 512mb ddr sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). commands (address and control signals) ar e registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write com- mand. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge func- tion may be enabled to provide a self-timed row precharge that is initiated at th e end of the burst access. as with standard sdrams, the pipelined, multibank architec- ture of ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row pre- charge and activation time. an auto refresh mode is prov ided along with a power-saving power down mode. all inputs are compatible with the jedec standard for sstl_2. all outputs are sstl_2, class ii com- patible. the functionality described a nd the timing specifications included in this data sheet are for the dll enabled mode of operation. cas latency and frequency cas latency maximum operating frequency (mhz) ddr400 (5t) ddr333 (6k) ddr266b (75b) 2- 133 100 2.5 166 166 133 3200 - -
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 2 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. ordering information (non-green) org. part number package speed comments clock (mhz) cl-t rcd -t rp 128m x 4 nt5ds128m4bt-5t 66 pin tsop-ii 200 3-3-3 ddr400 NT5DS128M4BT-6K 166 2.5-3-3 ddr333 nt5ds128m4bt-75b 133 2.5-3-3 ddr266 nt5ds128m4bf-5t 60ball bga 0.8mmx1.0mm pitch 200 3-3-3 ddr400 nt5ds128m4bf-6k 166 2.5-3-3 ddr333 nt5ds128m4bf-75b 133 2.5-3-3 ddr266 64m x 8 nt5ds64m8bt-5t 66 pin tsop-ii 200 3-3-3 ddr400 nt5ds64m8bt-6k 166 2.5-3-3 ddr333 nt5ds64m8bt-75b 133 2.5-3-3 ddr266 nt5ds64m8bf-5t 60ball bga 0.8mmx1.0mm pitch 200 3-3-3 ddr400 nt5ds64m8bf-6k 166 2.5-3-3 ddr333 nt5ds64m8bf-75b 133 2.5-3-3 ddr266 32m x 16 nt5ds32m16bt-5t 66 pin tsop-ii 200 3-3-3 ddr400 nt5ds32m16bt-6k 166 2.5-3-3 ddr333 nt5ds32m16bt-75b 133 2.5-3-3 ddr266 nt5ds32m16bf-5t 60ball bga 0.8mmx1.0mm pitch 200 3-3-3 ddr400 nt5ds32m16bf-6k 166 2.5-3-3 ddr333 nt5ds32m16bf-75b 133 2.5-3-3 ddr266 note: 1. at the present time, there are no plans to support ddr sdrams with the qfc function. all reference to qfc are for information only
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 3 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. ordering information (green) org. part number package speed comments clock (mhz) cl-t rcd -t rp 128m x 4 nt5ds128m4bs-5t 66 pin tsop-ii 200 3-3-3 ddr400 nt5ds128m4bs-6k 166 2.5-3-3 ddr333 nt5ds128m4bs-75b 133 2.5-3-3 ddr266 nt5ds128m4bg-5t 60ball bga 0.8mmx1.0mm pitch 200 3-3-3 ddr400 nt5ds128m4bg-6k 166 2.5-3-3 ddr333 nt5ds128m4bg-75b 133 2.5-3-3 ddr266 64m x 8 nt5ds64m8bs-5t 66 pin tsop-ii 200 3-3-3 ddr400 nt5ds64m8bs-6k 166 2.5-3-3 ddr333 nt5ds64m8bs-75b 133 2.5-3-3 ddr266 nt5ds64m8bg-5t 60ball bga 0.8mmx1.0mm pitch 200 3-3-3 ddr400 nt5ds64m8bg-6k 166 2.5-3-3 ddr333 nt5ds64m8bg-75b 133 2.5-3-3 ddr266 32m x 16 nt5ds32m16bs-5t 66 pin tsop-ii 200 3-3-3 ddr400 nt5ds32m16bs-6k 166 2.5-3-3 ddr333 nt5ds32m16bs-75b 133 2.5-3-3 ddr266 nt5ds32m16bg-5t 60ball bga 0.8mmx1.0mm pitch 200 3-3-3 ddr400 nt5ds32m16bg-6k 166 2.5-3-3 ddr333 nt5ds32m16bg-75b 133 2.5-3-3 ddr266 note: 1. at the present time, there are no plans to support ddr sdrams with the qfc function. all reference to qfc are for information only
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 4 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. pin configuration - 400mil tsop ii (x4 / x8 / x16) 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 66 65 64 63 62 61 58 57 56 55 54 53 60 59 52 51 50 49 48 47 46 45 23 24 25 44 43 42 26 27 41 40 28 29 30 31 32 33 39 38 37 36 35 34 v dd dq0 v ddq nc dq1 v ssq v ddq nc dq3 v ssq nc nc nc dq2 v ddq nc nc v dd nu nc we cas ras cs nc ba0 ba1 v ss dq7 v ssq nc dq6 v ddq v ssq nc dq4 v ddq nc nc nc dq5 v ssq dqs nc v ref v ss dm* ck ck cke nc a12 a11 a9 v dd nc v ddq nc dq0 v ssq v ddq nc dq1 v ssq nc nc nc nc v ddq nc nc v dd nu nc we cas ras cs nc ba0 ba1 v ss nc v ssq nc dq3 v ddq v ssq nc dq2 v ddq nc nc nc nc v ssq dqs nc v ref v ss dm* ck ck cke nc a12 a11 a9 a10/ap a0 a1 a2 a3 v dd a10/ap a0 a1 a2 a3 v dd a8 a7 a6 a5 a4 v ss a8 a7 a6 a5 a4 v ss column address table organization column address 128mb x 4 a0-a9, a11, a12 64mb x 8 a0-a9, a11 32mb x 16 a0-a9 *dm is internally loaded to match dq and dqs identically . 128mb x 4 64mb x 8 66-pin plastic tsop-ii 400mil 32mb x 16 v dd dq0 v ddq dq1 dq2 v ssq v ddq dq5 dq6 v ssq dq7 nc dq3 dq4 v ddq ldqs nc v dd nu ldm* we cas ras cs nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd v ss dq15 v ssq dq14 dq13 v ddq v ssq dq10 dq9 v ddq dq8 nc dq12 dq11 v ssq udqs nc v ref v ss udm* ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 5 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. pin configuration - 60 balls 0. 8mmx1.0mm pitc h csp package see the balls through the package. a b c d e f g h j k l m 128 x 4 1 vssq nc nc nc nc vref nc vddq vssq vddq vssq vss clk a12 a11 a8 a6 a4 2 vss dq3 nc dq2 dqs dqm clk cke a9 a7 a5 vss 3 vdd dq0 nc dq1 nc nc we ras ba1 a0 a2 vdd 7 nc vssq vddq vssq vddq vdd cas cs ba0 a10/ ap a1 a3 8 vddq nc nc nc nc nc 9 a b c d e f g h j k l m 64 x 8 vssq nc nc nc nc vref 1 dq7 vddq vssq vddq vssq vss clk a12 a11 a8 a6 a4 2 vss dq6 dq5 dq4 dqs dqm clk cke a9 a7 a5 vss 3 vdd dq1 dq2 dq3 nc nc we ras ba1 a0 a2 vdd 7 dq0 vssq vddq vssq vddq vdd cas cs ba0 a10/ ap a1 a3 8 vddq nc nc nc nc nc 9
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 6 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. pin configuration - 60 balls 0. 8mmx1.0mm pitc h csp package see the balls through the package. a b c d e f g h j k l m 32 x 16 1 vssq dq14 dq12 dq10 dq8 vref dq15 vddq vssq vddq vssq vss clk a12 a11 a8 a6 a4 2 vss dq13 dq11 dq9 udqs udm clk cke a9 a7 a5 vss 3 vdd dq2 dq4 dq6 ldqs ldm we ras ba1 a0 a2 vdd 7 dq0 vssq vddq vssq vddq vdd cas cs ba0 a10/ ap a1 a3 8 vddq dq1 dq3 dq5 dq7 nc 9
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 7 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. input/output functi onal description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all addre ss and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is refer- enced to the crossings of ck and ck (both directions of crossing). cke, cke0, cke1 input clock enable: cke high activates, and cke low deactiva tes, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all banks idle), or active po wer down (row active in any bank). cke is syn- chronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power down . input buffers, excluding cke, are disabled during self refresh. the standard pino ut includes one cke pin. optional pinouts might include cke1 on a different pin, in addition to cke0, to facilitate independent power down control of stacked devices. cs , cs 0 , cs 1 input chip select: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. the standard pinout includes one cs pin. optional pinouts might include cs 1 on a different pin, in addition to cs 0 , to allow upper or lower deck selection on stacked devices. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data dur ing a write access. dm is sampled on both edges of dqs. although dm pins are input only, t he dm loading matches the dq and dqs loading. dur- ing a read, dm can be driven high, low, or floated. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determi nes if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 - a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the pre- charge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inpu ts also provide the op-code during a mode register set command. dq input/output data input/output: data bus. dqs, ldqs, udqs input/output data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. used to capture write data. for the x16, ldqs corresponds to the data on dq0- dq7; udqs corresponds to the data on dq8-dq15 nc no connect: no internal electrical connection is present. nu electrical connection is pr esent. should not be connected at second level of assembly. v ddq supply dq power supply: 2.5v 0.2v. v ssq supply dq ground v dd supply power supply: 2.5v 0.2v. v ss supply ground v ref supply sstl_2 reference voltage: (v ddq / 2) 1%.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 8 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. block diagram (128mb x 4) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 12 command decode a0-a12, ba0, ba1 cke 13 15 i/o gating dm mask logic bank0 memory array (8192 x 2048 x 8) sense amplifiers bank1 bank2 bank3 13 11 1 2 2 refresh counter 4 4 4 input register 1 1 1 1 1 8 8 2 8 clk out data mask data ck, col0 col0 col0 clk in mux dqs generator 4 4 4 4 4 8 dq0-dq3, dm dqs 1 read latch write fifo & drivers note: this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circui t implementation. note: dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional dq and dqs signals. column decoder 2048 (x8) row-address mux registers 13 16384 bank0 row-address latch & decoder 8192 address register drivers bank control logic 15 ck
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 9 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. block diagram (64mb x 8) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 11 command decode a0-a12, ba0, ba1 cke 15 15 i/o gating dm mask logic bank0 memory array (8192 x 1024 x 16) sense amplifiers bank1 bank2 bank3 13 10 1 2 2 refresh counter 8 8 8 input register 1 1 1 1 1 16 16 2 16 clk out data mask data ck, col0 col0 col0 clk in mux dqs generator 8 8 8 8 8 16 dq0-dq7, dm dqs 1 read latch write fifo & drivers note: this functional block diagram is intended to facilitate us er understanding of the operation of the device; it does not represen t an actual circuit implementation. note: dm is a unidirectional si gnal (input only), but is internally loaded to match the load of the bidi- rectional dq and dqs signals. column decoder 1024 (x16) row-address mux registers 13 16384 bank0 row-address latch & decoder 8192 address register drivers bank control logic 13 ck
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 10 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. block diagram (32mb x 16) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 10 command decode a0-a12, ba0, ba1 cke 15 15 i/o gating dm mask logic bank0 memory array (8192 x 512 x 32) sense amplifiers bank1 bank2 bank3 13 9 1 2 2 refresh counter 16 16 16 input register 1 1 1 1 1 32 32 2 32 clk out data mask data ck, col0 col0 col0 clk in mux dqs generator 16 16 16 16 16 32 dq0-dq15, ldm, udm ldqs,udqs 2 read latch write fifo & drivers note: this functional block diagram is intended to facilitate us er understanding of the operation of the device; it does not represen t an actual circuit implementation. note: udm and ldm are unidirectional signals (input onl y), but is internally loaded to match the load of the bidirectional dq, udqs, and ldqs signals. column decoder 512 (x32) row-address mux registers 13 16384 bank0 row-address latch & decoder 8192 address register drivers bank control logic 13 ck
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 11 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. functional description the 512mb ddr sdram is a high-speed cmos, dynamic rando m-access memory containing 536,870,912 bits. the 512mb ddr sdram is internally configured as a quad-bank dram. the 512mb ddr sdram uses a double-data-rate architecture to achieve high-speed operation. the double-data-rate architec- ture is essentially a 2n prefetch architecture, wit h an interface designed to transfer tw o data words per clock cycle at the i/o pins. a single read or write access for the 512mb ddr sdram consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corr esponding n-bit wide, one-half clock cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected lo cation and continue for a pro- grammed number of locations in a programm ed sequence. accesses begin wit h the registration of an active command, which is then followed by a read or write command. the address bits r egistered coincident with the ac tive command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0 -a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. initialization only one of the following two conditions must be met. ? no power sequencing is specified during power up or power down given the following criteria: v dd and v ddq are driven from a single power converter output v tt meets the specification a minimum resistance of 42 ohms limits the input current from the vtt supply into any pin and v ref tracks v ddq /2 or ? the following relationships must be followed: v ddq is driven after or with v dd such that v ddq < v dd + 0.3v v tt is driven after or with v ddq such that v tt < v ddq + 0.3v v ref is driven after or with v ddq such that v ref < v ddq + 0.3v the dq and dqs outputs are in the high-z state, where they remain until driven in normal operation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable command. once the 200 s delay has been satisfied, a deselect or nop comma nd should be applied, and cke must be brought high. following the nop command, a precharge a ll command must be applied. next a mode register set command must be issued for the extended mode register, to enable the dll, then a mode register set command must be issued for the mode register, to reset the dll, and to program the operating parameters. 200 clock cycles are required between the dll reset and any read command. a precharge all command should be applie d, placing the device in the ?all banks idle? state once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated (i.e. to program o perating parameters without resetting the dll) must be performed . following these cycles, the ddr sdra m is ready for normal operation. ddr sdram?s may be reinitialized at any time during normal opera tion by asserting a valid mrs command to either the base or extended mode registers without affecting th e contents of the memory array. the cont ents of either the mode register or extended mode register can be modified at any valid time duri ng device operation without affecti ng the state of the internal address refresh counters used for device refresh.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 12 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. register definition mode register the mode register is used to define the specific mode of operatio n of the ddr sdram. this definition includes the selection of a burst length, a burst ty pe, a cas latency, and an operating mode. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing). mode register bits a0-a2 specify the burst length, a3 specifies the type of burst (s equential or interleaved), a4-a6 specify th e cas latency, and a7-a12 specify the operating mode. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of thes e requirements results in unspecified operation. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effect ively selected. all accesses for that burst take place within this block, meaning that the burs t wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two, by a 2 -ai when the burst length is set to four and by a 3 -ai when the burst length is set to eight (where ai is the most significa nt column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the st arting location within the block. the programmed burst length applies to both read and write bursts.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 13 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. mode register operation a8 a7 a6 a5 a4 cas latency a3 a2 a1 a0 burst length bt address bus cas latency a6 a5 a4 latency 0 0 0 reserved 0 0 1 reserved 010 2 0 1 1 3 (option) 1 0 0 reserved 101 1.5 (option) 110 2.5 1 1 1 reserved burst length a2 a1 a0 burst length 000 reserved 001 2 010 4 011 8 100 reserved 101 reserved 110 reserved 111 reserved ba1 ba0 a11 a10 a9 0* 0* mode register operating mode * ba0 and ba1 must be 0, 0 to select the mode register (vs. the extended mode register). a12 - a9 a8 a7 a6 - a0 operating mode 000valid normal operation do not reset dll 010valid normal operation in dll reset 001vs ** vendor-specific test mode ??? reserved a3 burst type 0 sequential 1 interleave vs ** vendor specific a12
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 14 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. notes: 1. for a burst length of two, a1-a i selects the two-data-e lement block; a0 se lects the first acce ss within the block. 2. for a burst length of four, a2-a i selects the four-data-element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-a i selects the eight-data- element block; a0-a2 selects th e first access within the block. 4. whenever a boundary of the block is reached within a give n sequence above, the following access wraps within the block. burst type accesses within a given burst may be programmed to be either sequ ential or interleaved; this is re ferred to as the burst type and is selected via bit a3. the ordering of accesses within a bu rst is determined by the burst length, the burst type and the s tart- ing column address, as shown in burst definition on page 14. read latency the read latency, or cas latency, is the delay, in clock cycle s, between the registration of a read command and the availabilit y of the first burst of output data. the latency can be pr ogrammed 2 or 2.5 clocks for ddr266/333 and 3 clocks for ddr400. if a read command is registered at clock edge n, and the latency is m clocks, the data is availabl e nominally co incident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. burst definition burst length starting column address order of accesses within a burst a2 a1 a0 type = sequential type = interleaved 2 0 0-1 0-1 11-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 15 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. operating mode the normal operating mode is selected by issuing a mode regist er set command with bits a7-a12 to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a m ode register set command with bits a7 and a9-a12 each set to zero, bit a8 set to one, and bits a0-a6 set to the desired va lues. a mode register set command issued to reset the dll should always be followed by a mode register set command to select normal operating mode. all other combinations of values for a7-a 12 are reserved for future use and/or test modes. test modes and reserved states should not be used as unknown operation or inco mpatibility with future versions may result. cas latencies nop nop nop nop nop read cas latency = 2, bl = 4 shown with nominal t ac , t dqsck , and t dqsq . ck ck command dqs dq don?t care cl=2 nop nop nop nop nop read cas latency = 2.5, bl = 4 ck ck command dqs dq cl=2.5
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 16 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. extended mode register the extended mode register controls fu nctions beyond those controlled by the mo de register; these additional functions include dll enable/disable, bit a0; output drive strength selection, bit a1; and qfc output enable/disable, bit a2 (ntc optional). these functions are controlled via the bit settings shown in the extended mode register definition. the extended mode register is programmed via the mode register set command (with ba0 = 1 and ba1 = 0) and retains the stored informa- tion until it is programmed again or the device loses power. t he extended mode register must be loaded when all banks are idle, and the controller must wait the specified time before init iating any subsequent operation. violating either of these req uire- ments result in unspecified operation. dll enable/disable the dll must be enabled for normal operation. dll enable is r equired during power up initialization, and upon returning to nor- mal operation after having disabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enable d, 200 clock cycles must occur to a llow time for the internal clock to lock to the externally applied clock before a read command can be issued. this is the reason for introducing timing parameter t xsrd for ddr sdram?s (exit self refresh to read com- mand). non- read commands can be issued 2 clocks after the dll is enabled via the emrs command (t mrd ) or 10 clocks after the dll is enabled via self refresh exit command (t xsnr , exit self refresh to non-read command). output drive strength the normal drive strength for all output s is specified to be sstl_2, class ii. qfc enable/disable the qfc signal is an optional dram output control used to isolat e module loads (dimms) from the system memory bus by means of external fet switches when the giv en module (dimm) is not being accessed. the qfc function is an optional feature for nanya and is not included on all ddr sdram devices.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 17 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. extended mode register definition a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address bus drive strength a 1 drive strength 0normal 1 reserved ba1 ba0 operating mode a 11 a 10 a 9 0 * 1 * * ba0 and ba1 must be 1, 0 to select the extended mode register mode register extended ds dll a 0 dll 0 enable 1 disable a12 - a3 a2 - a0 operating mode 0 valid normal operation ?? all other states reserved (vs. the base mode register) qfc a 2 qfc 0 disable 1 enable (optional) a 12
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 18 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. commands truth tables 1a and 1b provide a reference of the commands s upported by ddr sdram devices. a verbal description of each commands follows. truth table 1a: commands name (function) cs ras cas we address mne notes deselect (nop) h x x x x nop 1, 9 no operation (nop) l h h h x nop 1, 9 active (select bank and acti vate row) l l h h bank/row act 1, 3 read (select bank and column, and start read burst) l h l h bank/col read 1, 4 write (select bank and column, and st art write burst) l h l l bank/col write 1, 4 burst terminate l h h l x bst 1, 8 precharge (deactivate row in bank or banks) l l h l code pre 1, 5 auto refresh or self refresh (enter self refresh mode) l l l h x ar / sr 1, 6, 7 mode register set llll op-code mrs 1, 2 1. cke is high for all commands shown except self refresh. 2. ba0, ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selec ts extended mode register; other combinations of ba0-ba1 are reserv ed; a0-a12 provide the op-code to be written to the selected mo de register.) 3. ba0-ba1 provide bank address and a0-a12 provide row address. 4. ba0, ba1 provide bank address; a0-a i provide column address (where i = 9 for x8 and 9, 11 for x4); a10 high enables the auto pre- charge feature (non-persistent), a10 low disables the auto precharge feature. 5. a10 low: ba0, ba1 determ ine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row and bank addressing; all inputs and i/os are ?don?t care? except for cke. 8. applies only to read bursts with auto pr echarge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts 9. deselect and nop are functionally interchangeable. truth table 1b: dm operation name (function) dm dqs notes write enable l valid 1 write inhibit h x 1 1. used to mask write data; provided coincident with the corresponding data.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 19 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. deselect the deselect function pr events new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to a ddr sdram. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mode register set the mode registers are loaded via inputs a0-a12, ba0 and ba1 while issuing the mode register set command. see mode reg- ister descriptions in the register definition section. the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent ex ecutable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a12 selects the row. this row remains active (or open) for accesses until a precharge (or read or write with auto precharge) is issued to that ban k. a precharge (or read or write with auto precharge) command must be issued and complete d before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 9, j = don?t care] for x8; where [i = 9, j = 11] for x4) sel ects the starting column location. the value on input a10 determines wh ether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the read burst; if auto precharge is not selected, the row remains open for subsequent accesses. write the write command is used to initiate a bu rst write access to an active (open) ro w. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 9, j = don?t care] for x8; where [i = 9, j = 11] for x4) sel ects the starting column location. the value on input a10 determines wh ether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the write bu rst; if auto precharge is not selected, the row remain s open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresp onding data is written to memory; if the dm signal is registered high, the corresponding data inputs are ignored, and a write is not executed to that byte/column location. precharge the precharge command is used to deactivate (close) the open ro w in a particular bank or the open row(s) in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don? t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 20 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. auto precharge auto precharge is a feature which performs the same individual-bank precharge functi on described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or writ e command is automatically performed upon completion of the read or write burst. auto precharge is non-persistent in that it is either enabled or disabled for each indiv idual read or write command. auto precharge ensures that the precharge is initiated at the earliest va lid stage within a burst. this is determined as if an explicit precharge command was i ssued at the earliest possible time without violating t ras (min). the user must not issue another command to th e same bank until the precharge (t rp ) is completed. the ntc ddr sdram devices supports the optional t ras lockout feature. this feature allows a read command with auto pre- charge to be issued to a bank that has been activated (opened) but has not yet satisfied the t ras (min) specification. the t ras lockout feature essentially delays the onset of the auto prechar ge operation until two conditions occur. one, the entire burst length of data has been successfully prefetched from the memory array; and two, t ras (min) has been satisfied. as a means to specify whether a ddr sdram device supports the t ras lockout feature, a new parameter has been defined, t rap (ras command to read command with auto precharge or bett er stated bank activate to read command with auto pre- charge). for devices that support the t ras lockout feature, t rap = t rcd (min). this allows any read command (with or without auto precharge) to be issued to an open bank once t rcd (min) is satisfied. burst terminate the burst terminate command is used to trun cate read bursts (with auto precharge di sabled). the most re-cently registered read command prior to the burst terminate co mmand is truncated, as shown in the oper ation section of this data sheet. write burst cycles are not to be terminated with the burst te rminate command. t rap definition ck ck command dq (bl=2) t rapmin nop act nop rd a nop nop nop nop act nop nop t rcdmin t rasmin dq0 dq1 the above timing diagrams show the effects of t rap for devices that support t ras lockout. in these cases, the read with auto precharge command (rda) is issued with t rcd (min) and dataout is available with the shortest latency from the bank activate command (act). the internal prechar ge operation, however, does not begin until after t ras (min) is satisfied. cl=2, t ck =10ns command dq (bl=4) nop act nop rd a nop nop nop nop act nop nop dq0 dq1 dq2 dq3 command dq (bl=8) nop act nop rd a nop nop nop nop nop act nop dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 * * * * indicates auto precharge begins here t rpmin t rpmin t rpmin
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 21 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. auto refresh auto refresh is used during normal operation of the ddr sdram and is analogous to cas before ras (cbr) refresh in pre- vious dram types. this command is nonpersistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh co ntroller. this makes the address bits ?don?t care? during an auto refresh command. the 512mb ddr sdram requires auto refr esh cycles at an average periodic interval of 7.8 s (maximum). self refresh the self refresh command can be used to retain da ta in the ddr sdram, ev en if the rest of the system is powered down. when in the self refresh mode, the ddr s dram retains data without external clocking . the self refresh command is initiated as an auto refresh command coincident with cke transitioning low. the dll is automatically disabled upon entering self refresh, and is automatically enabled upon exiting self refres h (200 clock cycles must then occur before a read command can be issued). input signals except cke (low) ar e ?don?t care? during self refresh operation. the procedure for exiting self refresh requ ires a sequence of commands. ck (and ck ) must be stable prior to cke returning high. once cke is high, the sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for 200 clock cycles before app lying any other command.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 22 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. operations bank/row activation before any read or write commands can be issued to a bank within the ddr sdram, a row in that bank must be ?opened? (activated). this is accomplished via the active command and addresses a0-a12, ba0 and ba1 (see activating a specific row in a specific bank), which decode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. a s ubsequent active com- mand to a different row in the same bank can only be issued after the previous acti ve row has been ?closed? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active com- mand to another bank can be issued while the first bank is bein g accessed, which results in a reduction of total row-access overhead. the minimum time interval between successiv e active commands to different banks is defined by t rrd . activating a specific row in a specific bank ra ba high ra = row address. ba = bank address. ck ck cke cs ras cas we a0-a12 ba0, ba1 don?t care
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 23 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. reads subsequent to programming the mode register with cas latency, burst type, and burst length, r ead bursts are initiated with a read command. the starting column and bank addresses are provided with th e read command and auto precharge is either enabled or dis- abled for that burst access. if auto prechar ge is enabled, the row that is accessed st arts precharge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out el ement from the starting column address is available following the cas latency after th e read command. each subsequent data-out el ement is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of ck and ck ). the following timing figure entitled ?read burst: cas latencies (burst length=4)? illustrates the general timing for each supported cas latency setting. dqs is driven by the ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coinci dent with the last data-out elemen t is known as the read post- amble. upon completion of a burst, assuming no other comma nds have been initiated, the dqs and dqs goes high-z. data from any read burst may be concatenated with or truncated with data from a subsequent read command. in either case, a con- tinuous flow of data can be maintained. the first data element from the new burst follows either the last element of a complete d burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs ( pairs are required by the 2n prefetch architecture). this is shown in timing figure entitled ?consecutive read bursts: cas latencies (b urst length =4 or 8)? . a read command can be initia ted on any positive clock cycle following a prev ious read command. nonc onsecutive read data is shown in timing figure entitled ?non- consecutive read bursts: cas latencies (bur st length = 4)?. full-speed random read accesses: cas latencies (burst length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 28. t rcd and t rrd definition row act nop col row ba y ba y ba x act nop nop ck ck command a0-a12 ba0, ba1 don?t care rd/wr t rcd t rrd rd/wr nop nop
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 24 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. read command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don?t care ca x4: a0-a9, a11 x8: a0-a9 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 25 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. read burst: cas latenci es (burst length = 4) cas latency = 2 nop nop nop nop nop read ck ck command address dqs dq cas latency = 2.5 don?t care ba a,col n doa-n cl=2.5 nop nop nop nop nop read ck ck command address dqs dq ba a,col n doa-n do a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . cl=2 qfc qfc t qcs t qch (optional) t qch (optional) t qcs qfc is an open drain driver. the output high level is achi eved through an external pull up resistor connected to v ddq .
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 26 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. consecutive read bursts: cas late ncies (burst length = 4 or 8) cas latency = 2 nop read nop nop nop read ck ck command address dqs dq cl=2 baa, col n baa, col b don?t care do a-n (or a-b) = data out from bank a, column n (or bank a, column b). when burst length = 4, the bursts are concatenated. when burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following do a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following do a-b. shown with nominal t ac , t dqsck , and t dqsq . cas latency = 2.5 nop read nop nop nop read ck ck command address dqs dq cl=2.5 baa, col n baa,col b doa-n doa- n doa- b doa-b
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 27 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. non-consecutive read bursts: cas latencies (burst length = 4) cas latency = 2 nop nop read nop nop read ck ck command address dqs dq do a-n doa- b do a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programm ed order following do a-n (and following do a-b). shown with nominal t ac , t dqsck , and t dqsq . don?t care baa, col n baa, col b cl=2 cas latency = 2.5 nop nop read nop nop read do a-n doa- b baa, col n baa, col b cl=2.5 ck ck command address dqs dq nop
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 28 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. random read accesses: cas latencies (burst le ngth = 2, 4 or 8) doa-n cas latency = 2 read read read nop nop read doa-b doa-n' doa-x doa-x' doa-b? doa-g ck ck command address dqs dq do a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of n, etc. (i.e., column address lsb inverted). reads are to active rows in any banks. shown with nominal t ac , t dqsck , and t dqsq . don?t care baa, col n baa, col x baa, col b baa, col g cl=2 doa-n cas latency = 2.5 read read read nop nop read doa-b doa-n' doa-x doa-x' doa-b? ck ck command address dqs dq baa, col n baa, col x baa, col b baa, col g cl=2.5
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 29 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. data from any read burst may be truncated with a burst terminate command, as shown in timing figure entitled terminating a read burst: cas latencies (burst length = 8) on page 30. the burst terminate latency is equal to the read (cas) latency, i.e. the burst terminate command shoul d be issued x cycles after the read command , where x equals the num ber of desired data element pairs. data from any read burst must be completed or truncated befor e a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in timing figure entitled read to write: cas latencies (burst length = 4 or 8) on page 31. the example is shown for t dqss (min). the t dqss (max) case, not shown here, has a longer bus idle time. t dqss (min) and t dqss (max) are defined in t he section on writes. a read burst may be followed by, or trun cated with, a precharge command to the sa me bank (provided that auto precharge was not activated). the precharge command should be issued x cycl es after the read command, where x equals the number of desired data element pairs (pairs are required by the 2n pref etch architecture). this is shown in timing figure read to pre- charge: cas latencies (b urst length = 4 or 8) on page 32 for read latencies of 2 and 2.5. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data elements. in the case of a read being executed to completion, a precha rge command issued at the optimum time (as described above) provides the same operation that would result from the same read burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the pr echarge command is that it c an be used to truncate bursts.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 30 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. terminating a read burst: cas la tencies (burst length = 8) cas latency = 2 nop bst nop nop nop read ck command address dqs dq do a-n = data out from bank a, column n. cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . doa-n don?t care ck baa, col n cl=2 cas latency = 2.5 nop bst nop nop nop read ck command address dqs dq doa-n ck baa, col n cl=2.5 no further output data after this point. dqs tristated. no further output data after this point. dqs tristated.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 31 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. read to write: cas latenci es (burst length = 4 or 8) cas latency = 2 bst nop write nop nop read di a-b ck ck command address dqs dq dm doa-n do a-n = data out from bank a, column n 1 subsequent elements of data out appear in the programmed order following do a-n. data in elements are applied following dl a-b in the programmed order, according to burst length. don?t care baa, col n baa, col b cl=2 t dqss (min) cas latency = 2.5 bst nop nop write nop read ck ck command address dqs dq dm doa-n baa, col n baa, col b cl=2.5 t dqss (min) dla-b shown with nominal t ac , t dqsck , and t dqsq . . di a-b = data in to bank a, column b
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 32 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. read to precharge: cas latenc ies (burst length = 4 or 8) cas latency = 2 nop pre nop nop act read ck ck command address dqs dq doa-n do a-n = data out from bank a, column n. cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . don?t care ba a, col n ba a or all ba a, row cl=2.5 cas latency = 2.5 nop pre nop nop act read ck ck command address dqs dq doa-n t rp ba a, col n ba a or all ba a, row cl=2 t rp
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 33 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. writes write bursts are initiated with a write command, as shown in timing figure write command on page 34. the starting column and bank addresses are provided with the wr ite command, and auto precharge is either enabled or dis- abled for that access. if auto precharge is enabled, the row be ing accessed is precharged at th e completion of the burst. for the generic write commands used in the followin g illustrations, auto precharge is disabled. during write bursts, the first valid data-in element is register ed on the first rising edge of dqs following the write command, and subsequent data elements are regi stered on successive edges of dqs. the lo w state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time betw een the write command and the first corresponding rising edge of dqs (t dqss ) is specified with a relatively wide range (from 75% to 125 % of one clock cycle), so most of the writ e diagrams that follow are drawn for the two extreme cases (i.e. t dqss (min) and t dqss (max)). timing figure write burst (burst length = 4) on page 35 shows the two extremes of t dqss for a burst of four. upon completion of a burst, a ssuming no other commands have been initiated, the dqs and dqs enters high-z and any additional input data is ignored. data for any write burst may be concatenate d with or truncated with a s ubsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any positive edge of clock following the previ- ous write command. the first data element from the new burst is applied after either th e last element of a completed burst or the last desired data element of a longer burst which is be ing truncated. the new write command should be issued x cycles after the first write command, where x equal s the number of desired data element pairs (pairs are required by the 2n prefetch architecture). timing figure write to write (b urst length = 4) on page 36 shows concatenated bur sts of 4. an example of non- consecutive writes is shown in timing figure write to write: max dqss, non- consecutive (burst length = 4) on page 37. full- speed random write accesses within a page or pages can be performed as shown in timing figure random write cycles (burst length = 2, 4 or 8) on page 38. data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr (write to read) should be me t as shown in timing figure write to read: non-interrupting (cas latency = 2; burst length = 4) on page 39. data for any write burst may be truncated by a subsequent (inte rrupting) read command. this is illustrated in timing figures ?write to read: interrupting (cas latency =2; bu rst length = 8)?, ?write to read: minimum d qss , odd number of data (3 bit write), interrupting (cas latency = 2; burst length = 8)?, and ?write to read: nominal d qss , interrupting (cas latency = 2; burst length = 8)?. note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in must be masked with dm, as shown in the diagrams noted previously. data for any write burst may be followed by a subsequent prechar ge command. to follow a writ e without truncating the write burst, t wr should be met as shown in timing figure write to precharge: non-inte rrupting (burst length = 4) on page 43. data for any write burst may be truncated by a subse quent precharge command, as shown in timing figures write to pre- charge: interrupting (burst length = 4 or 8) on page 44 to write to precharge: nominal dqss (2 bit write), interrupting (burst length = 4 or 8) on page 46. note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data in should be masked with dm . following the precharge comma nd, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a write burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that w ould result from the same burst with auto precharge. the disadvantage of the pre- charge command is that it requi res that the command and address busses be ava ilable at the appropriate time to issue the com- mand. the advantage of the prec harge command is that it can be used to truncate bursts.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 34 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don?t care ca x4: a0-a9, a11 x8: a0-a9 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 35 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write burst (burst length = 4) t1 t2 t3 t4 t dqss (max) nop nop nop write di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. a10 is low with the write comm and (auto precharge is disabled). ck ck command address dqs dq dm don?t care maximum d qss ba a, col b t1 t2 t3 t4 t dqss (min) nop nop nop write ck ck command address dqs minimum d qss ba a, col b dq dm dla-b dla-b qfc t qcsw (max) t qchw (min) (optional) qfc t qcsw (max) t qchw (max) qfc is an open drain driver. its output high le vel is achieved through an externally c onnected pull up resistor connected to v ddq .
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 36 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write to write (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) maximum d qss nop write nop nop nop write di a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. each write command may be to any bank. ck ck command address dqs dq dm don?t care t1 t2 t3 t4 t5 t6 minimum d qss nop write nop nop nop write ck ck command address dqs dq dm baa, col b baa, col n ba, col b ba, col n t dqss (min) di a-b di a-n di a-b di a-n
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 37 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write to write: max dqss, non- consecutive (burst length = 4) t1 t2 t3 t4 t5 t dqss (max) nop nop write nop write di a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. each write command may be to any bank. ck ck command address dqs dq dm don?t care baa, col b baa, col n di a-b di a-n
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 38 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. random write cycles (burst length = 2, 4 or 8) t1 t2 t3 t4 t5 t dqss (max) maximum d qss write write write write write di a-b di a-n di a-b, etc. = data in for bank a, column b, etc. b', etc. = odd or even complement of b, etc. (i.e., column address lsb inverted). each write command may be to any bank. di a-b? di a-x di a-x? di a-n? di a-a di a-a? ck ck command address dqs dq dm don?t care baa, col b baa, col x baa, col n baa, col a baa, col g t1 t2 t3 t4 t5 minimum d qss write write write write write di a-b di a-n di a-b? di a-x di a-x? di a-n? di a-a di a-a? ck ck command address dqs dq dm baa, col b baa, col x baa, col n baa, col a baa, col g t dqss (min) di a-g
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 39 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write to read: non-inte rrupting (cas latency = 2; burst length = 4) cl = 2 t1 t2 t3 t4 t5 t6 t wtr nop nop nop read write di a-b nop di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t wtr is referenced from the first positiv e ck edge after the last data in pair. a10 is low with the write command (auto precharge is disabled). the read and write commands may be to any bank. ck ck command address dqs dq dm don?t care maximum d qss baa, col b baa, col n t1 t2 t3 t4 t5 t6 t wtr nop nop nop read write nop ck ck command address minimum d qss baa, col b baa, col n t dqss (max) di a-b dqs dq dm t dqss (min) cl = 2
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 40 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write to read: interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (max) maximum d qss nop nop nop read write nop di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). the read and write commands are not necessarily to the same bank. dia- b ck ck command address dqs dq dm don?t care baa, col b baa, col n t wtr cl = 2 t1 t2 t3 t4 t5 t6 minimum d qss nop nop nop read write nop ck ck command address baa, col b baa, col n t wtr di a-b dqs dq dm cl = 2 t dqss (min) 1 = these bits are incorrectly written into the memory array if dm is low. 11 11
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 41 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write to read: minimum dqss, odd number of data (3 bit write) , interrupting (cas latency = 2; burst length = 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last desired data in pair (not the last desired data in element) the read command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). the read and write commands are not necessarily to the same bank. don?t care t1 t2 t3 t4 t5 t6 nop nop nop read write nop ck ck command address baa, col b baa, col n t wtr di a-b dqs dq cl = 2 t dqss (min) dm 122 1 = this bit is correctly written into the memory array if dm is low. 2 = these bits are incorrectly written into the memory array if dm is low.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 42 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write to read: nominal dqss, interrupti ng (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (nom) nop nop nop read write nop di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last desired data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). the read and write commands are not necessarily to the same bank. di a-b ck ck command address dqs dq dm don?t care baa, col b baa, col n t wtr cl = 2 1 = these bits are incorrectly written into the memory array if dm is low. 1 1
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 43 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write to precharge: non-interr upting (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) nop nop nop nop write di a-b pre di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t wr is referenced from the first positive ck edge after the last data in pair. a10 is low with the write comm and (auto precharge is disabled). ck ck command address dqs dq dm don?t care ba a, col b ba (a or all) t wr maximum d qss t1 t2 t3 t4 t5 t6 nop nop nop nop write pre ck ck command address ba a, col b ba (a or all) t wr minimum d qss di a-b dqs dq dm t dqss (min) t rp t rp
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 44 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write to precharge: interrupti ng (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data el ements in the burst, for burst length = 8. a10 is low with the write comm and (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address maximum d qss di a-b 11 2 dqs dq dm t dqss (max) t rp t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) minimum d qss t wr t rp di a-b 11 dqs dq dm t dqss (min) 2 ba a, col b ba (a or all) t wr 3 = these bits are incorrectly written into the memory array if dm is low. 3 3 3 3
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 45 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write to precharge: minimum dqss, odd numb er of data (1 bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 1 data element is written. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) t wr t rp di a-b dqs dq t dqss (min) 2 11 dm 344 3 = this bit is correctly written in to the memory array if dm is low. 4 = these bits are incorrectly written into the memory array if dm is low.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 46 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write to precharge: nominal dq ss (2 bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) t rp t dqss (nom) di a-b 1 2 dqs dq dm 1 t wr 3 3 3 = these bits are incorrectly written into the memory array if dm is low.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 47 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) is available for a subsequent row access some specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. precharge command ba high ba = bank address ck ck cke cs ras cas we a10 ba0, ba1 don?t care all banks one bank (if a10 is low, otherwise don?t care). a0-a9, a11, a12
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 48 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. power down power down is entered when cke is registered low (no accesse s can be in progress). if power down occurs when all banks are idle, this mode is referred to as precharge power down; if power down occurs when there is a row active in any bank, this mode is referred to as active power down. entering power do wn deactivates the input and output buffers, excluding ck, ck and cke. the dll is still running in power down mode, so for ma ximum power savings, the user has the option of disabling the dll prior to entering power do wn. in that case, the dll must be enabled afte r exiting power down, and 200 clock cycles must occur before a read command can be issued. in power down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr sdram, and all other input signals are ?d on?t care?. however, power down duration is limited by the refresh requirements of the device, so in most applications, th e self refresh mode is preferred over the dll-disabled power down mode. the power down state is synchronously exit ed when cke is registered high (along with a nop or deselect command). a valid, executable command may be applied one clock cycle later. power down t is t is ck ck cke command no column access in progress valid nop valid don?t care exit power down mode enter power down mode (burst read or write operation must not be in progress) nop t pdex
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 49 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. truth table 2: clock enable (cke) 1. cke n is the logic state of cke at clock edge n: c ke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command n is the command registered at clock e dge n, and action n is a result of command n. 4. all states and sequences not shown are illegal or reserved. current state cke n-1 cken command n action n notes previous cycle current cycle self refresh l l x maintain self-refresh self refresh l h deselect or nop exit self-refresh 1 power down l l x maintain power down power down l h deselect or nop exit power down all banks idle h l deselect or nop precharge power down entry all banks idle h l auto re fresh self refresh entry bank(s) active h l deselect or nop active power down entry hh see ?truth table 3: current state bank n - command to bank n (same bank)? on page 50 1. deselect or nop commands should be issued on any cl ock edges occurring during the self refresh exit (t xsnr ) period. a minimum of 200 clock cycles are needed before appl ying a read command to allow the dll to lock to the input clock.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 50 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. truth table 3: current state bank n - command to bank n (same bank) current state cs ras cas we command action notes any h x x x deselect nop. continue previous operation 1-6 l h h h no operation nop. continue previous operation 1-6 idle l l h h active select and activate row 1-6 l l l h auto refresh 1-7 l l l l mode register set 1-7 row active l h l h read select column and start read burst 1-6, 10 l h l l write select column and start write burst 1-6, 10 l l h l precharge deactivate row in bank(s) 1-6, 8 read (auto precharge disabled) l h l h read select column and start new read burst 1-6, 10 l l h l precharge truncate read burst, start precharge 1-6, 8 l h h l burst terminate burst terminate 1-6, 9 write (auto precharge disabled) l h l h read select column and start read burst 1-6, 10, 11 l h l l write select column and start write burst 1-6, 10 l l h l precharge truncate write burst, start precharge 1-6, 8, 11 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted, i.e., the curr ent state is for a specific bank and the commands shown are th ose allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto prechar ge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto prechar ge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the idle state. row activating: starts with registrati on of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with registrati on of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or nop commands, or allowable commands to the other bank should be issued on any cl ock edge occurring during these states. allowable commands to the other bank are determined by its current state and according to truth table 4. 5. the following states must not be interrupted by any execut able command; deselect or nop commands must be applied on each posi tive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ?all banks idle? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ?all banks idle? state. precharging all: starts with registrati on of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. 6. all states and sequences not s hown are illegal or reserved. 7. not bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/action column include r eads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 51 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. truth table 4: current state bank n - command to bank m (different bank) (part 1 of 2) current state cs ras cas we command action notes any h x x x deselect nop/continue previous operation 1-6 l h h h no operation nop/cont inue previous operation 1-6 idle xxxx any command otherwise allowed to bank m 1-6 row activating, active, or precharging l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-7 l h l l write select column and start write burst 1-7 l l h l precharge 1-6 read (auto precharge disabled) l l h h active select and activate row 1-6 l h l h read select column and start new read burst 1-7 l l h l precharge 1-6 write (auto precharge disabled) l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-8 l h l l write select column and start new write burst 1-7 l l h l precharge 1-6 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table describes alternate bank operat ion, except where noted, i.e., the current state is for bank n and the commands sho wn are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are cov- ered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto prechar ge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precha rge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see note 10. write with auto precharge enabled: see note 10. 4. auto refresh and mode register set commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not s hown are illegal or reserved. 7. reads or writes listed in the command/action column include r eads or writes with auto prec harge enabled and reads or writes w ith auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of data output. 10. the read with auto precharge enabled or write with auto prechar ge enabled states can each be broken into two parts: the acce ss period and the precharge period. for read with auto precharge, t he precharge period is defined as if the same burst was execute d with auto precharge disabled and then followed with the earliest possible prechar ge command that still accesses all of the data in t he burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access period starts with registration of the command and ends where the precharge period (or t rp ) begins. during the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, active, precharge, read, and write command s to the other bank may be applied; during the access period, only ac tive and precharge commands to the other bank may be applied. i n either case, all other related limitations apply (e.g. c ontention between read data and write data must be avoided).
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 52 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. read (with auto precharge) l l h h active select and activate row 1-6 l h l h read select column and start new read burst 1-7,10 l h l l write select column and start write burst 1-7,9,10 l l h l precharge 1-6 write (with auto precharge) l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-7,10 l h l l write select column and start new write burst 1-7,10 l l h l precharge 1-6 truth table 4: current state bank n - command to bank m (different bank) (part 2 of 2) current state cs ras cas we command action notes 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table describes alternate bank operat ion, except where noted, i.e., the current state is for bank n and the commands sho wn are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are cov- ered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto prechar ge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precha rge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see note 10. write with auto precharge enabled: see note 10. 4. auto refresh and mode register set commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not s hown are illegal or reserved. 7. reads or writes listed in the command/action column include r eads or writes with auto prec harge enabled and reads or writes w ith auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of data output. 10. the read with auto precharge enabled or write with auto prechar ge enabled states can each be broken into two parts: the acce ss period and the precharge period. for read with auto precharge, t he precharge period is defined as if the same burst was execute d with auto precharge disabled and then followed with the earliest possible prechar ge command that still accesses all of the data in t he burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access period starts with registration of the command and ends where the precharge period (or t rp ) begins. during the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, active, precharge, read, and write command s to the other bank may be applied; during the access period, only ac tive and precharge commands to the other bank may be applied. i n either case, all other related limitations apply (e.g. c ontention between read data and write data must be avoided).
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 53 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. simplified state diagram self auto idle mrs emrs row precharge power write power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh down power down active on a read a read a write a burst stop preall active precharge precharge preall read write preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 54 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to v ss ? 0.5 to v ddq + 0.5 v v in voltage on inputs relative to v ss ? 0.5 to + 3.6 v v dd voltage on v dd supply relative to v ss ? 0.5 to + 3.6 v v ddq voltage on v ddq supply relative to v ss ? 0.5 to + 3.6 v t a operating temperature (ambient) 0 to + 70 c t stg storage temperature (plastic) ? 55 to + 150 c p d power dissipation 1.0 w i out short circuit output current 50 ma note: stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rat- ing only, and functional operation of the dev ice at these or any other conditions abov e those indicated in the operational sect ions of this speci- fication is not implied. exposure to absolute maximum rati ng conditions for extended peri ods may affect reliability.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 55 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. capacitance parameter symbol min. max. units notes input capacitance: ck, ck ci 1 2.0 3.0 pf 1 delta input capacitance: ck, ck delta ci 1 0.25 pf 1 input capacitance: all other input-only pins (except dm) ci 2 2.0 3.0 pf 1 delta input capacitance: all other input-only pins (except dm) delta ci 2 0.5 pf 1 input/output capacitance: dq, dqs, dm c io 4.0 5.0 pf 1, 2 delta input/output capacitance: dq, dqs, dm delta c io 0.5 pf 1 1. v ddq = v dd = 2.5v 0.2v (minimum range to maximum range), f = 100mhz, t a = 25 c, vo dc = v ddq/2 , vo peak -peak = 0.2v. 2. although dm is an input-only pin, the input capacitance of this pin must model the input capa citance of the dq and dqs pins. this is required to match input propagation time s of dq, dqs and dm in the system. dc electrical characteristics and operating conditions (0c t a 70 c; v ddq = v dd = + 2.5v 0.2v (ddr266/333); v ddq = v dd = + 2.6v 0.1v (ddr400), see ac characteristics) symbol parameter min max units notes v dd supply voltage ddr266/333 2.3 2.7 v 1 v dd supply voltage ddr400 2.5 2.7 v 1 v ddq i/o supply voltage ddr266/333 2.3 2.7 v 1 v ddq i/o supply voltage ddr400 2.5 2.7 v 1 v ss , v ssq supply voltage i/o supply voltage 00v v ref i/o reference voltage 0.49 x v ddq 0.51 x v ddq v1, 2 v tt i/o termination voltage (system) v ref ? 0.04 v ref + 0.04 v 1, 3 v ih(dc) input high (logic1) voltage v ref + 0.15 v ddq + 0.3 v 1 v il(dc) input low (logic0) voltage ? 0.3 v ref ? 0.15 v 1 v in(dc) input voltage level, ck and ck inputs ? 0.3 v ddq + 0.3 v 1 v id(dc) input differential voltage, ck and ck inputs 0.30 v ddq + 0.6 v 1, 4 v ix(dc) input crossing point voltage, ck and ck inputs 0.30 v ddq + 0.6 v 1, 4 vi ratio v-i matching pullup current to pulldown current ratio 0.71 1.4 5 i i input leakage current any input 0v v in v dd ; (all other pins not under test = 0v) ? 22 a1 i oz output leakage current (dqs are disabled; 0v v out v ddq ? 55 a1 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variati ons in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck . 5. the ratio of the pullup current to the pulldown current is s pecified for the same temperature and voltage, over the entire te mperature and voltage range, for device drain to source voltages for 0.25 volt s to 1.0 volts. for a given output, it represents the maximum d ifference between pullup and pulldown drivers due to process variation.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 56 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. normal strength driver pulldown and pullup characteristics 1. the full variation in driver pulldown current from minimum to maximum process, temperatur e and voltage will lie within the outer bounding lines of the v-i curve. 2. it is recommended that the ?typical? ibis pulldown v-i curve lie within the shaded region of the v-i curve. 3. the full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve. 4. it is recommended that the ?typical? ibis pullup v- i curve lie within the shaded region of the v-i curve. i oh output current: nominal strength driver high current (v out = v ddq -0.373v, min v ref , min v tt ) low current (v out = 0.373v, max v ref , max v tt ) ? 16.8 ma 1 i ol 16.8 i ohw output current: half- strength driver high current (v out = v ddq -0.763v, min v ref , min v tt ) low current (v out = 0.763v, max v ref , max v tt ) ? 9.0 ma 1 i olw 9.0 normal strength driver pulldown characteristics dc electrical characteristics and operating conditions (0c t a 70 c; v ddq = v dd = + 2.5v 0.2v (ddr266/333); v ddq = v dd = + 2.6v 0.1v (ddr400), see ac characteristics) symbol parameter min max units notes 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variati ons in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck . 5. the ratio of the pullup current to the pulldown current is s pecified for the same temperature and voltage, over the entire te mperature and voltage range, for device drain to source voltages for 0.25 volt s to 1.0 volts. for a given output, it represents the maximum d ifference between pullup and pulldown drivers due to process variation. 0 2.7 0 140 i out (ma) v out (v) maximum typical high typical low minimum
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 57 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. 5. the full variation in the ratio of the maximum to minimum pullu p and pulldown current will not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. the full variation in the ratio of the ?typical? ibis pullup to ?typical? ibis pulldown current should be unity + 10%, for device drain to source voltages from 0.1 to 1.0. this specification is a design objective only. it is not guaranteed. 7. these characteristics are intended to obey the sstl_2 class ii standard. 8. this specification is intended for ddr sdram only. normal strength driver pullup characteristics maximum typical high typical low minimum v out (v) 2.7 0 0 -200 i out (ma)
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 58 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. normal strength driver pu lldown and pullup currents pulldown current (ma) pullup current (ma) voltage (v) typical low typical high min max typical low typical high min max 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 normal strength driver evaluation conditions typical minimum maximum temperature (t ambient ) 25 c 70 c0 c v ddq 2.5v 2.3v 2.7v process conditions typical process slow-slow process fast-fast process
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 59 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. ac characteristics (notes 1-5 apply to the following tables; electrical characteri stics and dc operating conditions, ac operating conditions, i dd specifications and conditions, and electr ical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operat ion are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. re fer to the ac output load circuit below. 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environm ent, but input timing is still referenced to v ref (or to the crossing point for ck, ck ), and parameter specifications are guar anteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e . the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level. ac output load circuit diagrams 50 timing reference point output (v out ) 30pf v tt
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 60 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. ac input operating conditions (0 c t a 70 c ; v dd = v ddq = 2.5v 0.2v (ddr266/333); v dd = v ddq = 2.6v 0.1v (ddr400); see ac characteristics) symbol parameter/condition min max unit notes v ih(ac) input high (logic 1) voltage, dq, dqs, and dm signals v ref + 0.31 v 1, 2 v il(ac) input low (logic 0) voltage, dq, dqs, and dm signals v ref ? 0.31 v 1, 2 v id(ac) input differential voltage, ck and ck inputs 0.62 v ddq + 0.6 v 1, 2, 3 v ix(ac) input crossing point voltage, ck and ck inputs 0.5*v ddq ? 0.2 0.5*v ddq + 0.2 v 1, 2, 4 1. input slew rate = 1v/ns . 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. i dd specifications and conditions (0 c t a 70 c ; v dd = v ddq = 2.5v 0.2v (ddr266/333); v dd = v ddq = 2.6v 0.1v (ddr400); see ac characteristics) symbol parameter/condition ddr400 (5t) t ck =5ns ddr333 (6k) t ck =6ns ddr266b (75b) t ck =7.5ns unit notes i dd0 operating current : one bank; active / precharge; t rc = t rc (min); dq, dm, and dqs inputs changing twice per cloc k cycle; address and control inputs changing once per clock cycle 120 110 100 ma 1 i dd1 operating current : one bank; active / read / precharge; burst = 2; t rc = t rc (min); cl = 2.5; i out = 0ma; address and control inputs changing once per clock cycle 140 120 105 ma 1 i dd2p precharge power down standby current : all banks idle; power down mode; cke v il (max) 77 7ma1 i dd2n idle standby current: cs v ih (min); all banks idle; cke v ih (min); address and control inputs c hanging once per clock cycle 35 35 35 ma 1 i dd3p active power down standby current : one bank active; power down mode; cke v il (max) 20 15 15 ma 1 i dd3n active standby current : one bank; active / precharge; cs v ih (min); cke v ih (min); t rc = t ras (max); dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 60 50 50 ma 1 i dd4r operating current: one bank; burst = 2; reads ; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2.5; i out = 0ma 160 140 120 ma 1 i dd4w operating current : one bank; burst = 2; writ es; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per cloc k cycle; cl = 2.5 210 180 150 ma 1 i dd5 auto-refresh current : t rc = t rfc (min) 250 230 210 ma 1 i dd6 self-refresh current : cke 0.2v 5 5 5 ma 1, 2 i dd7 operating curren t: four bank; four bank interleaving with bl = 4, address and control inputs randomly changing; 50% of data changing at every trans- fer; t rc = t rc (min); i out = 0ma. 420 400 380 ma 1 1. i dd specifications are tested after the device is properly initialized. 2. enables on-chip refresh and address counters. values are averaged from high and lo w temp values using x16 devices.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 61 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. electrical characteristi cs & ac timing - absolute specifications (0 c t a 70 c ; v dd = v ddq = 2.5v 0.2v (ddr266/333); v dd = v ddq = 2.6v 0.1v (ddr400); see ac characteristics) symbol parameter ddr400 (5t) ddr333 (6k) ddr266b (75b) unit notes min max min max min max t ac dq output access time from ck/ck ? 0.65 + 0.65 ? 0.7 + 0.7 ? 0.75 + 0.75 ns 1-4 t dqsck dqs output access time from ck/ck ? 0.55 + 0.55 ? 0.6 + 0.6 ? 0.75 + 0.75 ns 1-4 t ch ck high-level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 1-4 t cl ck low-level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 1-4 t ck clock cycle time cl = 3.0 5 8 ns 1-4 cl = 2.5 6 12 6 12 7.5 12 ns 1-4 cl = 2.0 7.5 12 10 12 ns 1-4 t dh dq and dm input hold time 0.4 0.45 0.5 ns 1-4, 15, 16 t ds dq and dm input setup time 0.4 0.45 0.5 ns 1-4, 15, 16 t ipw input pulse width 2.2 2.2 2.2 ns 2-4, 12 t dipw dq and dm input pulse width (each input) 1.75 1.75 1.75 ns 1-4 t hz data-out high-impedance time from ck/ck ? 0.6 + 0.6 ? 0.7 + 0.7 ? 0.75 + 0.75 ns 1-4, 5 t lz data-out low-impedance time from ck/ck ? 0.6 + 0.6 ? 0.7 + 0.7 ? 0.75 + 0.75 ns 1-4, 5 t dqsq dqs-dq skew (dqs & associated dq signals) tsop package + 0.4 + 0.45 + 0.5 ns 1-4 bga package + 0.4 + 0.4 + 0.5 ns 1-4 t hp minimum half clk period for any given cycle; defined by clk high (t ch ) or clk low (t cl ) time min (t cl , t ch ) min (t cl , t ch ) min (t cl , t ch ) t ck 1-4 t qh data output hold time from dqs t hp - t qhs t hp - t qhs t hp - t qhs t ck 1-4 t qhs data hold skew factor tsop package 0.5 0.55 0.75 ns 1-4 bga package 0.5 0.5 0.75 ns 1-4 t dqss write command to 1st dqs latching transition 0.72 1.28 0.75 1.25 0.75 1.25 t ck 1-4 t dqsh dqs input high pulse width (write cycle) 0.35 0.35 0.35 t ck 1-4 t dqsl dqs input low pulse width (write cycle) 0.35 0.35 0.35 t ck 1-4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 0.2 t ck 1-4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0.2 0.2 t ck 1-4 t mrd mode register set command cycle time 2 2 2 t ck 1-4 t wpres write preamble setup time 0 0 0 ns 1-4, 7 t wpst write postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck 1-4, 6 t wpre write preamble 0.25 0.25 0.25 t ck 1-4 t ih address and control input hold time (fast slew rate) 0.60.750.9ns 2-4, 9, 11, 12 t is address and control input setup time (fast slew rate) 0.60.750.9ns 2-4, 9, 11, 12 t ih address and control input hold time (slow slew rate) 0.7 0.8 1.0 ns 2-4, 10-12, 14 t is address and control input setup time (slow slew rate) 0.7 0.8 1.0 ns 2-4, 10, 11, 12, 14 t rpre read preamble 0.9 1.1 0.9 1.1 0.9 1.1 t ck 1-4 t rpst read postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck 1-4
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 62 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. t ras active to precharge command 40 120,000 42 120,000 45 120,000 ns 1-4 t rc active to active/auto-refresh command period 55 60 65 ns 1-4 t rfc auto-refresh to active/auto-refresh command period 70 72 75 ns 1-4 t rcd active to read or write delay 15 18 20 ns 1-4 t rap active to read command with autoprecharge min (t rcd , t ras ) min (t rcd , t ras ) min (t rcd , t ras ) ns 1-4 t rp precharge command period 15 18 20 ns 1-4 t rrd active bank a to active bank b command 10 12 15 ns 1-4 t wr write recovery time 15 15 15 ns 1-4 t dal auto precharge write recovery + precharge time (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) t ck 1-4, 13 t wtr internal write to read command delay 2 1 1 t ck 1-4 t pdex power down exit time 5 6 7.5 ns 1-4 t xsnr exit self-refresh to non-read command 75 75 75 ns 1-4 t xsrd exit self-refresh to read command 200 200 200 t ck 1-4 t refi average periodic refresh interval 7.8 7.8 7.8 s1-4, 8 electrical characteristi cs & ac timing - absolute specifications (0 c t a 70 c ; v dd = v ddq = 2.5v 0.2v (ddr266/333); v dd = v ddq = 2.6v 0.1v (ddr400); see ac characteristics) symbol parameter ddr400 (5t) ddr333 (6k) ddr266b (75b) unit notes min max min max min max
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 63 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. electrical characteristics & ac timing - absolute specifications notes 1. input slew rate = 1v/ns. 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross; the input reference level for signals other than ck/ck is v ref . 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at th e timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific vo ltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic an d meeting the input slew rate specifications of the device. when no writes were previous ly in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in prog ress, dqs could be high, low, or transi tioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefr esh commands can be posted to any given ddr sdram device. 9. for command/address input slew rate 1.0v/ns. slew rate is measured between v oh (ac) and v ol (ac). 10. for command/address input slew rate 0.5v/ns and < 1.0v/ns. slew rate is measured between v oh (ac) and v ol (ac). 11. ck/ck slew rates are 1.0v/ns. 12. these parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. for each of the terms in parentheses, if not alre ady an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. fo r example, for ddr266b at cl = 2.5, t dal = (15ns/7.5ns) + (20ns/7.5ns) = 2 + 3 = 5.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 64 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. 14. an input setup and hold time derating table is used to increase t is and t ih in the case where the input slew rate is below 0.5 v/ns. 15. an input setup and hold time derating table is used to increase t ds and t dh in the case where the i/o slew rate is below 0.5 v/ns. 16. an i/o delta rise, fall derating table is used to increase t ds and t dh in the case where dq, dm, and dqs slew rates differ. input slew rate delta (t is ) delta (t ih ) unit notes 0.5 v/ns 00ps1,2 0.4 v/ns +50 0 ps 1,2 0.3 v/ns +100 0 ps 1,2 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or te ster characterization and are not necessarily tested on each devi ce. input slew rate delta (t ds ) delta (t dh ) unit notes 0.5 v/ns 00ps1,2 0.4 v/ns +75 +75 ps 1,2 0.3 v/ns +150 +150 ps 1,2 1. i/o slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or te ster characterization and are not necessarily tested on each devi ce. input slew rate delta (t ds ) delta (t dh ) unit notes 0.0 v/ns 0 0 ps 1,2,3,4 0.25 v/ns +50 +50 ps 1,2,3,4 0.5 v/ns +100 +100 ps 1,2,3,4 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. input slew rate is based on the larger of ac to ac delta rise, fall rate and dc to dc delta rise, fall rate. 3. the delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] for example: slew rate 1 = 0.5 v/ns; slew rate 2 = 0.4 v/ns delta rise, fall = (1/0.5) - (1/0.4) [ns/v] = -0.5 ns/v using the table above, this would result in an increase in t ds and t dh of 100 ps. 4. these derating parameters may be guaranteed by design or te ster characterization and are not necessarily tested on each devi ce.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 65 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. data input (write) (timing burst length = 4) data output (read) (timing burst length = 4) t dh t ds t dh t ds t dsl di n = data in for column n. 3 subsequent elements of data in are applied in programmed order following di n. di n dqs dq dm don?t care t dsh t dqsq (max) occurs when dqs is the earlie st among dqs and dq signals to transition. dqs dq t dqsq t dqsq data output hold time from data strobe is shown as t qh . t qh is a function of the clock high or low time (t hp ) t qh2 t qh1 t dqsq t qh3 t qh4 t dqsq ck ck t hp t hp t hp t hp1 t hp2 t hp3 t hp4 t hp is the half cycle pulse widt h for each half cycle clock. t hp is referenced to the clock duty cycle only and not to the data strobe (dqs) duty cycle. for that given clock cycle. note correlation of t hp to t qh in the diagram above (t hp1 to t qh1 , etc.).
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 66 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. initialize and mode register sets t ih 200 s t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t mrd t rfc t rfc t rp t mrd t mrd t cl t ck t ch t vtd pre emrs mrs pre ar ar mrs nop act code code code ra code code code ra ba0=l ba0=l ba high-z high-z power-up: v dd and ck stable extended mode register set load mode register, reset dll load mode register (with a8 = l) v dd v ddq v tt (system * ) v ref ck cke command dm a0-a9, a11 a10 ba0, ba1 dqs dq lvcmos low level all banks ba0=h ba1=l ba1=l ba1=l all banks * v tt is not applied directly to the device, however t vtd must be ** t mrd is required before any command can be applied and the two autorefresh commands may be moved to follow the first mrs, greater than or equal to zero to avoid device latchup. 200 cycles of ck are required before a read command can be applied. but precede the second precharge all command. don?t care 200 cycles of ck ** ck
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 67 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. power down mode t ih t is t ih t is t is t is t ih t is t cl t ch t ck nop valid valid * valid valid enter power down mode exit power down mode no column accesses are allowed to be in progress at the time power down is entered. * = if this command is a precharge (or if the device is already in the idle state) then the power down mode shown is precharge power down. if this command is an acti ve (or if at least one row is already active), then the power down mode shown is active power down. cke command addr dqs dq dm don?t care ck ck nop t pdex
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 68 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. auto refresh mode t ih t is t ih t is t ih t is t rfc t rp t cl t ch t ck pre nop nop ar nop ar nop nop nop ra ra ba pre = precharge; act = active; ra = row address; ba = bank address; ar = autorefresh. nop commands are shown for ease of illustration; ot her valid commands may be possible at these times. dm, dq, and dqs signals are all don't care/high-z for operations shown. valid valid act ra cke command a0-a8 a9, a11,a12 a10 ba0, ba1 dqs dq dm bank(s) don?t care all banks one bank t rfc ck ck
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 69 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. self refresh mode 200 cycles t ih t is t xsrd, t xsrn t ih t is t is t is t ih t is t rp * t ck t cl t ch ar valid nop valid enter self refresh mode exit self refresh mode nop * = device must be in the all banks idle state before entering self refresh mode. ** = t xsnr is required before any non-read command can be applied, and t xsrd (200 cycles of ck). cke command addr dqs dq dm don?t care are required before a read command can be applied. ck ck clock must be stable before exiting self refresh mode
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 70 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. read without auto prechar ge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck pre nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are prov ided in the programmed order following do n. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. ba x ba x valid valid valid nop read col n ra ra ba x * do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 all banks one bank t dqsck (max) t rpre cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n ck ck dis ap dis ap = disable auto precharge.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 71 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. read with auto precha rge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck nop nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. en ap = enable auto precharge. act = active; ra = row address. nop commands are shown for ease of illustration; other commands may be valid at these times. ba x valid valid valid nop read col n ra ra do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 t dqsck (max) t rpre cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n en ap ba x ck ck t hz (min)
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 72 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. bank read access (bur st length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t is t cl t ch t ck read nop pre nop nop act nop nop ba x ba x* valid nop act ra ra ba x do n ck ck cke command a10 ba0, ba1 dm dqs dq dqs dq t dqsck (max) t rpre cl=2 cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n col n ra ra all banks ra one bank dis ap ba x t rp do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration ; other commands may be valid at these times. t rcd a0-a9, a11, a12 t ras t rc t lz (min)
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 73 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write without auto prechar ge (burst length = 4) t ih t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t ih t is t rp t cl t ch t ck nop nop nop pre nop nop act nop ba x ba nop write col n ra ra ba x * valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; othe r valid commands may be possible at these times. din ck ck cke command a10 ba0, ba1 dqs dq dm dis ap all banks one bank t wr t wpres t dqsh don?t care a0-a9, a11, a12 t dqss = min. t dqss t wpre t dsh
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 74 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write with auto precharge (burst length = 4) nop commands are shown for ease of illustration; other valid commands may be possible at these times. act = active; ra = row address; ba = bank address. t ih t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t is t rp t cl t ch t ck nop nop nop nop nop nop act nop ba x ba nop write col n ra ra valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. en ap = enable auto precharge. ck ck cke command a10 ba0, ba1 dqs dq dm t wr t dqss t wpres t dqsh don?t care valid valid en ap a0-a9, a11, a12 t dal t dqss = min. t dsh t wpre din
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 75 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. bank write access (b urst length = 4) t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t ih t is t cl t ch t ck t ras write nop nop nop nop pre nop nop ba x nop act ra ra di n = data in for column n. 3 subsequent elements of data in are applie d in the programmed order following di n. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address. nop commands are shown for ease of illustration; ot her valid commands may be possible at these times. din valid ba x cke command a10 ba0, ba1 dqs dq dm ck ck t wpres t wr t rcd all banks one bank dis ap don?t care a0-a9, a11, a12 col n ba x t dqss t dqsh t dsh t wpre t dqss = min.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 76 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. write dm operation (burst length = 4) t ih t wpst t dqsl t ih t is t ih t is t is t rp t cl t ch t ck nop nop nop pre nop nop act nop nop write col n ra din ck ck cke command a10 ba0, ba1 dqs dq dm t wr t dqss don?t care valid t ih t is t ih t is ba x ba ra ba x * all banks one bank dis ap di n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following di n (the second element of the 4 is masked). dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; ot her valid commands may be possible at these times. a0-a9, a11, a12 t dqsh t dsh t dqss = min. t wpres
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 77 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. package dimensions (400mil; 66 lead; thin small outline package) 10.16 . 0.13 11.76 0.20 lead #1 0.65 basic 0.30 - 0.08 + 0.03 0.71ref detail a 0.10 seating plane detail a 0.5 0.1 0.05 min 1.20 max 0.25 basic gage plane 22.22 0.10
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 78 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. package dimensions (60 balls; 0.8mmx1.0mm pitch; wbga package) 0.80 10.00 nom. 9.90 min. 10.10 max. 1.00 12.0 nom. 11.90 min. 12.10 max. 0.25 min. 0.40 max. 1.20 max. dia. 0.40 min 0.50 max note : all dimensions are typical unless otherwise stated . unit : millimeters 6.40 11.00 0.1 min. 0.1 min.
nt5ds128m4bg nt5ds128m4bs nt5ds128m4bf nt5ds128m4bt nt5ds64m8bg nt5ds64m8bs nt5ds64m8bf nt5ds64m8bt nt5ds32m16bg nt5ds32m16bs nt5ds32m16bf nt5ds32m16bt 512mb ddr sdram rev 1.6 27 nov 2007 79 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to cha nge products and specifications without notice. revision log rev date modification 0.1 22 mar 2004 preliminary release 0.2 14 apr 2004 part number updates 0.3 19 apr 2004 correction to tck values in ac/dc timing table 1.0 9 nov 2004 changed bga deminsions from 8x13 to 10x12 mm updated idd data for 333 & 400 speed grades 1.1 17 feb 2005 added green product 1.2 25 feb 2005 correction to idd2p and idd6 in idd specificication 1.3 15 feb 2006 update package dimensions 1.4 16 aug 2006 update ac timing. 1.5 13 jun 2007 update idd current. 1.6 27 nov 2007 support ddr440
nanya technology corporation. all rights reserved. printed in taiwan, r.o.c. the following are trademarks of nanya technology corporation: nanya and the nanya logo other company, product and service names ma y be trademarks or service marks of others. nanya technology corporation (ntc) reserves the right to make changes without notice. ntc warrants performance of its semiconductor products and related softw are to the specifications ap plicable at the time of sale in accordance with ntc? s standard warranty. testing and other quality control techniques ar e utilize to the extent ntc deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, exce pt those mandated by government requirements. certain applications using semiconductor products may involve pot ential risks of death, personal in jury, or severe property or environmental damage (?critical applications?). ntc semiconductor products are not designed, in tend, authorized, or warranted to be suitable for use in life-support appli cations, devices or systems or other critical applications. inclusion of ntc products in such applications is understood to be fully at the risk of the customer. use of ntc products in su ch applications requires the written approval of an appropriate ntc officer. question conc erning potential risk applications shoul d be directed to ntc through a local sales office. in order to minimize risks associated with the customer?s a pplications, adequate design and o perating safeguards should be provided by customer to minimize the inherent or procedural hazards. ntc assumes no liability of applications assist ance, customer product design, software pe rformance, or infrin gement of patents or services described herein. nor does ntc warrant or represen t that any license, either expre ss or implied, is granted under any patent right, copyright, mask work righ t, or other intellectual property right of ntc covering or relating to any combinati on, machine, or process in which such semiconducto r products or services might be or are used. nanya technology corporation hwa ya technology park 669, fu hsing 3rd rd., kueishan, taoyuan, taiwan, r.o.c. the nanya technology corporation home pag e can be found at: http:\\www.nanya.com ?

▲Up To Search▲

Price & Availability of NT5DS128M4BT-6K

	To Download NT5DS128M4BT-6K Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .