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1 of 53 rev: 110905 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales c hannels. for information about device errata, click here : www.maxim-ic.com/errata . general description the ds80c390 is a fast 8051-compatible microprocessor with dual can 2.0b controllers. the redesigned processor core executes 8051 instructions up to 3x faster than the original for the same crystal speed. the ds80c390 supports a maximum crystal speed of 40mhz, resulting in apparent execution speeds of 100mhz (approximately 2.5x). an optional internal frequency multiplier allows the microprocessor to operate at full speed with a reduced crystal frequency, reducing emi. a hardware math accelerator further increases the speed of 32-bit and 16-bit multiply and divide operations as well as high -speed shift, normalization, and accumulate functions. the high-speed microcontroller user?s guide and high-speed microcontroller user?s guide: ds80c390 supplement must be used in conjunction with this data sheet. download both at: www.maxim-ic.com/microcontrollers . applications industrial controls agricultural equipment factory automation gaming equipment medical equipment automotive heating, ventilation, and air conditioning features 80c52 compatible high-speed architecture 4kb internal sram usable as program/ data/stack memory enhanced memory architecture two full-function can 2.0b controllers two full-duplex hardware serial ports programmable irda clock high integration controller 16 interrupt sources with six external available in 64-pin lqfp, 68-pin plcc see page 29 for a complete list of features. ordering information part temp range pin-package ds80c390-qcr 0c to +70c 68 plcc ds80c390-qcr+ 0c to +70c 68 plcc ds80c390-qnr -40c to +85c 68 plcc ds80c390-qnr+ -40c to +85c 68 plcc ds80c390-fcr 0c to +70c 64 lqfp ds80c390-fcr+ 0c to +70c 64 lqfp ds80c390-fnr -40c to +85c 64 lqfp ds80c390-fnr+ -40c to +85c 64 lqfp + denotes a lead(pb)-free/rohs-compliant device. pin configurations ds80c390 dual can high-speed microprocesso r www.maxim-ic.com 1 61 9 10 26 27 43 60 44 dallas semiconductor ds80c390 plcc 49 dallas semiconductor ds80c390 48 33 32 17 16 1 64 lqfp top view
ds80c390 dual can high-speed microprocessor 2 of 53 absolute maximum ratings voltage range on any pin relative to ground?????????????????????.-0.3v to (v cc + 0.5v) voltage range on v cc relative to ground??????????????????????????-0.3v to +6.0v operating temperature range??????????????????????????????..-40c to +85c storage temperature range??????????????????????????????...-55c to +125c soldering temperature?..???????????? ??????????????..see ipc/jedec j-std-020 stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating c onditions for extended periods may affect device reliability. dc electrical charac teristics (note 10) parameter symbol min typ max units supply voltage v cc v rst 5.0 5.5 v power-fail warning v pfw 4.10 4.38 4.60 v minimum operating voltage v rst 3.85 4.13 4.35 v supply current, active mode (note 1) i cc 80 150 ma supply current, idle mode (note 2) i idle 40 75 ma supply current, stop mode (note 3) i stop 1 120 a supply current, stop mode, bandgap enabled (note 3) i spbg 150 350 a input low level v il -0.5 +0.8 v input high level v ih 2.0 v cc +0.5 v input high level for xtal1, rst v ih2 0.7 x v cc v cc +0.5 v output low voltage for port 1, 3, 4, 5 at i ol = 1.6ma v ol1 0.45 v output low voltage for port 0, 1, 2, 4, 5, rd , wr , rstol , psen , and ale at i ol = 3.2ma (note 5) v ol2 0.45 v output high voltage for po rt 1, 3, 4, 5 at i oh = -50 a (note 4) v oh1 2.4 v output high voltage for po rt 1, 3, 4, 5 at i oh = -1.5ma (note 6) v oh2 2.4 v output high voltage for po rt 0, 1, 2, 4, 5, rd , wr , rstol , psen , and ale at i oh = -8ma (note 5, 7) v oh3 2.4 v input low current for port 1, 3, 4, 5 at 0.45v (note 8) i il -55 a logic 1 to 0 transition current fo r port 1, 3, 4, 5 (note 9) i t1 -650 a input leakage current for port 0 (input mode only) i l -300 +300 a rst pulldown resistance r rst 50 170 k note 1: active current measured with 40mhz clock source on xtal1, v cc = rst = 5.5v, all other pins disconnected. note 2: idle mode current measured with 40mhz clock source on xtal1, v cc = 5.5v, rst = ea = v ss , all other pins disconnected. note 3: stop mode current measured with xtal1 = rst = ea = v ss , v cc = 5.5v, all other pins disconnected. note 4: rst = v cc . this condition mimics operat ion of pins in i/o mode. note 5: applies to port pins when they are used to addre ss external memory or as can interface signals. note 6: this measurement reflects the port during a 0-to-1 transition in i/o mode. du ring this period a one-shot circuit drives the por ts hard for two clock cycles. if a port 4 or 5 pin is functioning in memo ry mode with pin state of 0 and the sfr bit contains a 1, chan ging the pin to an i/o mode (by writing to p4cnt) will not enable the 2- cycle strong pullup. during stop or idle mode the pins switc h to i/o mode, and so port 2 and port 1 (in nonmultiplexed mode) will not exhibit the 2-cycle strong pullup when entering stop or id le mode. note 7: port 3 pins 3.6 and 3.7 have a stronger than normal pullup driv e for one oscillator period following the transition of either t he rd or wr from a 0-to-1 transition. note 8: this is the current required from an ex ternal circuit to hold a logic low level on an i/o pin while the corresponding port latc h bit is set to 1. this is only the current required to hold the low level; transitions from 1 to 0 on an i/o pin also have to overcome the transition current. note 9: ports 1(in i/o mode), 3, 4, and 5 source transition current when being pulled down externally. it reaches its maximum at approximately 2v. note 10: specifications to -40 c are guaranteed by design and not production tested.
ds80c390 dual can high-speed microprocessor 3 of 53 ac electrical characteristics?(m ultiplexed addr ess/data bus) (note 10, note 11) 40mhz variable clock parameter symbol conditions min max min max units external oscillator 0 40 0 40 oscillator frequency 1 / t clcl external crystal 1 40 1 40 mhz ale pulse width t lhll 0.375 t mcs - 5 ns port 0 instruction address or ce0?4 valid to ale low t avll 0.125 t mcs - 5 ns address hold after ale low t llax1 0.125 t mcs - 5 ns ale low to valid instruction in t lliv 0.625 t mcs - 20 ns ale low to psen low t llpl 0.125 t mcs - 5 ns psen pulse width t plph 0.5 t mcs - 8 ns psen low to valid instruction in t pliv 0.5 t mcs - 20 ns input instruction hold after psen t pxix 0 0 ns input instruction float after psen t pxiz 0.25 t mcs - 5 ns port 0 address to valid instruction in t aviv1 0.75 t mcs - 22 ns port 2, 4 address to valid instruction in t aviv2 0.875 t mcs - 30 ns psen low to address float t plaz 0 0 ns note 11: all parameters apply to both commercial and industrial te mperature operation unless otherwise noted. the value t mcs is a function of the machine cycle clock in terms of the processor?s i nput clock frequency. these relationships are described in the stretch value timing table. all signals characteri zed with load capacitance of 80pf except port 0, ale, psen , rd , and wr with 100pf. interfacing to memory devices with float times (turn off time s) over 25ns can cause bus cont ention. this does not damage the parts, but causes an increase in operating cu rrent. specifications assume a 50% duty cy cle for the oscillator. port 2 and ale t iming changes in relation to duty cycle variation. some ac timing charac teristic drawings contain refe rences to the clk signal. this waveform is provided to assist in determining the relative occurrence of events and cannot be used to determine the timing of signals relative to the external clock. ac timing is characterized and guarante ed by design but is not production tested.
ds80c390 dual can high-speed microprocessor 4 of 53 ac symbols the ds80c390 uses timing parameters and symbols similar to the original 8051 family. the following list of timing symbols is provided as an aid to understanding the timing diagrams. symbol function t time a address c clock ce chip enable d input data h logic level high l logic level low i instruction p psen q output data r rd signal v valid w wr signal x no longer a valid logic level. z tri-state figure 1. multiplexed external program memory read cycle
ds80c390 dual can high-speed microprocessor 5 of 53 movx characteristics (multiplexe d address/data bus) (note 12) parameter symbol min max units stretch values c st (md2:0) 0.375 t mcs - 5 ns c st = 0 0.5 t mcs - 5 ns 1 c st 3 movx ale pulse width t lhll2 1.5 t mcs - 10 ns 4 c st 7 0.125 t mcs - 5 ns c st = 0 0.25t mcs - 5 ns 1 c st 3 port 0 movx address, ce0?4 , pce0?4 valid to ale low t avll2 1.25 t mcs - 10 ns 4 c st 7 0.25t mcs -5 ns c st = 0 0.125 t mcs - 5 ns 1 c st 3 address hold after movx read/write t llax2 t llax3 1.25 t mcs - 5 ns 4 c st 7 0.5 t mcs - 6 ns c st = 0 rd pulse width t rlrh c st x t mcs - 10 ns 1 c st 7 0.5 t mcs - 6 ns c st = 0 wr pulse width t wlwh c st x t mcs - 10 ns 1 c st 7 0.5 t mcs - 20 ns c st = 0 rd low to valid data in t rldv c st x t mcs - 25 ns 1 c st 7 data hold after read t rhdx 0 ns 0.25 t mcs - 5 ns c st = 0 0.5t mcs - 5 ns 1 c st 3 data float after read t rhdz 1.5 t mcs - 5 ns 4 c st 7 0.625 t mcs - 20 ns c st = 0 (c st + 0.25) x t mcs - 20 ns 1 c st 3 ale low to valid data in t lldv (c st + 1.25) x t mcs - 20 ns 4 c st 7 0.75 t mcs - 26 ns c st = 0 (4c st + 0.5) x t mcs - 30 ns 1 c st 3 port 0 address, port 4 ce, port 5 pce to valid data in t avdv1 (4c st + 2.5) x t mcs - 30 ns 4 c st 7 0.75 t mcs - 30 ns c st = 0 (4c st + 0.5) x t mcs - 30 ns 1 c st 3 port 2, 4 address to valid data in t avdv2 (4c st + 2.5) x t mcs - 30 ns 4 c st 7 0.125 t mcs - 5 0.125 t mcs + 10 ns c st =0 0.25t mcs - 5 0.25t mcs + 10 ns 1 c st 3 ale low to rd or wr low t llwl 1.25 t mcs - 5 1.25 t mcs + 10 ns 4 c st 7 0.25 t mcs - 11 ns c st = 0 0.5t mcs - 11 ns 1 c st 3 port 0 address, port 4 ce, port 5 pce to rd or wr low t avwl1 2.5 t mcs - 11 ns 4 c st 7 0.375 t mcs - 11 ns c st = 0 0.625t mcs - 11 ns 1 c st 3 port 2, 4 address to or wr low t avwl2 2.625 t mcs - 11 ns 4 c st 7 data valid to wr transition t qvwx -8 ns 0.25 t mcs - 8 ns c st = 0 0.5t mcs - 10 ns 1 c st 3 data hold after wr high t whqx 1.5 t mcs - 10 ns 4 c st 7 rd low to address float t rlaz see note 12 -5 +10 ns c st = 0 0.25 t mcs - 7 0.25 t mcs + 5 ns 1 c st 3 rd or wr high to ale, port 4 ce or port 5 pce high t whlh 1.25 t mcs - 7 1.25 t mcs +10 ns 4 c st 7 note 12: all parameters apply to both commercial and industrial temperature operation. c st is the stretch cycle value determined by the md2:0 bits. t mcs is a time period shown in the t mcs time periods table. all signals characteriz ed with load capacitance of 80pf except port 0, ale, psen , rd , and wr with 100pf. interfacing to memory devices with float times over 25ns can cause bus contention and an increase in operating curr ent. specifications assume a 50% duty cycl e for the oscillator; port 2 and ale timi ng changes in relation to duty cycle variation. some ac timing characteristic drawings show the clk signal, provided to determine the relative occurrence of events and not the timing of signals relati ve to the external clock. during the external addressing mode , weak latches maintain the previously driven val ue from the processor on port 0 until port 0 is overdriven by external memory; and on port 1, 2 and 4 for one xtal1 cycle prior to change in output address from port 1, 2, and 4.
ds80c390 dual can high-speed microprocessor 6 of 53 figure 2. multiplexed 9-cycle address/data ce0-3 movx read/write operation
ds80c390 dual can high-speed microprocessor 7 of 53 figure 3. multiplexed 9-cycle address/data pce0-3 movx read/write operation
ds80c390 dual can high-speed microprocessor 8 of 53 figure 4. multiplexed 2-cycle data memory pce0-3 read or write figure 5. multiplexed 2-cycle data memory ce0-3 read
ds80c390 dual can high-speed microprocessor 9 of 53 figure 6. multiplexed 2-cycle data memory ce0-3 write figure 7. multiplexed 3-cycle data memory pce0-3 read or write
ds80c390 dual can high-speed microprocessor 10 of 53 figure 8. multiplexed 3-cycle data memory ce0-3 read figure 9. multiplexed 3-cycle data memory ce0-3 write
ds80c390 dual can high-speed microprocessor 11 of 53 figure 10. multiplexed 9-cycle data memory pec0-3 read or write figure 11. multiplexed 9-cycle data memory ce0-3 read
ds80c390 dual can high-speed microprocessor 12 of 53 figure 12. multiplexed 9-cycle data memory ce0-3 write
ds80c390 dual can high-speed microprocessor 13 of 53 electrical characteristics?(non multiplexed addr ess/data bus) (note 13) 40mhz variable clock parameter symbol conditions min max min max units external oscillator 0 40 0 40 oscillator frequency 1 / t clcl external crystal 1 40 1 40 mhz psen pulse width t plph 0.5 t mcs - 8 ns psen low to valid instruction in t pliv 0.5 t mcs - 20 ns input instruction hold after psen t pxix 0 0 ns input instruction float after psen t pxiz see movx characteristics ns port 1 address, port 4 ce to valid instruction in t aviv1 0.75 t mcs - 22 ns port 2, 4 address to valid instruction in t aviv2 0.875 t mcs - 30 ns note 13: all parameters apply to both commercial and industrial te mperature operation unless otherwise noted. the value t mcs is a function of the machine cycle clock in terms of the processor?s input clock frequency. these relationships are described in the stretch value timing table. all signals characterized with load capacitance of 80pf except port 0, ale, psen , rd , and wr with 100pf. interfacing to memory devices with float times (turn off times) over 25ns can caus e bus contention. this does not damage the parts, but cau ses an increase in operating current. specifications assume a 50% dut y cycle for the oscillator. port 2 and ale timing changes in r elation to duty cycle variation. some ac timing char acteristic drawings contain references to the clk signal. this waveform is provided to assist in determining the relative occurrence of events and cannot be used to determine the timing of signals relative to the e xternal clock. figure 13. nonmultiplexed external program memory read cycle
ds80c390 dual can high-speed microprocessor 14 of 53 movx characteristics (nonmultiplexed address/data bus) parameter symbol min max units stretch values c st (md2:0) 0.5 t mcs - 6 c st = 0 rd pulse width t rlrh c st x t mcs - 6 ns 1 c st 7 0.5 t mcs - 6 c st = 0 wr pulse width t wlwh c st x t mcs - 6 ns 1 c st 7 0.5 t mcs - 20 c st = 0 rd low to valid data in t rldv c st x t mcs - 25 ns 1 c st 7 data hold after read t rhdx 0 ns 0.125 t mcs - 5 c st = 0 0.375t mcs - 5 1 c st 3 data float after read t rhdz 1.375 t mcs - 5 ns 4 c st 7 0.75 t mcs - 26 c st = 0 (4c st + 0.5) x t mcs - 30 1 c st 3 port 1 address, port 4 ce, port 5 pce to valid data in t avdv1 (4c st + 2.5) x t mcs - 30 ns 4 c st 7 0.75 t mcs - 30 c st = 0 (4c st + 0.625) x t mcs - 30 1 c st 3 port 2, 4 address to valid data in t avdv2 (4c st + 2.625) x t mcs - 30 ns 4 c st 7 0.25 t mcs - 11 c st = 0 0.5 t mcs - 11 1 c st 3 port 0 address, port 4 ce, port 5 pce to rd or wr low t avwl1 2.5 t mcs - 11 ns 4 c st 7 0.375 t mcs - 11 c st = 0 0.625t mcs - 11 1 c st 3 port 2, 4 address to rd or wr low t avwl2 2.625 t mcs - 11 ns 4 c st 7 data valid to wr transition t qvwx -8 ns 0.25 t mcs - 8 c st = 0 0.5t mcs - 10 1 c st 3 data hold after wr high t whqx 1.5 t mcs - 10 ns 4 c st 7 -5 10 c st = 0 0.25 t mcs - 7 0.25 t mcs + 10 1 c st 3 rd or wr high to ale, port 4 ce or port 5 pce high t whlh 1.25 t mcs - 7 1.25 t mcs + 10 ns 4 c st 7
ds80c390 dual can high-speed microprocessor 15 of 53 figure 14. nonmultiplexed 9-cycle address/data ce0-3 movx read/write operation
ds80c390 dual can high-speed microprocessor 16 of 53 figure 15. nonmultiplexed 9-cycle address/data pce0-3 movx read/write operation
ds80c390 dual can high-speed microprocessor 17 of 53 figure 16. nonmultiplexed 2-cycle data memory 3 - pce0 read or write figure 17. nonmultiplexed 2-cycle data memory ce0-3 read
ds80c390 dual can high-speed microprocessor 18 of 53 figure 18. nonmultiplexed 2-cycle data memory ce0-3 write figure 19. nonmultiplexed 3-cycle data memory pec0-3 read or write
ds80c390 dual can high-speed microprocessor 19 of 53 figure 20. nonmultiplexed 3-cycle data memory ce0-3 read figure 21. nonmultiplexed 3-cycle data memory ce0-3 write
ds80c390 dual can high-speed microprocessor 20 of 53 figure 22. nonmultiplexed 9-cycle data memory pce0-3 read or write figure 23. nonmultiplexed 9-cycle data memory ce0-3 read
ds80c390 dual can high-speed microprocessor 21 of 53 figure 24. nonmultiplexed 9-cycle data memory ce0-3 write t mcs time periods system clock selection 4x/ 2x cd1 cd0 t mcs 1 0 0 1 t clcl 0 0 0 2 t clcl x 1 0 4 t clcl x 1 1 1024 t clcl external clock characteristics parameter symbol min max units clock high time t chcx 8 ns clock low time t clcx 8 ns clock rise time t clch 4 ns clock fall time t chcl 4 ns figure 25. external clock drive
ds80c390 dual can high-speed microprocessor 22 of 53 serial port mode 0 timing characteristics parameter symbol conditions typ units sm2 = 0:2 clocks per cycle 12 t clcl serial port clock cycle time t xlxl sm2 = 1:4 clocks per cycle 4 t clcl ns sm2 = 0:12 clocks per cycle 10 t clcl output data setup to clock rising t qvxh sm2 = 1:4 clocks per cycle 3 t clcl ns m2 = 0:12 clocks per cycle 2 t clcl output data hold from clock rising t xhqx sm2 = 1:4 clocks per cycle t clcl ns sm2 = 0:12 clocks per cycle t clcl input data hold after clock rising t xhdx sm2 = 1:4 clocks per cycle 0 ns sm2 = 0:12 clocks per cycle 11 t clcl clock rising edge to input data valid t xhdv sm2 = 1:4 clocks per cycle 2 t clcl ns
ds80c390 dual can high-speed microprocessor 23 of 53 figure 26. serial port 0 (synchronous mode) high-speed operation, txd clk = xtal/4 (sm2 = 1) traditional 8051 operation, txd clock = xtal/12 (sm2 = 0)
ds80c390 dual can high-speed microprocessor 24 of 53 power-cycle timing characteristics parameter symbol typ max units crystal startup time (note 14) t csu 1.8 ms power-on reset delay (note 15) t por 65,536 t clcl note 14: startup time for crystals varies with load capacitance and manufacture r. time shown is for an 11.0592mhz crystal manufactured by fox electronics. note 15: reset delay is a synchronous c ounter of crystal oscillations during crystal star tup. counting begins when the level on the xta l1 input meets the v ih2 criteria. at 40mhz, this time is approximately 1.64ms. figure 27. power- cycle timing
ds80c390 dual can high-speed microprocessor 25 of 53 pin description pin lqfp plcc name function 8, 22, 40, 56 17, 32, 51, 68 v cc +5v 9, 25, 41, 57 1, 18, 35, 52 gnd digital circuit ground 46 57 ale address latch enable, output. when the mux pin is low, this pin outputs a clock to latch the external address lsb from the multiplexed address/data bus on port 0. this signal is commonly connected to the latch enable of an external transparent latch. ale has a pulse width of 1.5 xtal1 cy cles and a period of four xtal1 cycles. when the mux pin is high, the pin will toggle continuously if the aleoff bit is cleared. ale is forced high when the device is in a reset condition or if the aleoff bit is set while the mux pin is high. 45 56 psen program store enable, output. this signal is the chip enable for external rom memory. psen provides an active-low pulse and is driven high when external rom is not being accessed. 47 58 ea external access enable, input. this pin must be wired to gnd for proper operation. 26 36 mux multiplex/demultiplex select, input. this pin selects if the address/data bus operates in multiplexed ( mux = 0) or demultiplexed ( mux = 1) mode. 2 11 rst reset, input. the rst input pin contains a schmitt voltage input to recognize external active-high reset inputs. the pin also employs an internal pulldown resistor to allow for a combination of wired-or external reset sources. an rc circuit is not required for power-up, as the device provides this function internally. 3 12 rstol reset output low, output. this active-low signal is asserted: when the processor has entered reset through the rst pin, during crystal warmup period following power-on or stop mode, during a watchdog timer reset (2 cycles duration), during an oscillator failure (if ofde = 1), whenever v cc v rst. 23 33 xtal2 24 34 xtal1 xtal1, xtal2. crystal oscillator pins support fundamental mode, parallel resonant, and at-cut crystals. xtal1 is the input if an external clock source is used in place of a crystal. xtal2 is the output of the crystal amplifier. 55 67 ad0/d0 54 66 ad1/d1 53 65 ad2/d2 52 64 ad3/d3 51 63 ad4/d4 50 62 ad5/d5 49 61 ad6/d6 48 59 ad7/d7 ad0?7 (port 0), i/o. when the mux pin is wired low, port 0 is the multiplexed address/data bus. while ale is high, the lsb of a memory address is presented. while ale falls, the port transitions to a bidirectional data bus. when the mux pin is wired high, port 0 functions as the bidirectional data bus. port 0 cannot be modified by software. the reset condition of port 0 pins is high. no pullup resistors are needed.
ds80c390 dual can high-speed microprocessor 26 of 53 pin description (continued) pin lqfp plcc name function 58?64, 1 2?8, 10 p1.0?p1.7 port 1, i/o. port 1 can function as an 8-bit bidirectional i/o port, the nonmultiplexed a0?a7 signals (when the mux pin = 1), and as an alternate interface for internal resources. setting the sp1ec bit relocates rxd1 and txd1 to port 5. the reset condition of port 1 is all bits at logic 1 through a weak pullup. the logic 1 state also serves as an input mode, since external circuits writing to the port can overdrive the weak pullup. when software clears any port pin to 0, a strong pulldown is activated that remains on until either a 1 is written to the port pin or a reset occurs. writing a 1 after the port has been at 0 activates a strong transition driver, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port once again becomes the output (and input) high state. port alternate function 58 2 a0 p1.0 t2 external i/o for timer/counter 2 59 3 a1 p1.1 t2ex timer/counter 2 capture/reload trigger 60 4 a2 p1.2 rxd1 serial port 1 input 61 5 a3 p1.3 txd1 serial port 1 output 62 6 a4 p1.4 int2 external interrupt 2 (positive edge detect) 63 7 a5 p1.5 int3 external interrupt 3 (negative edge detect) 64 8 a6 p1.6 int4 external interrupt 4 (positive edge detect) 1 10 a7 p1.7 int5 external interrupt 5 (negative edge detect) 35 46 a8 (p2.0) 36 47 a9 (p2.1) 37 48 a10 (p2.2) 38 49 a11 (p2.3) 39 50 a12 (p2.4) 42 53 a13 (p2.5) 43 54 a14 (p2.6) 44 55 a15 (p2.7) a15?a8 (port 2), output. port 2 serves as the msb for external addressing. the port automatically asserts the address msb during external rom and ram access. although the port 2 sfr exists, the sfr value never appears on the pins (due to memory access). therefore, accessing the port 2 sfr is only useful for movx a, @ri or movx @ri, a instructions, which use the port 2 sfr as the external address msb. 4?7, 10?13 13?16, 19?22 p3.0?p3.7 port 3, i/o. port 3 functions as an 8-bit bidirectional i/o port and as an alternate interface for several resources found on the traditional 8051. the reset condition of port 1 is all bits at logic 1 through a weak pullup. the logic 1 state also serves as an input mode, since external circuits writing to the port can overdrive the weak pullup. when software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is written to the port pin or a reset occurs. writing a 1 after the port has been at 0 activates a strong transition driver, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port once again becomes the output (and input) high state. port alternate function 4 13 p3.0 rxd0 serial port 0 input 5 14 p3.1 txd0 serial port 0 output 6 15 p3.2 int0 external interrupt 0 7 16 p3.3 int1 external interrupt 1 10 19 p3.4 t0 timer 0 external input 11 20 p3.5 t1/xclk timer 1 external input/external clock output 12 21 p3.6 wr external data memory write strobe 13 22 p3.7 rd external data memory read strobe
ds80c390 dual can high-speed microprocessor 27 of 53 pin description (continued) pin lqfp plcc name function 34?27 45, 44, 42?37 p4.0?p4.7 port 4, i/o. port 4 can function as an 8-bit, bidirectional i/o port, and as the source for external address and chip enable signals for program and data memory. port pins are configured as i/o or memory signals via the p4cnt register. the reset condition of port 1 is all bits at logic 1 via a weak pull up. the logic 1 state also serves as an input mode, since external circuits writing to the port can overdrive the weak pullup. when software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is written to the port pin or a reset occurs. writing a 1 after the port has been at 0 will activate a strong transiti on driver, followed by a weaker sustaining pullup. once the mom entary strong driver turns off, the port once again becomes the output (and input) high state. port alternate function 34 45 p4.0 ce0 program memory chip enable 0 33 44 p4.1 ce1 program memory chip enable 1 32 42 p4.2 ce2 program memory chip enable 2 31 41 p4.3 ce3 program memory chip enable 3 30 40 p4.4 a16 program/data memory address 16 29 39 p4.5 a17 program/data memory address 17 28 38 p4.6 a18 program/data memory address 18 27 37 p4.7 a19 program/data memory address 19 21?14 31?27, 25?23 p5.0?p5.7 port 5, i/o. port 5 can function as an 8-bit, bidirectional i/o port, the can interface, or as peripheral enable signals. setting the sp1ec bit will relocate the rxd1 and txd1 f unctions to p5.3-p5.2 as described in the high-speed microcontroller user?s guide: ds80c390 supplement . the reset condition of port 1 is all bits at logic 1 via a weak pullup. the logic 1 state also serves as an input mode, since external circuits writing to the port can overdrive the weak pullup. when software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is written to the port pin or a reset occurs. writing a 1 after the port has been at 0 will activate a strong transition driver, followed by a weaker sustaining pullup. once the momentary strong driver turn s off, the port once again becomes the output (and input) high state. port alternate function 21 31 p5.0 c0tx can0 transmit output 20 30 p5.1 c0rx can0 receive input 19 29 p5.2 c1rx can1 receive input (optional rxd1) 18 28 p5.3 c1tx can1 transmit output (optional txd1) 17 27 p5.4 pce0 peripheral chip enable 0 16 25 p5.5 pce1 peripheral chip enable 1 15 24 p5.6 pce2 peripheral chip enable 2 14 23 p5.7 pce3 peripheral chip enable 3 9, 26, 43, 60 n.c. not connected. reserved. these pins are reserved for use with future devices in this family and should not be connected.
ds80c390 dual can high-speed microprocessor 28 of 53 figure 28. block diagram ds80c390
ds80c390 dual can high-speed microprocessor 29 of 53 features 80c52 compatible 8051-instruction-set compatible four 8-bit i/o ports three 16-bit timer/counters 256 bytes scratchpad ram high-speed architecture 4 clocks/machine cycle (8051 = 12) runs dc to 40mhz clock rates frequency multiplier reduces electromagnetic interference (emi) single-cycle instruction in 100ns 16/32-bit math coprocessor 4kb internal sram usable as program/data/stack memory enhanced memory architecture addresses up to 4mb external defaults to true 8051-memory compatibility user-enabled 22-bit program/data counter 16-bit/22-bit paged/22-bit contiguous modes user-selectable multiplexed/nonmultiplexed memory interface optional 10-bit stack pointer two full-function can 2.0b controllers 15 message centers per controller standard 11-bit or extended 29-bit identification modes supports devicenet?, sds, and higher layer can protocols disables transmitter during autobaud siesta low-power mode two full-duplex hardware serial ports programmable irda clock high-integration controller includes : power-fail reset early-warning power-fail interrupt programmable watchdog timer oscillator-fail detection 16 interrupt sources with six external available in 64-pin lqfp and 68-pin plcc detailed description the ds80c390 features two full-function controller area network (can) 2.0b controllers. status and control registers are distributed between sfrs and 512 bytes of internal movx memory for maximum flexibility. in addition to standard 11-bit or 29-extended me ssage identifiers, the device supports two separate 8-bit media masks and media arbitration fields to support the use of higher -level can protocols such as devicenet and sds. all of the standard 8051 resources such as three timer/counters, serial port, and four 8-bit i/o ports (plus two 8-bit ports dedicated to memory interfacing) are included in the ds80c390. in addition it includes a second hardware serial port, seven additional interrupts, programmable watchdog timer, brownout monitor, power-fail reset, and a programmable output clock that supports an irda inte rface. the device provides dual data pointers with increment/decrement features to speed block data memo ry moves. it also can adjust the speed of movx data memory access from 2 to 12 machine cycles for flex ibility in addressing external memory and peripherals. the device incorporates a 4kb sram, which can be configured as various combinations of movx memory, program memory, and optional stack memory. a 22-bit prog ram counter supports access to a maximum of 4mb of external program memory and 4mb of external data memory . a 10-bit stack pointer addresses up to 1kb of movx memory for increased code efficiency. a new power-management mode (pmm) is useful for portable or power-conscious applications. this feature allows software to switch from the standard machine cycle rate of 4 clocks per cycle to 1024 clocks per cycle. for example, at 12mhz standard operation has a machine cycle rate of 3mhz. in pmm at the same external clock speed, software can select 11.7khz machine cycle rate. there is a corresponding reduction in power consumption when the processor runs slower. the emi reduction feature allows software to select a reduced electromagnetic interference (emi) mode by disabling the ale signal when it is unneeded. the device also incorporates active current control on the address and data buses, reducing emi by minimizing transients when interfacing to external circuitry. 80c32 compatibility the ds80c390 is a cmos 80c32-compatible microcontro ller designed for high performance. every effort has been made to keep the core device familiar to 80c32 users while adding many new features. devicenet is a trademark of open devicenet vendor association, inc.
ds80c390 dual can high-speed microprocessor 30 of 53 because the device runs the standard 8051 instruction set, in general, software written for existing 80c32-based systems will work on the ds80c390. the primary exceptions are related to ti ming-critical issues, since the high- performance core of the microcontroller executes instructio ns much faster than the original. memory interfacing is performed identically to the standard 80c32. the high- speed nature of the ds80c390 core slightly changes the interface timing, and designers are advised to consult the ti ming diagrams in this data sheet for more information. the ds80c390 provides the same timer/counter resource s, full duplex serial port, 256 bytes of scratchpad ram and i/o ports as the standard 80c32. timers default to a 12 clocks-per-machine cycle operation to keep timing compatible with original 8051 systems, but can be programm ed to run at the faster four clocks-per-machine cycle if desired. new hardware functions are accessed using specia l function registers that do not overlap with standard 80c32 locations. this data sheet provides only a summary and overview of the ds80c390. detailed descriptions are available in the high-speed microcontroller user?s guide: ds80c390 supplement . this data sheet assumes a familiarity with the architecture of the standard 80c32. in addition to the ba sic features of that device, the ds80c390 incorporates many new features. performance overview the ds80c390?s higher performance comes not just from increasing the clock frequency but also from a more efficient design. this updated core removes the dummy memo ry cycles that are present in a standard, 12 clocks- per-machine cycle 8051. in the ds80c 390, the same machine cycle takes 4 cl ocks. thus the fastest instruction, one machine cycle, executes three times faster for the same crystal frequency. the majority of instructions on the ds80c390 see the full 3-to-1 speed improvement, while a few execute between 1.5 and 2.4 times faster. regardless of specific performance improvements, al l instructions are faster than the original 8051. improvement of individual programs depends on the actual mix of instructions used. speed-sensitive applications should make the most use of instructio ns that are three times faster. however, the large number of 3-to-1 improved op codes makes dramatic speed improvements likely fo r any arbitrary combination of instructions. these architecture improvements and the submicron cmos design produce a peak instruction cycle in 100ns (10 mips). the dual data pointer feature also allows the user to elim inate wasted instructions when moving blocks of memory. instruction set summary all instructions perform exactly the same functions as t heir 8051 counterparts. their e ffect on bits, flags, and other status functions is identical. however, the timing of inst ructions is different, both in absolute and relative number of clocks. the absolute timing of software loops can be calculated using a table in the high-speed microcontroller user?s guide: ds80c390 supplement . however, counter/timers default to r un at the traditional 12 clocks per increment. in this way, timer-based even ts occur at the standard intervals with software executing at higher speed. timers optionally can run at the faster four clocks per incr ement to take advantage of faster processor operation. the relative time of two ds80c390 instructions might diffe r from the traditional 8051. for example, in the original architecture the ?movx a, @dptr? instruction and the ?m ov direct, direct? instruct ion required the same amount of time: two machine cycles or 24 oscillator cycles. in the ds80c390, the movx instruct ion takes as little as two machine cycles, or eight oscillator cy cles, but the ?mov direct, direct? uses three machine cycles, or 12 oscillator cycles. while both are faster than their original counterp arts, they now have different execution times. this is because the device usually uses one instruction cycle for each instruction byte. examine the timing of each instruction for familiarity with the changes. note that a machine cycle now requires just four clocks, and provides one ale pulse per cycle. many instructions require on ly one cycle, but some require five. refer to the high-speed microcontroller user?s guide: ds80c390 supplement for details and individual instruction timing. special function registers (sfrs) special function registers (sfrs) control most special feat ures of the microcontroller, allowing the device to have many new features but use the same instruction set as the 8051. when writing software to use a new feature, an equate statement defines the sfr to an assembler or comp iler. this is the only change needed to access the new function. the ds80c390 duplicates the sf rs contained in the standard 80c52. table 1 shows the register addresses and bit locations. many are standard 80c52 registers. the high-speed microcontroller user?s guide: ds80c390 supplement contains a full description of all sfrs.
ds80c390 dual can high-speed microprocessor 31 of 53 table 1. sfr locations register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address p4 p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 80h sp 81h dpl 82h dph 83h dpl1 84h dph1 85h dps id1 id0 tsl ? ? ? ? sel 86h pcon smod_0 smod0 ofdf ofde gf1 gf0 stop idle 87h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88h tmod gate c/ t m1 m0 gate c/ t m1 m0 89h tl0 8ah tl1 8bh th0 8ch th1 8dh ckcon wd1 wd0 t2m t1m t0m md2 md1 md0 8eh p1 int5/p1.7 int4/p1.6 int3/p1.5 int2/p1. 4 txd1/p1.3 rxd1/p1.2 t2ex/p1.1 t2/p1.0 90h exif ie5 ie4 ie3 ie2 ckry rgmd rgsl bgs 91h p4cnt ? sbcan p4cnt.5 p4cnt.4 p4cnt.3 p4cnt.2 p4cnt.1 p4cnt.0 92h dpx 93h dpx1 95h c0rms0 96h c0rms1 97h scon0 sm0/fe_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 98h sbuf0 99h esp ? ? ? ? ? ? esp.1 esp.0 9bh ap 9ch acon ? ? ? ? ? sa am1 am0 9dh c0tma0 9eh c0tma1 9fh p2 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 a0h p5 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 a1h p5cnt can1ba can0ba sp1ec c1_i/o c0_i/o p5cnt.2 p5cnt.1 p5cnt.0 a2h c0c erie stie pde siesta crst autob ercs swint a3h c0s bss ec96/128 wks rxs txs er2 er1 er0 a4h c0ir intin7 intin6 inti n5 intin4 intin3 inti n2 intin1 intin0 a5h c0te a6h c0re a7h ie ea es1 et2 es0 et1 ex1 et0 ex0 a8h saddr0 a9h saddr1 aah c0m1c msrdy eti eri intrq ex trq mtrq row/tih dtup abh c0m2c msrdy eti eri intrq extrq mtrq row/tih dtup ach c0m3c msrdy eti eri intrq extrq mtrq row/tih dtup adh c0m4c msrdy eti eri intrq ex trq mtrq row/tih dtup aeh c0m5c msrdy eti eri intrq extrq mtrq row/tih dtup afh p3 p3.7 p3.6 t1 t0 int1 int0 txd0 rxd0 b0h c0m6c msrdy eti eri intrq extrq mtrq row/tih dtup b3h c0m7c msrdy eti eri intrq extrq mtrq row/tih dtup b4h c0m8c msrdy eti eri intrq extrq mtrq row/tih dtup b5h c0m9c msrdy eti eri intrq extrq mtrq row/tih dtup b6h c0m10c msrdy eti eri intrq extrq mtrq row/tih dtup b7h ip ? ps1 pt2 ps0 pt1 px1 pt0 px0 b8h saden0 b9h saden1 bah c0m11c msrdy eti eri intrq ex trq mtrq row/tih dtup bbh c0m12c msrdy eti eri intrq extrq mtrq row/tih dtup bch c0m13c msrdy eti eri intrq extrq mtrq row/tih dtup bdh
ds80c390 dual can high-speed microprocessor 32 of 53 table 1. sfr locations (continued) register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address c0m14c msrdy eti eri intrq ex trq mtrq row/tih dtup beh c0m15c msrdy eti eri intrq extrq mtrq row/tih dtup bfh scon1 sm0/fe_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 c0h sbuf1 c1h pmr cd1 cd0 swb ctm 4x/ 2x aleoff ? ? c4h status pip hip lip ? spta1 spra1 spta0 spra0 c5h mcon idm1 idm0 cma ? pdce3 pdce2 pdce1 pdce0 c6h ta c7h t2con tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 c8h t2mod ? ? ? d13t1 d13t2 ?- t2oe dcen c9h rcap2l cah rcap2h cbh tl2 cch th2 cdh cor irdack c1bpr7 c1bpr6 c0bpr7 c0bpr6 cod1 cod0 clkoe ceh psw cy ac f0 rs1 rs0 ov f1 p d0h mcnt0 lshift cse scb mas4 mas3 mas2 mas1 mas0 d1h mcnt1 mst mof ? clm ? ? ? ? d2h ma d3h mb d4h mc d5h c1rms0 d6h c1rms1 d7h wdcon smod_1 por epfi pfi wdif wtrf ewt rwt d8h c1tma0 deh c1tma1 dfh acc e0h c1c erie stie pde siesta crst autob ercs swint e3h c1s bss cece wks rxs txs er2 er1 er0 e4h c1ir intin7 intin6 inti n5 intin4 intin3 inti n2 intin1 intin0 e5h c1te e6h c1re e7h eie canbie c0ie c1ie ewdi ex5 ex4 ex3 ex2 e8h mxax eah c1m1c msrdy eti eri intrq ex trq mtrq row/tih dtup ebh c1m2c msrdy eti eri intrq extrq mtrq row/tih dtup ech c1m3c msrdy eti eri intrq extrq mtrq row/tih dtup edh c1m4c msrdy eti eri intrq ex trq mtrq row/tih dtup eeh c1m5c msrdy eti eri intrq extrq mtrq row/tih dtup efh b f0h c1m6c msrdy eti eri intrq extrq mtrq row/tih dtup f3h c1m7c msrdy eti eri intrq extrq mtrq row/tih dtup f4h c1m8c msrdy eti eri intrq extrq mtrq row/tih dtup f5h c1m9c msrdy eti eri intrq extrq mtrq row/tih dtup f6h c1m10c msrdy eti eri intrq extrq mtrq row/tih dtup f7h eip canbip c0ip c1ip pwdi px5 px4 px3 px2 f8h c1m11c msrdy eti eri intrq extrq mtrq row/tih dtup fbh c1m12c msrdy eti eri intrq extrq mtrq row/tih dtup fch c1m13c msrdy eti eri intrq extrq mtrq row/tih dtup fdh c1m14c msrdy eti eri intrq extrq mtrq row/tih dtup feh c1m15c msrdy eti eri intrq ex trq mtrq row/tih dtup ffh note: shaded bits are timed-access protected.
ds80c390 dual can high-speed microprocessor 33 of 53 on-chip arithmeti c accelerator an on-chip math accelerator allows the microcontroller to perform 32-bit and 16-bit multiplication, division, shifting, and normalization using dedicated hardware. math operations are performed by sequentially loading three special registers. the mathematical operation is determined by the sequence in which three dedicated sfrs (ma, mb, and mc) are accessed, eliminating the need for a special st ep to choose the operation. the normalize function facilitates the conversion of 4-byte unsigned binary integers into floating point format. table 2 shows the operations supported by the math accelerator and their time of execution. table 2. arithmetic a ccelerator execution times operation result execution time ( t clcl ) 32-bit/16-bit divide 32-bit quotient, 16-bit remainder 36 16-bit/16-bit divide 16-bit quotient, 16-bit remainder 24 16-bit/16-bit multiply 32-bit product 24 32-bit shift left/right 32-bit result 36 32-bit normalize 32-bit mantissa, 5-bit exponent 36 table 3 demonstrates the procedure to perform mathematical operations using the hardwar e math accelerator. the ma and mb registers must be loaded and read in the order shown for proper operation, although accesses to any other registers can be performed between access to the ma or mb registers. an access to the ma, mb, or mc registers out of sequence corrupts t he operation, requiring the software to cl ear the mst bit to restart the math accelerator state machine. consult the description of the mcnt0 sfr for details of how the shift and normalize functions operate. software must ensure that the input value for the normalize operation is not zero or the function will not complete. compilers such as the one from keil software have updated their libraries and compensate for this condition. table 3. arithmetic accelerator sequencing divide (32/16 or 16/16) multiply (16 x 16) load ma with dividend lsb. load ma with dividend lsb + 1.* l oad ma with dividend lsb + 2 .* load ma with dividend msb. load mb with divisor lsb. load mb with divisor msb. poll the mst bit until cleared. (9 machine cycles). read ma to retrieve the quotient msb. read ma to retrieve the quotient lsb + 2.** read ma to retrieve the quotient lsb + 1.** read ma to retrieve the quotient lsb. read mb to retrieve the remainder msb. read mb to retrieve the remainder lsb. load mb with multiplier lsb. load mb with multiplier msb. load ma with multiplicand lsb. load ma with multiplicand msb. poll the mst bit until cleared. (6 machine cycles). read ma for product msb. read ma for product lsb + 2. read ma for product lsb + 1. read ma for product lsb. shift right/left normalize load ma with data lsb. load ma with data lsb + 1. load ma with data lsb + 2. load ma with data msb. configure mcnt0 register as required poll the mst bit until cleared. (9 machine cycles) read ma for result msb. read ma for result lsb + 2. read ma for result lsb + 1. read ma for result lsb. load ma with data lsb. load ma with data lsb + 1. load ma with data lsb + 2. load ma with data msb.*** load mcnt0 with 00h. poll the mst bit until cleared. (9 machine cycles) read ma for mantissa msb. read ma for mantissa lsb + 2. read ma for mantissa lsb + 1. read ma for mantissa lsb. read mcnt0.4?mcnt0.0 for exponent. * not performed for 16-bit numerator. ** not performed for 16/16 divide. ***value to be normalized must be nonzero.
ds80c390 dual can high-speed microprocessor 34 of 53 40-bit accumulator the accelerator also incorporates an automatic accumula tor function, permitting the implementation of multiply- and-accumulate and divide-and-accumulate functions without any additional delay. each time the accelerator is used for a multiply or divide operation, the result is tr ansparently added to a 40-bit accumulator. this can greatly increase speed of dsp and other high-level math operations. the accumulator can be accessed anytime the multiply/a ccumulate status flag (mcn t1;d2h) is cleared. the accumulator is initialized by performing five writes to the multiplier c register (mc;d5h), lsb first. the 40-bit accumulator can be read by performing five reads of the multiplier c register, msb first. memory addressing the ds80c390 incorporates three internal memory areas: 256 bytes of scratchpad (or direct) ram 4kb of sram configurable as various combinatio ns of movx data memory, stack memory, and movc program memory 512 bytes of ram reserved fo r the can message centers. up to 4mb of external memory is addressed via a multip lexed or demultiplexed 20-bit address bus/8-bit data bus and four chip-enable (active during program memory access ) or four peripheral-enable (active during data memory access) signals. three differ ent addressing modes are supported, as sele cted by the am1, am0 bits in the acon sfr. 16-bit address mode memory is accessed by 16-bit address mode similarly to the traditional 8051. it is op-code compatible with the 8051 microprocessor and identical to the byte and cycle count of the dallas se miconductor high-speed microcontroller family. a device operating in this mode can access up to 64kb of program and data memory. the device defaults to this mode following any reset. 22-bit paged-address mode the 22-bit paged-address mode retains binary-code co mpatibility with the 8051 instruction set, but adds one machine cycle to the acall, lcall, ret, and reti instructions with respect to dallas semiconductor?s high- speed microcontroller family timing. this is transparent to standard 8051 compilers. interrupt latency is also increased by one machine cycle. in this m ode, interrupt vectors are fetched from 0000xxh. 22-bit contiguous address mode the 22-bit contiguous addressing mode uses a full 22-bit program counter, and all modified branching instructions automatically save and restore the entir e program counter. the 22-bit branch ing instructions such as acall, ajmp, lcall, ljmp, mov dptr, ret, and reti instructio ns require an assembler, compiler, and linker that specifically supports these features. the inc dptr is lengthened by one cy cle but remains byte-count-compatible with the standard 8051 instruction set. internally, the device uses a 22-bit program counter. t he lowest order 22 bits are used for memory addressing, with a special 23rd bit used to map the 4kb sram above the 4mb memory space in boot strap loader applications. address bits 16?23 for the 22-bit addressing modes are gene rated through additional sfrs dependent on the type of instruction as shown in table 4 . table 4. extended address generation instruction address bits 23?16 address bits 15?8 address bits 7?0 movx instructions using dp tr dpx;93h dph;83h dpl;82h movx instructions using dptr1 dpx1;95h dph1;85h dpl1;84h movx instructions using @ri mxax;eah p2;a0h ri addressing program memory in 22-bit paged mode ap;9ch ? ? 10-bit stack pointer mode ? esp;9bh sp;81h
ds80c390 dual can high-speed microprocessor 35 of 53 internal movx sram the ds80c390 contains 4kb of sram that can be configured as user accessible movx memory, program memory, or optional stack memory. the specific configuration and locations are governed by the internal data memory configuration bits (idm1, idm0) in the memory control register (mcon;c6h). note that when the sa bit (acon.2) is set, the first 1kb of the movx data memory is reserved for use by the 10-bit expanded stack. internal memory accesses will not generate wr , rd , or psen strobes. the ds80c390 can configure its 4kb of internal sram as combined program and data memory. this allows the application software to execute self-modifiable code. the technique loads the 4kb sram with bootstrap loader software, and then modifies the idm1 and idm0 bits to map the 4kb starting at memory location 40000h. this allows the system to run the bootstrap loader without di sturbing the 4mb external memory bus, making the device in-system reprogrammable for flash or nv ram. table 5. internal mo vx sram configuration memory idm1 idm0 cma movx data can message shared program/data 0 0 0 00f000h?00ffffh 00ee00h?00efffh ? 0 0 1 00f000h?00ffffh 401000h?4011ffh ? 0 1 0 000000h?000fffh 00ee00h?00efffh ? 0 1 1 000000h?000fffh 401000h?4011ffh ? 1 0 0 400000h?400fffh 00ee00h?00efffh ? 1 0 1 400000h?400fffh 401000h?4011ffh ? 1 1 0 ? 00ee00h?00efffh 400000h?400fffh* 1 1 1 ? 401000h?4011ffh 400000h?400fffh* * 10-bit expanded stack is not available in shared program/data memory mode. external memo ry addressing the enabling and mapping of the chip-enable signals is done through the port 4 control register (p4cnt;92h) and memory control register (mcon; 96h). table 7 shows which chip-enable and address line signals are active on port 4. following reset, the device will be configured with p4.7?p4.4 as a ddress lines and p4.3?p 4.0 configured as ce3-0 , with the first program fetch being performed from 00000h with ce0 active. the following tables illustrate which memory ranges are controlled by each chip enabl e as a function of which address lines are enabled. table 6. external memory addressing pin assignments address/data bus ce3?ce0 pce3?pce0 addr 19?16 addr 15?8 addr 7?0 data bus multiplexed p4.3?p4.0 p5.7?p 5.4 p4.7?p4.4 p2 p0 p0 demultiplexed p4.3?p4.0 p5. 7?p5.4 p4.7?p4.4 p2 p1 p0 table 7. extended address and chip-enable generation port 4 pin function port 4 pin function p4cnt.5?3 p4.7 p4.6 p4.5 p4.4 p4cnt.2?0 p4.3 p4.2 p4.1 p4.0 000 i/o i/o i/o i/o 000 i/o i/o i/o i/o 100 i/o i/o i/o a16 100 i/o i/o i/o ce0 101 i/o i/o a17 a16 101 i/o i/o ce1 ce0 110 i/o a18 a17 a16 110 i/o ce2 ce1 ce0 111(default) a19 a18 a17 a16 111(default) ce3 ce2 ce1 ce0
ds80c390 dual can high-speed microprocessor 36 of 53 table 8. program memory chip-enable boundaries p4cnt.5?3 ce0 ce1 ce2 ce3 000 0h?7fffh 8000h?ffffh 100 00h?17fffh 18000h?1ffffh 100 0h?1ffffh 20000h?3ffffh 40000h?5ffffh 60000h?7ffffh 101 0h?3ffffh 40000h?7ffffh 800 00h?bffffh c0000h?fffffh 110 0h?7ffffh 80000h?fffffh 100 000h?17ffffh 180000h?1fffffh 111(default) 0?fffffh 100000h?1fffffh 200000h?2fffffh 300000h?3fffffh the ds80c390 incorporates a feature allowing pce and ce signals to be combined. this is useful when incorporating modifiable code memory as part of a bootstr ap loader or for in-system reprogrammability. setting the pdce3?0 ( mcon.3?0 ) bits causes the corresponding chip-enable signal to function for both movc and movx operations. write access to combined program a nd data memory blocks is controlled by the wr signal, and read access is controlled by the psen signal. this feature is especially us eful if the design achieves in-system reprogrammability via external flash me mory, in which a single device is acce ssed through both mo vc instructions (program fetch) and movx write operati ons (updates to code memory). in this case, the internal sram is placed in the program/data configuration and loaded with a small boot strap loader program stored in the external flash memory. the device then executes the internal bootstra p loader routine to modify/update the program memory located in the external flash memory. stretch memory cycles the ds80c390 allows user-application so ftware to select the number of mach ine cycles it takes to execute a movx instruction, allowing access to both fast and slow off-chip data memory and/or peripherals without glue logic. high-speed systems often includ e memory-mapped peripherals such as lcds or uarts with slow access times, so it may not be necessary or desirable to access external devices at full speed. the microprocessor can perform a movx instruction in as little as two machine cycles or as many as twelve machine cycles. accesses to internal movx sram always use two cycles. note that stretch cycle settings affect external movx memory operations only and that there is no way to slow the ac cesses to program memory other than to use a slower crystal (or external clock). external movx timing is governed by the selection of 0 to 7 stretch cycles, controlled by the md2?md0 sfr bits in the clock-control register (ckcon.2?0). a stretch of zero results in a 2-machine cycle movx instruction. a stretch of seven results in a movx of 12 machine cycles. so ftware can dynamically change the stretch value depending on the particular memory or peripheral being accessed. the default of one stretch cycle allows the use of commonly available srams without dramatically lengthening the memory access times. stretch cycle settings affect external movx timing in thr ee gradations. changing the stretch value from 0 to 1 adds an additional clock cycle each to the data setup and hold time s. when a stretch value of 4 or above is selected, the interface timing changes dramatically to allow for very sl ow peripherals. first, the ale signal is lengthened by 1 machine cycle. this increases the address setup time in to the peripheral by this amount. next, the address is held on the bus for one additional machine cycle increasing the address hold time by this amount. the wr and rd signals are then lengthened by a machine cycle. finally, dur ing a movx write the data is held on the bus for one additional machine cycle, thereby increasing the data hold time by this amount. for every stretch value greater than 4, the setup and hold times remain constant, and only th e width of the read or write signal is increased. these three gradations are reflected in the ac electrical characteristics , where the eight movx timing specifications are represented by only three timing diagrams. the reset default of one stretch cycle results in a three-cy cle movx for any external access. therefore, the default off-chip ram access is not at full speed. this is a c onvenience to existing designs that use slower ram. when maximum speed is desired, software should select a st retch value of zero. when using very slow ram or peripherals, the application software can select a larger stretch value. the specific timing of movx instructions as a fu nction of stretch settings is provided in the electrical specifications section of this data sheet. as an example, table 9 shows the read and write strobe widths corresponding to each stretch value.
ds80c390 dual can high-speed microprocessor 37 of 53 table 9. data memory cycle stretch values rd , wr pulse width (in oscillator clocks) md2 md1 md0 stretch cycle count movx machine cycles t mcs (4x/ 2x = 1 cd1:0 = 00) t mcs (4x/ 2x = 0 cd1:0 = 00) t mcs (4x/ 2x = x cd1:0 = 10) t mcs (4x/ 2x = x cd1:0 = 11) 0 0 0 0* 2 0.5 t clcl 1 t clcl 2 t clcl 2048 t clcl 0 0 1 1** 3 t clcl 2 t clcl 4 t clcl 4096 t clcl 0 1 0 2 4 2 t clcl 4 t clcl 8 t clcl 8192 t clcl 0 1 1 3 5 3 t clcl 6 t clcl 12 t clcl 12,288 t clcl 1 0 0 4 9 4 t clcl 8 t clcl 16 t clcl 16,384 t clcl 1 0 1 5 10 5 t clcl 10 t clcl 20 t clcl 20,480 t clcl 1 1 0 6 11 6 t clcl 12 t clcl 24 t clcl 24,576 t clcl 1 1 1 7 12 7 t clcl 14 t clcl 28 t clcl 28,672 t clcl *all internal movx operations execute at the 0 stretch setting. **default stretch setting for extern al movx operations following reset. extended stack pointer the ds80c390 supports both the traditional 8-bit and an extended 10-bit stack point er that improves the performance of large programs written in high-level language s such as c. enable the 10-bi t stack pointer feature by setting the stack address mode bit, sa (acon.2). the bit is cleared following a reset, forcing the device to use an 8-bit stack located in the scratchpad ram area. when t he sa bit is set, the device will address up to 1kb of stack memory in the first 1kb of the internal movx memory . the 10-bit stack pointer address is generated by concatenating the lower two bits of the extended stac k pointer (esp;9bh) and the tr aditional 8051 stack pointer (sp;81h). the 10-bit stack pointer cannot be enabled when the 4kb of sram is mapped as both program and data memory. enhanced dual data pointers the ds80c390 contains two data pointers, dptr0 and dptr 1, designed to improve performance in applications that require high data throughput. incorporating a second dat a pointer allows the software to greatly speed up block data (movx) moves by using one data pointer as a source register and the other as the destination register. dptr0 is located at the same address as the origi nal 8051 data pointer, allowing the ds80c390 to execute standard 8051 code with no modifications. the second data pointer, dptr1, is split between the dph1 and dpl1 sfrs, similar to the dptr0 configuration. the active data pointer is selected with the data pointer select bit sel (dps.0). any instructions that refere nce the dptr (i.e., movx a, @dptr), will select dptr0 if sel = 0, and dptr1 if sel = 1. because the bits adjacent to sel are not implemented, the state of sel (and thus the active data pointer) can be quickly toggled by the inc dps instruction without disturbing other bits in the dps register. unlike the standard 8051, the ds80c390 has the ability to decrement as well as increment the data pointers without additional instructions. when the inc dptr instruction is executed, t he active dptr increments or decrements according to the id1, id 0 (dps.7-6), and sel (dps.0) bits as shown. the inactive dptr is not affected. table 10. data pointer auto increment/ decrement configuration id1 id0 sel inc dptr result x 0 0 increment dptr0 x 1 0 decrement dptr0 0 x 1 increment dptr1 1 x 1 decrement dptr1 another useful feature of the device is its ability to automatically switch the active data pointer after a dptr-based instruction is executed. this feature can greatly reduce the software overhead associated with data memory block moves, which toggle between the source and destination regi sters. when the toggle-select bit (tsl;dps.5) is set to 1, the sel bit (dps.0) is automat ically toggled every time one of the fo llowing dptr-related instructions is executed.
ds80c390 dual can high-speed microprocessor 38 of 53 inc dptr mov dptr, #data16 movc a, @a+dptr movx a, @dptr movx @dptr, a as a brief example, if tsl is set to 1, then both data pointers can be updated with two inc dptr instructions. assume that sel = 0, making dptr the active data point er. the first inc dptr increments dptr and toggles sel to 1. the second instruction incr ements dptr1 and toggles sel back to 0. inc dptr inc dptr clock control and power management the ds80c390 includes a number of unique features that a llow flexibility in selecting system clock sources and operating frequencies. to support the use of inexpensive crystals while allowing full speed operation, a clock multiplier is included in the processor?s clock circuit. also, in addition to the standard 80c32 idle and power-down (stop) modes, the ds80c390 provides a new power m anagement mode. this mode allows the processor to continue instruction execution, yet at a very low speed to significantly reduce power co nsumption (below even idle mode). the ds80c390 also features several enhanceme nts to stop mode that make this extremely low-power mode more useful. each of these features is discussed in detail below. system clock control as mentioned previously, the microcontr oller contains special clock-control ci rcuitry that simultaneously provides maximum timing flexibility and maximum availability and economy in crystal selection. the logical operation of the system clock-divide contro l function is shown in figure 29 . a 3:1 multiplexer, controlle d by cd1, cd0 (pmr.7-6), selects one of three sources for the internal system clock: crystal oscillator or external clock source (crystal oscillator or extern al clock source) divided by 256 (crystal oscillator or external clock so urce) frequency multiplied by 2 or 4 times figure 29. system clock control diagram the system clock-control circuitry generates two cloc k signals that are used by the microcontroller. the internal system clock provides the time base for timers and internal pe ripherals. the system cloc k is run through a divide- by-4 circuit to generate the machine cycle clock that provides the time base for cpu operations. all instructions execute in one to five machine cycles. it is important to note the distinction between these two clock signals, as they are sometimes confused, creating errors in timing calculations. setting cd1, cd0 to 0 enables the frequency multiplier, eit her doubling or quadrupling the frequency of the crystal oscillator or external clock source. the 4x/ 2x bit controls the multiplying factor, selecting twice or four times the frequency when set to 0 or 1, respectively. enabling t he frequency multiplier results in apparent instruction execution speeds of 2 or 1 clocks. regardless of the confi guration of the frequency mult iplier, the system clock of
ds80c390 dual can high-speed microprocessor 39 of 53 the microcontroller can never be operated faster than 40mhz. this me ans that the maximum crystal oscillator or external clock source is 10mhz when using the 4x setting, and 20mhz when using the 2x setting. the primary advantage of the clock multiplie r is that it allows the microcontroller to use slower crystals to achieve the same performance level. this reduces emi and cost, as slower crystals are generally more available and thus less expensive. table 11. system cl ock configuration cd1 cd0 4x/ 2x function clocks per machine cycle max external frequency (mhz) 0 0 0 frequency multiplier (2x) 2 20 0 0 1 frequency multiplier (4x) 1 10 0 1 n/a reserved ? ? 1 0 n/a divide-by-4 (default) 4 40 1 1 n/a power management mode 1024 40 the system clock and machine cycle rate changes one ma chine cycle after the instruction changing the control bits. note that the change affects all aspects of system op eration, including timers and baud rates. the use of the switchback feature, described later, can eliminat e many of the problems associated with the pmm. changing the system clock/m achine cycle clock frequency the microcontroller incorporates a special locking sequence to ensure ?glitch-free? switching of the internal clock signals. all changes to the cd1, cd0 bits must pass th rough the 10 (divide-by-4) stat e. for example, to change from 00 (frequency multiplier) to 11 (pmm), the softwar e must change the bits in the following sequence: 00 10 11. attempts to switch between invalid states will fail, leaving the cd1, cd0 bi ts unchanged. the following sequence must be followed when switching to the frequency multiplier as the internal time source. this sequence can only be performed when the device is in divide-by-4 operation. the steps must be followed in this order, although it is possible to have other instruct ions between them. any deviation from this order will cause the cd1, cd0 bits to remain unchanged. switching from frequency multiplier to non-mu ltiplier mode requires no steps other than the changing of the cd1, cd0 bits. 1) ensure that the cd1, cd0 bits are se t to 10, and the rgmd (exif.2) bit = 0. 2) clear the ctm (crystal multiplier enable) bit. 3) set the 4x/2x bit to the appropriate state. 4) set the ctm (crystal multiplier enable) bit. 5) poll the ckrdy bit (exif.4), waiting until it is set to 1. this will take approximately 65,536 cycles of the external crystal or clock source. 6) set cd1, cd0 to 00. the frequency multiplier is engaged on the machine cycle following the write to these bits. oscillator-fail detect the microprocessor contains a safety mechanism called an on-chip oscillator-fail-detect circuit. when enabled, this circuit causes the processor to be held in reset if the oscill ator frequency falls below 40kh z. in operation, this circuit complements the watchdog timer. normally, the watchdog ti mer is initialized so that it times out and causes a processor reset in the event that the processor loses control. in the event of a crystal or external oscillator failure, however, the watchdog timer does not function and there is t he potential for the processor to fail in an uncontrolled state. the use of the oscillator-fail-de tect circuit forces the processor to a known state (i.e., reset) even if the oscillator stops. the oscillator-fail-detect circ uitry is enabled when software sets the ena ble bit ofde (pcon.4) to 1. please note that software must use a timed-access procedure (described later) to write this bit. the ofdf (pcon.5) bit also sets to 1 when the circuitry detects an oscillator failure, and the processor is forced into a reset state. this bit can only be cleared to 0 by a power-fail reset or by software. t he oscillator-fail-detect circuitry is not activated when the oscillator is stopped due to the processor entering stop mode.
ds80c390 dual can high-speed microprocessor 40 of 53 power management mode (pmm) and switchback power consumption in pmm is less than in idle mode, and approximately one quarter of that consumed in divide- by-four mode. while pmm and idle modes leave the power-h ungry internal timers running, pmm runs all clocked functions such as timers at the rate of crystal divided by 1024, rather than crystal divided by 4. even though instruction execution continues in pmm (albeit at a reduced speed), it still consumes less power than idle mode. as a result there is little reason to use idle mode in new designs. when enabled, the switchback feature allows serial ports an d interrupts to automatically switch back from divide by 1024 (pmm) to divide-by-4 (standard speed) operation. this feature makes it very convenient to use the pmm in real-time applications. software can simply set the cd1 and cd0 clock control bits to the 4 clocks-per-cycle mode to exit pmm. however, the microcontroller provides har dware alternatives for autom atic switchback to standard speed (divide-by-4) operation. setting the sfr bit swb (pmr.5) to 1 enables the switchback feature. once it is enabled, and when pmm is selected, two possible events can cause an automatic switch back to divide-by-4 mode. first, if an interrupt occurs and is acknowledged, the system clock reverts fr om pmm to divide-by-4 mode. for example, if int0 is enabled and the cpu is not servicing a higher priori ty interrupt, then switchback occurs on int0 . however, if int0 is not enabled or the cpu is servicing a higher priority interrupt, then activity on int0 does not cause switchback to occur. a switchback can also occur when an enabled uart detects the start bit indicating the beginning of an incoming serial character or when the sbuf register is loaded initiati ng a serial transmission. note that a serial character?s start bit does not generate an interrupt. the interrupt occurs only on reception of a complete serial word. the automatic switchback on detection of a start bit allows ti mer hardware to return to divide-by-4 operation (and the correct baud rate) in time for a proper serial reception or transmission. so with switchback enabled and a serial port enabled, the automatic switch to divide-by-4 operation occurs in time to receive or transmit a complete serial character as if nothing special had happened. status the status register (status; c5h) provides information about interrupt and serial port activity to assist in determining if it is possible to enter p mm. the microprocessor supports three leve ls of interrupt priority: power-fail, high, and low. the pip (power-fail prio rity interrupt status; status.7), hi p (high-priority interrupt status; status.6), and lip (low-priority interrupt status; status .5) status bits, when set to logic 1, indicate the corresponding level is in service. software should not rely on a lower-priority level interrupt source to remove pmm (switchback) when a higher level is in service. check the current priority service level before entering pmm. if the current service level locks out a desired switchback source, then it would be advisable to wait until this condition clears before entering pmm. alternately, software can prevent an undesired exit from pmm by intentionally enterin g a low priority interrupt service level before entering pmm. this will prevent other low priority interrupts from causing a switchback. entering pmm during an ongoing serial port transmission or reception can corrupt the serial port activity. to prevent this, a hardware lockout feature ignores changes to the clock divisor bits while the serial ports are active. serial port activity can be monitored via the serial port activity bits located in the status register. idle mode setting the idle bit (pcon.0) invokes the idle mode. idle l eaves internal clocks, serial ports, and timers running. power consumption drops because memory is not being accessed and instructions are not being executed. since clocks are running, the idle power consumption is a functi on of crystal frequency. it should be approximately one- half of the operational power at a given frequency. the cpu can exit idle mode with any interrupt or a reset. because pmm consumes less power than idle mode, as well as leaving timers and cpu operating, idle mode is no longer recommended for new designs, and is included for backward software compatibility only.
ds80c390 dual can high-speed microprocessor 41 of 53 stop mode setting the stop bit of the power control register (pco n.1) invokes stop mode. stop mode is the lowest power state (besides power off) since it turns off all internal clocking. all processor operat ion ceases at the end of the instruction that sets the stop bit. the cpu can exit stop mode via an extern al interrupt, if enabled, or a reset condition. internally generated interrupts (timer, se rial port, watchdog) cannot cause an exit from stop mode because internal clocks are not active in stop mode. bandgap select the ds80c390 provides two enhancements to stop mode . as described below, the device provides a band-gap reference to determine power-fail interrupt and reset thres holds. the bandgap select bit, bgs (rcon.0), controls the bandgap reference. setting bgs to 1 keeps the bandgap reference enabled during stop mode. the default or reset condition of the bit is logic 0, which disables the bandgap during stop mode. this bit has no control of the reference during full power, pmm, or idle modes. with the bandgap reference enabled, the power-fail reset and interrupt are valid means for leaving stop mode. this allows software to detect and compensate for a power-su pply sag or brownout, even when in stop mode. in stop mode with the bandgap enabled, i cc is higher compared to with the bandgap disabled. if a user does not require a power-fail reset or interrupt while in stop mode, the b andgap can remain disabled. only the most power-sensitive applications should disable the bandgap reference in stop mode, as this results in an uncontrolled power-down condition. ring oscillator the second enhancement to stop mode reduces power cons umption and allows the device to restart instantly when exiting stop mode. the ring oscillator is an internal clock that can optionally prov ide the clock source to the microcontroller when exiting stop mode in response to an interrupt. during stop mode the crystal oscillator is halted to maximize power savings. typically, 4ms to 10ms is required for an external crystal to begin oscillating again once the device receives the exit stimulus . the ring oscillator, by contrast, is a free-running digi tal oscillator that has no startup delay. se tting the ring oscillator select bit, rgsl (exif.1), enables the ring oscillator fe ature. if enabled, the microcontroller us es the ring oscillator as the clock source to exit stop mode, resuming operation in less t han 100ns. after 65,536 oscillations of the external clock source (not the ring oscillator), the device clears the ri ng-oscillator-mode bit, rgmd (exi f.2), to indicate that the device has switched from the ring oscill ator to the external clock source. the ring oscillator runs at approximately 10mhz but varies over temperature and voltage. as a result, no serial communication or precision timing should be attempted while running from the ring oscillator since the operating frequency is not precise. the default state exit s stop mode without using the ring oscillator.
ds80c390 dual can high-speed microprocessor 42 of 53 timed-access protection selected sfr bits are critical to operation, making it desirable to protect them against an accidental write operation. the timed-access procedure pr events an errant processor from acci dentally altering bits that would seriously affect processor operation. the timed-access pr ocedure requires that the write of a protected bit be immediately preceded by the following two instructions: mov 0c7h, #0aah mov 0c7h, #55h writing an aah followed by a 55h to the timed-access regi ster (location c7h) opens a three-cycle window that allows software to modify one of the protected bits. if the in struction that seeks to modi fy the protected bit is not immediately preceded by these instructions, t he write is ignored. the protected bits are: wdcon.6 por power-on reset flag wdcon.3 wdif watchdog interrupt flag wdcon.1 ewt watchdog reset enable wdcon.0 rwt reset watchdog timer rcon.0 bgs bandgap select acon.2 sa stack address mode acon.1?0 am1?am0 address mode select bits mcon.7?6 idm1?idm0 internal memory configuration and location bits mcon.5 cma can data memory assignment mcon.3?0 pdce3?pdce.0 program/data chip enables c0c.3 crst can 0 reset c1c.3 crst can 1 reset p4cnt.6 sbcan single bus can p4cnt.5?0 port 4 pin configuration control bits p5cnt.2?0 p5.7?p5.5 c onfiguration control bits cor.7 irdack i rda clock output enable cor.6?5 c1bpr7?c1bpr6 can 1 baud rate prescale bits cor.4?3 c0bpr7?c0bpr6 can 0 baud rate prescale bits cor.2?1 cod1?cod0 can clock output divide bit 1 and bit 0 cor.0 clkoe can clock output enable emi reduction one of the major contributors to radiated noise in an 8051 -based system is the toggling of ale. the microcontroller allows software to disable ale when not used by sett ing the aleoff (pmr.2) bit to 1. when aleoff = 1, ale automatically toggles during an off-ch ip movx. however, ale remains static when performing on-chip memory access. the default state of aleoff is 0 so ale normally toggles at a frequency of xtal/4. peripheral overview the ds80c390 provides several of the most commonly needed peripheral functions in microcomputer-based systems. new functions include a second serial port, pow er-fail reset, power-fail interrupt flag, and a programmable watchdog timer. in addition, the microcontroller cont ains two can modules for industrial communication applications. each of these peripherals is described in the following paragraphs. more details are available in the high-speed microcontroller user?s guide and the ds80c390 supplement . serial ports the microcontroller provides a serial port (uart) that is identical to the 80c52. in addition it includes a second hardware serial port that is a full dup licate of the standard one. this second port optionally uses pins p1.2 (rxd1) and p1.3 (txd1). it has duplicate control functions incl uded in new sfr locations. the second serial port can alternately be mapped to p5.2 and p5.3 to allow use of both serial ports in nonmultiplexed mode. both ports can operate simultaneously but can be at diffe rent baud rates or even in different modes. the second serial port has similar control registers (scon1, sbuf1) to the original. the new serial port can only use timer 1 for baud-rate generation.
ds80c390 dual can high-speed microprocessor 43 of 53 the scon0 register provides control for serial port 0 while its i/o buffer is sbuf0. the registers scon1 and sbuf1 provide the same functions for the second serial port. a full description of the use and operation of both serial ports can be found in the high-speed microcontroller user?s guide: ds80c390 supplement . watchdog timer the watchdog is a free-running, progra mmable timer that can set a flag, cause an interrupt, and/or reset the microcontroller if allowed to reach a presel ected timeout. it can be restarted by software. a typical application uses the watchdog timer as a reset source to prevent software from losing control. the watchdog timer is initialized, selecting the timeout period and enabling the reset and/or interrupt functions. after enabling the reset function, software must then restart the ti mer before its expiration or the hardware will reset the cpu. in this way, if the code ex ecution goes awry and software does not reset the watchdog as scheduled, the processor is put in a known good state: reset. software can select one of four timeout values as contro lled by the wd1 and wd0 bits. timeout values are precise since they are a function of the crystal frequency. when the watchdog times out, it sets the watchdog timer-reset flag (wtrf = wdcon.2), which generates a reset if enabled by the enable watchdog-timer reset (ewt = wdcon.1) bit. both the enable watchdog-timer reset and t he reset watchdog timer control bits are protected by timed-access circuitry. this prevents errant softwar e from accidentally clearing or disabling the watchdog. the watchdog interrupt is useful for systems that do not require a reset circuit. it set the wdif (watchdog interrupt) flag 512 clocks before setting the reset flag. software ca n optionally enable this interrupt source, which is independent of the watchdog-reset function. the in terrupt is commonly used during the debug process to determine where watchdog-reset commands must be located in the application software. the interrupt also can serve as a convenient time base generator or can wake up the processor from power-saving modes. the clock control (ckcon) and the watchdog control (wdc on) sfrs control the watchdog timer. ckcon.7 and ckcon.6 (wd1 and wd0, respectively) select the watchdog timeout period. of course, the 4x/ 2x (pmr.3) and cd1:0 (pmr.7:6) system cl ock-control bits also affect the timeout period. table 12 shows the timeout selection. table 12. watchdog timeout values watchdog interrupt timeout watchdog reset timeout 4x/ 2x cd1:0 wd1:0 = 00 wd1:0 = 01 wd1:0 = 10 wd1:0 = 11 wd1:0 = 00 wd1:0 = 01 wd1:0 = 10 wd1:0 = 11 1 00 2 15 2 18 2 21 2 24 2 15 +512 2 18 +512 2 21 +512 2 24 +512 0 00 2 16 2 19 2 22 2 25 2 16 +512 2 19 +512 2 22 +512 2 25 +512 x 01 2 17 2 20 2 23 2 26 2 17 +512 2 20 +512 2 23 +512 2 26 +512 x 10 2 17 2 20 2 23 2 26 2 17 +512 2 20 +512 2 23 +512 2 26 +512 x 11 2 25 2 28 2 31 2 34 2 25 +512 2 28 +512 2 31 +512 2 34 +512 table 12 demonstrates that for a 33mhz crystal frequency, the watchdog timer can produce timeout periods from 3.97ms (2 17 x 1/33mhz) to over 2 seconds (2.034 = 2 26 x 1/33mhz) with the default setting of cd1:0 (=10). this wide variation in timeout periods allows very flexible system implementation. in a typical initialization, the user selects one of the po ssible counter values to determine the timeout. once the counter chain has completed a full count, hardware sets the interrupt flag (wdif = wdcon.3). regardless of whether the software makes use of this flag, there are then 512 clocks left until the reset flag (wtrf = wdcon.2) is set. software can enable (1) or disable (0) the reset using the enable watchdog-timer-reset (ewt = wdcon.1) bit.
ds80c390 dual can high-speed microprocessor 44 of 53 power-fail reset the microcontroller incorporates an internal precisi on bandgap voltage reference and comparator circuit that provide a power-on and power-fail reset function. this circuit monitors the processor?s incoming power supply voltage (v cc ), and holds the processor in reset while v cc is below the minimum voltage level. when power exceeds the reset threshold, a full power-on reset is performed. in this way, this internal voltage monitoring circuitry handles both power-up and power-down conditions without the need for additional external components. once v cc has risen above v rst , the device automatically rest arts the oscillator for the external crystal and counts 65,536 clock cycles before program exec ution begins at location 0000h. this helps the system maintain reliable operation by only permitting proc essor operation when the supp ly voltage is in a known good state. software can determine that a power-on reset has occurred by chec king the power-on reset flag (por;wdcon.6). software should clear the por bit after reading it. power-fail interrupt the bandgap voltage reference that sets a precise reset th reshold also generates an optional early warning power- fail interrupt (pfi). when enabled by software, the processor vectors to rom address 0033h if v cc drops below v pfw . pfi has the highest priority. the pfi enable is in the watchdog control sfr (epfi;wdcon.5). setting this bit to logic 1 enables the pfi. application software can also re ad the pfi flag at wdcon.4. a pfi condition sets this bit to 1. the flag is independent of the in terrupt enable and must be cleared by software. external reset pins the ds80c390 has reset input (rst) and reset output ( rstol ) pins. the rstol pin supplies an active-low reset when the microprocessor is issued a reset from either a high on the rst pin, a tim eout of the watchdog timer, a crystal oscillator fail, or an internally detected power fail. the timing of the rstol pin is dependent on the source of the reset. reset type/source rstol duration power-on reset 65,536 t clcl (as described in power cycle timing characteristics ) external reset <1.25 machine cycles power fail 65,536 t clcl (as described in power cycle timing characteristics ) watchdog timer reset 2 machine cycles oscillator-fail detect 65,536 t clcl (as described in power cycle timing characteristics ) interrupts the microcontroller provides 16 interrupt sources with three priority levels. all interrupts, with the exception of the power-fail interrupt, are controlled by a series combination of individual enable bits and a global interrupt-enable, ea (ie.7). setting ea to 1 allows individual interrupts to be enabled. clearing ea disables all interrupts regardless of their individual enable settings. the three available priority levels are low, high, and highe st. the highest priority level is reserved for the power-fail interrupt only. all other interrupt priority levels have i ndividual priority bits that, when set to 1, establish the particular interrupt as high priority. in addition to the user -selectable priorities, each interrupt also has an inherent natural priority, used to determine the priority of si multaneously occurring interrupts. the available interrupt sources, their flags, their enables, their natural priority, and their available priority selection bits are identified in table 13 .
ds80c390 dual can high-speed microprocessor 45 of 53 table 13. interrupt summary name description vector natural priority flag bit enable bit priority control bit pfi power-fail interrupt 33h 0 pfi (wdcon.4) epfi (wdcon.5) n/a int0 external interrupt 0 03h 1 ie0 (tcon.1)** ex0 (ie. 0) px0 (ip.0) tf0 timer 0 0bh 2 tf0 (tcon. 5)* et0 (ie.1) pt0 (ip.1) int1 external interrupt 1 13h 3 ie1 (tcon.3)** ex1 (ie. 2) px1 (ip.2) tf1 timer 1 1bh 4 tf1 (tcon. 7)* et1 (ie.3) pt1 (ip.3) scon0 ti0 or ri0 from serial port 0 23h 5 ri_0 (scon0.0); ti_0 (scon0.1) es0 (ie.4) ps0 (ip.4) tf2 timer 2 2bh 6 tf2 (t2con.7) et2 (ie.5) pt2 (ip.7) scon1 ti1 or ri1 from serial port 1 3bh 7 ri_1 (scon1.0); ti_1 (scon1.1) es1 (ie.6) ps1 (ip.6) int2 external interrupt 2 43h 8 ie2 (exif.4) ex2 (eie.0) px2 (eip.0) int3 external interrupt 3 4bh 9 ie 3 (exif.5) ex3 (eie.1) px3 (eip.1) int4 external interrupt 4 53h 10 ie4 (exif.6) ex4 (eie.2) px4 (eip.2) int5 external interrupt 5 5bh 11 ie 5 (exif.7) ex5 (eie.3) px5 (eip.3) c0i can0 interrupt 6bh 12 variou s c0ie (eie.6) c0ip (eip.6) c1i can1 interrupt 73h 13 variou s c1ie (eie.5) c1ip (eip.5) wdti watchdog timer 63h 14 wdif (wdcon.3) ewdi (eie.4) pwdi (eip.4) canbus can0/1 bus activity 7bh 15 va rious canbie (eie.7) canbip (eip.7) unless marked, all flags must be cleared by the application software. * cleared automatically by hardware w hen the service routine is entered. ** if edge-triggered, flag is cleared automatically by hardware when the service routine is entered. if level-triggered, flag foll ows the state of the interrupt pin. controller area ne twork (can) module the ds80c390 incorporates two can contro llers that are fully compliant with th e can 2.0b specification. can is a highly robust, high-performance communication protocol for serial communications. popular in a wide range of applications including automotive, medical, heating, ventilation, and industrial control, the can architecture allows for the construction of sophisticated networks with a minimum of external hardware. the can controllers support the use of 11-bit standard or 29-bit extended acceptance identifiers for up to 15 messages, with the standard 8-byte data field, in each message. fourteen of the 15 message centers are programmable in either transmit or receive modes, wi th the 15th designated as a fifo-buffered, receive-only message center to help prevent data overruns. all mess age centers support two separate 8-bit media masks and media arbitration fields for incoming message verification. this feature supports the use of higher-level protocols, which make use of the first and/or second byte of data as a part of the acceptance layer for storing incoming messages. each message center can also be programmed i ndependently to test incoming data with or without the use of the global masks. global controls and status registers in each can uni t allow the microcontroller to evaluate error messages, generate interrupts, locate and validate new data, establish the can bus timing, establish identification mask bits, and verify the source of individual messages. each messag e center is individually equipped with the necessary status and control bits to establish direction, identification mode (standard or extended), data field size, data status, automatic remote frame request and acknowledgment, and perform masked or non-masked identification acceptance testing.
ds80c390 dual can high-speed microprocessor 46 of 53 communicating with the can module the microcontroller interface to the can modules is divided in to two groups of registers. all the global can status and control bits as well as the individual message center c ontrol/status registers are lo cated in the sfr map. the remaining registers associated with the message centers (data identification, identi fication/arbitration masks, format, and data) are located in movx data space. the cma bit (mcon.5) allows the message centers to be mapped to either 00ee00h?00eeffh (cma = 0) or 401000h?4011ffh (cma = 1), reducing the possibility of a memory conflict with application softwar e. note that setting the cma bit employs a special 23rd address bit that is only used for addressing can movx memory. the ds80c390?s in ternal architecture requires that the device be in one of the two 22-bit addressing modes when the cma bit is set to correctly use the 23rd bit and access the can movx memory. a special lockout feature prevents the accid ental software corruption of the control, status, and mask registers while a can operation is in progress. each can processor uses 15 message centers. each message center is composed of four sp ecific areas, including the following: 1) four arbitration registers (c0mxar 0?3 and c1mxar0?3) that store either the 11-bit or 29-bit arbitration value. these registers are located in the movx memory map. 2) a format register (c0mxf and c1mxf) that informs the can processor as to the direction (transmit or receive), the number of data bytes in the messag e, the identification format (standar d or extended), and the optional use of the identification mask or media mask during message evaluation. this register is located in the movx memory map. 3) eight data bytes for storage of 0 to 8 bytes of data (c0mxd0?7 and c1mxd0?7), which are located in the movx memory map. 4) message control registers (c0mxc and c1mxc), whic h are located in the sfr memory for fast access. each of the message centers is identical with the exc eption of message center 15. message center 15 has been designed as a receive-only center, and is also buffered through the use of a two-message fifo to help prevent message loss in a message-overrun situation. the receipt of a third message before either of the first two are read will overwrite the second message, leaving the first message undisturbed. modification of the can registers located in movx me mory is protected through the swint bits, with one bit protecting each respective can module. consult the description of this bit in the high-speed microcontroller user?s guide: ds80c390 supplement for more information. each can module contains a block of control/status/mask registers, 14 functionally identical message centers, plus a 15th message center that is receive-only and incorporates a buffered fifo. the following tables describe the organization of the message centers located in movx space.
ds80c390 dual can high-speed microprocessor 47 of 53 movx message centers for can 0 can 0 control/status/mask registers register 7 6 5 4 3 2 1 0 movx data address 1 c0mid0 mid07 mid06 mid05 mid04 mid03 mid02 mid01 mid00 xxxx00h c0ma0 m0aa7 m0aa6 m0aa5 m0aa4 m0aa3 m0aa2 m0aa1 m0aa0 xxxx01h c0mid1 mid17 mid16 mid15 mid14 mid13 mid12 mid11 mid10 xxxx02h c0ma1 m1aa7 m1aa6 m1aa5 m1aa4 m1aa3 m1aa2 m1aa1 m1aa0 xxxx03h c0bt0 sjw1 sjw0 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 xxxx04h c0bt1 smp tseg26 tseg25 tseg24 tseg13 tseg12 tseg11 tseg10 xxxx05h c0sgm0 id28 id27 id26 id25 id24 id23 id22 id21 xxxx06h c0sgm1 id20 id19 id18 0 0 0 0 0 xxxx07h c0egm0 id28 id27 id26 id25 id24 id23 id22 id21 xxxx08h c0egm1 id20 id19 id18 id17 id16 id15 id14 id13 xxxx09h c0egm2 id12 id11 id10 id9 id8 id7 id6 id5 xxxx0ah c0egm3 id4 id3 id2 id1 id0 0 0 0 xxxx0bh c0m15m0 id28 id27 id26 id25 id24 id23 id22 id21 xxxx0ch c0m15m1 id20 id19 id18 id17 id16 id15 id14 id13 xxxx0dh c0m15m2 id12 id11 id10 id9 id8 id7 id6 id5 xxxx0eh c0m15m3 id4 id3 id2 id1 id0 0 0 0 xxxx0fh can 0 message center 1 reserved xxxx10h?11h c0m1ar0 can 0 message 1 arbitration register 0 xxxx12h c0m1ar1 can 0 message 1 arbitration register 1 xxxx13h c0m1ar2 can 0 message 1 arbitration register 2 xxxx14h c0m1ar3 can 0 message 1 arbitration register 3 wtoe xxxx15h c0m1f dtbyc3 dtbyc2 dtbyc1 dtbyc0 t/ r ex/ st meme mdme xxxx16h c0m1d0?7 can 0 message 1 data bytes 0?7 xxxx17h?1eh reserved xxxx1fh can 0 message centers 2?14 message center 2 registers (similar to message center 1) xxxx20h?2fh message center 3 registers (similar to message center 1) xxxx30h?3fh message center 4 registers (similar to message center 1) xxxx40h?4fh message center 5 registers (similar to message center 1) xxxx50h?5fh message center 6 registers (similar to message center 1) xxxx60h?6fh message center 7 registers (similar to message center 1) xxxx70h?7fh message center 8 registers (similar to message center 1) xxxx80h?8fh message center 9 registers (similar to message center 1) xxxx90h?9fh message center 10 registers (similar to message center 1) xxxxa0h?afh message center 11 registers (similar to message center 1) xxxxb0h?bfh message center 12 registers (similar to message center 1) xxxxc0h?cfh message center 13 registers (similar to message center 1) xxxxd0h?dfh message center 14 registers (similar to message center 1) xxxxe0h?efh can 0 message center 15 ? reserved xxxxf0h?f1h c0m15ar0 can 0 message 15 arbitration register 0 xxxxf2h c0m15ar1 can 0 message 15 arbitration register 1 xxxxf3h c0m15ar2 can 0 message 15 arbitration register 2 xxxxf4h c0m15ar3 can 0 message 15 arbitration register 3 wtoe xxxxf5h c0m15f dtbyc3 dtbyc2 dtbyc1 dtbyc0 0 ex/ st meme mdme xxxxf6h c0m15d0? c0m15d7 can 0 message 15 data byte 0?7 xxxxf7h?feh reserved xxxxffh 1 the first two bytes of the can 0 movx memory address are dependent on the setting of the cma bit (mcon.5) cma = 0, xxxx = 00ee; cma = 1, xxxx = 4010.
ds80c390 dual can high-speed microprocessor 48 of 53 movx message centers for can 1 can 1 control/status/mask registers register 7 6 5 4 3 2 1 0 movx data address 1 c1mid0 mid07 mid06 mid05 mid04 mid03 mid02 mid01 mid00 xxxx00h c1ma0 m0aa7 m0aa6 m0aa5 m0aa4 m0aa3 m0aa2 m0aa1 m0aa0 xxxx01h c1mid1 mid17 mid16 mid15 mid14 mid13 mid12 mid11 mid10 xxxx02h c1ma1 m1aa7 m1aa6 m1aa5 m1aa4 m1aa3 m1aa2 m1aa1 m1aa0 xxxx03h c1bt0 sjw1 sjw0 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 xxxx04h c1bt1 smp tseg26 tseg25 tseg24 tseg13 tseg12 tseg11 tseg10 xxxx05h c1sgm0 id28 id27 id26 id25 id24 id23 id22 id21 xxxx06h c1sgm1 id20 id19 id18 0 0 0 0 0 xxxx07h c1egm0 id28 id27 id26 id25 id24 id23 id22 id21 xxxx08h c1egm1 id20 id19 id18 id17 id16 id15 id14 id13 xxxx09h c1egm2 id12 id11 id10 id9 id8 id7 id6 id5 xxxx0ah c1egm3 id4 id3 id2 id1 id0 0 0 0 xxxx0bh c1m15m0 id28 id27 id26 id25 id24 id23 id22 id21 xxxx0ch c1m15m1 id20 id19 id18 id17 id16 id15 id14 id13 xxxx0dh c1m15m2 id12 id11 id10 id9 id8 id7 id6 id5 xxxx0eh c1m15m3 id4 id3 id2 id1 id0 0 0 0 xxxx0fh can 1 message center 1 reserved xxxx10h?11h c1m1ar0 can 1 message 1 arbitration register 0 xxxx12h c1m1ar1 can 1 message 1 arbitration register 1 xxxx13h c1m1ar2 can 1 message 1 arbitration register 2 xxxx14h c1m1ar3 can 1 message 1 arbitration register 3 wtoe xxxx15h c1m1f dtbyc3 dtbyc2 dtbyc1 dtbyc0 t/ r ex/ st meme mdme xxxx16h c1m1d0?7 can 1 message 1 data bytes 0?7 xxxx17h?1eh reserved xxxx1fh can 1 message centers 2?14 message center 2 registers (similar to message center 1) xxxx20h?2fh message center 3 registers (similar to message center 1) xxxx30h?3fh message center 4 registers (similar to message center 1) xxxx40h?4fh message center 5 registers (similar to message center 1) xxxx50h?5fh message center 6 registers (similar to message center 1) xxxx60h?6fh message center 7 registers (similar to message center 1) xxxx70h?7fh message center 8 registers (similar to message center 1) xxxx80h?8fh message center 9 registers (similar to message center 1) xxxx90h?9fh message center 10 registers (similar to message center 1) xxxxa0h?afh message center 11 registers (similar to message center 1) xxxxb0h?bfh message center 12 registers (similar to message center 1) xxxxc0h?cfh message center 13 registers (similar to message center 1) xxxxd0h?dfh message center 14 registers (similar to message center 1) xxxxe0h?efh can 1 message center 15 ? reserved xxxxf0h?f1h c1m15ar0 can 1 message 15 arbitration register 0 xxxxf2h c1m15ar1 can 1 message 15 arbitration register 1 xxxxf3h c1m15ar2 can 1 message 15 arbitration register 2 xxxxf4h c1m15ar3 can 1 message 15 arbitration register 3 wtoe xxxxf5h c1m15f dtbyc3 dtbyc2 dtbyc1 dtbyc0 0 ex/ st meme mdme xxxxf6h c1m15d0? c1m15d7 can 1 message 15 data byte 0?7 xxxxf7h?feh reserved xxxxffh 1 the first two bytes of the can 1 movx memory address are dependent on the setting of the cma bit (mcon.5) cma = 0, xxxx = 00ef; cma = 1, xxxx = 4011.
ds80c390 dual can high-speed microprocessor 49 of 53 can interrupts the ds80c390 supports three interrupts associated with t he can controllers. one interrupt is dedicated to each can controller, providing receive/transmit acknowledgment s from each of its 15 message centers. the remaining interrupt, the can bus activity interrupt, is used to detect can bus activity on the c0rx or c1rx pins. the message center interrupts are enabled/disabled by indi vidual eti (transmit) and eri (receive) enable bits in the corresponding message control regist er (located in sfr memory) for each message center. all the message center interrupts of each can module are ored together into their respective can interrupt. the successful transmission or receipt of a message se ts the intrq bit in the corresponding message control register (located in sfr memory). this bit can only be cleared through software. in addition, the global interrupt-enable bit (ie.7) and the specific can interrupt-enable bit, eie.6 (can0) or eie.5 (can1), must be correctly set to acknowledge a message center interrupt. interrupt assertion of error and status conditions associ ated with the can modules is controlled by the erie and stie bits located in the can control registers, c0c and c1c. arbitration and masking after a can module has ascertained that an incoming messag e is bit-error-free, the identification field of that message is then compared against one or more arbitrati on values to determine if they will be loaded into a message center. each enabled message center (see the msrdy bit in the can message control register ) is tested in order from 1 to 15. the first message center to successfully pass the test re ceives the incoming message and ends the testing. using masking regi sters allows the use of more comple x identification schemes, as tests can be made based on bit patterns rather than an exact match betw een all bits in the identification field and arbitration values. each can processor also incorporates a set of five masks to allow messages with different ids to be grouped and successfully loaded into a message center. no te that some of these masks are optional as per the bits shown in the arbitration/masking feature summary table ( table 14 ). there are several possible arbitration tests, varying according to which message center is involved. if all the enabled tests succeed, the message is loaded into the resp ective message center. the most basic test, performed on all messages, compares either 11 (can 2.0a) or 29 (can 2.0b) bits of the identification field to the appropriate arbitration register, based on the ex/ st bit in the can 0/1 format register. the meme bit (c0mxf.1 or c1mxf.1) controls whether the arbitration and id registers are compared directly or thro ugh a mask register. a special set of arbitration registers dedicated to message center 15 allows added flexibility in filtering this location. if desired, further arbitration can be perf ormed by comparing the first two bytes of the data field in each message against two 8-bit media arbitration register bytes. the mdme bit in the can message center format registers (c0mxf.0 or c1mxf.0) either disables (mdme = 0) arbitr ation, or enables (mdme = 1) arbitration using the media id mask registers 0?1. if the 11-bit or 29-bit arbitration and the optional media-byte arbitration are successful, the message is loaded into the respective message center. the fo rmat register also allows the microcontroller to program each message center to function in a receive or transmit mode through the t/ r bit, and to use from 0 to 8 data bytes within the data field of a message. note that message center 15 can only be used in a receive mode. to avoid a priority inversion, the ds80c390 can processors are configured to reload the transmit buffer with the message of the highest priority (lowest message center number) whenever an arbitration is lost or an error condition occurs.
ds80c390 dual can high-speed microprocessor 50 of 53 table 14. arbitration/ masking feature summary test name arbitration registers mask registers control bits and conditions standard 11-bit arbitration (can 2.0a) message center arbitration registers 0?1 (located in each message center, movx memory) standard global mask registers 0?1 (located in each can control/status/mask register bank, movx memory) ex/ st = 0 meme = 0: mask register ignored. id and arbitration register must match exactly. meme = 1: only bits corresponding to 1 in mask register are compared in id and arbitration registers. extended 29-bit arbitration (can 2.0b) message center arbitration registers 0?3 (located in each message center, movx memory) extended global mask registers 0?3 (located in each can control/status/mask register bank, movx memory) ex/ st = 1 meme = 0: mask register ignored. id and arbitration register must match exactly. meme = 1: only bits corresponding to 1 in mask register are compared in id and arbitration registers. media byte arbitration media arbitration registers 0?3 (located in each can control/status/mask register bank, movx memory) media id mask registers 0?1 (located in each can control/status/mask register bank, movx memory) mdme = 0: media byte arbitration disabled. mdme = 1: only bits corresponding to 1 in media id mask register are compared between data bytes 1 and 2 and media arbitration registers. message center 15, standard 11-bit arbitration (can 2.0a) message center 15 arbitration registers 0?1 (located in message center 15, movx memory) message center 15 mask registers 0?1 (located in each can control/status/mask register bank, movx memory) ex/ st = 0 meme = 0: mask register ignored. id and arbitration register must match exactly. meme = 1: message center 15 mask registers are anded with global mask register. only bits corresponding to 1 in resulting value are compared in id and arbitration registers. message center 15, extended 29-bit arbitration (can 2.0b) message center 15 arbitration registers 0?3 (located in message center 15, movx memory) message center 15 mask registers 0?3 (located in each can control/status/mask register bank, movx memory) ex/ st = 1 meme = 0: mask register ignored. id and arbitration register must match exactly. meme = 1: message center 15 mask registers are anded with global mask register. only bits corresponding to 1 in resulting value are compared in id and arbitration registers.
ds80c390 dual can high-speed microprocessor 51 of 53 message buffering/overwrite if a message center is configured for reception (t/ r = 0) and the previous message has not been read (dtup = 1), then the disposition of an incoming message to that message center is controlled by the wtoe bit (located in can arbitration register 3 of each mess age center). when wtoe = 0, the in coming message is discarded and the current message is untouched. if the wtoe bit is set, the incoming message is received and written over the existing data bytes in that message center. the receiver overwrite bit (row) is also set in the corresponding message center control register, located in sfr memory. message center 15 is unique in that it incorporates a buffe r that can receive up to two messages without loss. if a message is received by message center 15 while it cont ains an unread message, the new incoming message is held in an internal buffer. when the can processor read s the message-center-15 memo ry location and then clears dtup = intrq = extrq = 0, the content s of the internal buffer is automatic ally loaded into the message-center- 15 movx-memory location. the message-center-15 wtoe bit controls what happen s if a third message is received when both the message- center-15 movx-memory location and the buffer contain unread messages. if wtoe = 0, the new message is discarded, leaving the message-center -15 movx-memory location and the buffer untouched. if wtoe = 1, then the third message writes over the buffered message but leaves the message-center-15 movx-memory location untouched. error counter interrupt generation each can module can be independently configured to alert t he microprocessor when either 96 or 128 errors have been detected by the transmit or receive error counters. th e error count select bit, ercs (c0c.1 or c1c.1) selects whether the limit is 96 (ercs = 0) or 128 (ercs = 1) erro rs. when the error limit is ex ceeded, the can error count exceeded bit, cece (c0s.6 or c1s.6), bit is set. if the er ie, c0ie (or c1ie), and ea sfr bits are configured, an interrupt is generated. if the ercs bit is set, the device ge nerates an interrupt when the cece bit is set or cleared, if the interrupt is enabled. bit timing bit timing of the can transmission can be adjusted per the can 2.0b specificatio n. the can 0/1 bus timing register zero (c0bt0 and c1bt0)?located in the contro l/status/mask register block in movx memory?controls the phase_seg1 and phase_seg2 time segm ents as well as the baud-rate prescaler (bpr5?bpr0). the can 0/1 bus timing register one (c0bt1 and c1bt1) contains the controls for the sampling rate and the number of clock cycles assigned to the phase segment 1 and 2 portions of the nominal bit time. the values of both bus timing registers are automatically loaded into the can processor following each software change of the swint bit from a 1 to a 0 by the microcontroller. the bit timing param eters must be set before star ting operation of the can processor. these registers can only be modified during a software initialization, (swint = 1), when the can processor is not in a bus-off mode, and after the removal of a system reset or a can reset. to avoid unpredictable behavior of the can proces sor, the software cannot clear the swint bit when tseg1 and tseg2 are both cleared to 0.
ds80c390 dual can high-speed microprocessor 52 of 53 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type pa ckage code document no. 68 plcc q68-1 21-0049 64 lqfp c64l-2 21-0083
ds80c390 dual can high-speed microprocessor 53 of 53 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products \ the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corp. revision history revision description 062299 initial preliminary release. 090799 clarifies that unused/unimplemented bi ts in the can movx sram read 0. corrected the t mcs time period table. corrected multiplexed 2-cycle date memory ceo-3 read figure to show rd and wr inactive. 110199 corrected p5.2 and p5.3 pin descriptions. corrected description of sequence to ac tivate the crystal frequency multiplier. corrected references to pqfp to read lqfp. added rstol timing information. 032904 official release (removed ?preliminary? status). abs max soldering temp now references jedec standard. ac and dc specifications updated to reflect final characterization data. clarified dc characteristics note 6 concerning port 4 and 5. removed figure 1. typical i cc vs. frequency. added t llax3 specification (identical to t llax2 ). clarified that t rlaz is held weak latch until overdriven by external memory. removed t pxiz , t phav , t phwl , and t phrl from nonmultiplexed address/data bus table. corrected psen trace in figure 10 to not show assertion during movx write. corrected table 3 to show unnecessary steps during 16/16 divide. supplied approximate oscillator-fail detection frequency. removed text references to stop mode current. corrected location of pt2 in table 14. 022305 in absolute maxi mum ratings section (page 2): removed ?a? from ipc/jedec j-std-020a s pecification to support lead-free devices. in dc electrical characteristics table (page 2): changed v pfw min to 4.10v from 4.20v changed v pfw max to 4.60v from 4.55v changed v rst min to 3.85v from 3.95v changed v rst max to 4.35v from 4.3v changed v ih2 min reference to 0.7 x v cc from 0.7 x v dd added note 10 in ac electrical characteristics table (page 3): added note to (now) note 11 that ac timing is characterized and guaranteed by design but is not production tested. 060805 added lead-free part numbers to ordering information table. 110905 added new paragraph to page 33 stating ?softwar e must ensure that the input value for the normalize operation is not zero or the function will not complete. compilers such as the one from keil software have updated their libraries and compensate for this condition.? table 3: clarified text under ?normalize? f unction. changed ?configure mcnto register as required.? to ?load mcnt0 with 00h.?

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