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8mx 72 bit sdram ? intel ? register ed dimm h -series without pll & p c/100 sdram specification supporting based on 8mx8 sdram, lvttl, 2/4-banks & 4k /8k refresh h ym7v 75ae 80 0a/ h ym7v 75ae 801 a/ h ym7v 75ae 8 30a/ h ym7v 75ae 8 3 1 a this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. sep . 199 8 rev 4.0 description the hym7v 75ae 800 a / 75ae 801 a / 75ae 830 a / 75ae 831 a h -series are high speed 3.3-volt synchro - nous dynamic ram modules composed of nine 8mx8 bit synchronous drams in 54-pin tsopii , two 48-pin sop register buffers and 8-pin tssop 2k bit e 2 prom on a 168-pin glass-epoxy printed circuit board. a 0. 22 m f and 0. 0022 m f decoupling capacitors per each sdram are mounted on the module. the hym7v 75ae 800 a / 75ae 801 a / 75ae 830 a / 75ae 831 a h -series are gold plated socket type dual in- line memory modules suitable for easy interchange and addition of 64m bytes memory. all addresses, data and control inputs are latched on the rising edge of the master clock input. the data paths are internally pipelined to achieve very high bandwidths. features 1.500 ? (38.10mm) pcb height 168-pin register ed dimm with double sided ecc support one 0. 22 m f and one 0. 0022 m f decoupling capacitors adopted serial presence detect with serial e 2 prom two register buffers & one inverter used (without pll) supports flow-through or register mode by pin no. 147 (rege) meets all the other jedec specifications single 3.3v 0.3v power supply all device pins are lvttl compatible 4096 refresh cycles every 64ms or 8192 refresh cycles every 128ms auto precharge/ precharge all banks by a 10 flag possible to assert random column address every clock cycle interleaved auto refresh mode programmable burst lengths and sequences - 1,2,4,8,full page for sequential type - 1,2,4,8 for interleave type programmable /cas latency ; 2,3 clocks support clock suspend/power down mode by cke0 data mask function by dqm mode register set programming burst termination command self refresh provides minimum power, full internal refresh control ordering information part no. max. frequency sdram bank ref . package plating hym7v 75ae 800 a t h g - 8 / 10p /1 0s 1 25 / 100 / 100 mhz 2 banks 4k tsop ii gold hym7v 75ae 801 a t h g - 8 / 10p / 10s 1 25 / 100 / 100 mhz 4 banks 4k tsop ii gold hym7v 75ae 830 a t h g - 8 / 10p /1 0s 1 25 / 100 / 100 mhz 2 banks 8k tsop ii gold hym7v 75ae 831 a t h g - 8 /1 0p /1 0s 1 25 / 100 / 100 mhz 4 banks 8k tsop ii gold based components module part no. based comp. part no. module part no. based comp. part no. hym7v75ae800athg hy57v658010atc hym7v75ae830athg hy57v648010atc hym7v75ae801athg hy57v658020atc hym7v75ae831athg hy57v648020atc
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 2 pin description pin name pin type description ck0-ck3 input system clock input; all other inputs except cke are registered to the sdram on the rising edge of clk. cke0 input clock enable; controls internal clock signal and when deactiva- ted, the sdram will be either one of the states among power down, suspend, or self refresh. /s0, /s2 input chip select; functions command mask(nop). /ras input row address strobe /cas input column address strobe /we input write enable dqm0-7 input data input / output mask dq0-dq63 input/ output data input / output; include inputs, outputs, or hi-z state. cb0-cb7 input/ output check bit input / output; include inputs, outputs, or hi-z state. v cc supply power supplies; 3.3v 0.3v v ss supply ground sda input/ output serial address and data input / output. scl input serial clock sa0-sa2 input addresses in serial e 2 prom for socket presence. hym7v 75ae 800 a /hym7v 75ae 830 a h -series ( 2bank 8mx8 sdram based ) pin name pin type description ba0 input bank select address inputs; select one of dual banks during both /ras and /cas activity. a0-a12 input address inputs; a0-a8; x&y addresses a10; precharge flag, a9-a12 ; x addresses only. hym7v 75ae 801 a /hym7v 75ae 831 a h -series ( 4bank 8mx8 sdram based ) pin name pin type description ba0, ba1 input bank address inputs; select one of quad banks during both /ras and /cas activity. a0-a11 input address inputs; a0-a8; x&y addresses a10; precharge flag, a9-a11 ; x addresses only.
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 3 pin name # name # name # name # name 1 vss 43 vss 85 vss 127 vss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 /s2 87 dq33 129 nc 4 dq2 46 dqm2 88 dq34 130 dqm6 5 dq3 47 dqm3 89 dq35 131 dqm7 6 vcc 48 nc 90 vcc 132 nc 7 dq4 49 vcc 91 dq36 133 vcc 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 vss 54 vss 96 vss 138 vss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 vcc 101 dq45 143 vcc 18 vcc 60 dq20 102 vcc 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 cb0 63 nc 105 cb4 147 rege 22 cb1 64 vss 106 cb5 148 vss 23 vss 65 dq21 107 vss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 vcc 68 vss 110 vcc 152 vss 27 /we 69 dq24 111 /cas 153 dq56 28 dqm0 70 dq25 112 dqm4 154 dq57 29 dqm1 71 dq26 113 dqm5 155 dq58 30 /s0 72 dq27 114 nc 156 dq59 31 nc 73 vcc 115 /ras 157 vcc 32 vss 74 dq28 116 vss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 vss 120 a7 162 vss 37 a8 79 ck2 121 a9 163 ck3 38 a10(ap) 80 nc 122 ba0 164 nc 39 * ba1 81 wp 123 a11 165 sa0 40 vcc 82 sda 124 vcc 166 sa1 41 vcc 83 scl 125 ck1 167 sa2 42 ck0 84 vcc 126 * a12 168 vcc note : 1. ba1 is used for hym7v75a e 801a / hym7v75a e 8 3 1a h -series ( 4 bank 8mx8 based ) 2. a12 is used for hym7v75a e 800a / hym7v75a e 8 3 0a h -series ( 2 bank 8mx8 based )
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 4 block diagram note : 1. the serial resistor values of dqs are 10 ohms.
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 5 i- 1 serial presence detect [ hym7v 75ae 800 a /hym7v 75ae 830 a h -series; 2 banks ] byte function function value number described -8 -10p -10s -8 -10p -10s note byte0 # of bytes written into serial memory at module manufacturer 128 bytes 80h byte1 total # of bytes of spd memory device 256 bytes 08h byte2 fundamental memory type sdram 04h byte3 # of row addresses on this assembly 2 banks; 1 3 0 d h 1 byte4 # of column addresses on this assembly 9 09h byte5 # of module banks on this assembly 1 bank 01h byte6 data width of this assembly 72 bits 4 8 h byte7 data width of this assembly (continued) - 00h byte8 voltage interface standard of this assembly lvttl 01h byte9 sdram cycle time @ /cas latency=3 8ns 10ns 10ns 80h a0h a0h byte10 access time from clock @ /cas latency=3 6ns 6ns 6ns 60h 60h 60h byte11 dimm configuration type ecc 0 2 h byte12 refresh rate/type 15.625 m s / self refresh supported 80h byte13 primary sdram width x8 08h byte14 error checking sdram width x8 0 8 h byte15 min imum clock delay back to back random column address t ccd =1 latency 01h byte16 burst lengths supported 1,2,4,8,full page 8fh 2 byte17 # of banks on sdram device 2 banks 0 2 h byte18 sdram device attributes, cas # latency /cas latency=2,3 0 6 h byte19 sdram device attributes, cs # latency /cs latency=0 01h byte20 sdram device attributes, write latency /we latency=0 01h byte21 sdram module attributes registered w/o pll 12 h byte22 sdram device attributes , general +/-10% voltage tolerance, burst read, precharge all, auto prechare 0 6 h byte23 sdram cycle time @ /cas latency=2 10ns 10ns 12ns a0h a0h c0h byte2 4 access time from clock @ /cas latency= 2 6ns 6ns 6ns 60h 60h 60h byte2 5 sdram cycle time @ /cas latency= 1 - - - 00h 00h 00h byte2 6 access time from clock @ /cas latency= 1 - - - 00h 00h 00h byte2 7 minimum row precharge time ( t rp ) 20ns 20ns 20ns 14h 14h 14h byte2 8 minimum row active to row active delay ( t rrd ) 16ns 20ns 20ns 10h 14h 14h byte2 9 minimum /ras to /cas delay ( t rcd ) 20ns 20ns 20ns 14h 14h 14h byte 30 minimum /ras pulse width ( t ras ) 48ns 50ns 50ns 30h 32h 32h byte 31 module bank density 64mb 10h byte 32 command & address signal input setup time ( t as ) 2ns 2ns 2ns 20h 20h 20h byte 33 command & address signal input hold time ( t ah ) 1ns 1ns 1ns 10h 10h 10h byte 34 data signal input setup time ( t ds ) 2ns 2ns 2ns 20h 20h 20h byte 35 data signal input hold time ( t dh ) 1ns 1ns 1ns 10h 10h 10h
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 6 i- 2 serial presence detect [ hym7v 75ae 800 a /hym7v 75ae 830 a h -series;2 banks :continued ] byte function function value number described -8 -10p -10s -8 -10p -10s note byte 36 -61 superset information(may be used in the future) - 00h byte 62 spd revision intel spd 1.2a 12h 4, 5 byte 63 checksum for byte 0-62 fah 20h 40h byte 64 manufacturer jedec id code hyundai jedec id ad h byte 65 -71 ? ..manufacturer jedec id code unused ff h byte 72 manufacturing location hei (korea) hea (united states) heu (europe) 0 1 h 02h 03h byte 73 manufacturer ? s part number (sdram) 7 37 h 6 byte 74 manufacturer ? s part number (3.3v) v 56 h 6 byte 75 manufacturer ? s part number (data width) 7 37 h 6 byte 76 ? ..manufacturer ? s part number (data width) 5 35 h 6 byte 77 manufacturer ? s part number (ecc) a 41h 6 byte 78 ? ..manufacturer ? s part number (intel registered without pll) e 45h 6 byte7 9 manufacturer ? s part number (memory depth) 8 38 h 6 byte 80 manufacturer ? s part number (refresh) 0 (4k ref.) 3 (8k ref.) 30 h 33h 6 byte 81 manufacturer ? s part number (2 internal banks) 0 30h 6 byte 82 manufacturer ? s part number (generation) a 41h 6 byte 83 manufacturer ? s part number (tsopii mounted) t 54h 6 byte 84 manufacturer ? s part number (x8 registered) h 48 h 6 byte 85 manufacturer ? s part number (plating type : gold) g 47 h 6 byte 86 manufacturer ? s part number (hyphen) - 2d h 6 byte 87 manufacturer ? s part number (min. cycle time) 8 1 1 38h 31h 31h 6 byte 88 ? ..manufacturer ? s part number (min. cycle time) blank 0 0 20h 30h 30h 6 byte 89 ? ..manufacturer ? s part number (min. cycle time) blank p s 20h 50h 53h 6 byte 90 manufacturer ? s part number blanks 20h 6 byte91 revision code for components process code - 3, 6 byte92 ? ..revision code for pcb process code - 3, 6 byte93 manufacturing date work week - 3, 5 byte94 ? ..manufacturing date year - 3, 5 byte95 -98 assembly serial number - - 3 byte99 -125 manufacturer specific data (may be used in the future) none 00h byte126 system frequency support 100mhz 64h 4 byte127 intel specification details for 100mhz support note 7 f7h f7h f5h 4 byte128 -256 unused storage locations - 00h note: 1. the bank address is excluded. 2. in interleaved type, the burst lengths supported is 1, 2, 4, 8. 3. not fixed but dependent. 4. refer to intel spd 1.2a specifications. 5. bcd adopted. 6. ascii adopted. 7. clk0-3 connected to the dimm, tbd junction temp, cl=2(3) support and supporting intel defined concurrent auto precharge.
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 7 ii- 1 serial presence detect [ hym7v 75ae 80 1a /hym7v 75ae 83 1a h -series; 4 banks ] byte function function value number described -8 -10p -10s -8 -10p -10s note byte0 # of bytes written into serial memory at module manufacturer 128 bytes 80h byte1 total # of bytes of spd memory device 256 bytes 08h byte2 fundamental memory type sdram 04h byte3 # of row addresses on this assembly 4 banks; 1 2 0 c h 1 byte4 # of column addresses on this assembly 9 09h byte5 # of module banks on this assembly 1 bank 01h byte6 data width of this assembly 72 bits 4 8 h byte7 data width of this assembly (continued) - 00h byte8 voltage interface standard of this assembly lvttl 01h byte9 sdram cycle time @ /cas latency=3 8ns 10ns 10ns 80h a0h a0h byte10 access time from clock @ /cas latency=3 6ns 6ns 6ns 60h 60h 60h byte11 dimm configuration type ecc 0 2 h byte12 refresh rate/type 15.625 m s / self refresh supported 80h byte13 primary sdram width x8 08h byte14 error checking sdram width x8 0 8 h byte15 min imum clock delay back to back random column address t ccd =1 latency 01h byte16 burst lengths supported 1,2,4,8,full page 8fh 2 byte17 # of banks on sdram device 4 banks 0 4 h byte18 sdram device attributes, cas # latency /cas latency=2,3 0 6 h byte19 sdram device attributes, cs # latency /cs latency=0 01h byte20 sdram device attributes, write latency /we latency=0 01h byte21 sdram module attributes registered w/o pll 12 h byte22 sdram device attributes , general +/-10% voltage tolerance, burst read, precharge all, auto prechare 0 6 h byte23 sdram cycle time @ /cas latency=2 10ns 10ns 12ns a0h a0h c0h byte2 4 access time from clock @ /cas latency= 2 6ns 6ns 6ns 60h 60h 60h byte2 5 sdram cycle time @ /cas latency= 1 - - - 00h 00h 00h byte2 6 access time from clock @ /cas latency= 1 - - - 00h 00h 00h byte2 7 minimum row precharge time ( t rp ) 20ns 20ns 20ns 14h 14h 14h byte2 8 minimum row active to row active delay ( t rrd ) 16ns 20ns 20ns 10h 14h 14h byte2 9 minimum /ras to /cas delay ( t rcd ) 20ns 20ns 20ns 14h 14h 14h byte 30 minimum /ras pulse width ( t ras ) 48ns 50ns 50ns 30h 32h 32h byte 31 module bank density 64mb 10h byte 32 command & address signal input setup time ( t as ) 2ns 2ns 2ns 20h 20h 20h byte 33 command & address signal input hold time ( t ah ) 1ns 1ns 1ns 10h 10h 10h byte 34 data signal input setup time ( t ds ) 2ns 2ns 2ns 20h 20h 20h byte 35 data signal input hold time ( t dh ) 1ns 1ns 1ns 10h 10h 10h
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 8 i i- 2 serial presence detect [ hym7v 75ae 80 1a /hym7v 75ae 83 1a h -series; 4 banks :continued ] byte function function value number described -8 -10p -10s -8 -10p -10s note byte 36 -61 superset information(may be used in the future) - 00h byte 62 spd revision intel spd 1.2a 12h 4, 5 byte 63 checksum for byte 0-62 fbh 21h 41h byte 64 manufacturer jedec id code hyundai jedec id ad h byte 65 -71 ? ..manufacturer jedec id code unused ff h byte 72 manufacturing location hei (korea) hea (united states) heu (europe) 0 1 h 02h 03h byte 73 manufacturer ? s part number (sdram) 7 37 h 6 byte 74 manufacturer ? s part number (3.3v) v 56 h 6 byte 75 manufacturer ? s part number (data width) 7 37 h 6 byte 76 ? ..manufacturer ? s part number (data width) 5 35 h 6 byte 77 manufacturer ? s part number (ecc) a 41h 6 byte 78 ? ..manufacturer ? s part number (intel registered without pll) e 45h 6 byte7 9 manufacturer ? s part number (memory depth) 8 38 h 6 byte 80 manufacturer ? s part number (refresh) 0 (4k ref.) 3 (8k ref.) 30 h 33h 6 byte 81 manufacturer ? s part number (4 internal banks) 1 31h 6 byte 82 manufacturer ? s part number (generation) a 41h 6 byte 83 manufacturer ? s part number (tsopii mounted) t 54h 6 byte 84 manufacturer ? s part number (x8 registered) h 48 h 6 byte 85 manufacturer ? s part number (plating type : gold) g 47 h 6 byte 86 manufacturer ? s part number (hyphen) - 2d h 6 byte 87 manufacturer ? s part number (min. cycle time) 8 1 1 38h 31h 31h 6 byte 88 ? ..manufacturer ? s part number (min. cycle time) blank 0 0 20h 30h 30h 6 byte 89 ? ..manufacturer ? s part number (min. cycle time) blank p s 20h 50h 53h 6 byte 90 manufacturer ? s part number blanks 20h 6 byte91 revision code for components process code - 3, 6 byte92 ? ..revision code for pcb process code - 3, 6 byte93 manufacturing date work week - 3, 5 byte94 ? ..manufacturing date year - 3, 5 byte95 -98 assembly serial number - - 3 byte99 -125 manufacturer specific data (may be used in the future) none 00h byte126 system frequency support 100mhz 64h 4 byte127 intel specification details for 100mhz support note 7 f7h f7h f5h 4 byte128 -256 unused storage locations - 00h note: 1. the bank address is excluded. 2. in interleaved type, the burst lengths supported is 1, 2, 4, 8. 3. not fixed but dependent. 4. refer to intel spd 1.2a specifications. 5. bcd adopted. 6. ascii adopted. 7. clk0-3 connected to the dimm, tbd junction temp, cl=2(3) support and supporting intel defined concurrent auto precharge.
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 9 absolute maximum ratings symbol parameter rating unit t a ambient temperature 0 to 70 c t stg storage temperature -55 to 125 c v in , v out voltage on any pin relative to v ss -1.0 to 4.6 v v cc voltage on v cc relative to v ss -1.0 to 4.6 v i os short circuit output current 50 ma p d power dissipation 9 w t solder soldering temperature time 260 10 c sec note : operation at above absolute maximum ratings can adversely affect device reliability. recommended dc operating conditions* (t a =0 c to 70 c) symbol parameter min. typ. max. unit note v cc , v cc q power supply voltage 3.0 3.3 3.6 v vss power supply voltage 0 0 0 v v ih input high voltage 2.0 3.0 v cc + 0.4 v 1,3 v il input low voltage -0.3 0 0.8 v 2,3 note : 1. v ih (max)=4.6v ac for pulse width 10ns acceptable. 2. v il (min)=-1.5v ac for pulse width 10ns acceptable. recommended ac operating conditions* (t a =0 c to 70 c, v cc =3.3v 10%, v ss =0v) symbol parameter value unit note v ih / v il ac input high/low level voltage 2.4/0.4 v vtrip input timing measurement reference level voltage 1.4 v tr / tf input rise/fall time 1 ns voutref output reference voltage 1.4 v c l output load capacitance for access time measurement 50 pf note : output load to measure access times is equivalent to two ttl gates and one capacitance(50pf). note : * dc output load circuit ac output load circuit output vtt=1.4v rt= 250 w 50pf output 50pf
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 10 dc characteristics(i) (t a =0 c to 70 c, v cc =3.3v 10%, v ss =0v) symbol parameter test condition min. max. unit i li input leakage current v i =0 to 3.6v, all other pins not undertest=0v - 90 90 m a i lo output leakage current d out is disabled, v o =0 to 3.6v - 5 5 m a v ol output low voltage i o l = 4 .0ma - 0.4 v v oh output high voltage i o h =- 4 .0ma 2.4 - v dc characteristics(ii) (t a =0 c to 70 c, v cc =3.3v 10%, v ss =0v) parameter symbol test condition max. unit note burst length=1, one bank active -8 1255 operating current i cc1 t ras 3 t ras (min), - 1 0p 1100 ma 1 t rp 3 t rp (min), i o =0ma - 1 0s 1100 i cc2p cke v il (max) , tck=15ns 238 precharge standby current in power down mode i cc2p s cke v il (max) , tck= 98 ma i cc2n cke 3 v il (min), /cs 3 v il (min), t ck =15ns input signals are chaged one time during 30ns. all other pins 3 v dd -0.2v or 0.2v 435 precharge standby current in non power down mode i cc2n s cke 3 v il (min), t ck = input signals are stable 137 ma i cc3p cke v il (max), tck=15ns 247 active standby current in power down mode i cc3p s cke v il (max) , tck= 107 ma i cc3n cke 3 v il (min), /cs 3 v il (min), t ck =15ns input signals are chaged one time during 30ns. all other pins 3 v dd -0.2v or 0.2v 615 active standby current in non power down mode i cc3n s cke 3 v il (min), t ck = input signals are stable 395 ma -8 1210 -10p 1120 cl=3 -10s 1120 -8 1030 -10p 850 burst mode operating current i cc4 t ck 3 t ck (min), t ras 3 t ras (min), i o =0ma all banks active cl=2 -10s 850 ma 1 auto refresh current i cc5 t rrc 3 t rrc (min), all banks active 1900 ma 2 self refresh current i cc6 cke 0.2v 138 ma note : 1. i cc1 and i cc4 depend on output loading and cycle rates. specified values are measured with the output open. 2. minimum of t rrc (refresh /ras cycle time)=96ns
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 11 ac characteristics i -8 -10p -10s parameter symbol min max min max min max unit note cl=3 tck3 8 10 10 ns system clock cycle time cl=2 tck2 10 1000 10 1000 10 1000 ns clock high pulse width tchw 3 - 3 - 3 - ns 1 clock low pulse width tclw 3 - 3 - 3 - ns 1 cl=3 tac3 - 6 - 6 - 6 ns 2 access time from clock cl=2 tac2 - 6 - 6 - 6 ns 2 data-out hold time toh 3 - 3 - 3 - ns 2 data-input setup time tds 2 - 2 - 2 - ns 1 data-input hold time tdh 1 - 1 - 1 - ns 1 address setup time tas 2 - 2 - 2 - ns 1 address hold time tah 1 - 1 - 1 - ns 1 cke setup time tcks 2 - 2 - 2 - ns 1 cke hold time tckh 1 - 1 - 1 - ns 1 command setup time tcs 2 - 2 - 2 - ns 1 command hold time tch 1 - 1 - 1 - ns 1 clk to data output in low z-time tolz 1 - 1 - 1 - ns 2 cl=3 tohz3 3 6 3 6 3 6 ns clk to data output in high z-time cl=2 tohz2 3 6 3 6 3 6 ns note : 1. assumed input rise and fall time ( tr / tf) is 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered. i.e., [( tr+tf)/2-1] ns should be added to the parameter. 2. if clock rising time is longer than 1ns, (tr/2-0.5 ) ns should be added to the parameter. ac characteristics ii -8 -10p -10s parameter symbol min max min max min max unit note operation trc 70 - 70 - 70 - ns /ras cycle time auto refresh trrc 70 - 70 - 70 - ns /ras to /cas delay trcd 20 - 20 - 20 - ns /ras active time tras 48 100k 50 100k 50 100k ns /ras precharge time trp 20 - 20 - 20 - ns /ras to /ras bank active delay trrd 16 - 20 - 20 - ns /cas to /cas delay tccd 1 - 1 - 1 - clk write command to data-in delay twtl 1 - 1 - 1 - clk 2 data-in to precharge command tdpl 0 - 0 - 0 - clk 2 data-in to active command tdal 3 - 3 - 3 - clk 2 dqm to data-out hi-z tdqz 3 - 3 - 3 - clk 2 dqm to data-in mask tdqm 0 - 0 - 0 - clk mrs to new command tmrd 2 - 2 - 2 - clk cl=3 tproz3 4 - 4 - 4 - clk 2 precharge to data output hi-z cl=2 tproz2 3 - 3 - 3 - clk 2 power down exit time tpde 1 - 1 - 1 - clk self refresh exit time tsre 1 - 1 - 1 - clk 1 4k 64 - 64 - 64 - refresh time 8k tref 128 - 128 - 128 - ms note : 1. a new command can be given trrc after self refresh exit. 2. timing skew is occurred because of the buffering in register.
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 12 capacitance (t a =25 c, f=1mhz) symbol parameter pin typ. max. unit c in1 input capacitance a0-a11/12, ba0/ba1 - 16 pf c in2 input capacitance /ras, /cas, /we - 16 pf c in3 input capacitance /s0, /s2 - 16 pf c in4 input capacitance ck0 - ck 3 - 40 pf c in5 input capacitance cke0 16 pf c in6 input capacitance dqm0-dqm7 - 16 pf c out output capacitance dq0-dq63, cb0-cb7 - 17 pf module operating option table hym7v75ae800/801/830/831athg-8 /cas latency t rcd t ras t rc t rp t ac t oh 125mhz 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz 2clks 2clks 4clks 6clks 2clks 6ns 3ns 66mhz 2clks 2clks 4clks 5clks 2clks 6ns 3ns hym7v75ae800/801/830/831athg-10p /cas latency t rcd t ras t rc t rp t ac t oh 100mhz 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz 2clks 2clks 5clks 6clks 2clks 6ns 3ns 66mhz 2clks 2clks 4clks 5clks 2clks 6ns 3ns 50mhz 2clks 1clks 3clks 4clks 1clks 6ns 3ns hym7v75ae800/801/830/831athg-10s /cas latency t rcd t ras t rc t rp t ac t oh 100mhz 3clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz 2clks 2clks 5clks 6clks 2clks 6ns 3ns 66mhz 2clks 2clks 4clks 5clks 2clks 6ns 3ns 50mhz 2clks 1clks 3clks 4clks 1clks 6ns 3ns
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 13 command truth table command cken-1 cken /cs /ras /cas /we dqm addr a 10 / ap ba note mode register set h x l l l l x op code 1, 2 h x x x no operation h x l h h h x x bank active h x l l h h x ra v read l 4 read with autoprecharge h x l h l h x ca h v 4, 5 write l 4 write with autoprecharge h x l h l l x ca h v 4, 5 precharge all baknks h x precharge selected bank h x l l h l x x l v burst stop h x l h h l x x 6 dqm h x v x 7 auto refresh h h l l l h x x 3 entry h l l l l h x 3 h x x x self refresh exit l h l h h h x x 3 h x x x entry h l l h h h x h x x x precharge power down exit l h l h h h x x h x x x entry h l x clock suspend exit l h x x x ( v=valid, x=don ? t care, h=logic high, l=logic low) note: 1. op code : operand code. addr, a 10 /ap, ba : program keys (@mrs) 2.mrs can be issued only at both banks precharge state. a new command can be issued after 2clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram the automatical precharge without row precharge command is meant by ? auto ? . auto/self refresh can be issued only at both banks precharge state. 4. ba : bank select address. if ? low ? at read, write, row active and precharge, bank a is selected. if ? high ? at read, write, row active and precharge, bank b is selected. if a 10 /ap is ? high ? at row precharge, ba is ignored and both banks are selected. 5. during burst read or write with auto precharge , new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2clk cycles after. (read dqm latency is 2)
hym7v 75ae 8 00a/ hym7v 75ae 8 0 1 a/ hym7v 75ae 8 30a/ hym7v 75ae 8 3 1 a h -series rev 4.0 14 package dimension

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