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ld7530/LD7530A 12/5/2007 1 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 green-mode pwm controller with integrated protections and adjustable olp delay time rev: 04 general description the ld7530/LD7530A are specifically designed for the low total system cost by integratin g many functions, protections, and the emi-improved solution in a tiny sot-26 package which usually need a lot of extra components or circuits on the general designs. furthermore, the ld7530/7530a features green mode operation, leading edge blanking time, internal slope compensation and adjustable over load protection (olp) delay time to minimize the co mponent counts for switching power supply. and to satisfy different designs, 2 versions of ovp levels are implemented as --- z ld7530 --- 28.0v 1.2v. z LD7530A --- 21.0v 1.2v. features z high-voltage cmos process with excellent esd protection z very low startup current (<20 a) z current mode control z non-audible-noise green mode control z uvlo (under voltage lockout) z leb (leading-edge blanking) on cs pin z internal slope compensation z ovp (over voltage protection) on vcc pin z olp (over load protection) z 300ma driving capability z adjustable olp delay time applications z switching ac/dc adaptor and battery charger z open frame switching power supply typical application
ld7530/LD7530A 2 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 pin configuration (ld7530) dip-8 (top view) sot-26 (top view) yy, y : year code (d: 2004, e: 2005?..) ww, w: week code p : ld75.. (product family code) ## : production code 123 4 5 6 gnd comp ct out vcc cs wp 30 1 8 2 3 4 7 6 5 top mark yyww## out vcc nc cs gnd comp nc ct y the pb free package is identified in embossed font while green package in regular font. y pin configuration (LD7530A) dip-8 (top view) sot-26 (top view) yy, y : year code (d: 2004, e: 2005?..) ww, w: week code p : ld75.. (product family code) ## : production code 123 4 5 6 gnd comp ct out vcc cs wp 30a 1 8 2 3 4 7 6 5 top mark yyww## out vcc nc cs gnd comp nc ct y the pb free package is identified in embossed font while green package in regular font. y
ld7530/LD7530A 3 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 ordering information part number package top mark shipping ld7530 pl sot-26 pb free ywp/30 3000 /tape & reel ld7530 gl sot-26 green package ywp/30 3000 /tape & reel ld7530 pn dip-8 pb free ld7530pn 3600 /tube /carton LD7530A pl sot-26 pb free ywp/30a 3000 /tape & reel LD7530A gl sot-26 green package ywp/30a 3000 /tape & reel LD7530A pn dip-8 pb free LD7530Apn 3600 /tube /carton note: the ld7530 and LD7530A are rohs compliant/ green package. pin descriptions pin (sot-26) pin (dip-8) name function 1 8 gnd ground 2 7 comp voltage feedback pin (same as the comp pin in uc384x), by connecting a photo-coupler to close the control loop and achieve the regulation. 3 5 ct this pin is to program the frequency of the low frequency timer. by connecting a capacitor to ground to set the olp delay time. 4 4 cs current sense pin, connect to sense the mosfet current 5 2 vcc supply voltage pin 6 1 out gate drive output to drive the external mosfet
ld7530/LD7530A 4 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 block diagram comp cs out internal bias & vref gnd pwm comparator 16.0v/ 10.0v green-mode control leading edge blanking 2r r r sq vref ok pg + + slope compensation 28.0v(ld7530) 21.0v(LD7530A) vcc
ld7530/LD7530A 5 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 absolute maximum ratings supply voltage vcc 30v comp, ct, cs -0.3 ~7v junction temperature 150 c operating ambient temperature -40 c to 85 c storage temperature range -65 c to 150 c package thermal resistance (sot-26) 250 c/w package thermal resistance (dip-8) 100 c/w power dissipation (sot-26, at ambient temperature = 85 c) 250mw power dissipation (dip-8, at ambient temperature = 85 c) 650mw lead temperature (soldering, 10sec) 260 c esd voltage protection, human body model 2.5 kv esd voltage protection, machine model 250 v gate output current 300ma caution: stresses beyond the ratings specified in ?absolute maximum r atings? may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this s pecification is not implied. recommended operating conditions item min. max. unit supply voltage vcc (ld7530) 11 25 v supply voltage vcc (LD7530A) 11 18 v ct value 0.047 0.1 f
ld7530/LD7530A 6 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 electrical characteristics (t a = +25 o c unless otherwise stated, v cc =15.0v) parameter conditions min typ max units supply voltage (vcc pin) startup current 8 20 a v comp =0v 2.0 3.0 ma v comp =3v 2.5 ma operating current (with 1nf load on out pin) protection tripped (olp , ovp) 0.5 ma uvlo (off) 9.0 10.0 11.0 v uvlo (on) 15.0 16.0 17.0 v ld7530 26.8 28.0 29.2 v ovp level LD7530A 19.8 21.0 22.2 v voltage feedback (comp pin) short circuit current v comp =0v 1.5 2.2 ma open loop voltage comp pin open 6.0 v green mode threshold vcomp 2.35 v current sensing (cs pin) maximum input voltage, vcs(off) 0.80 0.85 0.90 v leading edge blanking time 200 ns input impedance 1 m delay to output 100 ns oscillator for switching frequency frequency 60 65 70 khz green mode frequency 20 khz trembling frequency 3.5 khz temp. stability (-40 c ~105 c) 3 % voltage stability (vcc=11v-25v) 1 % low frequency timer (ct pin) low frequency period 4.7 ms gate drive output (out pin) output low level vcc=15v, io=20ma 1 v output high level vcc=15v, io=20ma 8 v rising time load capacitance=1000pf 50 200 ns falling time load capacitance=1000pf 30 100 ns olp (over load protection) olp trip level vcomp(olp) 5.0 v olp delay time(note) ct=0.047 f 50 ms the olp delay time is proportional to capacitance of ct pin.
ld7530/LD7530A 7 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 typical performance characteristics uvlo (on) (v) fig. 1 uvlo (on) vs. temperature temperature ( c) 14.0 14.8 15.6 16.4 17.2 18.0 -40 0 40 80 120 125 uvlo (off) (v) temperature ( c) fig. 2 uvlo (off ) vs. temperature 8 9.6 10.4 12 8.8 -40 0 40 80 120 125 11. 2 frequency (khz) fig. 3 frequency vs. temperature temperature ( c) -40 60 62 64 66 68 70 0 40 80 120 125 green mode frequency (khz) temperature ( c) fig. 4 green mode frequency vs. temperature 16 18 20 22 24 26 -40 0 40 80 120 125 frequency (khz) vcc (v) fig. 5 frequency vs. vcc 12 14 16 18 20 22 24 60 11 25 62 64 66 68 70 green mode frequency (khz) vcc (v) fig. 6 green mode frequency vs. vcc 12 14 16 18 20 22 24 11 25 19 21 23 25 17 15
ld7530/LD7530A 8 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 max duty (%) temperature ( c) fig. 7 max duty vs. temperature -40 0 40 80 120 125 65 70 75 80 85 60 v cs (off) (v) temperature ( c) fig. 8 v cs (off) vs. temperature 0.80 0.82 0.84 0.86 0.88 0.90 -40 0 40 80 120 125 ste istartup ( a) temperature ( c) fig. 9 startup current (istartup) vs. temperature -40 0 40 80 120 125 3 6 9 12 15 0 18 vcc ovp (v) temperature ( c) fig. 10 vcc ovp vs. temperature 10 15 20 25 30 35 -40 0 40 80 120 125 ld7530 LD7530A v comp (v) temperature ( c) fig. 11 v comp open loop voltage vs. temperature -40 0 40 80 120 125 4.5 5.0 5.5 6.0 6.5 7.0 olp (v) temperature ( c) fig. 12 olp-trip level vs. temperature -40 0 40 80 120 125 3.5 4.0 4.5 5.0 5.5 6.0
ld7530/LD7530A 9 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 application information operation overview the ld7530/LD7530A meet the green-power requirement and is intended for the use in those modern switching power suppliers and adaptors which demand higher power efficiency and power-saving. it integrated more functions to reduce the external components counts and the size. its major features are described as below. under voltage lockout (uvlo) an uvlo comparator is implemented in it to detect the voltage on the vcc pin. it would assure the supply voltage enough to turn on the ld7530/LD7530A pwm controllers and further to drive the power mosfet. as shown in fig. 13, a hysteresis is built in to prevent the shutdown from the voltage dip during startup. the turn-on and turn-off threshold level are set at 16.0v and 10.0v, respectively. vcc uvlo(on) uvlo(off) t t i(vcc) startup current (~ua) operating current (~ ma) fig. 13 startup current and startup circuit the typical startup circuit to generate the ld7530/LD7530A vcc is shown in fig. 14. du ring the startup transient, the vcc is lower than the uvlo threshold thus there is no gate pulse produced from ld7530/LD7530A to drive power mosfet. therefore, the current through r1 will provide the startup current and to charge the capacitor c1. whenever the vcc voltage is high enough to turn on the ld7530/LD7530A and further to de liver the gate drive signal, the supply current is provided from the auxiliary winding of the transformer. lower startup current requirement on the pwm controller will help to increase the value of r1 and then reduce the power consumption on r1. by using cmos process and the special circuit design, the maximum startup current of ld7530/LD7530A is only 20 a. if a higher resistance value of the r1 is chosen, it usually takes more time to start up. to carefully select the value of r1 and c1 will optimize the power consumption and startup time. fig. 14 current sensing and leading-edge blanking the typical current mode of pwm controller feedbacks both current signal and voltage signal to close the control loop and achieve regulation. as shown in fig. 15, the ld7530/LD7530A detect the primary mosfet current from the cs pin, which is not only for the peak current mode control but also for the pulse-by-pulse current limit. the maximum voltage threshold of the current sensing pin is set at 0.85v. from above, the mosfet peak current can be obtained from below. s ) max ( peak r v 85 . 0 i =
ld7530/LD7530A 10 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 fig. 15 a 200ns leading-edge blanking (leb) time is included in the input of cs pin to prevent the false-trigger from the current spike. in the low power application, if the total pulse width of the turn-on spikes is less than 200ns and the negative spike on the cs pin doesn?t exceed -0.3v, it could eliminated the r-c filter (as shown in the figure16). however, the total pulse width of the turn-on spike is decided by the output power, circuit design and pcb layout. it is strongly recommended to adopt a smaller r-c filter (as shown in figure 17) for higher power application to avoid the cs pin being damaged by the negative turn-on spike. output stage and maximum duty-cycle an output stage of a cmos buffer, with typical 300ma driving capability, is incorporated to drive a power mosfet directly. and the maximum duty-cycle of ld7530/LD7530A is limited to 75% to avoid the transformer saturation. voltage feedback loop the voltage feedback signal is provided from the tl431 at the secondary side through the photo-coupler to the comp pin of the ld7530/LD7530A. similar to uc3842, the ld7530/LD7530A would carry 2 diodes voltage offset at the stage to feed the voltage divider at the ratio of 1/3, that is, ) 2 ( 3 1 ) ( f comp pwm v v v comparator ? = ? a pull-high resistor is embedded internally and can be eliminated externally. fig. 16 fig. 17 oscillator and switching frequency the switching frequency of ld7530/LD7530A is fixed as 65 khz internally to provide the optimized operations by considering the emi perfor mance, thermal treatment, component sizes and transformer design.
ld7530/LD7530A 11 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 internal slope compensation in the conventional application, the problem of the stability is a critical issue for current mode controlling, when it operates in higher than 50% of the duty-cycle. as uc384x, it takes slope compensation from injectin g the ramp signal of the rt/ct pin through a coupling capacitor. it therefore requires no extra design for the ld7530/LD7530A since it has integrated it already. on/off control the ld7530/LD7530A can be turned off by pulling comp pin lower than 1.2v. the gate output pin of the ld7530/LD7530A will be disabled immediately under such condition. the off-mode can be released when the pull-low signal is removed. dual-oscillator green-mode operation there are many different topologies has been implemented in different chips for the green-mode or power saving requirements such as ?burst-m ode control?, ?skipping-cycle mode?, ?variable off-time cont rol ??etc. the basic operation theory of all these approaches intended to reduce the switching cycles under light-load or no-load condition either by skipping some switching pulses or reduce the switching frequency. what ld7530/LD7530A use to implement the power-saving operation is leadtrend technology?s own ip. by using this dual-oscillator control, the green-mode frequency can be well controlled and further to avoid the generation of audible noise. ovp (over voltage protection) on vcc the v gs ratings of the nowadays power mosfets are often limited up to max. 30v. to prevent the v gs from the fault condition, ld7530/LD7530A are implemented an ovp function on vcc. whenever the vcc voltage is higher than the ovp threshold voltage, the ou tput gate drive circuit will be shutdown simultaneously thus to stop the switching of the power mosfet until the next uvlo(on). the vcc ovp function in ld7530/LD7530A is an auto-recovery type protection . if the ovp condition, usually caused by the feedback loop opened, is not released, the vcc will tripped the ovp level again and re-shutdown the output. the vcc is working as a hiccup mode. the figure 18 shows its operation. on the other hand, if the ovp condition is removed, the vcc level will get back to normal level and the output will automatically return to the normal operation. fig. 18 over load protection (olp) to protect the circuit from being damaged under over load condition or short condition, a smart olp function is implemented in the ld7530/LD7530A. the figure 19 shows the waveforms of the olp operation. in this case, the feedback system will force the voltage loop proceed toward the saturation and then pull up the voltage on comp pin (v comp ). whenever the v comp trips up to the olp threshold 5v and stays longer than the olp delay time, the protection will activate and then turn off the gate output to stop the switching of power circuit. t he olp delay time, set by ct pin, is to prevent the false trigger from the power-on and turn-off transient. higher ct value will generate longer olp delay time. for the recommended ct value, the olp delay time is around 90ms when ct=0.1 f and will be around 50ms if ct=0.047 f. by such protection mechanism, the average input power can be reduced to very low level so that the component temperature and stress can be controlled within the safe operating area.
ld7530/LD7530A 12 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 vcc uvlo(on) uvlo(off) t t comp olp 5.0v t out olp delay time switching switching non-switching olp trip level uvlo(off) olp reset fig. 19
ld7530/LD7530A 13 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 reference application circuit --- 10w (5v/2a) adapter schematic photocoupler ic1 r7 q1 rs1 ic2 cy1 c5 ct ld7530/ LD7530A ct vcc gnd comp cs out ac input f1 ntc1 cx1 r1a r1b d1a~d1d c1 r2a c2 r6 d4 r4a c4 t1 cr51 c51 r51a l51 c52 r51b r2b c54 fl1 d2 r4b zd51 r56a r56b r54 r52 c55 r55 r53 ic51 z1 rs2 1 2 34 5 6 r8
ld7530/LD7530A 14 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 reference application circuit --- 10w (5v/2a) adapter bom p/n component value original r1a n/a r1b n/a r2a 750k , 1206 r2b 750k , 1206 r4a 39k , 1206 r4b 39k , 1206 r6 10 , 1206 r7 10 , 1206 r8 10k , 1206 rs1 2.70 , 1206, 1% rs2 2.70 , 1206, 1% r51a 100 , 1206 r51b 100 , 1206 r52 2.49k , 0805, 1% r53 2.49k , 0805, 1% r54 220 , 0805 r55 10k , 0805 r56a 510 , 1206 r56b n/a ntc1 08sp005 fl1 20mh uu9.8 t1 ei-22 l51 2.7 h p/n component value note c1 22 f, 400v l-tec c2 10 f, 50v c4 1000pf, 1000v, 1206 holystone c5 0.01 f, 16v, 0805 c51 1000pf, 50v, 0805 c52 1000 f, 10v l-tec c54 470 f, 10v l-tec c55 0.01 f, 16v, 0805 ct 0.047 f, 16v, 0805 x7r cx1 0.1 f x-cap cy1 2200pf y-cap d1a 1n4007 d1b 1n4007 d1c 1n4007 d1d 1n4007 d2 ps102r d4 1n4007 q1 2n60b 600v/2a cr51 sb540 zd51 6v2c ic1 ld7530/LD7530A cl sot-26 ic2 el817b ic51 tl431 1% f1 250v, 1a z1 n/a
ld7530/LD7530A 15 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 reference application circuit #2 --- 10 w adapter with 2-st age startup circuit pin < 0.25w when pout = 0w
ld7530/LD7530A 16 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 reference application circuit #2 --- 10w adapter with 2-stage startup circuit bom p/n component value original r1a n/a r1b n/a r2a 2.2m , 1206 r2b 2.2m , 1206 r4a 39k , 1206 r4b 39k , 1206 r6 2.2 , 1206 r7 10 , 1206 r8 10k , 1206 rs1 2.70 , 1206, 1% rs2 2.70 , 1206, 1% r51a 100 , 1206 r51b 100 , 1206 r52 2.49k , 0805, 1% r53 2.49k , 0805, 1% r54 220 , 0805 r55 10k , 0805 r56a 1k , 1206 r56b n/a ntc1 5 , 3a 08sp005 fl1 20mh uu9.8 t1 ei-22 l51 2.7 h p/n component value note c1 22 f, 400v l-tec c2 10 f, 50v l-tec c3 2.2 f, 50v c4 1000pf, 1000v, 1206 holystone c5 0.01 f, 16v, 0805 c51 1000pf, 50v, 0805 c52 1000 f, 10v l-tec c54 470 f, 10v l-tec c55 0.01 f, 16v, 0805 ct 0.047 f, 16v, 0805 x7r cx1 0.1 f x-cap cy1 2200pf y-cap d1a 1n4007 d1b 1n4007 d1c 1n4007 d1d 1n4007 d2 ps102r d3 1n4148 d4 1n4007 q1 2n60b 600v/2a cr51 sb540 zd51 6v2c ic1 ld7530/LD7530A pl sot-26 ic2 el817b ic51 tl431 1% f1 250v, 1a z1 n/a
ld7530/LD7530A 17 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 package information sot-26 dimension in millimeters dimensions in inches symbol min max min max a 2.692 3.099 0.106 0.122 b 1.397 1.803 0.055 0.071 c ------- 1.450 ------- 0.058 d 0.300 0.550 0.012 0.022 f 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 i 0.050 0.150 0.002 0.006 j 2.600 3.000 0.102 0.118 m 0.300 0.600 0.012 0.024 0 10 0 10
ld7530/LD7530A 18 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 package information dip-8 dimension in millimeters dimensions in inches symbol min max min max a 9.017 10.160 0.355 0.400 b 6.096 7.112 0.240 0.280 c ----- 5.334 ------ 0.210 d 0.356 0.584 0.014 0.023 e 1.143 1.778 0.045 0.070 f 2.337 2.743 0.092 0.108 i 2.921 3.556 0.115 0.140 j 7.366 8.255 0.290 0.325 l 0.381 ------ 0.015 -------- important notice leadtrend technology corp. reserves the right to make changes or corrections to its products at any time without notice. custom ers should verify the datasheets are current and complete before placing order.
ld7530/LD7530A 19 leadtrend technology corporation ld7530&LD7530A-ds-04 december 2007 revision history rev. date change notice 00 8/10/06 original specification. 01 01/03/07 description for trembling 02 02/13/07 revise olp (45ms to 50ms)and leb(350ns to 200ns) timing 03 10/22/07 modulating frequency 04 11/30/07 1. feature/ adjustable olp delay time 2. electrical characteristics/ low frequency timer 3. block diagram revision 4. green package option

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