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variable resolution, 10 - bit to 16 - bit r /d converter with reference oscillator ad2s1210 - ep rev. 0 information furnished by analog devices is believed to be accurate and reliable. however , no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 0206 2- 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. f eatures complete monolithic resolver - to - digital converter 3125 rps maximum tracking rate (10 - bit resolution) 2.5 arc minutes of accuracy 10 -/ 12 -/ 14- /16 - bit resolution, set by u ser parallel and serial 10 - bit to 16 - bit data ports absolute position and velocity outputs system fault detection programmable f ault d etection thresholds differential inputs incremental encoder emulation programmable sinusoidal oscillator on board compatible with dsp and spi interface standards 5 v s upply with 2.3 v to 5 v logic i nterface support d efense and a erospace a pplications (aqec) military temperature range ( ? 55 c to +125 c) controlled manufacturing baseline one a ssembly/ test s ite one f abrication s ite enhanced p roduct c hange n otification qualification data available up on req uest a pplications dc and ac s ervo m otor c ontrol encoder emulation electric power steering electric vehicles integrated starter generator s /alternator s automotive motion sensing and control general description the ad2s1210 - ep is a complete 10 - bit to 16- bit r esolution tracking resolver - to - digital converter, integrating an on - board programmable sinusoidal oscillator that provides sine wave excitation for resolvers. the converter accepts 3.15 v p - p 27% input signals, in the range of 2 khz to 20 khz on the sin e and c os ine inputs. a type ii servo loop is employed to track the inputs and convert the input sin e and c os ine information into a digital representation of the input angle and velocity. the maximum tracking rate is 3125 rps. full details about this enhanc ed product, including theory of operation, registers details, and applications information, are available in the ad2s1210 data sheet, which should be concluded in conjunction with this data sheet. functiona l block diagram reference oscill at or (dac) exci ta tion outputs ad2s1210-e p encoder emula tion synthetic reference reset dat a i/o inputs from resolver encoder emula tion outputs volt age reference reference pins interna l clock generat or crystal type ii tracking loo p f au lt detection f au lt detection outputs position register adc adc configur a tion register mu ltiplexer d at a bus output dat a i/o velocit y register 09154-001 figure 1. product highlights 1. ratiometric t racking c onversion. the type ii tracking loop provides continuous output position data without conversion delay. it also provides noise immunity and tolerance of harmoni c distortion on the reference and input signals. 2. system f ault d etection. a fault detection circuit can sense loss of resolver signals, out - of - range input signals, input signal mismatch, or loss of position tracking. the fault detection threshold levels ca n be individually programmed by the user for optimization within a particular application. 3. input signal r ange. the sine and cosine inputs can accept differential input voltages of 3.15 v p - p 27%. 4. programmable e xcitation f requency. excitation frequency is easily programmable to a number of standard frequencies between 2 khz and 20 khz. 5. triple f ormat p osition d ata. absolute 10 - bit to 16 - bit angular position data is accessed via either a 16 - bit parallel port or a 4- wire serial interface. incremental encoder emulation is in standard a- quad - b format with direction output available. 6. digital v elocity o utput. 10 - bit to 16 - bit signed digital velocity accessed via either a 16 - bit parallel port or a 4 - wire serial interface.
AD2S1210-EP rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................7 esd caution ...................................................................................7 pin configuration and function descriptions ..............................8 typical performance characteristics ........................................... 10 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 6/ 10 rev ision 0: initial version
AD2S1210-EP rev. 0 | page 3 of 16 specifications av dd = dv dd = 5.0 v 5%, clkin = 8.192 mhz 25%, exc, exc frequency = 10 khz to 20 khz (10 - bit); 6 khz to 20 khz (12 - bit); 3 khz to 12 khz (14 - bit); 2 khz to 10 khz (16 - bit) ; t a = t min to t max ; unless otherwise noted . 1 table 1 . parameter min typ max unit conditions/comments sine, cosin e inputs 2 voltage amplitude 2.3 3.15 4.0 v p - p sinusoidal waveforms, d ifferential sin to sinlo , cos to coslo input bias current 8.25 a v in = 4.0 v p - p, clkin = 8.192 mhz input impedance 485 k? v in = 4.0 v p - p, clkin = 8.192 mhz phase lock range ?44 +44 degrees sin e/ cosine vs. exc output, control register d3 = 0 common - mode rejection 20 arc sec/ v 10 hz to 1 mhz, control register d4 = 0 angular accuracy 3 angular accuracy 2.5 + 1 lsb 7 + 1 lsb arc min resolution 10, 12, 14 , 16 bits no missing codes linearity inl 10- bit 1 lsb 12- bit 2 lsb 14- bit 4 lsb 16- bit 16 lsb linearity dnl 0.9 lsb repeatability 1 lsb velocity output velocit y accuracy 4 10- bit 2 lsb zero acceleration 12- bit 2 lsb zero acceleration 14- bit 4 lsb zero acceleration 16- bit 16 lsb zero acceleration resolution 5 9, 11, 13, 15 bits dynamnic performance bandwidth 10- bit 2000 66 00 hz 2900 5400 hz clkin = 8.192 mhz 12- bit 900 2800 hz 1 200 2200 hz clkin = 8.192 mhz 14- bit 400 1 500 hz 600 1200 hz clkin = 8.192 mhz 16- bit 100 350 hz 125 275 hz clkin = 8.192 mhz tracking rate 10- bit 3 125 rps clkin = 10 .24 mhz 2500 clkin = 8.192 mhz 12- bit 1 250 rps clkin = 10.24 mhz 1000 clkin = 8.192 mhz 14- bit 625 rps clkin = 10.24 mhz 500 clkin = 8.192 mhz 16- bit 156.25 rps clkin = 10.24 mhz 125 clkin = 8.192 mhz acceleration error 10- bit 30 arc min at 50,000 rps, 2 clkin = 8.192 mhz 12- bit 30 arc min at 10,000 rps, 2 clkin = 8.192 mhz 14- bit 30 arc min at 2500 rps, 2 clkin = 8.192 mhz 16- bit 30 arc min at 125 rps, 2 clkin = 8.192 mhz
AD2S1210-EP rev. 0 | page 4 of 16 parameter min typ max unit conditions/comments settling time 10 step input 10- bit 0.6 0.9 ms to settle to within 2 lsb, clkin = 8.192 mhz 12- bit 2.2 3. 3 ms to settle to within 2 lsb, clkin = 8.192 mhz 14- bit 6.5 9. 8 ms to settle to within 2 lsb , clkin = 8.192 mhz 16- bit 27.5 48 ms to settle to within 2 lsb, clkin = 8. 192 mhz settling time 179 step input 10- bit 1.5 2.4 ms to settle to within 2 lsb , clkin = 8.192 mhz 12- bit 4.75 6. 1 ms to settle to within 2 lsb, clkin = 8.192 mhz 14- bit 10.5 15.2 ms to settle to within 2 lsb , clkin = 8.192 mhz 16- bit 45 68 ms to settle to within 2 lsb, clkin = 8.192 mhz exc, exc outputs voltage 3.2 3.6 4.0 v p - p load 100 a , t ypical differential outp ut (exc to exc ) = 7.2 v p -p center voltage 2.40 2.47 2.53 v frequenc y 2 20 khz exc/ exc dc mismatch 30 mv exc/ exc ac mismatch 1 32 mv thd ?58 db first five harmonics voltage reference refout 2.40 2.47 2.53 v i out = 100 a drift 100 ppm/c psrr ?60 db clkin, xtalout 6 v il voltage input low 0.8 v v ih voltage input high 2.0 v logic inputs v il voltage input low 0.8 v v drive = 2.7 v to 5.25 v 0.7 v v drive = 2.3 v to 2.7 v v ih voltage input high 2.0 v v drive = 2.7 v to 5.25 v 1.7 v v drive = 2.3 v to 2.7 v i il low level input current (non - pull - up ) 10 a i il low level input current (pull - up ) 80 a res0, res1, rd , wr / fsync , a0, a1, and reset pin s i ih high level input current ?10 a logic outputs v ol voltage output low 0.4 v v drive = 2.3 v to 5.25 v v oh voltage output high 2.4 v v drive = 2.7 v to 5.25 v 2.0 v v drive = 2.3 v to 2.7 v i ozh high level three - state leakage ?10 a i ozl low level three - state leakage 10 a power requirements av dd 4.75 5.25 v dv dd 4.75 5.25 v v drive 2.3 5.25 v power supply i avdd 12 ma i dvdd 35 ma i ovdd 2 ma 1 tempe rature range is as follows: C 55 c to + 12 5c. 2 the voltages sin, sinlo, cos, and coslo, relative to agnd, must always be between 0.15 v and av dd ? 0.2 v. 3 all specif ications within the angular accuracy parameter are tested at constant velocity, that is, zero acceleration. 4 the velocity accuracy specification includes velocity offset and dynamic ripple. 5 for example , when res0 = 0 and res1 = 1, the position output has a resolution of 12 bits. the velocity output has a resolution of 11 bits with the msb indicating the direction of rotation. in this example, with a clkin frequency of 8.192 mhz , the velocity lsb is 0.488 rps, that is, 1000 rps/(2 11 ). 6 the clock frequency of the ad2s1210 -ep can be supplied with a crystal, an oscillator, or directly from a dsp/microprocessor digital output. when using a single - ended clock signal directly from the dsp/microprocessor, the xtalout pin should remain open circuit and the logic levels outlined under the logic inputs parameter in table 1 apply.
AD2S1210-EP rev. 0 | page 5 of 16 timing specification s av dd = dv dd = 5 .0 v 5%, t a = t min to t max, unless otherwise noted. 1 table 2. parameter description limit at t min , t max unit f clkin frequency of clock input 6.144 mhz min 10.24 mhz max t ck clock period ( t ck = 1/f clkin ) 98 ns min 163 ns max t 1 a0 and a1 setup time before rd / cs low 2 ns min t 2 delay cs falling edge to wr / fsync rising edge 22 ns min t 3 address/data setup time during a write cy cle 3 ns min t 4 address/data hold time during a write cycle 2 ns min t 5 delay wr / fsync rising edge to cs rising edge 2 ns min t 6 delay cs rising edge to cs fallin g edge 10 ns min t 7 delay between writing address and writing data 2 t ck + 20 ns min t 8 a0 and a1 hold time after wr / fsync rising edge 2 ns min t 9 delay between successive write cycles 6 t ck + 20 ns min t 10 d elay between rising edge of wr / fsync and falling edge of rd 2 ns min t 11 delay cs falling edge to rd falling edge 2 ns min t 12 enable delay rd lo w to data valid in configuration mode v drive = 4.5 v to 5.25 v 37 ns min v drive = 2.7 v to 3.6 v 25 ns min v drive = 2.3 v to 2.7 v 30 ns min t 13 rd rising edge to cs rising edge 2 ns min t 14a disable delay rd high to data high - z 16 ns min t 14b disable delay cs high to data high - z 16 ns min t 15 delay between rising edge of rd and falling edge of wr / fsync 2 ns min t 16 sample pulse width 2 t ck + 20 ns min t 17 delay from sample before rd / cs low 6 t ck + 20 ns min t 18 hold time rd before rd low 2 ns min t 19 enable delay rd / cs low to data valid v drive = 4.5 v to 5.25 v 17 ns min v drive = 2.7 v to 3.6 v 21 ns min v drive = 2.3 v to 2.7 v 33 ns min t 20 rd pulse width 6 ns min t 21 a0 and a1 set time to data valid when rd / cs low v drive = 4.5 v to 5.25 v 36 ns min v drive = 2.7 v to 3.6 v 37 ns min v drive = 2.3 v to 2.7 v 29 ns min t 22 delay wr / fsync falling edge to sc lk rising edge 3 ns min t 23 delay wr / fsync falling edge to sdo release from high -z v drive = 4.5 v to 5.25 v 16 ns min v drive = 2.7 v to 3.6 v 26 ns min v drive = 2.3 v to 2.7 v 29 ns min t 24 delay sclk rising edge to dbx valid v drive = 4.5 v to 5.25 v 24 ns min v drive = 2.7 v to 3.6 v 18 ns min v drive = 2.3 v to 2.7 v 32 ns min t 25 sclk high time 0.4 t sclk ns min t 26 sclk low time 0.4 t sclk ns min t 27 sdi setup time prior to sclk falling edge 3 ns min t 28 sdi hold time after sclk falling edge 2 ns min
AD2S1210-EP rev. 0 | page 6 of 16 parameter description limit at t min , t max unit t 29 delay wr / fsync rising edge to sdo high -z 15 ns min t 30 delay from sample before wr / fsync falling ed ge 6 t ck + 20 ns ns min t 31 delay cs falling edge to wr / fsync falling edge in normal mode 2 ns min t 32 a0 and a1 setup time before wr / fsync falling edge 2 ns min t 33 a0 and a1 hold time after wr / fsync falling edge 2 in normal mode, a0 = 0, a1 = 0/1 24 t ck + 5 ns ns min in configuration mode, a0 = 1, a1 = 1 8 t ck + 5 ns ns min t 34 delay wr / fsync rising edge to wr / fsync falling edge 10 ns min f sclk frequency of sclk input v drive = 4.5 v to 5.25 v 20 mhz v drive = 2.7 v to 3.6 v 25 mhz v drive = 2.3 v to 2.7 v 15 mhz 1 temperature range is as follows: C 55 c to +125c. 2 a0 and a1 should remain constant for the duration of the serial readback. this may require 24 clock periods to read back the 8- bit fault information in addition to the 16 bits of position/velocity data. if the fault information is not required, a0/a1 may be released after 16 clock cycles.
AD2S1210-EP rev. 0 | page 7 of 16 absolute maximum rat ings table 3. parameter rating av dd to agnd, dgnd ? 0.3 v to +7.0 v dv dd to agnd, dgnd ? 0.3 v to +7.0 v v drive to agnd, dgnd ? 0.3 v to av dd av dd to dv dd ? 0.3 v to +0.3 v agnd to dgnd ? 0.3 v to +0.3 v analog input voltage to agnd ? 0.3 v to av dd + 0.3 v digital input voltage to dgnd ? 0.3 v to v drive + 0.3 v digital output voltage to dgnd ? 0.3 v to v drive + 0.3 v analog output voltage swing ? 0.3 v to av dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range (ambient) ep grade ? 55 c to +125c storage temperature ra nge ? 65c to +150c ja thermal impedance 2 54c/w jc thermal impedance 2 15c/w rohs -c ompliant te mperature, soldering reflow 260( ? 5/+0) o c esd 2 kv hbm 1 transient currents of up to 100 ma do not cause latch - up. 2 jedec 2s2p standard board. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
AD2S1210-EP rev. 0 | page 8 of 16 pin configuration and function descripti ons 48 res0 47 refout 46 refby p 45 cos 44 coslo 43 av dd 42 sinlo 41 sin 40 agnd 39 exc 38 exc 37 a0 35 dos 34 lot 33 reset 30 b 31 nm 32 dir 36 a1 29 a 28 db0 27 db1 25 db3 26 db2 2 cs 3 rd 4 wr/fsync 7 clkin 6 dv dd 5 dgnd 1 res1 8 xt alout 9 soe 10 sample 12 db14/sdi 11 db15/sdo 13 db13/sclk 14 db12 15 db 11 16 db10 17 db9 18 v drive 19 dgnd 20 db8 21 db7 22 db6 23 db5 24 db4 pin 1 ad2s1210-e p top view (not to scale) 09154-002 figure 2 . pin configuration table 4 . pin function descriptio ns pin no. mnemonic description 1 res1 resolution select 1. logic input. res1 in conjunction with res0 allows the resolution of the ad2s1210 -ep to be programmed. 2 cs chip select. active low logic input. the device is enabled when cs is held low. 3 rd edge - triggered logic input. when the soe pin is high, this pin acts as a frame synchronization signal and output enable for the parallel data outputs , db15 to db0. the output buffe r is enabled when cs and rd are held low. when the soe pin is low, the rd pin should be held high. 4 wr / fsync edge - triggered logic input. when the soe pin is high, this pin acts as a frame synchronization signal and input enable for the parallel data inputs , db7 to db0. the input buffer is enabled when cs and wr / fsync are held l ow. when the soe pin is low, the wr / fsync pin acts as a frame synchronization signal and enable for the serial data bus. 5, 19 dgnd digital ground. these pins are ground reference points for digital circuitry on the ad2s1210 -ep . refer a ll digital input signals to this dgnd voltage. both of these pins can be connected to the agnd plane of a system. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 6 dv dd digital supply voltage, 4.75 v to 5.25 v. this is the supply voltage for all digital circuitry on the ad2s1210 - ep . the av dd and dv dd voltages should ideally be at the same potential and must not be more than 0.3 v apar t, even on a transient basis. 7 clkin clock input. a crystal or oscillator can be used at the clkin and xtalout pins to supply the required clock frequency of the ad2s1210 - ep . alternatively , a single - ended clock can be applied to the clkin pin. the input frequency of the ad2s1210 - ep is specified from 6.144 mhz to 10.24 mhz. 8 x talout crystal output. when using a crystal or oscillator to supply the clock frequency to the ad2s1210 - ep , apply the crystal across the clkin and xtalout pins. when using a sin gle - ended clock source , the xtalout pin should b e considered a no connect pin. 9 soe serial output enable. logic input. this pin enables either the parallel or serial interface. the serial interface is selected by holding the soe pin low, and the parallel interface is selected by holding the soe pin high. 10 sample sample result. logic input. data is transferred from the position and velocity integrators to the position and velocity registers after a high -to - low transition on the sample signal. the fault register is also updated after a high -to - low transition on the sample signal. 11 db15/sdo data bit 15/serial data output bus. when the soe pin is high, this pin acts as db15, a three - state data output pin controlled by cs and rd . when the soe pin is low, this pin acts as sdo, the serial data output bus controlled by cs and wr / fsync . the bits are clocked out on the rising edge of sclk. 12 db14/sdi data bit 14/serial data input bus. when the soe pin is high, this pin acts as db14, a three - state data output pin controlled by cs and rd . when the soe pin is low, this pin acts as sdi, the serial data input bus controlled by cs and wr / fsync . the bits are c locked in on the falling edge of sclk.
AD2S1210-EP rev. 0 | page 9 of 16 pin no. mnemonic description 13 db13/sclk data bit 13/serial clock. in parallel mode , this pin acts as db13, a three - state data output pin controlled by cs and rd . in serial mode , this pin acts as the serial clock input. 14 to 17 db12 to db9 data bit 12 to data bit 9. t hree - state data output pins controlled by cs and rd . 18 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. decouple this pin to dgnd. the voltage range on this pin is 2.3 v to 5.25 v and may be different from the voltage range at av dd and dv dd but should never exceed either by more than 0.3 v. 20 db8 data bit 8. t hree - state data output pi n controlled by cs and rd . 21 to 28 db7 to db0 data bit 7 to data bit 0. t hree - state data input/output pins controlled by cs , rd , and wr / fsync . 29 a incremental encoder emulation output a. logic output. this output is free running and is valid if the resolver format input signals applied to the converter are valid. 30 b incremental encoder emulation output b. logic output. this output is free running and is valid if the resolver format input signals applied to the converter are valid. 31 nm north marker incremental encoder emulation output. logic output. this output is free running and is valid if the resolver format input signals applied to the converter are valid. 32 dir direction. logic output. this output is used in conjunction with the incremental encoder emulation outputs. the dir output indicates the direction of the input rotation and is high for increasing angular rotation. 33 reset reset. logic input. the ad2s1210 -ep requires an external reset signal to hold the reset input low until v dd is within the specified operating range of 4. 7 5 v to 5. 2 5 v. 34 lot loss of tracking. logic output. loss of tracking ( lot ) is indicated by a logic low on the lot pin and is not latched. 35 dos degradation of signal. logic output. degradation of signal (dos) is detected when either resolver input ( sine or cosine ) exceeds the specified dos sine / cosine thre shold or when an ampli t ude mismatch occurs between the sine and cosine input voltages. dos is indicated by a logic low on the dos pin. 36 a1 mode select 1. logic input. a1 in conjunction with a0 allows the mode of the ad2s1210 -ep to be selected. 37 a0 mode select 0. logic input. a0 in conjunction with a1 allows the mode of the ad2s1210 -ep to be selected. 38 exc excitation frequency. analog output. an on - board oscillator provides the sinusoidal excitation signal (exc) and its complement signal ( exc ) to the resolver. the frequency of this reference signal is programmable via the e xcitation f requency register. 39 exc excitation frequency complement. analog output. an on - board oscillator provides the sinusoidal excit ation signal (exc) and its complement signal ( exc ) to the resolver. the fre quency of this reference signal is programmable via the e xcitation f requency register. 40 agnd analog ground. this pin is the ground reference points for analog circuitry on the ad2s1210 -ep . refer a ll analog input signals and any external reference signal to this agnd voltage. connect t he agnd pin to the agnd plane of a system. the agnd and dgnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 41 sin positive analog input of differential sin/sin lo pair. the input range is 2.3 v p - p to 4.0 v p -p. 42 sin lo negative analog input of differential sin/sin lo pair. the input range is 2.3 v p - p to 4.0 v p -p. 43 av dd analog supply voltage, 4.75 v to 5.25 v. this pin is the supply voltage for all analog circuitry on the ad2s1210 -ep . the av dd and dv dd voltages ideally should be at the same potential and must not be more than 0.3 v apart, even on a trans ient basis. 44 cos lo negative analog input of differential cos/cos lo pair. the input range is 2.3 v p - p to 4.0 v p -p. 45 c os positive analog input of differential cos/cos lo pair. the input range is 2.3 v p - p to 4.0 v p -p. 46 refbyp reference bypass. connect r eference decoupling capacitors at this pin . typical recommended values are 10 f and 0.01 f. 47 refout voltage re ference output . 48 res0 resolution select 0. logic input. res0 in conjunction with res1 allows the resolution of the ad2s1210 -ep to be programmed.
AD2S1210-EP rev. 0 | page 10 of 16 typical performance characteristics t a = 25 c , av dd = dv dd = v drive = 5 v, sin/sinlo = 3.15 v p - p, cos/coslo = 3.15 v p - p, clkin = 8.192 mhz , unless otherwise noted. 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 1000 2000 3000 4000 5000 6000 7000 8000 9000 hits per code code 09154-003 figure 3. typical 16 - bit angular accuracy histogram of codes, 1 0,000 samples 8000 7000 6000 5000 4000 3000 2000 1000 0 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 hi ts per code code 09154-004 figure 4. typical 14 - bit angular accuracy histogram of codes , 1 0,000 samples , hysteresis disabled 12000 10000 8000 6000 4000 2000 0 2046 2047 2048 2049 2050 codes hits per code 09154-005 figure 5. typical 14 - bit angular accuracy histogram of codes , 1 0,000 samples , hysteresis enabled 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 8201 hits per code code 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 09154-006 figure 6. typical 12 - bit angular accuracy histogram of codes , 1 0,000 samples , hysteresis disabled 12000 10000 8000 6000 4000 2000 0 510 511 512 513 514 codes hits per code 09154-017 figure 7. typical 12 - bit angular accuracy histogram of codes , 1 0,000 samples , hysteresis enabled 1400 1200 1000 800 600 400 200 0 8178 8179 8176 8177 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 hi ts per code code 09154-018 figure 8. typical 10 - bit angular accuracy histogram of codes , 1 0,000 samples , hysteresis disabled
AD2S1210-EP rev. 0 | page 11 of 16 12000 10000 8000 6000 4000 2000 0 126 127 128 129 130 co des hits per code 09154-038 figure 9. typical 10 - bit angular accuracy histogram of codes , 10, 000 samples , hysteresis enabled 20 18 16 14 12 10 8 6 4 2 0 0 4 8 12 16 20 24 28 32 36 40 time (ms) angle (degrees) 09154-010 figure 10 . typical 16 - bit 10 step response 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 time (ms) angle (degrees) 09154-009 figure 11 . typical 14 - bit 10 step response 20 18 16 14 12 10 8 6 4 2 0 0 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 time (ms) angle (degrees) 09154-008 figure 12 . typical 12 - bit 10 step response 20 18 16 14 12 10 8 6 4 2 0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 time (ms) angle (degrees) 09154-007 figure 13 . typical 10 - bit 10 step response 250 225 200 175 150 125 100 75 50 25 0 0 8 16 24 32 40 48 56 64 72 80 time (ms) angle (degrees) 09154-014 figure 14 . typical 16 - bit 179 step response
AD2S1210-EP rev. 0 | page 12 of 16 20 18 16 14 12 10 8 6 4 2 0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 time ( ms ) angle (degrees) 09154-013 figure 15 . typical 14 - bit 179 step response 250 225 200 175 150 125 100 75 50 25 0 0 1 2 3 4 5 6 7 8 9 10 t ime (ms) angle (degrees) 09154-012 figure 16 . typical 12 - bit 179 step response 250 225 200 175 150 125 100 75 50 25 0 0 1 2 3 4 5 t ime (ms) angle (degrees) 09154-011 figure 17 . typical 10 - bit 179 step response 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?45 1 10 100 1k 10k 100k frequency (hz) magnitude (db) 16-bit 14-bit 12-bit 10-bit 09154-015 figure 18 . typical system magnitude response 0 ?40 ?20 ?60 ?80 ?100 ?120 ?140 ?160 ?180 ?200 1 10 100 1k 10k 100k f requency (hz) phase (db) 16-bit 14-bit 12-bit 10-bit 09154-016 figure 19 . typical system phase response 10 8 9 7 6 5 4 3 2 1 0 0 500 1000 1500 2000 2500 acceleration (rps 2 ) tracking error (degrees) 09154-022 figure 20 . typical 16 - bit tracking error vs. acceleration
AD2S1210-EP rev. 0 | page 13 of 16 10 8 9 7 6 5 4 3 2 1 0 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 acceleration (rps 2 ) tracking error (degrees) 09154-021 figure 21 . typical 14 - bit tracking error vs. acceleration 10 8 9 7 6 5 4 3 2 1 0 0 20000 60000 100000 140000 180000 acceleration (rps 2 ) tracking error (degrees) 09154-020 figure 22 . typical 12 - bit tracking error vs. acceleratio n 10 8 9 7 6 5 4 3 2 1 0 0 200000 400000 600000 800000 1000000 acceleration (rps 2 ) tracking error (degrees) 09154-019 figure 23 . typical 10 - bit tracking error vs. acceleration
AD2S1210-EP rev. 0 | page 14 of 16 outline dimensions compliant t o jedec s t andards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706- a figure 24 . 48 - lead low profile quad flat package [lqfp] (st - 48) dimensions shown in millimeters ordering guide model temperature range package description package option ad2s1210 sst- ep -rl7 ? 55 c to +12 5c 48- lead lqfp st- 48
AD2S1210-EP rev. 0 | page 15 of 16 notes
AD2S1210-EP rev. 0 | page 16 of 16 notes ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09154 -0- 6/10(0)

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