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NOII4SM014KA ibis4-14000 14-megapixel cmos image sensor ? semiconductor components industries, llc, 2011 1 publication order number: june, 2011 - rev. 7 NOII4SM014KA/d features 3048 4560 active pixels 8-m 8-m square pixels 36-mm 24-mm focal plane array 35 mm optical format 3 frames per second (fps) frame rate rolling shutter mode on-chip fpn correction 4 parallel analog outputs serial peripheral interface (spi) roi read out and smart sub-sampling dynamic range: 65.4 db supplies: 3.3 v 49-pin pga package <0.760-w power dissipation applications machine vision (pcb printing) document scanning biometrics (finger printing) digital photography description on semiconductor ibis4-14k cmos image sensor has an image resolution of 3048 by 4560 active pixels. the pixels are 8-m 8-m in size and consist of high sensitivity 3t rolling shutter capability. the ibis4-14k is available with 14 megapixels resolution at 3 fps which makes this product ideal for document scanning, biometrics and low speed machine vision applications. the ibis4-14k is housed in a 49-pin ceramic pga package contact your local on semiconductor representative for more information. figure 1. ibis4-14k photo ordering information note refer to ordering code definition on page 21 for more information. marketing part number description package NOII4SM014KA-gec mono with double-sided ar coating 49-pin pga
NOII4SM014KA rev. 7 | www.onsemi.com | page 2 of 25 contents features .................................................................................. 1 applications ........................................................................... 1 description.............................................................................. 1 ordering information ............................................................. 1 content ................................................................................... 2 specifications ........................................................................ 3 general specifications ..................................................... 3 electro-optical specifications . .......................................... 3 electrical specifications .................................................... 3 architecture and operation .................................................. 5 floor plan ......................................................................... 5 pixel specifications .......................................................... 6 readout and subsampling modes ................................... 8 sensor read out timing diagrams ..................................... 9 spi register ........................................................................ 13 spi interface architecture ...... ........................................ 13 spi register definition ................................................... 13 package information ............................................................ 15 pin configuration............................................................. 15 geometry and mechanical ...... ....................................... 17 pin number assignment.................................................. 18 package diagram ........................................................... 19 die placement dimensions and accuracy ...................... 19 glass lid ......................................................................... 20 handling precautions .......................................................... 21 limited warranty ................................................................. 21 return material authorization (rma) ............................. 21 acceptance criteria specificatio n ............. .............. .......... 21 ordering code definition .................................................... 21 acronyms ............................................................................. 22 glossary ............................................................................... 23 document history page ...................................................... 25
NOII4SM014KA rev. 7 | www.onsemi.com | page 3 of 25 specifications all parameters are measured using the default settings (s ee recommended operating conditions) unless otherwise specified. general specifications elec tro-optical specifications parameter value pixel architecture 3t pixel technology cmos pixel size 8- ? m 8- ? m resolution 3048 4560 power supply 3.3 v shutter type rolling shutter pixel rate 15 mhz nominal frame rate at full resolution 3.25 frames/s power dissipation 176 mw/53 ma dynamic range 65.4 db packaging 49-pins pga parameter value effective conversion gain [1] 18.5 v/e- spectral response fill factor 0.22 a/w (peak) peak quantum efficiency (qe) fill factor 45% between 500-700 nm range full well charge [1] 65000 electrons linear range 90% of full well charge temporal noise (ktc noise limited) 35 electrons sensitivity (at 650 nm) 1256 v.m 2 /w.s dynamic range [1] 1857:1 (65.4 db) linear dynamic range [1] 1671:1 (64.5 db) average dark current @ 24 c 55 pa/cm 2 dark current signal @ 24 c 223 electrons/s, 4.13 mv/s mtf at nyquist @ 600 nm 0.55 in x, 0.57 in y fixed pattern noise (local 32 x 32 pixel window) 0.11% vsat rms fixed pattern noise (global) 0.15% vsat rms photo response non-uniformity (prnu) <1% rms of signal anti-blooming 10 5 notes 1. absolute maximum ratings are limits beyond which damage may occur. 2. on semiconductor recommends that customers become familiar with, and follow the procedures in jedec standard jesd625-a. refer to application note an52561 . . table 1. absolute maximum ratings [1] symbol description min max units v dc dc supply voltage ?0.5 4.5 v v in dc input voltage ?0.5 v dc + 0.5 v v out dc output voltage ?0.5 v dc + 0.5 v i dc dc current per pin; any single input or output 50 ma t s [2] abs storage temperature range 0 150 ? c abs storage humidity range 5 90 %rh electrostatic discharge (esd) [2] human body model (hbm) jedec rating: class 0 v charged device model (cdm) jedec rating: class i v lu [2] latch-up ibis4-14k is not rated for latch-up ma
NOII4SM014KA rev. 7 | www.onsemi.com | page 4 of 25 table 2. recommended operating conditions [3], [4], [5] table 3. biasing currents [3], [4], [5] parameter description min typ max unit t j [4] operating temperature range 0 70 ? c t s [5] storage temperature range 20 40 ? c storage humidity range 30 60 %rh vdd nominal power supply ? 3.3 3.6 v vddrl vddrr reset power supply level ? 4 ? v vdd_array pixel supply level ? 3 ? v darkref dark reference offset level 1.7 2.65 3 v gndab anti-blooming ground level 0 0 1 v v out analog output level 0.5 ? 3 v v ih logic input high level 2.5 ? 3.3 v v il logic input low level 0 ? 1 v notes: 3. settings: vdd = 3.3v, vddr = 4v and vdd_array = 3v. 4. operating ratings are conditions in which operation of the device is intended to be functional. 5. tolerance on bias reference voltages: 150 mv due to process variances. pin number pin name connection input current pin voltage 1 obias 10 k to v dd 179 ? a 1.51 v 36 cbias 22 k to v dd 91 ? a 1.29 v 37 pcbias 22 k to v dd 91 ? a 1.29 v 48 xbias 10 k to v dd 181 ? a 1.49 v 49 abias or 10 m to v dd ? 0.8 v
NOII4SM014KA rev. 7 | www.onsemi.com | page 5 of 25 architecture and operation floor plan the architecture of the sensor is shown in the figure 2 . the y-shift registers point at a row of imager arrays. the imager arrays row is selected by the row drivers or reset by them. there are two y-shift registers, one points to the row that is read out and the other points to the row to be reset. the second pointer may lead the first pointer by a specific number of rows. in that case, the time difference between both pointers is the integration time. alternatively, both shift registers can point at the same row for reset and readout for a faster reset sequence. when the row is read out, it is also reset. this is to do double sampling for fpn reduction. the pixel array of the ibis4-14000 consists of 4536 3024 active pixels and 24 additional columns and rows which can be addressed (see figure 3 ). the column amplifiers read out the pixel information and perform the double sampling operation. they also multiplex the signals on the readout buses, which are buffered by the output amplifiers. the shift registers can be configured for various subsampling modes. the output amplifiers can be individually powered down and some other additional functions are available. these options are configurable using a serial input port. figure 2. ibis4-14k block diagram pixel array 4560 x 3048 active pixels x-shift register y shift registe r 3048 column amplifiers 4560 row drivers y shift register 4560 row drivers clk_yr sync_yr a nalog o utputs pixel (0,0) shs shr clk_x sync_x clk_yl sync_yl reset sy r syl
NOII4SM014KA rev. 7 | www.onsemi.com | page 6 of 25 figure 3. location of 24 additional columns and rows, scan direction of the array pixel specifications the pixel is a classic three transistor active pixel. the photodiode is a high-fill-factor n-well/p-substrate diode. the chip has separate power supplies for the following: general power supply for the analog image core (vdd) power supply for the reset line drivers (vddr) separate power supply for the pixel itself (vddarray). figure 4. pixel and column structure schematic fpn and prnu fpn correction is done on-chip using the double sampling technique. the pixel is read out and this voltage value is sampled on the capacitor shs. after readout, the pixel is reset again and this value is sampled by shr. both sample and reset values of each pixel are subtracted in the column amplifiers to subtract fpn. raw images taken by the sensor typically feature a residual (local) fpn of 0.11% rms of the saturation voltage. the photo response nonuniformity (prnu), caused by mismatch of photodiode node capacitances, is not corrected on-chip. measurements indicate that the typical prnu is less than 1% rms of the signal level. output stage unity gain buffers are implemented as output amplifiers. these amplifiers can be directly dc-coupled to the analog-digital converter or coupled to an external programmable gain amplifier (pga). the dark reference offset of the output signal is adjustable between 1.7 v and 3 v. the amplifier output signal is negative going with increasing light levels, with a maximum amplitude of 1.2 v (at 4 v reset voltage, in hard reset mode). the output signal range of the output amplifiers is between 0.5 v and 3 v. notes on analog video signal and output amplifier specifications: video polarity: the video signal is negative going with increasing light level. signal offset: the analog offset of the video signal can be set by an external dc bias (pin 12 darkref). the settable range is between 1.7 v and 3 v, with 2.65 v being the nominal expected set point. hence, the output range (including 1.2 v video signal) is between 3 v and 0.5 v. power control: the output amplifiers can be switched between an ?operating? mode and a ?standby? mode via the serial port of the imager (see spi register on page 13 for the configuration). coupling: the ibis4-14000 can be dc- or ac-coupled to the a/d converter. 3024 x 4536 active pixels 24 x 4536 dummy pixels ------------- sky -------------- 3024 x 24 dummy pixels 4 analog outputs top of camera 3048 x 4560 total pixels pixel 0,0 reset vdd_ array select column pc shs shr m1 m2 m3
NOII4SM014KA rev. 7 | www.onsemi.com | page 7 of 25 figure 5. spectral response curve
NOII4SM014KA rev. 7 | www.onsemi.com | page 8 of 25 output amplifier crossbar switch (multiplexer) a crossbar switch is available that routes the green pixels always to the same output. the switch can be controlled automatically (with a toggle on every clk_y rising edge) or manually (through the spi register). a pulse on sync_y resets the crossbar switch. the initial state after reset of the switchboard is read from the spi control register. when the automatic toggling of the switchboard is enabled, it toggles on every rising edge of the clk_y clock. separate pins are used for the sync_y and clk_y signals on the crossbar logic these pins can be connected to the sync_yl and clk_yl pins of the shift register that is used for readout as shown in figure 6 . figure 6. output amplifier crossbar switch readout and subsampling modes the subsampling modes available on the ibis4-14000 are summarized in table 4 . each mode is selected independently for the x-shift and y-shift registers. the subsampling mode is configured via the serial input port of the chip. the y-shift and x-shift registers have some difference in subsampling modes because of constraints in the design of the chip. the baseline full resolution operation mode uses four outputs to read out the entire image. four consecutive pixels of a row are put in parallel on the four parallel outputs. subsampling is implemented by a shift register with hard coded subsample modes. depending on the selected mode, the shift register skips the required number of pixels when shifting the row or column pointer. the x-shift register always sele cts four consecutive columns in parallel. you can subsample in x by activating one of the modes wherein a multiple of four consecutive columns are skipped on a clk_x pulse. the y-shift register se lects a single row. it consec- utively selects two adjacent rows and then skips a set number of rows (the number of rows to skip is set in the subsample mode). power power power power q sync_yr clk_yr manual table 4. subsampling modes subsampling modes programmed into spi register x-shift register subsampling settings bit- code mode use 000 001 010 1:1 full resolution (all columns) full resolution (4 outputs) 4:1 subsampling 011 24:1 select 4 columns/ skip 20 24:1 subsampling ( 2 outputs) 100 8:1 select 4 columns / skip 4s 8:1 subsampling (2 outputs) 101 12:1 select 4 columns / skip 8 12:1 subsampling (2 outputs) y-shift register subsampling settings bit- code mode use 000 010 100 4:1 select 2 rows / skip 2 4:1 subsampling 001 1:1 full resolution (all rows) full resolution 011 6:1 select 2 rows / skip 4 6:1 subsampling 101 12:1 select 2 rows / skip 10 12:1 subsampling
NOII4SM014KA rev. 7 | www.onsemi.com | page 9 of 25 one output can be used and every second row selected by the y-shift register can be skipped. this doubles the frame rate. note that for 2 or 1 channel readout, you can power down the not-used output amplifiers through the spi shift register. rows can also be skipped by extra clk_y pulses. you do not need to apply additional control pulses to rows that are skipped. this is another way to implement extra subsampling schemes. for example, to support the 24:1 x-shift register mode vertically, set the y-shift register to the 12:1 mode and given an additional clk_y pulse at the start of each row. ta b l e 5 lists the frame rates of the ibis4-14000 in various subsample modes with only one output. the row blanking time (dead time between readout of successive rows) is set to 17.5 s. note the 24 additional columns and rows do not subsample (see figure 3 on page 6). sensor read out timing diagrams row sequencer the row sequencer controls pulses to be given at the start of each new line. figure 7 on page 10 shows the timing diagram for this sequence. the signals to be controlled at each row are: clk_yl and clk_yr: these are the clocks of the yl and yr shift register. they can be driven by the same signals and at a continuous frequency. at every rising edge, a new row is being selected. select: this signal connects the pixels of the currently sampled line with the columns. it is important that pc and select are never active together. pc: an initialization pulse that needs to be given to precharge the column. shs (sample & hold pixel signal): this signal controls the track and hold circuits in the column amplifiers. it is used to sample the pixel signal in the columns. (0 = track ; 1 = hold). reset: this pulse resets the pixels of the row that is currently being selected. in ro lling shutter mode, t he reset signal is pulsed a second time to reset the row selected by the yr shift register. for ?reset black? dark reference signals, the reset pulse can be pulsed also during the first pc pulse. normally, the rising edge of reset and the falling edge of pc occur at the same position. the falling edge of reset lags behind the rising pc edge. shr (sample & hold pixel reset level): this signal controls another track and hold circuit in the column amplifiers. it is used to sample the pixel reset level in the columns (for double sampling). (0 = track ; 1 = hold). syl (select yl register): selects the yl shift register to drive the reset line of the pixel array. syr (select yr register): selects the yr shift register to drive the reset line of the pixel array. for rolling shutter applications, syl and syr are complementary. in full frame readout, both registers may be selected together, only if it is guaranteed that both shift registers point to the same row. this can reduce the row blanking time. sync_yr and sync_yl: synchronization pulse for the yr and yl shift registers. the sync_yr/sync_yl signal is clocked in during a rising edge on clk_yr/clk_yl and resets the yr/yl shift register to the first row. both pulses are pulsed only once each frame. the exact pulsing scheme depends on the mode of use (full frame/ rolling shutter). a 200 ns setup time applies. see table 6 on page 10 . sync_x: resets the column pointer to the first row. this has to be done before the end of the first pc pulse in case the previous line has not been read out completely. table 5. frame rates and resolu tion for various subsample modes ratio # outputs image resolution frame rate [frames/s] frame readout time [s] 1:1 4 3024 x 4536 3.25 0.308 4:1 1 756 x 1134 12.99 0.077 8:1 1 378 x 567 41.30 0.024 12:1 1 252 x 378 77.13 0.013
NOII4SM014KA rev. 7 | www.onsemi.com | page 10 of 25 figure 7 shows the basic timing diagram of the ibis4-14000 image sensor and table 6 on page 10 shows the timing specifications of the clocking scheme. figure 7. line read out timing notes clk = one clock period of the master clock, shortest system time period available. table 6. timing constraints for the row sequencer symbol min typ units description a 200 600 ns min. sync set-up times. sync_y is clocked in on rising edge on clk_y. sync_y pulse must overlap clk_y by one clock period. setup times of 200 ns apply after sync edges. within this setup time no rising clk edge may occur. b ? 2.7 ? s duration of pc pulse. c?10 ? s delay between falling edge on pc and rising edge on shs/shr. duration of shs/shr pulse. d?1.3 ? s delay between rising edge on pc and rising edge on select. e?6.5 ? s delay between rising edge on select and rising edge on shs/shr. f ? 100 ns delay between rising edge on shs and falling edge on select. g?1.4 ? s delay between falling edge of select and rising edge of reset. h?5 ? s duration of reset pulse. i ? 1.28 ? s delay between rising edge on shr and rising edge on syr. j h+2*clk 500 ns syl and syr pulses must overlap second reset pulse at both sides by one clock cycle. k ? 240 ns duration of clock_y pulse. l?3 ? s delay between falling edge of clk_y and falling edge of pc and shs. m ? 500 ns delay between fa lling edge of reset and falling edge of pc and shr. clock_yl pc shs select reset shr syl syr sync_yr sync_yl a bb c d e f c e d f g h h i jj once each frame for each new row only when the electronic shutter is used h optional reset pulse for reset black k l m
NOII4SM014KA rev. 7 | www.onsemi.com | page 11 of 25 in figure 7 on page 10 timing diagram, the yr shift register is used for the electronic shutter. the clk_yr is driven identically as clk_yl. the sync_yr pulse leads the sync_yl pulse by a given number of rows. relative to the row timing, both sync pulses are given at the same time position. sync_yr and sync_yl are only pulsed once each frame, sync_yl is pulsed when the first row is read out and sync_yr is pulsed for the electronic shutter at the appropriate moment. this timing assumes that the registers that control the subsam- pling modes have been loaded in advance (through the spi interface), before the pulse on sync_yl or sync_yr. the second reset pulse and the pulses on syl and syr (all pulses drawn in red) are only applied when the rolling electronic shutter is used. for full frame integration, these pulses are skipped. the sync_y pulse is also used to initialize the switchboard (output multiplexer). this is also done by a synchronous reset on the rising edge of clk_y. normally the switchboard is controlled by the shift register used for readout (this is the yl shift register). this means that pin sync_y can be connected to sync_yl, and pin clk_y can be connected to clk_yl. the additional reset black pulse (indicated in dashed lines in figure 7 on page 10) can be given to make one or more lines black. this is useful to generate a dark reference signal. timing pulse pattern for readout of a pixel figure 8 shows the timing diagram to preset (sync) the x shift register, read out the image row, and analog-digital conversion. there are 3 tasks: preset the x shift register: apply a low level to sync_x during a rising edge on clk_x at the start of a new row readout of the image row: pulse clk_x analog-digital conversion: clock the adc the sync pulses perform a synchronous reset of the shift registers to the first row/column on a rising edge on clk. this is identical for all shift registers (yr, yl and x). note the sync_x signal has a setup time ts of 150 ns. for the yr and ys shift registers, the setup time is 200 ns. clk_x must be stable at least during this setup time. if a partial row readout is performed, 2 clk_x pulses (with sync_x = low) are required to fully deselect the column where the x pointer is stopped. a single clk_x leaves the column partially selected which then has a different response when read out in the next row. when full row readout is performed, the last column is fully deselected by a single clk_x pulse (with sync_x = low). the x-register is reset by a single clk_x pulse (with sync_x = low). in case of partial row readout, give the sync_x pulse before the sample pulses (shr and shs) of the process to avoid a different response of the last column of the previous window. for the x shift register the analog signal is delayed by 2 clock periods before it becomes available at the output (due to internal processing of the signal in the columns and output amplifier). figure 8 gives an example of an adc clock for an adc that samples on the rising edge. figure 8. row readout timing sequence sync_x clk_x clk_adc (example) a nalog output pixel 1 pixel 2 pixel 3 x ts ts
NOII4SM014KA rev. 7 | www.onsemi.com | page 12 of 25 fast frame reset timing diagram figure 9 shows the reset timing for a fast frame reset. keep both syl and syr high to speed up the reset mechanism and reduce propagation delays. pc, shs, shr can be kept high since they do not interact with the pixel reset mechanism. ta b l e 7 lists the timing specific ations for reset, clk_y and select. figure 9. fast reset sequence timing table 7. fast reset timing constraints symbol typical description a 0 ? s delay between rising clk_y edge and reset. b 4 ? s reset pulse width. c 0 reset hold time. d 1.6 ? s select pulse width. e 1 ? s setup hold time. constraint: a + e > 1 us due to propagation delay on pixel select line. clk_yr clk_yl sync_y r sync_yl shs reset sh r syl sy r pc b b ac select d e
NOII4SM014KA rev. 7 | www.onsemi.com | page 13 of 25 spi register spi interface architecture the elementary unit cell of the serial to parallel interface consists of two d-flip-flops. the architecture is shown in figure 10 . 16 of these cells are connected in parallel, having a common /cs a nd sclk form the entire uploadable parameter block, where d in is connected to d out of the next cell. the uploaded settings are applied to the sensor on the rising edge of signal /cs. figure 10. spi interface spi register definition sensor parameters can be serially uploaded inside the sensor at the start of a frame. the parameters are: subsampling modes for x and y-shift registers (3-bit code for six subsampling modes) power control of the output amplifiers, column amps and pixel array. each amplifier can be individually powered up/down output crossbar switch control bits. the crossbar switch is used to route the green pixels to the same output amplifiers at all times. a first bit controls the crossbar. when a second bit is set, the first bit toggles on every clk_y edge to automatically route the green pixels of the bayer filter pattern. the code is uploaded serially as a 16-bit word (lsb uploaded first). table 9 on page 14 lists the register definition. the default code for a full resolution readout is 33342 (decimal) or 1000 0010 0011 1110. d q c d q c din to sensor core dout sclk cs 16 outputs to sensor core sclk din dout unity cell entire uploadable parameter block cs d0 d1 d2 d15 cs sclk din ts data valid tsclk th table 8. timing requirements serial parallel interface parameter value tsclk 100 ns ts 50 ns th 50 ns
NOII4SM014KA rev. 7 | www.onsemi.com | page 14 of 25 three pins are used for the serial data interface. this interface converts the serial data into an (internal) parallel data bus (serial-parallel interface or spi). the control lines are: data: the data input. lsb is clocked in first. clk: clock, on each rising edge, the value of data is clocked in cs: chip select, a rising edge on cs loads the parallelized data into the on-chip register. the initial state of the register is undefined. however, no state exists that destroys the device. table 9. serial sensor parameters register bit definitions bit description? 0 (lsb) set to zero (0). 1 1 = power on sensor array ; 0 = power-down. 2 1 = power up output amplifier 4; 0 = power-down. 3 1 = power up output amplifier 3; 0 = power-down. 4 1 = power up output amplifier 2; 0 = power-down. 5 1 = power up output amplifier 1; 0 = power-down. 6 3-bit code for subsampling mode of x shift register: 000 = full resolution 011 = select 4, skip 20 001 = full resolution 100 = select 4, skip 4 010 = full resolution 101 = select 4, skip 8 7 8 9 3-bit code for subsampling mode of y-shift registers: 000 = select 2, skip 2 011 = select 2, skip 4 001 = full resolution 100 = select 2, skip 2 010 = select 2, skip 2 101 = select 2, skip 2 10 11 12 crossbar switch (output multiplexer) control bit initial value. this initial value is clocked into the crossbar switch at a sync_yr rising edge pulse (when the array pointers jump back to row 1). the crossbar switch control bit selects the correspondence between multiplexer busses and output amplifiers. bus-to-output correspondence is according to the following table: bus when bit set to 0 when bit set to 1 1 output 1 output 2 2 output 2 output 1 3 (4 outputs) output 3 output 4 4 (4 outputs) output 4 output 3 13 1 = toggle crossbar switch control bit on every odd/even line. in order to let green pixels always use the same output amplifier automatically, this bit must be set to 1. on every clk_y rising edge (when a new row is selected), the crossbar switch control bit will toggle. initial value (after sync_y) is set by bit 12. 14 not used. 15 (msb) 1 = power-up sensor array; 0 = power-down.
NOII4SM014KA rev. 7 | www.onsemi.com | page 15 of 25 package information pin configuration ta b l e 1 0 lists the pin configuration of the ibis4-14000. figure 12 on page 18 shows the assignment of pin numbers on the package. table 10. pinout configuration pin # name function comment 1 obias bias current output amplifiers connect with 10 k ? to v dd and decouple with 100 nf to gnd 2 gnd ground for output 3 3 out3 output 3 4 gnd ground for output 4 5 out4 output 4 6 vdd power supply nominal 3.3 v 7 gnd ground 0 v 8 out2 output 2 9 gnd ground for output 2 10 out1 output 1 11 gnd ground for output 1 12 darkref offset level of output signal typ. 2.6 v. min. 1.7 v max. 3 v 13 temp1 temperature sensor. located near the output amplifiers (pixel 4536, 0) near the stitch line) any voltage above gnd forward biases the diode. connect to gnd if not used 14 phdiode photodiode output. yields the equivalent photocurrent of 250 x 50 pixels. diode is located right under the pad reverse biased by any voltage above gnd connect to gnd if not used. 15 clk_y y clock for switchboard clocks on rising edge connect to clk_yl (or drive identically) 16 sync_y y sync pulse for switchboard low active: synchronous sync on rising edge of clk_y connect to sync_yl (or drive identically) 17 temp2 temperature sensor located near pixel (24,0) any voltage above gnd forward biases the diode connect to gnd if not used 18 gndab anti-blooming reference level (= pin 33) typ. 0 v. set to 1.5 v for improved anti-blooming 19 gnd ground 0 v 20 vdd power supply nominal 3.3 v 21 vddr power supply for reset line drivers nominal 4 v connected on-chip to pin 30 22 clk_yr clock of yr shift register shifts on rising edge 23 syr activate yr shift register for driving of reset and select line of pixel array high active. exact pulsing pattern see timing diagram. both syr = 1 and syl = 1 is not allowed, except when the same row is selected 24 sync_yr sets the yr shift register to row 1 low active. synchronous sync on rising edge of clk_yr 200 ns setup time 25 vddarray pixel array power supply (= pin 26) 3 v 26 vddarray pixel array power supply (= pin 25) 3 v 27 sync_yl sets the yl shift register to row 1 low active. synchronous sync on rising edge of clk_yl 200 ns setup time 28 syl activate yl shift register for driving of reset and select line of pixel array high active. exact pulsing pattern see timing diagram. both syr = 1 and syl = 1 is not allowed, except when the same row is selected
NOII4SM014KA rev. 7 | www.onsemi.com | page 16 of 25 29 clk_yl clock of yl shift register shifts on rising edge 30 vddr power supply for reset line drivers nominal 4 v connected on-chip to pin 21 31 vdd power supply nominal 3.3 v 32 gnd ground 0 v 33 gndab anti-blooming reference level (pin 33) typ. 0 v. set to 1 v for improved anti-blooming 34 select control select line of pixel array high active. see timing diagrams 35 reset reset of the selected row of pi xels high active. see timing diagrams 36 cbias bias current column amplifiers connect with 22 k ? to v dd and decouple with 100 nf to gnd 37 pcbias bias current connect with 22 k ? to v dd and decouple with 100 nf to gnd 38 din serial data input 16-bit word. lsb first 39 sclk spi interface clock shifts on rising edge 40 cs chip select data copied to registers on rising edge 41 pc row initialization pulse see timing diagrams 42 sync_x sets the x-shift register to row 1 low active. synchronous sync on rising edge of clk_x 150 ns setup time 43 gnd ground 0 v 44 vdd power supply nominal 3.3 v 45 clk_x clock of yr shift register shifts on rising edge 46 shr row track and hold reset level (1 = hold; 0 = track). see timing diagram 47 shs row track and hold signal level (1 = hold; 0 = track) see timing diagram 48 xbias bias current x multiplexer connect with 10 k ? to v dd and decouple with 100 nf to gnd 49 abias bias current pixel array connect with 10 m ? to v dd and decouple with 100 nf to gnd table 10. pinout configuration (continued) pin # name function comment
NOII4SM014KA rev. 7 | www.onsemi.com | page 17 of 25 geometry and mechanical die geometry figure 11. die geometry and location of pixel (0,0) ground pad, also connected to package ground plane analog output pad ground for output pad (not connected to package ground plane) locations of temperature sensing diodes location of photodiode array 4 output channels pixel 0,0 500 m pin 1
NOII4SM014KA rev. 7 | www.onsemi.com | page 18 of 25 pin number assignment figure 12. pin number assignment note pins in black are connected to die attach area for a proper ground plane. package back side 1 2 3 4 5 6 13 12 11 10 9 8 7 19 18 17 16 15 14 20 21 22 23 24 25 31 30 29 28 27 26 32 33 34 35 36 37 38 39 40 41 42 43 49 48 47 46 45 44
NOII4SM014KA rev. 7 | www.onsemi.com | page 19 of 25 package diagram figure 13. package dimensions die placement dimensions and accuracy figure 14. die placement 001-07577 *b
NOII4SM014KA rev. 7 | www.onsemi.com | page 20 of 25 glass lid the cyii4sm014kaa-gec device uses the gl ass lid with double sided ar coating. 200 2 all dimensions in mm figure 15. tolerances
NOII4SM014KA rev. 7 | www.onsemi.com | page 21 of 25 handling precautions for proper handling and storage conditions, refer to the on semiconductor application note an52561. limited warranty on semiconductor image sensor business unit warrants that the image sensor products to be delivered hereunder if properly used and serviced, will conform to seller's published specifications and will be free from defects in material and workmanship for two (2) years following the date of shipment. if a defect were to manifest itself within two (2) years period from the sale date, on semiconductor will either replace the product or give credit for the product. return material authorization (rma) on semiconductor packages all of its image sensor products in a clean room environment under strict handling procedures and ships all image sensor products in esd-safe, clean room-approved shipping containers. products returned to on semiconductor for failure analysis should be handled under these same conditions and packed in its original packing materials, or the customer may be liable for the product. acceptance criteria specification the product acceptance criteria is available on request. this document contains the criteria to which the ibis4-14000 is tested before being shipped. ordering code definition o = opto n = on semiconductor ibis4 m=mono g= pga package commercial temperature range no i4 a 014k m se g -c s = standard process 14 mp resolution additional functionality e= double sided ar coating i i = image sensors
NOII4SM014KA rev. 7 | www.onsemi.com | page 22 of 25 acronyms acronym description adc analog-to-digital converter afe analog front end ansi american national standards institute bga ball grid array bl black pixel data cdm charged device model cds correlated double sampling cis cmos image sensor cmos complementary metal oxide semiconductor cmy cyan magenta yellow crc cyclic redundancy check dac digital-to-analog converter ddr double data rate dft design for test dnl differential nonlinearity dsnu dark signal nonuniformity eia electronic industries alliance esd electrostatic discharge fe frame end ff fill factor fot frame overhead time fpn fixed pattern noise fps frames per second fs frame start hbm human body model hmux horizontal multiplexer i2c inter-integrated circuit ieee institute of electrical and electronics engineers img regular pixel data inl integral nonlinearity ip intellectual property jtag joint test action group le line end ls line start lsb least significant bit lvds low-voltage differential signaling mbs mixed boundary scan msb most significant bit mtf modulation transfer function ndr nondestructive readout nir near infrared pga programmable gain amplifier pls parasitic light sensitivity prbs pseudo-random binary sequence prnu pixel random nonuniformity qe quantum efficiency rgb red green blue rms root mean square roi region of interest rot row overhead time s/h sample and hold snr signal-to-noise ratio spi serial peripheral interface tap test access port tbd to be determined tia telecommunications industry association tr training pattern upga micro pin grid array acronym description
NOII4SM014KA rev. 7 | www.onsemi.com | page 23 of 25 glossary blooming the leakage of charge from a saturated pixel into neighboring pixels. camera gain constant a constant that converts the number of elec trons collected by a pixel into digital output (in dn). it can be extracted from photon transfer curves. column noise variation of column mean signal strengths. t he human eye is sensitive to line patterns so this noise is analyzed separately. conversion gain a constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. conversion gain = q/c where q is the charge of an electron (1.602e 19 coulomb) and c is the capacitance of the photodiode or sense node. cds correlated double sampling. this is a method for sampling a pixel where the pixel voltage after reset is sampled and subtracted from the voltage after exposure to light. cfa color filter array. the materials deposited on top of pixels that selectively transmit color. color crosstalk the leakage of signal from one color channel into another when the imager is not saturated. the signal can leak through either optical means, in whic h a photon enters a pixel of the ?wrong? color, or electrical means, in which a charge carrier generated within one pixel diffuses into a neighboring pixel. cra chief ray angle. oblique rays that pass through the ce nter of a lens system aper ture stop. color filter array, metal, and micro lens shifts are determined by the chief ray angle of the optical system. in general, optical systems with smaller cra ar e desired to minimize color artifacts dn digital number. the number of bits (8, 12, 14, ?) should also be specified. dnl differential nonlinearity (for adcs) dsnu dark signal nonuniformity. this parameter characterizes the degree of nonuniformity in dark leakage currents, which can be a major source of fixed pattern noise. fill-factor a parameter that characterizes the optically active percentage of a pixel. in theory, it is the ratio of the actual qe of a pixel divided by the qe of a p hotodiode of equal area. in practice, it is never measured. grating monochromator an instrument that produces a monochroma tic beam of light. it typically consists of a broadband light source such as a tungsten lamp and a diffraction grating for selecting a particular wavelength. inl integral nonlinearity (for adcs) luminance light flux per unit area in photometric units (lux) ir infrared. ir light has wavelengths in the approximate range 750 nm to 1 mm. irradiance light flux per unit area in radiometric units (w/m 2 ) lag the persistence of signal after pixel reset when the irradiance changes from high to low values. in a video stream, lag appears as ?ghost? images that persist for one or more frames. lux photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m 2 = 1/683 w/m 2 ) nir near infrared. nir is part of the infrared portion of the spectrum and has wavelengths in the approximate range 750 nm to 1400 nm. pixel noise variation of pixel signals within a region of interest (roi). the roi typically is a rectangular portion of the pixel array and may be limited to a single color plane. photometric units units for light measurement that take into account human physiology. photon transfer measurement in which a bare imager (no extern al lens) is irradiated with uniform light from dark to saturation levels. typically the source is collimated, monochromatic 550 nm light. chapter 2 of j. janesick's book, scientific charge coupled devices, describes the technique in detail. pls parasitic light sensitivity. parasitic discharge of sampled information in pixels that have storage nodes. prnu photo-response nonuniformity. this parameter char acterizes the spread in response of pixels, which is a source of fpn under illumination. qe quantum efficiency. this parameter characterizes the effectiveness of a pixel in capturing photons and converting them into electrons. it is photon wavelength and pixel color dependent. radiometric units units for light measurement based on physics.
NOII4SM014KA rev. 7 | www.onsemi.com | page 24 of 25 read noise noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset the process by which a pixel photodiode or sense node is cleared of electrons. soft reset occurs when the reset transistor is operated below the threshold. hard reset occurs when the reset transistor is operated above threshold. reset noise noise due to variation in the reset level of a pixel. in 3t pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). in 4t pixel designs, reset noise can be removed with cds. responsivity the standard measure of p hotodiode performance (regardless of whet her it is in an imager or not). units are typically a/w and are dependent on the incident light wavelength. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. reverse saturation phenomenon in which the signal level decreases with increasing light intensity. it typically occurs at irradiance levels much higher than saturation, such as an image taken of the sun. roi region of interest. the area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. the roi can be the entire array or a small su bsection; it can be confined to a single color plane. row noise variation of row mean signal strengths. the hum an eye is sensitive to line patterns, so this noise is analyzed separately. sense node in 4t pixel designs, a capacitor used to convert charge into voltage. in 3t pixel designs it is the photodiode itself. sensitivity a measure of pixel perfor mance that characterizes the rise of the photodiode or sense node signal in volts upon illumination with light. units are typically v/(w/m 2 )/sec and are dependent on the incident light wavelength. sensitivity measurements are often taken with 550 nm incident light. at this wavelength, 1 683 lux = 1 w/m 2 ; the units of sensitivity are quoted in v/lux/sec. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. shot noise noise that arises from measurements of di scretised quanta (electrons or photons). it follows a poisson distribution with the strength of the noise increasing as the square root of the signal. spectral response the photon wavelength dependence of sensitivity or responsivity. snr signal-to-noise ratio. this number characterize s the ratio of the fundamental signal to the noise spectrum up to half the nyquist frequency. temporal noise noise that varies from frame to frame. in a video stream, temporal noise is visible as twinkling pixels. tint integration time.
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$$ NOII4SM014KA NOII4SM014KA/d document history page document title: NOII4SM014KA ibis4-140 00 14-megapixel cmos image sensor rev. ecn no. orig. of change submission date description of change ** 310213 sil see ecn initial release *a 428177 fvk see ecn layout converted figure 8 on page 11 updated storage and handling section added ibis4-14000-c added *b 642656 fpw see ecn ordering information update+package spec label. moved figure captions to the top of the figures and moved notes to the bottom of the page per new template. verified all cross-referencing. moved the specifications towards the back. corrected all variables on the master pages. *c 2220967 fpw see ecn eval kit section is removed. reference to defect spec is added. defect description for a rcca added. *d 2765859 nvea 09/18/09 updated ordering information table *e 3007128 nvea 08/13/10 updated ordering informat ion table. added acronyms, ordering code definition, and glossary sections. updated package diagram. *f 3048272 nvea 10/7/2010 updated ordering information table. pruned high grade version. removed reference to color mpn. edited spectral response curve . revised section on glass lid and ordering code definition . 7 n/a skw 06/03/2011 conversion to on semiconductor format and orderable part number changes.

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