View BT218KP20_8084604.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet l218_d august 25, 1999 bt218 20 msps monolithic cmos 8-bit flash video a/d converter the bt218 is an 8-bit flash a/d converter designed specifically for video digitizing applications. a flash converter topology is used with 256 high-speed comparators in parallel to digitize the analog input signal. flexible input ranges enable ntsc and ccir video signals to be digitized without requiring a video amplifier. the ttl-compatible output data and overflow are registered synchronously with the clock signal. the oe* three-states the d[7:0] outputs asynchronously to clock. the zero input is used to zero the comparators, while clamp allows dc restoration of an ac-coupled video signal (by forcing the vin input to the voltage on the level pin). the bt218 contains 256 high-speed comparators, a 255-to-8 encoder, an output register, and a resistor divider network. of the 256 comparators, 255 are used to digitize the analog signal; the additional comparator is used to generate the overflow bit. functional block diagram clamp zero circuit r e g i s t e r vref clock d[7:0] oe* gnd vaa 255 to 8 encoder ref? ref+ level vin zero 1.2 v 256 255 128 127 2 1 r/2 r/2 r r r r 218_001 distinguishing features ? 20 msps operation bt208 pin compatibility no video amplifier requirement 1/4 lsb typical dl error 1/2 lsb typical il error external zero and clamp control overflow output on-chip reference output enable control ttl compatibility +5 v cmos monolithic construction 24-pin 0.3" dip or 28-pin plcc packages typical power dissipation: 500 mw applications image processing image capture desktop publishing graphic art systems related products bt252 bt254 bt261
l218_d conexant information provided by conexant systems, inc. (conexant) is believed to be accurate and reliable. however, no responsibility i s assumed by conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use . no license is granted by implication or otherwise under any patent rights of conexant other than for circuitry embodied in conexan t products. conexant reserves the right to change circuitry at any time without notice. this document is subject to change withou t notice. conexant products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a conexant product can reasonably be expected to result in personal injury or death. conexant customers using or selling conexant products for use in such applications do so at their own risk and agree to fully indemnify conexant for any damages resulting f rom such improper use or sale. the trademarks ?conexant? and the conexant symbol are trademarks of conexant systems, inc. product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. all other marks mentioned herein are the property of their respective holders. ? 1999 conexant systems, inc. printed in u.s.a. all rights reserved reader response: conexant strives to produce quality documentation, and welcomes your feedback. please send comments and suggestions to conexant.tech.pubs@conexant.com . for technical questions, contact your local conexant sales office or field applications engineer. ordering information model number package speed ambient temperature range BT218KP20 24-pin 0.3? plastic dip 20 mhz 0 c to 70 c bt218kpj20 28-pin plastic j-lead 20 mhz 0 c to 70 c
l218_d conexant iii table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1.0 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 2.0 pc board layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 pc board considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 ground planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.3 power planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -2 2.4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 3.0 parametric information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 dc electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 ac electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3 package drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
table of contents bt218 20 msps monolithic cmos 8-bit flash video a/d converter iv conexant l218_d
bt218 list of figures 20 msps monolithic cmos 8-bit flash video a/d converter l218_d conexant v list of figures figure 1-1. pinout diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 figure 1-2. general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 figure 2-1. typical connection diagram (internal reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 figure 2-2. using an external reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 figure 3-1. input and output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 figure 3-2. bt218kpj output delay vs. capacitive loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 figure 3-3. 24-pin 0.300" plastic dip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 figure 3-4. 28-pin plastic j-lead (plcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
list of figures bt218 20 msps monolithic cmos 8-bit flash video a/d converter vi conexant l218_d
bt218 list of tables 20 msps monolithic cmos 8-bit flash video a/d converter l218_d conexant vii list of tables table 1-1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 table 1-2. output coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 table 2-1. typical parts (internal reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2-2. video signal tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 3-1. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -1 table 3-2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 table 3-3. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 table 3-4. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 table 3-5. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
list of tables bt218 20 msps monolithic cmos 8-bit flash video a/d converter viii conexant l218_d
l218_d conexant 1-1 1 1.0 circuit description 1.1 pin descriptions the bt218 is available as a 24-pin dip and as a 28-pin plastic leaded chip carrier (plcc). pin descriptions are listed in table 1-1 . both packages are illustrated in figure 1-1 . table 1-1. pin descriptions (1 of 2) pin name description d[7:0] data outputs (ttl compatible). d[0] is the least significant data bit. these outputs are latched and output following the second rising edge of clock. coding is binary. for optimum performance, d[7:0] should have minimal loading. if a large capacitive load is being driven, an external buffer is recommended. oe* output enable control input (ttl compatible). negating oe* three-states d[7:0] asynchronously. the overflow output is not affected by the state of oe*. overflow overflow output (ttl compatible). overflow is latched and output following the second rising edge of clock. oe* does not affect the overflow output signal. overflow is not available on the dip package. clock clock input (ttl compatible). it is recommended that this pin be driven by a dedicated ttl buffer to minimize sampling jitter. ref+ top of ladder voltage reference (voltage input). ref+ sets the vin voltage level that corresponds to $ff on the d[7:0] outputs. all ref+ pins must be connected together as close to the device as possible. for noise immunity reasons, a decoupling capacitor is not recommended on ref+. ref? bottom of ladder voltage reference (voltage input). typically, this input is connected to gnd. ref? sets the vin voltage level that corresponds to $00 on the d[7:0] outputs. all ref? pins must be connected together as close to the device as possible.
1.0 circuit description bt218 1.1 pin descriptions 20 msps monolithic cmos 8-bit flash video a/d converter 1-2 conexant l218_d r/2 midtap of reference ladder (voltage output). r/2 is not available on the dip package. if not used, this pin should remain floating. if used, it should be buffered by a voltage follower. for noise immunity reasons, a decoupling capacitor is not recommended on r/2. vin analog signal inputs (voltage input). all vin pins must be connected together as close to the device as possible. zero/clamp zeroing control input (ttl compatible). while zero is a logical one, the comparators are zeroed and d[7:0] output data is held to the current state. zero is latched on the rising edge of clock. on the 24-pin dip package, zero and clamp share the same pin; hence, zeroing and clamping occur simultaneously. clamp control input (ttl compatible). while clamp is a logical one, the vin inputs are forced to the voltage level on the level pin to perform dc restoration of an ac-coupled video signal. clamp is asynchronous to clock. on the 24-pin dip package, zero and clamp share the same pin; hence, zero and clamp are asserted simultaneously. level level control input (voltage input). this input is used to specify what voltage level to use for clamping while clamp is a logical one. level is used only to dc restore ac-coupled video signals. in applications where the video signal is dc-coupled to vin, the level pin should float or be connected to vin. vref voltage reference output pin. this pin provides a 1.2 v (typical) output. a decoupling capacitor is not recommended on vref. vaa analog power. all vaa pins must be connected together on the same pcb plane and as close to the device as possible to prevent latchup. a 0.1 f ceramic capacitor should be connected between each group of vaa pins and gnd, as close to the device as possible. gnd ground. all gnd pins must be connected together on the same pcb plane and as close to the device as possible to prevent latchup. table 1-1. pin descriptions (2 of 2) pin name description
bt218 1.0 circuit description 20 msps monolithic cmos 8-bit flash video a/d converter 1.1 pin descriptions l218_d conexant 1-3 figure 1-1. pinout diagrams note(s): n/c pins are reserved and must remain floating. vin vin ref + vref vaa vaa gnd gnd n/c ref ? level zero (clamp) d[0] d[1] d[2] d[3] vaa gnd oe* clock d[7] d[6] d[5] d[4] d[6] d[5] d[4] zero clamp level ref ? d[3] overflow vaa gnd oe* clock d[7] d[2] d[1] d[0] vin ref + ref + vref n/c r/2 n/c vaa gnd n/c ref ? 28-pin plastic j-lead (plcc) package 24-pin 0.3 ? dip package 218_002 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 18 17 16 15 14 13 12 25 24 23 22 21 20 19 26 27 1 2 3 4 5 5 6 7 8 9 10 11
1.0 circuit description bt218 1.2 general operation 20 msps monolithic cmos 8-bit flash video a/d converter 1-4 conexant l218_d 1.2 general operation the bt218 converts an analog signal in the range of ref? vin ref+, generating a binary number from $00 to $ff, and an overflow output (see table 1-2 ). the values of ref+ and ref? are flexible to enable various video signals to be digitized without requiring a video amplifier. refer to the parametric information and application information sections for suggested configurations. figure 1-2 illustrates the input and output timing of the bt218. the sample is taken following the falling edge of clock. the binary data and overflow are registered and output onto the d[7:0] and overflow pins on the second rising edge of clock. table 1-2. output coding example vin (v) (1) overflow d[7:0] oe* >0.998 1 $ff 0 0.996 0 $ff 0 0.992 0 $fe 0 ::: : 0.500 0 $81 0 0.496 0 $80 0 0.492 0 $7f 0 ::: : 0.004 0 $01 0 <0.002 0 $00 0 3?state 1 note(s): (1) with ref+ = 1.000 v and ref? = 0.000 v. ideal center values. 1lsb = 3.9063 mv.
bt218 1.0 circuit description 20 msps monolithic cmos 8-bit flash video a/d converter 1.2 general operation l218_d conexant 1-5 comparator zeroing the zero input is used to periodically zero the comparators. the comparators have an initial threshold mismatch caused by manufacturing tolerances. zeroing charges capacitors in the comparators that offset this threshold mismatch. but because capacitors discharge, the comparators must be periodically zeroed. while zero is a logical one, the comparators are zeroed. during zero cycles, d[7:0] and overflow are not updated. they retain the data loaded before the zero cycle. input signal clamping clamp and level are used only in applications where the video signal is ac coupled to vin. while clamp is a logical one, the vin input is forced to the voltage level of the level pin to dc restore the video signal. in applications where the video signal is dc coupled to vin, the level pin should float or be connected to vin, or clamp should always be a logical zero (on the 28-pin plcc package only). figure 1-2. general operation data n ? 1 data n ? 2 data n data n + 1 sample n + 1 sample n clock vin d[7:0] overflow 218_003
1.0 circuit description bt218 1.2 general operation 20 msps monolithic cmos 8-bit flash video a/d converter 1-6 conexant l218_d
l218_d conexant 2-1 2 2.0 pc board layout considerations 2.1 pc board considerations for optimum performance, before pcb layout is begun, study the cmos digitizer layout examples in the bt208, bt251, or bt253 evaluation module operation and measurements, application notes an-13, 14, and 15, respectively. these application notes can be found in the conexant applications handbook. the layout should be optimized for lowest noise on the bt218 power and ground lines by shielding the digital inputs and providing good decoupling. the lead length between groups of vaa and gnd pins should be as short as possible to minimize inductive ringing. 2.2 ground planes use a single ground plane covering both digital and analog logic.
2.0 pc board layout considerations bt218 2.3 power planes 20 msps monolithic cmos 8-bit flash video a/d converter 2-2 conexant l218_d 2.3 power planes the bt218 and any associated analog circuitry should have their own power plane, referred to as the analog power plane. this power plane should be connected to the regular pcb power plane (vcc) at a single point through a ferrite bead, as illustrated in figure 2-1 . table 2-1 lists the parts. this bead should be located within 3 inches of the bt218. the regular pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all bt218 power pins, any voltage reference circuitry, and any input amplifiers. it is important that the regular pcb power plane does not overlay the analog power plane. figure 2-1. typical connection diagram (internal reference) vaa gnd, ref ? c4 c1 10 0.1 0.01 c3 c2 0.1 +5 v (vcc) ground l1 use only if ac coupled to video signal 200 ref+ vref 50 75 video 0.1 vin bt218 218_004 +
bt218 2.0 pc board layout considerations 20 msps monolithic cmos 8-bit flash video a/d converter 2.3 power planes l218_d conexant 2-3 supply decoupling the bypass capacitors should be installed with the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. each group of vaa and gnd pins should have a 0.1 mf ceramic chip capacitor located as close as possible to the device pins. the capacitors should be connected directly to the vaa and gnd pins with short, wide traces. signal interconnect the digital signals of the bt218 must be isolated as much as possible from the analog inputs and other analog circuitry to prevent crosstalk. also, these digital signals should not overlay the analog power plane. termination resistors for the digital signals should be connected to the digital pcb power and ground planes. table 2-1. typical parts (internal reference) location description vendor part number c1, c3 0.1 f ceramic capacitor erie rpe112z5u104m50v c2 10 f capacitor mallory csr13g106km c4 0.01 f ceramic chip capacitor avx 12102t103qa1018 l1 ferrite bead fair-rite 2743001111 note(s): the vendor numbers above are listed only as a guide. substitution of devices with similar characteristics will not affect the performance of the bt218.
2.0 pc board layout considerations bt218 2.4 application information 20 msps monolithic cmos 8-bit flash video a/d converter 2-4 conexant l218_d 2.4 application information using the internal reference the bt218 has a 1.2 v on-chip reference available (vref). vref may be divided down and used to drive the ref+ input, as illustrated in figure 2-1 . the 200 w potentiometer serves three purposes: 1. to allow adjustment for different video signal levels, 2. to allow for video level tolerances, and 3. to adjust for tolerance of the internal reference. vref should supply at least 6 ma of current to maintain voltage stability over temperature. thus, vref should drive a resistive load between 90 and 240 w. using an external reference figure 2-2 illustrates the use of a 1.2 v lm385 and a tlc272 to generate a 0?1.2 v reference for applications that require a better reference tempco than the internal reference can supply. supply decoupling of the op-amp is not shown. any standard op-amp may be used that can operate from a single +5 v supply. to prevent ringing in the tlc272 from clock kickback, a 100 w resistor is recommended, as illustrated in figure 2-2 . if an op-amp is chosen that has a better transient response than the tlc272, the resistor may not be needed. this circuit may also be used to drive the ref? if a value other than ground is desired. because single-supply op-amps are limited, ref? may not be set below ~300 mv. to drive ref? to true 0 v in the op-amp configuration, a dual supply must be used. extreme care must be used in power sequencing to ensure all positive supplies (op-amp and a/d) power on before the negative supply. this will prevent latchup of the a/d. figure 2-2. using an external reference tlc272 vaa 100 0.1 ref+ bt218 ? + 2k 1k vaa lm385 ? 1.2 218_005
bt218 2.0 pc board layout considerations 20 msps monolithic cmos 8-bit flash video a/d converter 2.4 application information l218_d conexant 2-5 ac-coupled vs. dc-coupled input the bt218 may be either ac or dc coupled to the video signal, as illustrated in figure 2-1 . the 75 ? resistor to ground provides the typical 75 ? termination required by video signals. the 50 ? resistor provides isolation from any clock kick-back noise on vin and prevents it from being coupled onto the video signal. if the bt218 is dc-coupled to the video signal, the 0.1 mf capacitor is not used and clamp should be grounded. zeroing unlike many cmos a/d converters requiring the comparators to be zeroed every clock cycle, the comparators in the bt218 are designed to be only periodically zeroed. it is convenient to assert zero during each horizontal blanking interval. before the bt218 is used after a power-up condition, zero must be a logical one for at least 1000 clock cycles (cumulative) to initialize the comparators to the rated linearity. in normal video applications this will be transparent because of the number of horizontal scan lines that will have occurred before the bt218 was used. while the recommended zeroing interval is maintained, the bt218 will meet linearity specifications. the longer the time between zeroing intervals, the more the linearity error increases. input ranges table 2-2 lists some common video signal amplitudes. if a signal may possibly exceed 1.2 v, it should be attenuated (with a resistor divider network) so as not to exceed the 1.2 v input range. when a full-scale range less than 0.7 v is used to digitize, the bt218?s integral linearity errors are constant in terms of voltage, regardless of the value of the reference voltage. lower reference voltages will, therefore, produce larger integral linearity errors in terms of lsbs. for example, with a reference difference of 0.6 v, 0.6 v video signals may be digitized. however, the integral linearity (il) error will increase to about 1.8 lsb, and the snr will be about 40 db. with a reference difference of 0.5 v, 0.5 v video signals may be digitized with an il error of about 2 lsb, and the snr will be approximately 39 db. output noise although the bt218 does exhibit some output noise for a dc input, the output noise remains relatively constant for any input bandwidth (see the ac characteristics section). competitive a/d converters have no noise for a dc input; however, the output noise increases greatly as the input bandwidth and clock rate increase. pc board sockets if a socket is required, a low-profile socket is recommended, such as amp part number 641746?2 for the plcc package. table 2-2. video signal tolerances video standard nominal amplitude worst case amplitudes rs?170 w/o sync 1.0 v black?white 0.9?1.1 v rs?170 w/o sync 1.4 v sync?white 1.2?1.6 v rs?170 w/sync 1.2 v sync?white 1.0?1.4 v rs?170 w/sync 0.7 v black?white 0.6?0.85 v
2.0 pc board layout considerations bt218 2.4 application information 20 msps monolithic cmos 8-bit flash video a/d converter 2-6 conexant l218_d esd and latchup considerations correct esd-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat leaky inputs. all logic inputs should be held low until power to the device has settled to the specified tolerance. power decoupling networks with large time constants should be avoided. they could delay vaa power to the device. ferrite beads must be used only for analog power vaa decoupling. inductors can cause a power supply time constant delay that induces latchup. latchup can be prevented by ensuring that all vaa pins are at the same potential and that the vaa supply voltage is applied before the signal pin voltages. the correct power-up sequence ensures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 v.
l218_d conexant 3-1 3 3.0 parametric information 3.1 dc electrical parameters table 3-1. recommended operating conditions parameters symbol min typ max units power supply vaa 4.5 5.00 5.5 v voltage references top ref+ 0.7 1 2.0 v bottom ref? 0 0 1.3 v difference (top-bottom) ? 0.7 1 1.2 v input amplitude range ? 0.7 1 1.2 v analog input range ? ? ref? to ref+ ? v level input voltage ? gnd ? 0.5 ref? ref+ v time between zeroing intervals ? ? 60 150 s ambient operating temperature ta 0 ? +70 c
3.0 parametric information bt218 3.1 dc electrical parameters 20 msps monolithic cmos 8-bit flash video a/d converter 3-2 conexant l218_d table 3-2. absolute maximum ratings parameters symbol min typ max units vaa (measured to gnd) ? ? ? 7.0 v voltage on any signal pin (1) ? gnd ? 0.5 ? vaa + 0.5 v analog input voltage ? gnd ? 0.5 ? vaa + 0.5 v r/2 output current ???25a ambient operating temperature ta ?55 ? +125 c storage temperature ts ?65 ? +150 c junction temperature tj ? ? +150 c soldering temperature (5 seconds, ?? from pin) tsol ? ? 260 c vapor phase soldering (1 minute) tvsol ? ? 220 c note(s): (1) this device employs high-impedance cmos devices on all signal pins. it should be handled as an esd-sensitive device. voltage on any signal pin that exceeds the power supply voltage by more than +0.5 v can induce destructive latchup. 2. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
bt218 3.0 parametric information 20 msps monolithic cmos 8-bit flash video a/d converter 3.1 dc electrical parameters l218_d conexant 3-3 table 3-3. dc characteristics (1 of 2) parameters symbol min typ max units resolution ? 8 8 8 bits accuracy integral linearity error (1) il ? 0.5 1 lsb differential linearity error dl ? 0.25 1 lsb output noise (2) ??1?lsb coding no missing codes ? ? guaranteed ? binary vin analog inputs (3) clamp = 0 input current (leakage) ib ? ? 1 a input capacitance cain ? 35 ? pf clamp = 1 input impedance rin ? 50 ? ? ref+ reference input input impedance rref+ ? 500 ? ? digital inputs input high voltage vih 2.0 ? ? v input low voltage vil ? ? 0.8 v input high current (vin = 2.4 v) iih ? ? 1 a input low current (vin = 0.4 v) iil ? ? ?1 a input capacitance cin ? 10 ? pf digital outputs output high voltage (ioh = ?50 a) voh 2.4 ? ? v output low voltage (iol = 1.6 ma) vol ? ? 0.4 v three-state current ioz ? ? 10 a output capacitance cout ? ? 10 pf
3.0 parametric information bt218 3.1 dc electrical parameters 20 msps monolithic cmos 8-bit flash video a/d converter 3-4 conexant l218_d internal voltage reference vref ? 1.2 ? v regulation (at 6 ma) ? 5 ? mv output current iref ? ? 15 ma note(s): (1) using best-fit linearity (offset independent). (2) clock duty cycle adjusted for minimum output noise for a dc input. for a dc input, output noise may increase if clock duty cycle is not adjusted. (3) level = gnd. 4. test conditions (unless otherwise specified): ?recommended operating conditions? with ref+ = 1 v and ref? = gnd. ref? vin ref+, and level = float. typical values are based on nominal temperature, i.e. room temperature, and nominal voltage, i.e. 5 v. table 3-3. dc characteristics (2 of 2) parameters symbol min typ max units
bt218 3.0 parametric information 20 msps monolithic cmos 8-bit flash video a/d converter 3.2 ac electrical parameters l218_d conexant 3-5 3.2 ac electrical parameters table 3-4. ac characteristics (1 of 3) parameters symbol min typ max units conversion rate fs ? ? 20 mhz clock cycle time ( figure 3-1 )150??ns clock low time 2 20 ? ? ns clock high time 3 20 ? ? ns data output delay time ( figure 3-2 ) 4 ??40ns data output hold time 5 9 ? ? ns oe* asserted to d[7:0] valid 6 ? ? 25 ns oe* negated to d[7:0] 3-stated 7 ? ? 25 ns zero setup time 8 0 ? ? ns zero hold time 9 20 ? ? ns zero, clamp high time (1) ?1??clock aperture delay 10 ? 10 ? ns aperture jitter ? ? 50 ? ps full power input bandwidth bw ? ? fs/2 mhz transient response (2) ?? 1 ?clock overload recovery (3) ?? 1 ?clock zero recovery time (4) ?? 1 ?clock rms signal-to-noise ratio snr fin = 4.20 mhz, fs = 12.27 mhz ? ? 44 ? db fin = 4.20 mhz, fs = 13.50 mhz ? ? 44 ? db fin = 4.20 mhz, fs = 14.32 mhz ? ? 44 ? db fin = 5.75 mhz, fs = 13.50 mhz ? ? 43 ? db fin = 5.75 mhz, fs = 14.75 mhz ? ? 43 ? db fin = 5.75 mhz, fs = 17.72 mhz ? ? 43 ? db fin = 10.0 mhz, fs = 20.00 mhz ? ? 39 ? db
3.0 parametric information bt218 3.2 ac electrical parameters 20 msps monolithic cmos 8-bit flash video a/d converter 3-6 conexant l218_d rms signal and distortion-to-noise ratio sinad fin = 4.20 mhz, fs = 12.27 mhz ? ? 42 ? db fin = 4.20 mhz, fs = 13.50 mhz ? ? 42 ? db fin = 4.20 mhz, fs = 14.32 mhz ? ? 42 ? db fin = 5.75 mhz, fs = 13.50 mhz ? ? 41 ? db fin = 5.75 mhz, fs = 14.75 mhz ? ? 41 ? db fin = 5.75 mhz, fs = 17.72 mhz ? ? 41 ? db fin = 10.0 mhz, fs = 20.00 mhz ? ? 37 ? db total harmonic distortion thd fin = 4.20 mhz, fs = 12.27 mhz ? ? 47 ? db fin = 4.20 mhz, fs = 13.50 mhz ? ? 47 ? db fin = 4.20 mhz, fs = 14.32 mhz ? ? 47 ? db fin = 5.75 mhz, fs = 13.50 mhz ? ? 47 ? db fin = 5.75 mhz, fs = 14.75 mhz ? ? 47 ? db fin = 5.75 mhz, fs = 17.72 mhz ? ? 47 ? db fin = 10.0 mhz, fs = 20.00 mhz ? ? 44 ? db spurious free dynamic range sfdr fin = 4.20 mhz, fs = 12.27 mhz ? ? 50 ? db fin = 4.20 mhz, fs = 13.50 mhz ? ? 50 ? db fin = 4.20 mhz, fs = 14.32 mhz ? ? 50 ? db fin = 5.75 mhz, fs = 13.50 mhz ? ? 50 ? db fin = 5.75 mhz, fs = 14.75 mhz ? ? 50 ? db fin = 5.75 mhz, fs = 17.72 mhz ? ? 50 ? db fin = 10.0 mhz, fs = 20.00 mhz ? ? 47 ? db table 3-4. ac characteristics (2 of 3) parameters symbol min typ max units
bt218 3.0 parametric information 20 msps monolithic cmos 8-bit flash video a/d converter 3.2 ac electrical parameters l218_d conexant 3-7 differential gain error (5) dg ? 2 ? % differential phase error (5) dp ? 1 ? degree supply current (excluding ref+) (6) iaa ? 100 160 ma pipeline delay (7) ?222clocks test conditions (unless otherwise specified): ?recommended operating conditions? with ref+ = 1 v and ref? = gnd. ref? vin ref+ and , level = float. ttl input values are 0?3 v with input rise and fall times 4 ns, measured between the 10 percent and 90 percent points. timing reference points at 1.5 v for digital inputs and outputs. d0?d7 and overflow output load 40 pf. typical values are based on nomimal temperature, i.e. room temperature, and nominal voltage, i.e., 5 v. note(s): (1) number of clock cycles zero is a logical one does not affect linearity. for best performance, zero should be a logical one for an odd number of clock cycles. (2) for full-scale step, input, full accuracy attained in specified time. (3) time to recover to full accuracy after a >1.2 v input signal. (4) time to recover to full accuracy following a zero cycle. (5) 4x ntsc subcarrier, unlocked. (6) iaa (typ) at vaa = 5.0 v, fin = 4.2 mhz, and fs = 14.32 mhz, t case = ambient. iaa (max) at vaa = 5.5 v, fin = 10 mhz, and fs = 20 mhz, t case = 0 c. (7) pipeline delay is defined as discrete clock period in addition to the half-cycle analog sampling delay. table 3-4. ac characteristics (3 of 3) parameters symbol min typ max units figure 3-1. input and output timing zero sample n 5 2 8 9 1 3 7 6 10 4 sample n + 1 data n ? 2 data n ? 1 data n data n (zero data) clock vin d[7:0] overflow oe* 218_006
3.0 parametric information bt218 3.2 ac electrical parameters 20 msps monolithic cmos 8-bit flash video a/d converter 3-8 conexant l218_d figure 3-2. bt218kpj output delay vs. capacitive loading 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 0 5 10 15 20 25 30 35 40 45 50 55 capacitance (pf) delay (ns) 218_007
bt218 3.0 parametric information 20 msps monolithic cmos 8-bit flash video a/d converter 3.3 package drawings l218_d conexant 3-9 3.3 package drawings figure 3-3. 24-pin 0.300" plastic dip 0.06 [1.524] r 1.210 [30.73] max 24 1 13 12 0.290 - 0.330 [7.37 - 8.38] 0.009 - 0.015 [0.228 - 0.381] 0.350 [8.89] nom 0.015 [0.381] min 0.014 - 0.028 [0.36 - 0.58] 0.250 - 0.300 [6.35 - 7.62] 0.100 [2.54] typ 0.075 [1.905] 0.125 [3.175] min 0.200 max [5.08] 218_008 figure 3-4. 28-pin plastic j-lead (plcc) 218_009 pin no. 1 pin no. 1 0.045 x 45? [1.143] 0.045 x 45? [1.143] 0.485 - 0.495 [12.32 - 12.57] sq 0.450 - 0.456 [11.43 - 11.58] sq pin no. 1 ident 0.165 - 0.180 [4.19 - 4.57] 0.026 - 0.032 [0.661 - 0.812] 0.090 - 0.120 [2.29 - 3.04] 0.390 - 0.430 [9.91 - 10.92] 0.013 - 0.021 [0.331 - 0.533] 0.050 [1.27] typ 0.300 ref [7.62]
3.0 parametric information bt218 3.4 revision history 20 msps monolithic cmos 8-bit flash video a/d converter 3-10 conexant l218_d 3.4 revision history table 3-5. revision history revision change from previous revision b changes to figure 2-2 . new configuration for the external reference voltage. c deleted 30 mhz device information. revised pc board layout considerations. revised and expanded dc characteristics. added figure 3-2 . datasheet status changed to preliminary. d obsolete evm module.

further information literature@conexant.com 1-800-854-8099 (north america) 33-14-906-3980 (international) web site www.conexant.com world headquarters conexant systems, inc. 4311 jamboree road p. o. box c newport beach, ca 92658-8902 phone: (949) 483-4600 fax: (949) 483-6375 u.s. florida/south america phone: (727) 799-8406 fax: (727) 799-8306 u.s. los angeles phone: (805) 376-0559 fax: (805) 376-8180 u.s. mid-atlantic phone: (215) 244-6784 fax: (215) 244-9292 u.s. north central phone: (630) 773-3454 fax: (630) 773-3907 u.s. northeast phone: (978) 692-7660 fax: (978) 692-8185 u.s. northwest/pacific west phone: (408) 249-9696 fax: (408) 249-7113 u . s. south central phone: (972) 733-0723 fax: (972) 407-0639 u.s. southeast phone: (919) 858-9110 fax: (919) 858-8669 u.s. southwest phone: (949) 483-9119 fax: (949) 483-9090 apac headquarters conexant systems singapore, pte. ltd. 1 kim seng promenade great world city #09-01 east tower singapore 237994 phone: (65) 737 7355 fax: (65) 737 9077 australia phone: (61 2) 9869 4088 fax: (61 2) 9869 4077 china phone: (86 2) 6361 2515 fax: (86 2) 6361 2516 hong kong phone: (852) 2827 0181 fax: (852) 2827 6488 india phone: (91 11) 692 4780 fax: (91 11) 692 4712 korea phone: (82 2) 565 2880 fax: (82 2) 565 1440 phone: (82 53) 745 2880 fax: (82 53) 745 1440 europe headquarters conexant systems france les taissounieres b1 1681 route des dolines bp 283 06905 sophia antipolis cedex france phone: (33 1) 41 44 36 50 fax: (33 4) 93 00 33 03 europe central phone: (49 89) 829 1320 fax: (49 89) 834 2734 europe mediterranean phone: (39 02) 9317 9911 fax: (39 02) 9317 9913 europe north phone: (44 1344) 486 444 fax: (44 1344) 486 555 europe south phone: (33 1) 41 44 36 50 fax: (33 1) 41 44 36 90 middle east headquarters conexant systems commercial (israel) ltd. p. o. box 12660 herzlia 46733, israel phone: (972 9) 952 4064 fax: (972 9) 951 3924 japan headquarters conexant systems japan co., ltd. shimomoto building 1-46-3 hatsudai, shibuya-ku, tokyo 151-0061 japan phone: (81 3) 5371-1567 fax: (81 3) 5371-1501 taiwan headquarters conexant systems, taiwan co., ltd. room 2808 international trade building 333 keelung road, section 1 taipei 110, taiwan, roc phone: (886 2) 2720 0282 fax: (886 2) 2757 6760 0 . 0 s a l es offi ces

▲Up To Search▲

Price & Availability of BT218KP20

	To Download BT218KP20 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .