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1 p i 3v d p 411l s a pin configuration (48-pin tqfn) 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 gnd vdd in_d1- in_d1+ in_d2- in_d2+ gnd in_d3- in_d3+ in_d4- in_d4+ vdd gnd vdd out_d1- out_d1+ out_d2- out_d2+ gnd out_d3- out_d3+ out_d4- out_d4+ vdd gnd vdd nc sqsel ddc_en gnd hpd_sink sda_sink scl_sink vdd oe# gnd gnd sr1 vdd sr0 gnd nc hpd_source sda_source scl_source vdd gnd ddcbsel gnd description pericom semiconductors PI3VDP411LSA provides the ability to use a dual-mode displayport? transmitter in hdmi? mode. tis fexibility provides the user a choice of how to connect to their favorite display. all signal paths accept ac coupled video signals. te PI3VDP411LSA converts this ac coupled signal into an hdmi rev 1.3 compliant signal with proper signal swing. tis conversion is automatic and transparent to the user. output squelch function is provided for each channel. when out - put channel is enable (oe#=0) and operating, that tmds pixel clock input signal determines whether the output is enabled. when no tmds pixel clock is present, tmds output channel will be disabled. te PI3VDP411LSA supports up to 2.5gbps, which provides 12- bits of color depth per channel, as indicated in hdmi rev 1.3. features ? ? converts low-swing ac coupled diferential input to hdmi? rev 1.3 compliant open-drain current steering rx terminated diferential output ? ? hdmi level shifing operation up to 2.5gbps per lane (250mhz pixel clock) ? ? integrated 50-ohm termination resistors for ac-coupled diferential inputs. ? ? provide output squelch function to turn of tmds common mode output bufer when tmds clock is not present ? ? enable/disable feature to turn of tmds outputs to enter low-power state. ? ? output slew rate control on tmds outputs to minimize emi ? ? integrated active / passive ddc level shifers (3.3v source to 5v sink) ? ? transparent operation: no re-timing or confguration required ? ? level shifer for hpd signal from hdmi/dvi connector ? ? integrated pull-down on hpd_sink input guarantees "input low" when no display is plugged in ? ? 3.3v power supply required ? ? tmds output enable control ? ? esd protection on all i/o pins 4kv hbm 8kv contact esd protection on the following pins out_dx sda_sink, scl_sink hpd_sink ? ? packaging (pb-free & green available): 48 tqfn, 7mm 7mm (zbe) dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) www.pericom.com ps9059a 07/28/12 12-0236
2 block diagram oe# i n_d4/3/2/1+ in_d4/3/2/1- out_d4/3/2/1+ out_d4/3/2/1- 50? 50? 0v rx hpd_source 100k? hpd_sink hpd sr1/0 ddc_en (0v to 3.3v) ddcbsel sqsel control logic sda_sink scl_sink sda_source scl_source www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
3 pin description pin name i/o ty pe descriptions 1, 5, 12, 18, 24, 27, 31, 36, 37, 43 gnd power ground 2, 11, 15, 21, 26, 33, 40, 46 v dd power power, 3.3v 10% 3, 4 sr0, sr1 i slew rate control. acceptable connections to srx pin are: resistor to 3.3v or short to gnd. (internal 200k pull-low) 6, 35 nc o no connect 7 hpd_source o hpd_source: 0v to 3.3v (nominal) output signal. hpd_sink input can be as high as 5v and then hpd_source will output no higher than 3.3v. 8 sda_source i/o 3.3v ddc data i/o. pulled up by external termination to 3.3v. ddc_en ddcbsel ddc level shifer type low x disable ddc level shifer high low passive level shifer enable connected to sda_sink through voltage- limiting integrated nmos passgate high high active level shifer enable connected to sda_sink through bi-direc - tion bufer 9 scl_source i/o 3.3v ddc data i/o. pulled up by external termination to 3.3v. ddc_en ddcbsel ddc level shifer type low x disable ddc level shifer high low passive level shifer enable connected to scl_sink through voltage- limiting integrated nmos passgate high high active level shifer enable connected to scl_sink through bi-direction bufer 10 ddcbsel i active ddc level shifer enable pin. (internal 200k pull-low) ddcbsel ddc path low (0v) passive ddc level shifer high (3.3v) active ddc level shifer 13 out_d4+ o hdmi 1.3 compliant tmds output. out_d4+ makes a diferential output signal with out_d4-. 14 out_d4- o hdmi 1.3 compliant tmds output. out_d4- makes a diferential output signal with out_d4+ 16 out_d3+ o hdmi 1.3 compliant tmds output. out_d3+ makes a diferential output signal with out_d3-. 17 out_d3- o hdmi 1.3 compliant tmds output. out_d3- makes a diferential output signal with out_d3+ www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
4 pin name i/o ty pe descriptions 19 out_d2+ o hdmi 1.3 compliant tmds output. out_d2+ makes a diferential output signal with out_d2-. 20 out_d2- o hdmi 1.3 compliant tmds output. out_d2- makes a diferential output signal with out_d2+ 22 out_d1+ o hdmi 1.3 compliant tmds output. out_d1+ makes a diferential output signal with out_d1-. 23 out_d1- o hdmi 1.3 compliant tmds output. out_d1- makes a diferential output signal with out_d1+ 25 oe# i enable for level shifer path. oe# in_d termination out_d outputs 1 > 100k high-z 0 50 active 28 scl_sink i/o 5v ddc clock i/o. pulled up by external termination to 5v. ddc_en ddcbsel ddc level shifer type low x disable ddc level shifer high low passive level shifer enable connected to scl_source through voltage- limiting integrated nmos passgate high high active level shifer enable connected to scl_source through bi- direction bufer 29 sda_sink i/o 5v ddc data i/o. pulled up by external termination to 5v. ddc_en ddcbsel ddc level shifer type low x disable ddc level shifer high low passive level shifer enable connected to sda_source through voltage- limiting integrated nmos passgate high high active level shifer enable connected to sda_source through bi- direction bufer 30 hpd_sink i low frequency, 0v to 5v (nominal) input signal. tis signal comes from the tmds connector. voltage high indicates plugged state; voltage low indicated unplugged. hpd_sink is pulled down by an integrated 100k ohm pull-down resistor. 32 ddc_en i enables ddc level shifer path ddc_en passgate low (0v) disable high (3.3v) enable www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
5 pin name i/o ty pe descriptions 34 sqsel i tmds clock detection setting pulled up by external termination to 3.3v or short to gnd. sqsel clock monitor pin 0 device monitor hdmi pixel clock on pin38/39 (channel in_d1 ) 1 device monitor dvi pixel clock on pin 47/48 (channel in_d4 ) 38 in_d1- i low-swing dif input from dp tx outputs. in_d1- makes a diferential pair wit h in_d1+. 39 in_d1+ i low-swing dif input from dp tx outputs. in_d1+ makes a diferential pair with in_d1-. 41 in_d2- i low-swing dif input from dp tx outputs. in_d2- makes a diferential pair with in_d2+. 42 in_d2+ i low-swing dif input from dp tx outputs. in_d2+ makes a diferential pair with in_d2-. 44 in_d3- i low-swing dif input from dp tx outputs. in_d3- makes a diferential pair with in_d3+. 45 in_d3+ i low-swing dif input from dp tx outputs. in_d3+ makes a diferential pair with in_d3-. 47 in_d4- i low-swing dif input from dp tx outputs. in_d4- makes a diferential pair with in_d4+. 48 in_d4+ i low-swing dif input from dp tx outputs. in_d4+ makes a diferential pair with in_d4-. www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
6 truth table (slew rate control function) sr1 sr0 rise/fall time (typ) 1 1 140ps 1 0 130ps 0 1 120ps 0 0 110ps table 1: oe pin description oe# device state comments asserted (low voltage) diferential input bufers and output bufers enabled. input impedance = 50 normal functioning state for in_d to out_d level shifing function. unasserted (high voltage) low-power state. diferential input bufers and termination are disabled. diferential inputs are in a high impedance state. out_d level-shifing outputs are disabled. out_d level-shifing outputs are in high impedance state. internal bias currents are turned of. intended for lowest power condition when: no display is plugged in or te level shifed data path is disabled hpd_sink input and hpd_source output are not afected by oe# scl_ source, scl_sink, sda_source and sda_sink signals and functions are not afected by oe# test setup condition v dd = 3.3v, ambient temperature 25c rise/fall time is from 20% to 80% on rising/falling edge date rate: 620 mbps input: 1v diferential peak-to-peak clock pattern equalization : 3db www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
7 absolute maximum ratings (over operating free-air temperature range) item rating supply voltage to ground potential 5.5v all inputs and outputs -0.5v to v dd +0.5v ambient operating temperature -40 to +85c storage temperature -65 to +150c junction temperature 150c soldering temperature 260c stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. electrical characteristics table: power supplies and temperature range symbol parameter min typ max units comments v dd 3.3v power supply 3.0 3.3 3.6 v i cc max current 100 ma i cc_squelch supply current when no tmds clock present 8 ma i ccq standby current 2 ma oe# = high t case case temperature range for operation with spec. -40 85 celsius () www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
8 table: diferential input characteristics forin_dx signals symbol parameter min typ max units comments t bit ui, unit interval 360 ps t bit is determined by the display mode. nominal bit rate ranges from 250mbps to 2.5gbps per lane. nominal tbit at 2.5 gbps = 400 ps. 360ps = 400ps- 10% v rx_diff input diferential volt - age level 0.175 1.200 v see note 1 below t rx_eye minimum eye width at in_d input pair 0.8 tbit v cm-acp-p ac peak common mode input voltage 100 mv see note 2 below z rx_dc 40 50 60 required in_d+ as well as in_d- dc impedance (50 20% tolerance). z rx-bias 0 2.0 v intended to limit power-up stress on chipset's pcie output bufers. z rx_high-z 100 k diferential inputs must be in a high impedance state when oe# is high. 1. v rx-diff = 2x|v rx-d- - v rx-d- | applies to in_dx signals 2. v cm-ac-p-p = |v rx-d - - v rx-d -|/2 - v rx-cm-dc v rx-cm-dc = dc(avg) of |v rx-d+ + v rx-d -|/2 v cm-ac-p-p includes all frequencies above 30 khz. tmds outputs te level shifer's tmds outputs are required to meet hdmi 1.3 specifcations. te hdmi 1.3 specifcation is assumed to be the correct reference in instances where this document conficts with the hdmi 1.3 specifcation. www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
9 table 2: diferential output characteristics for tmds_out signals symbol parameter min typ max units comments v h single-ended high level output voltage v dd -10mv v dd v dd +10mv v v dd is the dc termination voltage in the hdmi or dvi sink. v dd is nominally 3.3v v l single-ended low level output voltage v dd - 60 0mv v dd -50 0mv v dd - 40 0mv v te open-drain output pulls down from v dd . v swing single ended output swing voltage 425 500 600 mv swing down from tmds termina - tion voltage (3.3v 10%) i off single-ended current in high-z state 50 a measured with tmds outputs pulled up to v dd max _(3.6v) through 50 resistors. t skew-intra intra-pair diferential skew 30 ps tis diferential skew budget is in addition to the skew presented be - tween d+ and d- paired input pins. hdmi revision 1.3 source allowable intrapair skew is 0.15 t bit . t skew-inter inter-pair lane-to-lane output skew 100 ps tis lane-to-lane skew budget is in addition to skew between diferen - tial input pairs t jit jitter added to tmds signals 25 ps jitter budget for tmds signals as they pass through the level shifer. 25ps = 0.056 at 2.25 gbps tmds output oscillation elimination te inputs already incorporate a squelch circuit. terefore, nothing is needed from application standpoint to eliminate tmds output oscillation when there is no tmds input present. te ic will do this automatically. table 3: hpd characteristics symbol parameter min ty p max units comments v ih-hpd input high level 2.0 5.0 5.3 v low-speed input changes state on cable plug/ unplug v il-hpd hpd_sink input low level 0 0.8 v i in-hpd hpd_sink input leakage current 70 a measured with hpd_sink at v ih-hpd max and v il-hpd min v oh-hpd hpd_source output high-level 2.5 v dd v v dd = 3.3v 10% i oh = -4ma(min) / -8ma(max) v ol-hpd hpd_source output low- level 0 0.4 v i ol = 4ma(min) / 8ma(max) t hpd hpd_sink to hpd_ source propagation delay 200 ns time from hpd_sink changing state to hpd_source changing state. includes hpd_ source rise/fall time t rf-hpdb hpd_source rise/ fall time 1 20 ns time required to transition from v oh- hpdb to v ol-hpdb or from v ol-hpdb to v oh-hpdb www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
10 table 4: oe# input, sqsel and ddc_en symbol parameter min ty p max units comments v ih input high level 2.0 v dd v tmds enable input changes state on cable plug/unplug v il input low level 0 0.8 v i in input leakage current 10 a measured with input at v ih-en max and v il-en min table 5: termination resistor symbol parameter min ty p max units comments r hpd hpd_sink input pull- down resistor. 100k guarantees hpd_sink is low when no display is plugged in. www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
11 pericom semiconductor corporation ? 1-800-435-2336 packaging mechanical: 48-pin tqfn (zb) all trademarks are property of their respective owners. note: 1.for latest package info, please check: http://www.pericom.com/support/packaging/packaging-mechanicals-and-thermal-characteristics 2.te exposed die paddle size is 3.6x3.6mm for PI3VDP411LSAzbe 3. pad size (d2 * e2) is 157 x 157 mm 1 description: 48-pin, thin fine pitch quad flat no-lead (tqfn) p ackage code: zb48 document control #: pd-2080 revision: a da te: 02/1 1/09 unit : mm notes: 1. all dimensions are in millimeters, angles are in degrees. 2. coplanarity applies to the exposed thermal pad as well as the terminals. 3. refer jedec mo-220 4. recommended land pattern is for reference onl y . 5. thermal pad soldering area 09-0091 www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
12 related products part number product description pi3eqxdp1201 displayport 1.2 re-driver with built-in aux listener pi3vdp1430 dual mode displayport to hdmi level shifer and re-driver pi3hdmi511 3.4g hdmi1.4 re-driver for source-side application, supporting dual mode displayport pi3hdmi611 3.4g hdmi1.4 re-driver for sink-side application, supporting dual mode displayport pi3vdp3212 2-lane displayport1.2 compliant switch pi3vdp12412 4-lane displayport1.2 compliant switch pi3hdmi412ad 1:2 active 3.4gbps hdmi1.4 compliant splitter/re-driver pi3hdmi521 2:1 3.4gbps hdmi1.4 switch/re-driver with built-in arc and fast switching support for sink application pi3hdmi621 2:1 3.4gbps hdmi1.4 switch/re-driver with built-in arc and fast switching support for sink application pi3hdmi336 3:1 active 3.4gbps hdmi switch/re-driver with i 2 c control and arc transmitter reference information document description vesa vesa displayport standard version 1 revision 2, video electronics standards association, january 5, 2010 vesa displayport dual-mode standard version 1, video electronics standards association, february 10, 2012 vesa displayport interoperability guideline version 1.1a, video electronics standards association, febru - ary 5, 2009 hdmi high-defnition multimedia interface specifcation version 1.4, hdmi licensing, llc, june 5, 2009 ordering information ordering code package code pack age ty pe pi3v dp411lsa zbe zb pb-free & green, 48-pin tqfn 1. termal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb-free and green 3. adding an x sufx = tape/reel www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236
13 revision history date changes 7/28/2012 actual pad size 157 x 157 mil in package drawing www.pericom.com ps9059a 07/28/12 p i 3v d p 411l s a dual mode displayport? to dvi/hdmi? electrical bridge (level shifer) 12-0236

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