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1. abstract the trend from through-hole packages to low-cost smd-applications is marked by the improvement of chip technologies. "silicon instead of heatsink" is therefore possible in many cases. many applications today use pcbs assembled with smd-technologies, the emphasis being on power ics in smd packages mounted on single-sided pcbs laminated on one side. the printed circuit board (pcb) itself becomes the heatsink. in early fabrications a solid heatsink was either screwed or clamped to the power package. it was easy to calculate the thermal resistance from the geometry of the heatsink. in smd-technology, this calculation is much more difficult because the heat path must be evaluated: chip (junction) - lead frame - case or pin - footprint - pcb materials (basic material, thickness of the laminate) - pcb volume - surroundings. as the layout of the pcb is a main contributor to the result, a new technique must be applied. surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. the power dissipation for a smd device is a function of the drain pad size, which can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. the measurements achieved on smd packages for different drain pad size show that by increasing the area of the drain pad the power dissipation can be increased. although one can achieve improvements in power dissipation with this method, the tradeoff is to use valuable board area. next we consider the common st mosfet smd packages (d 2 pak, dpak, sot-223, so-8, powerso- 8?, powerflat? (5x5) and (6x5), tssop8 and powerso-10?) with their recommended footprints. for each of these packages we will show the power dissipation for the minimum footprint and for a large drain pad area (1in 2 or 600mm 2 ) using the max measured r thj-pcb . we will show the maximum allowable power dissipation versus drain pad area for different t j -t a values as well. finally we will make a thermal performance comparison for all smd packages analysed. information regarding the mechanical dimensions for each smd package can be found on the related datasheets. 2. thermal measurements the most practical method of optimizing thermal performance is to characterize the mosfet on the pcb where it will be used. the basis of this method is to dissipate a known amount of power in the mosfet, and to measure the amount of temperature rise this causes in the junction, given the data june 2003 1/22 AN1703 application note r.gulino guidelines for using sts mosfet smd packages
AN1703 - application note 2/22 required to calculate the junction to pcb thermal resistance (c/w). the procedure has two main steps. first is the characterization of the body diode. second is the temperature rise measurements and calculation of the thermal resistance. as an inherent part of the mosfet structure, the body diode makes the ideal sensor to measure the junction temperature, since the forward voltage v f varies with temperature, approximately -2.2mv/c. for this the diode's temperature coefficient is needed to get an accurate representation of the junction temperature. the forward voltage is measured with a low level current flowing through it to ensure there is no self heating, which would make the junction temperature measurement inaccurate. the mosfet being characterized is soldered on to the thermal test pcb and has the gate shorted to the source, to insure the mosfet cannot turn on. the copper mounting pad reaches the remote connection points through fine traces that do not contribute significant thermal dissipation but serve the purpose of electrical connections. figure 1 illustrate the schematic of r th measurements where the mosfet 's drain and source are connected with two power supplies. figure 1: schematic of temperature measurements the first power supply forces current through the body diode to heat the junction with a fixed power level, when the switch is in the "heating" position. the second power supply provides the sensing current for measuring the junction temperature, through the v f measurement, when the switch is in the "sensing" position. the measure of r thj-pcb is based on the well know relationship between the power being dissipated in the devices and the relevant arising junction temperature: this computation is made from pulsed operation to steady state in order to achieve the whole thermal transient response of the device under test. the applied power p d is fixed by the equipment in terms of magnitude and time duration, so it is an input data. heating current vf heating sensing pmos d.u.t. sense current heating current vf heating sensing pmos d.u.t. sense current d c j d pcb thj p t t p t r - = d = -
AN1703 - application note 3/22 what we now have to compute is the t j value since t c is also an input data related to ambient or case temperature. to detect the arising junction temperature (t j ), we look at the variation of the forward drop of the drain-source diode, since this variation is proportional to the change in junction temperature. 3. d 2 pak the d 2 pak is a surface mounting version of the standard to-220 package, with the lead formed and the tab removed. it has been designed to achieve the high quality and reliability levels required by end users in the automotive industry. figure 2 shows d 2 pak and its recommended footprint: figure 2: d 2 pak and its recommended footprint (all dimensions are in mm) figure 3 shows a graph of r thj-pcb versus drain pad area from minimum recommended footprint to 10cm 2 : figure 3: r thj-pcb versus drain pad area for d 2 pak 30 35 40 45 50 55 60 65 0 100 200 300 400 500 600 700 800 900 1000 rthj- pcb [c/w] fr-4, 2 oz copper board minimum recommended footprint r thj-a
AN1703 - application note 4/22 in free air we must consider the r thj-a , with a value of 62.5c/w, like that of the to-220. for the minimum recommended footprint (120mm 2 ) the r thj-pcb value is 42c/w and the maximum allowable power dissipation turns out to be: for a drain pad area of 1in 2 (about 600mm 2 ) we obtain : the next figure shows the maximum allowable power dissipation versus drain pad area for different t j -t a values: figure 4: maximum allowable power dissipation versus drain pad area w 5 . 3 42 150 r t p pcb thj d = = d = - (t jmax = 175 c, t c = 25 c) w 4 . 4 r t p w c 34 r pcb thj d pcb thj = d = t = - - 0 1 2 3 4 5 0 200 400 600 800 1000 pd [w] tj- ta=150c tj-ta=125c tj-ta=100c tj-ta=75c tj-ta=50c area mm 2
AN1703 - application note 5/22 4. dpak similar considerations can be made for dpak, where its minimum recommended footprint is shown in figure 5: figure 5: dpak and its recommended footprint (all dimensions are in mm) figure 6 shows a graph of r thj-pcb versus drain pad area from minimum recommended footprint to 10cm 2 : figure 6: r thj_pcb versus drain pad area for dpak 40 60 80 100 120 0 100 200 300 400 500 600 700 800 900 1000 rthj- pcb [c/w] fr-4, 2 oz copper board minimum recommended footprint r thj-a area mm 2
AN1703 - application note 6/22 in free air we must consider the r thj-a and its value 100c/w. for the recommended footprint (45mm 2 ) the r thj-pcb value is 62c/w and the maximum allowable power dissipation is: for a drain pad area of 1in 2 (about 600mm 2 ) we obtain: the next figure shows the maximum allowable power dissipation as function of a pcb drain pad area for different t j -t a values: figure 7: maximum allowable power dissipation versus drain pad area 5. sot-223 the sot-223 is a small package designed for surface mount applications. the formed leads absorb thermal stress during soldering, thereby eliminating the possibility of damage to the die. the encapsulation material used in this package enhances the device reliability which allows it to exhibit excellent performance in high temperature environments. w r t p pcb thj d 4 . 2 62 150 = = d = - (t jmax = 175 c, t c = 25c) w r t p pcb thj d 4 . 2 62 150 = = d = - (t jmax = 175c, t c = 25c) w r t p w c r pcb thj d pcb thj 3 50 = d = t = - - 0 1 2 3 4 0 200 400 600 800 1000 pd [w] tj- ta=150c tj-ta=125c tj-ta=100c tj-ta=75c tj-ta=50c area mm 2
AN1703 - application note 7/22 figure 8: sot-223 and its recommended footprint (all dimensions are in mm) figure 9 shows the measured values of r thj-pcb versus drain pad area from minimum recommended footprint to 10cm 2 , for t 10 s as power pulse: figure 9: r thj-pcb versus drain pad area for sot-223 measurements performed for minimum recommended footprint (15mm 2 ) and t 10 s give r thj-pcb = 56.6c/w and the maximum allowable power dissipation results: 30 40 50 60 0 200 400 600 800 1000 rthj- pcb [c/w] minimum recommended footprint area mm 2 fr-4, 2 oz copper board w r t p pcb thj d 2 . 2 6 . 56 125 = = d = - (t jmax = 150 c, t c = 25c) w r t p pcb thj d 2 . 2 6 . 56 125 = = d = - (t jmax = 150c, t c = 25c)
AN1703 - application note 8/22 for a drain pad area of 1in 2 (about 600mm 2 ) we obtain: in the next figure the maximum allowable power dissipation as function of a pcb drain pad area for different t j -t a values is shown: figure 10: maximum allowable power dissipation versus drain pad area 6. so-8 the basis of the pad design for an so-8 mosfet is the package footprint. in converting the footprint to the pad set for a mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. for the so-8 the thermal connections are very simple. pins 5, 6, 7 and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. in figure 11 the basic so-8 footprint is shown. figure 11: so-8 and its basic footprint (all dimensions are in mm) for a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. w r t p w c r pcb thj d pcb thj 3 . 3 38 = d = t = - - 0 1 2 3 4 0 200 400 600 800 1000 pd [w] tj- ta=125c tj-ta=100c tj-ta=75c tj-ta=50c tj-ta=25c area mm 2
AN1703 - application note 9/22 the minimum recommended pad patterns for the single mosfet so-8 (figure 12a) and dual mosfet so-8 (figure 12b) show the starting point for utilizing the board area available for the heat-spreading copper. to create this pattern, a plane of copper overlies the drain pins. figure 12:single (a) & dual mosfet (b) so-8 minimum recommended pad pattern (all dimensions are in mm) these connections provide planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the pcb. these patterns use all the available area underneath the body for this purpose. figure 13 shows a graph of r thj-pcb versus drain pad area from minimum recommended footprint to 15cm 2 , for t 10 s as power pulse: figure 13: r thj-pcb versus drain pad area for so-8 a b 40 60 80 100 120 0 200 400 600 800 1000 1200 1400 1600 rthj- pcb [c/w] fr-4, 2 oz copper board minimum recommended footprint area mm 2
AN1703 - application note 10/22 for the minimum recommended footprint (22mm 2 for a single mosfet and 10mm 2 for a dua l mosfet) the thermal resistance value is about r thj-pcb = 100c/w and the maximum allowable power dissipation results: for a drain pad area of 1in 2 (about 600mm 2 ) we obtain: the next figure shows the maximum allowable power dissipation as function of a pcb drain pad area for different t j -t a values. figure 14: maximum allowable power dissipation versus drain pad area 7. powerso-8? to enlarge our product range and, in the meantime, improve the performance of our mosfets housed in smd packages, we are introducing new options to comply with the next generation of dc to dc converters for the computer and telecom areas. in such applications high output current and good thermal performances are required. this new package tailored to the above requirements is powerso-8. furthermore, power devices housed in this package can be used for automotive applications such as body electronic applications (door looking, wipers, seat positioning systems and so on). powerso-8 is the power version of the standard so-8 package. it maintains the same footprint as so-8, but it also has a solderable drain contact on the back. given that heat is dissipated through the drain and source leads and also through the back of the package, the junction-case thermal resistance is w r t p pcb thj d 25 . 1 100 125 = = d = - (t jmax = 150 c, t c = 25c) w r t p pcb thj d 25 . 1 100 125 = = d = - (t jmax = 150c, t c = 25c) w r t p w c r pcb thj d pcb thj 5 . 2 50 = d = t = - - 0 1 2 3 0 500 1000 1500 pd [w] tj- ta=125c tj-ta=100c tj-ta=75c tj-ta=50c area mm 2
AN1703 - application note 11/22 drastically reduced and consequently the device is able to manage higher currents. figure 15 shows powerso-8 and its minimum recommended footprint. figure 15: powerso-8 with its minimum recommended footprint (all dimension are in mm) commonly pins 5 to 8 are the drain and are connected together to the exposed pad, so we have the same situation as figure 12a, while pin 4 is the gate and pins 1 to 3 are the source. figure 16 shows the powerso-8 internal structure. figure 16: powerso-8? internal structure solder paste die heat slug drain source electrolitic solder resin
AN1703 - application note 12/22 figure 17 shows a graph of r thj-pcb versus drain pad area from minimum recommended footprint to 10cm 2 , for t 10 s as power pulse: figure 17: r thj_pcb versus drain pad area for powerso-8? for the minimum recommended footprint (23mm 2 ) the thermal resistance value is about r thj-pcb = 56.6 c/w and the maximum allowable power dissipation results: for a drain pad area of 1in 2 (about 600mm 2 ) we obtain: that is 20% higher than that of the standard so-8 . in the next figure the maximum allowable power dissipation as function of a pcb drain pad area for different t j -t a values is shown: figure 18: maximum allowable power dissipation versus drain pad area 30 40 50 60 0 200 400 600 800 1000 rthj- pcb [c/w] fr-4, 2 oz copper board area mm 2 minimum recommended footprint w r t p pcb thj d 2 . 2 6 . 56 125 = = d = - (t jmax = 150 c, t c = 25c) w r t p pcb thj d 2 . 2 6 . 56 125 = = d = - (t jmax = 150c, t c = 25c) w r t p w c r pcb thj d pcb thj 3 42 = d = t = - - area mm 2 0 1 2 3 4 0 200 400 600 800 1000 pd [w] tj- ta=125c tj-ta=100c tj-ta=75c tj-ta=50c
AN1703 - application note 13/22 8. powerflat? (5x5) and powerflat? (6x5) powerflat, in both (5x5) and (6x5) versions, depending on the package body size in (mm x mm), allows substantially bigger die capability with respect to the old-fashioned so-8, still with reduced height and weight. this in turn translates into a remarkable board space reduction. furthermore, the lower profile (1mm) allows higher operation frequency due to less inductance. the leads are accommodated into the plastic body in such a way that a perfect co-planarity in assured. also a better thermal impedance is achieved by means of the exposed pad that provides a thermal path from the die attached copper frame directly to the pcb. the above features are exactly what designers demand in making their designs increasingly more efficient. not only is the powerflat (5x5) smaller, but it also differs from powerflat (6x5) in the way the pads are connected to the package. in fact, in powerflat (5x5) the source terminals are on both sides while the drain coincides with the exposed back metal side only. the powerflat (6x5) case is pin to pin compatible with a standard so-8 package, it can house a larger die, and the exposed pad is connected to the drain as well. figure 19: powerflat (5x5) and powerflat (6x5) figure 20 shows minimum recommended footprints for both types of powerflat. figure 20:powerflat (5x5) (a) and powerflat (6x5) (b) minimum recommended footprints (all dimension are in mm) a b
AN1703 - application note 14/22 figure 21 (obtained by measurements performed on powerflat) shows the r thj-pcb versus drain pad area from minimum recommended footprint to 10cm 2 , for t 10 s as power pulse: figure 21: r thj_pcb versus drain pad area for both types of powerflat? for the minimum recommended footprint the thermal resistance value is about r thj-pcb = 60 c/w and the maximum allowable power dissipation results: for a drain pad area of 1in 2 (about 600mm 2 ) we obtain: in the next figure the maximum allowable power dissipation as function of a pcb drain pad area for different t j -t a values is shown: 20 30 40 50 60 0 200 400 600 800 1000 rthj-pcb [c/w] fr-4, 2 oz copper board minimum recommended footprint area mm 2 w r t p pcb thj d 1 . 2 60 125 = = d = - (t jmax = 150 c, t c = 25c) w r t p pcb thj d 1 . 2 60 125 = = d = - (t jmax = 150c, t c = 25c) w r t p w c r pcb thj d pcb thj 4 2 . 31 = d = t = - -
AN1703 - application note 15/22 figure 22: maximum allowable power dissipation versus drain pad area 9. tssop8 the new tssop8 power mosfet package is the natural evolutionary response to the continuing demands of many markets for smaller packages. it has a smaller footprint and a lower profile than standard the so-8 package, while maintaining low on-resistance and a good thermal performance. furthermore tssop8 packages require approximately half the pcb area of a standard so-8. it is available both in single die and/or in double dice in common drain configuration. figure 23 shows tssop8 and its internal schematic for dual configuration: figure 23: tssop8 package and its internal schematic 0 1 2 3 4 5 0 200 400 600 800 1000 pd [w] tj- ta=125c tj-ta=100c tj-ta=75c tj-ta=50c area mm 2
AN1703 - application note 16/22 figure 24 shows the r thj-pcb versus drain pad area from minimum recommended footprint to 10cm 2 , for t 10 s as power pulse: figure 24: r thj_pcb versus drain pad area for tssop8 for the minimum recommended footprint the thermal resistance value is about r thj-pcb = 100 c/w and the maximum allowable power dissipation results: for a drain pad area of 1in 2 (about 600mm 2 ) we obtain: in the next figure the maximum allowable power dissipation as function of a pcb drain pad area for different t j -t a values is shown: figure 25: maximum allowable power dissipation versus drain pad area 75 80 85 90 95 100 105 0 200 400 600 800 1000 rthj-pcb [c/w] fr-4, 2 oz copper board minimum recommended footprint area mm 2 w r t p pcb thj d 25 . 1 100 125 = = d = - (t jmax = 150 c, t c = 25c) w r t p pcb thj d 25 . 1 100 125 = = d = - (t jmax = 150c, t c = 25c) w r t p w c r pcb thj d pcb thj 5 . 1 5 . 83 = d = t = - - 0 0.5 1 1.5 2 0 200 400 600 800 1000 pd [w] tj- ta=125c tj-ta=100c tj-ta=75c tj-ta=50c area mm 2
AN1703 - application note 17/22 10. powerso-10? surface mounting packages, by their very nature are restricted to smaller footprints. power devices need larger footprints to dissipate heat. powerso-10 is an optimized balance between these two conflicting requirements. figure 26 shows powerso-10 with its minimum recommended footprint. figure 26: powerso-10? package and its minimum recommended footprint (all dimensions are in mm) a 10-pin dip package was manufactured also for use in intelligent power devices, which require many leads. discrete can use high pin count packages to distribute the current through the power circuit. the maximum die-size is the same as to-220 and its derived versions, d 2 pak and i 2 pak. the lowering of the powerso-10 height results in about a 37% decrease in total volume of the package, while the spreader area remains large. not only does this result in a lower package cost, but also from a high frequency standpoint, low height and less inductance are two big advantages. the use of epoxy fr-4 boards is quite common in through-hole techniques; for surface mounting techniques, however, its poor thermal conduction means that it is not possible to benefit from the outstanding thermal performance of powerso-10. one way to improve the thermal conduction is the use of large heat spread areas at the copper layer of the pc board. this leads to a reduction of thermal resistance from 35-38c/w for 3 to 6cm 2 on board heatsink (see figure 27).
AN1703 - application note 18/22 figure 27: r thj_pcb versus drain pad area for powerso-10 for the recommended footprint (about 60mm 2 ) the value is r thj-pcb = 50c/w and the maximum allowable power dissipation results: by increasing the area of the drain pad, the power dissipation can be increased. for a drain pad area of 1in 2 (about 600mm 2 ) we obtain: 30 35 40 45 50 55 0 100 200 300 400 500 600 700 800 900 1000 rthj- pcb [c/w] fr-4, 2 oz copper board area mm 2 minimum recommended footprint w r t p pcb thj d 3 50 150 = = d = - (t jmax = 175 c, t c = 25c) w r t p pcb thj d 3 50 150 = = d = - (t jmax = 175c, t c = 25c) w r t p w c r pcb thj d pcb thj 3 . 4 35 = d = t = - -
AN1703 - application note 19/22 the next figure shows the maximum allowable power dissipation as function of a pcb drain pad area for different t j -t a values. figure 28: maximum allowable power dissipation versus drain pad area use of copper-filled through-holes with conventional fr-4 techniques increases the metallization and decreases thermal resistance accordingly. using a configuration with 16 holes under the spreader of the package with a pitch of 1.8mm and a diameter of 0.7mm, the thermal resistance (junction - heats ink) can be reduces to 15 c/w (see figure 29) figure 29: mounting on fr-4 using copper-filled through holes for heat transfe r apart from the thermal advantage, this solution allows the use of multi-layer boards. however, the limitations of this conventional material prevent its use in very high power, high current circuits. 0 1 2 3 4 5 0 200 400 600 800 1000 pd [w] tj- ta=150c tj-ta=125c tj-ta=100c tj-ta=75c tj-ta=50c area mm 2
AN1703 - application note 20/22 the thermal characteristics of powerso-10 are comparable with those of the d 2 pak, as shown in the next table. table 1: comparison between powerso-10? and d2pak steady-state thermal resistance (junction-case) studies show approximately 0.8c/w for both powerso-10 and d 2 pak, but powerso-10 exhibits 30% less footprint area than d 2 pak. the test vehicle used is a mosfet with a die-size of about 32,000 mils 2 (about 20.6mm 2 ). furthermore, since powerso-10 has been designed solely to be an smd, symmetry in the x- and y-planes gives the package excellent weight balance. moreover, powerso-10 offers the unique opportunity to easily control the flatness and quality of the soldering process. both the top and the bottom soldered edges of the package are accessible for visual inspection. powerso-10 is a package "designed for testability". co-planarity between the substrate and the package can be easily verified. 11. smd packages comparison thermal performances for smd packages are summarized in the following table: table 2: thermal performances for smd packages (*) when mounted on 1 in 2 fr-4 board, 2 oz cu, tp < 10s for small packages. (**) when mounted on minimum recommended footprint. package package shaping area [mm 2 ] recomme nde d mi n. footprint area [mm 2 ] t jmax [c] r thj-pcb [c/w ] (*) r thj-pcb [c/w ] (**) p d [w] (*) d 2 pak 210 120 175 34.0 42.0 4.4 powerso-10 140 60 175 35.0 50.0 4.3 dpak 80 45 175 50.0 62.0 3.0 powerflat 5x5 25 15 150 31.2 60.0 4.0 powerflat 6x5 30 23 150 31.2 60.0 4.0 sot-223 50 15 150 38.0 56.6 3.3 powerso-8 30 23 150 42.0 56.6 3.0 so-8 30 23 150 50.0 100 2.5 tssop8 20 15 150 83.5 100 1.5
AN1703 - application note 21/22 first of all we have to note that the maximum allowable power dissipation for the newest small packages (powerflat and powerso-8) is quite similar to that for dpak but require approximately half the pc board space. this advantage is more impressive if we note that the max die housed in powerflat (6x5 version) is about 30% greater than those in dpak. also sot-223 has a high thermal performance, but the max die housed is half that of those for dpak and powerso-8. since several automotive applications require devices rated at 175 c, up to now only the standard smd packages (d 2 pak, dpak, powerso-10) are automotive graded. these packages have been designed to withstand the high stresses in under-hood applications. 12. soldering profile the most commonly used techniques for mounting smd packages to the pcb are infrared and vapor phase reflow. these are preferred over wave soldering because this typically involves increased heating rate, higher temperatures and increased flux exposure. the infrared reflow technique involves thermal energy supplied via lamps radiating at given wavelengths. therefore, the amount of thermal energy absorbed varies with board size, component size, component orientation, and materials used. the surface temperature of the board is not uniform and the board edges tend to run 10c to 20c higher than the center. the vapor phase reflow technique uses vapor from a boiling inert fluorocarbon liquid. the heat of condensation provides a thermal constraint dependent on the liquid selected. with essentially no temperature gradient across the surface of the board, component location design rules even for heating is not significant compared to infrared reflow. the theoretical solder reflow temperature profile used, and the temperatures and time duration are shown in the next figure: figure 30: soldering profile, recommended reflow oven profile temp. c time (sec) * package volume < 350mm 3 / package thickness < 2.5mm ** package volume 3 350mm 3 / package thickness < 2.5mm and all bgas * tmax=235 +5 / -0 c ** tmax=220 +5 / -0 c max 20 sec
AN1703 - application note 22/22 any solder temperature profile should be within these limits. the soldering process causes considerable thermal stress to a semiconductor component. this has to be minimized to ensure a reliable and extended lifetime of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, in order to minimize the thermal stress to which the devices are subject, the device should always be preheated (max 120sec at 125 25 c). soldering a device without preheating can cause excessive thermal shock and stress that can result in damage to the device. voids pose a difficult reliability problem for large surface mount devices. pockets of air under the package result in poor thermal contact and the resulting high thermal resistance leads to complete failure. because of co-planarity problems, weight balance is critical. the quality of the solder joints is very important for two reasons: firstly, poor quality solder joints result directly in poor reliability, and secondly, solder thickness significantly affects the thermal resistance. thus a tight control of this parameter results in thermally efficient and reliable solder joints. thermal conductivity in the region of 0.5c/w can easily be lost through uneven solder and poor co-planarity of tabs and leads. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - isreal - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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