devices incorporated lpr520/521 4 x 16-bit multilevel pipeline register pipeline registers 06/30/95Clds.p520/1-k 1 q q q q q four 16-bit registers q q q q q implements double 2-stage pipe- line or single 4-stage pipeline register q q q q q hold, shift, and load instructions q q q q q separate data in and data out pins q q q q q high-speed, low power cmos technology q q q q q three-state outputs q q q q q desc smd no. 5962-89716 q q q q q available 100% screened to mil-std-883, class b q q q q q package styles available: ? 40-pin plastic dip ? 40-pin ceramic dip ? 44-pin plastic lcc, j-lead ? 44-pin ceramic lcc features description lpr520/521 4 x 16-bit multilevel pipeline register devices incorporated the lpr520 and lpr521 are functionally compatible with the idt29fct520/ idt29fct521 and amd am29520/ am29521 but have 16-bit inputs and outputs. they are implemented in low power cmos. the lpr520 and lpr521 contain four registers which can be configured as two independent, 2-level pipelines or as one 4-level pipeline. the instruction pins, i 1-0 , control the loading of the registers. for either device, the registers may be config- ured as a four-stage delay line, with data loaded into r1 and shifted sequentially through r2, r3, and r4. also, for the lpr520, data may be loaded from the inputs into either r1 or r3 with only r2 or r4 shifting. the lpr521 differs from the lpr520 in that r2 and r4 remain unchanged during this type of data load, as shown in tables 1 and 2. finally, i 1-0 may be set to prevent any register from changing. the s 1-0 select lines control a 4-to-1 multiplexer which routes the contents of any of the registers to the y output pins. the independence of the i and s controls allows simultaneous write and read operations on different registers. s 1 s 0 register selected l l register 4 l h register 3 h l register 2 h h register 1 t able 3. o utput s elect i 1 i 0 description lld t r1 r1 t r2 r2 t r3 r3 t r4 l h hold hold d t r3 hold hld t r1 hold hold hold h h all registers on hold t able 2. lpr521 i nstruction t able i 1 i 0 description lld t r1 r1 t r2 r2 t r3 r3 t r4 l h hold hold d t r3 r3 t r4 hld t r1 r1 t r2 hold hold h h all registers on hold t able 1. lpr520 i nstruction t able lpr520/521 b lock d iagram mux reg 1 reg 2 reg 3 reg 4 register 1 register 2 register 3 register 4 mux d 15-0 16 16 oe y 15-0 s 1-0 i 1-0 clk 2 2
devices incorporated lpr520/521 4 x 16-bit multilevel pipeline register 06/30/95Clds.p520/1-k 2 pipeline registers symbol parameter test condition min typ max unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.5 v v ih input high voltage 2.0 v cc v v il input low voltage (note 3) 0.0 0.8 v i ix input current ground v in v cc (note 12) 20 a i oz output leakage current ground v out v cc (note 12) 20 a i cc1 v cc current, dynamic (notes 5, 6) 10 40 ma i cc2 v cc current, quiescent (note 7) 1.0 ma storage temperature ........................................................................................................... C65c to +150c operating ambient temperature .......................................................................................... C55c to +125c v cc supply voltage with respect to ground .......................................................................... C0.5 v to +7.0 v input signal with respect to ground ........................................................................................ C3.0 v to +7.0 v signal applied to high impedance output ............................................................................... C3.0 v to +7.0 v output current into low outputs............................................................................................................. 25 ma latchup current ............................................................................................................................... > 400 ma m aximum r atings above which useful life may be impaired (notes 1, 2, 3, 8) o perating c onditions to meet specified electrical and switching characteristics e lectrical c haracteristics over operating conditions (note 4) mode temperature range (ambient) supply voltage active operation, commercial 0c to +70c 4.75 v v cc 5.25 v active operation, military C55c to +125c 4.50 v v cc 5.50 v
devices incorporated lpr520/521 4 x 16-bit multilevel pipeline register pipeline registers 06/30/95Clds.p520/1-k 3 switching characteristics lpr520/521C 30 24 18 symbol parameter min max min max min max t pd clock to output delay 30 24 18 t sel select to output delay 30 22 18 t pw clock pulse width 15 10 9 t si instruction setup time 15 10 8 t hi instruction hold time 5 3 2 t sd data setup time 15 10 8 t hd data hold time 5 3 2 t ena three-state output enable delay (note 11) 25 22 16 t dis three-state output disable delay (note 11) 20 16 13 m ilitary o perating r ange (C55c to +125c) notes 9, 10 (ns) s witching w aveforms lpr520/521C 25 22 15 symbol parameter min max min max min max t pd clock to output delay 25 22 15 t sel select to output delay 25 20 15 t pw clock pulse width 10 10 8 t si instruction setup time 13 10 6 t hi instruction hold time 3 3 1 t sd data setup time 13 10 6 t hd data hold time 3 3 1 t ena three-state output enable delay (note 11) 25 21 15 t dis three-state output disable delay (note 11) 25 15 12 c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) high impedance t ena t dis t pw t si t sd d 15-0 clk oe t pd t hd t hi t pw t sel i 1-0 s 1-0 y 15-0
devices incorporated lpr520/521 4 x 16-bit multilevel pipeline register 06/30/95Clds.p520/1-k 4 pipeline registers ncv f
4 2 1. maximum ratings indicate stress specifications only. functional oper- ation of these products at values be- yond those indicated in the operating conditions table is not implied. expo- sure to maximum rating conditions for extended periods may affect reliability. 2. the products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. never- theless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot and overshoot. input levels below ground or above v cc will be clamped beginning at C0.6 v and v cc + 0.6 v. the device can withstand indefinite operation with inputs in the range of C0.5 v to +7.0 v. device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guaranteed as specified. 5. supply current for a given applica- tion can be accurately approximated by: where n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency 6. tested with all outputs changing ev- ery cycle and no load, at a 5 mhz clock rate. 7. tested with all inputs within 0.1 v of v cc or ground, no load. 8. these parameters are guaranteed but not 100% tested. 9. ac specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 v (except t ena / t dis test), and input levels of nominally 0 to 3.0 v. output loading may be a resistive divider which provides for specified i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5 v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. for t enable and t disable measurements, the load current is increased to 10 ma to reduce the rc delay component of the measurement. this device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device under test (dut) as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the dut socket or contactor fingers. c. input voltages should be adjusted to compensate for inductive ground and v cc noise to maintain required dut input levels relative to the dut ground pin. 10. each parameter is shown as a min- imum or maximum value. input re- quirements are specified from the point of view of the external system driving the chip. setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. responses from the internal circuitry are specified from the point of view of the device. output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. transition is measured 200 mv from steady-state voltage with speci- fied loading. 12. these parameters are only tested at the high temperature extreme, which is the worst case for leakage current. notes high impedance oe tristate
outputs 0.2 v 0.2 v t ena t dis 0.2 v 0.2 v f igure 1. t hreshold l evels
devices incorporated lpr520/521 4 x 16-bit multilevel pipeline register pipeline registers 06/30/95Clds.p520/1-k 5 plastic dip (p3) lpr520pc25 lpr520pc22 lpr520pc15 40-pin 0.6" wide lpr520 ordering information 44-pin 0c to +70c c ommercial s creening plastic j-lead chip carrier (j1) lpr520jc25 lpr520jc22 lpr520jc15 speed 25 ns 22 ns 15 ns 30 ns 24 ns 18 ns ceramic leadless chip carrier (k2) lpr520kmb30 lpr520kmb24 lpr520kmb18 ceramic dip (c11) lpr520cmb30 lpr520cmb24 lpr520cmb18 C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21 i 0
i 1
d 0
d 1
d 2
d 3
d 4
d 5
d 6
d 7
d 8
d 9
d 10
d 11
d 12
d 13
d 14
d 15
clk
gnd v cc
s 0
s 1
y 0
y 1
y 2
y 3
y 4
y 5
y 6
y 7
y 8
y 9
y 10
y 11
y 12
y 13
y 14
y 15
oe 41 7
8
9
10
11
12
13
14
15
16
17 39
38
37
36
35
34
33
32
31
30
29 44
top
view 1 42 43 18 23 24 25 26 27 40 6 28 2 5
3 4 19 20 21 22 nc
y 2
y 3
y 4
y 5
y 6
y 7
y 8
y 9
y 10
y 11 d 3
d 4
d 5
d 6
d 7
d 8
d 9
d 10
d 11
d 12
nc nc
d 2
d 1
d 0
i 1
i 0
v cc
s 0
s 1
y 0
y 1 d 13
d 14
d 15
clk
gnd
oe
y 15
y 14
y 13
y 12
nc
devices incorporated lpr520/521 4 x 16-bit multilevel pipeline register 06/30/95Clds.p520/1-k 6 pipeline registers plastic dip (p3) lpr521pc25 lpr521pc22 lpr521pc15 40-pin 0.6" wide lpr521 ordering information 44-pin 0c to +70c c ommercial s creening plastic j-lead chip carrier (j1) lpr521jc25 lpr521jc22 lpr521jc15 speed 25 ns 22 ns 15 ns 30 ns 24 ns 18 ns ceramic leadless chip carrier (k2) lpr521kmb30 LPR521KMB24 lpr521kmb18 ceramic dip (c11) lpr521cmb30 lpr521cmb24 lpr521cmb18 C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21 i 0
i 1
d 0
d 1
d 2
d 3
d 4
d 5
d 6
d 7
d 8
d 9
d 10
d 11
d 12
d 13
d 14
d 15
clk
gnd v cc
s 0
s 1
y 0
y 1
y 2
y 3
y 4
y 5
y 6
y 7
y 8
y 9
y 10
y 11
y 12
y 13
y 14
y 15
oe 41 7
8
9
10
11
12
13
14
15
16
17 39
38
37
36
35
34
33
32
31
30
29 44
top
view 1 42 43 18 23 24 25 26 27 40 6 28 2 5
3 4 19 20 21 22 nc
y 2
y 3
y 4
y 5
y 6
y 7
y 8
y 9
y 10
y 11 d 3
d 4
d 5
d 6
d 7
d 8
d 9
d 10
d 11
d 12
nc nc
d 2
d 1
d 0
i 1
i 0
v cc
s 0
s 1
y 0
y 1 d 13
d 14
d 15
clk
gnd
oe
y 15
y 14
y 13
y 12
nc
|
