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4013BE D53TP25D F5016AL3 IRF7467 SI2308 74456115 72045 CONTROLS
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  93 clk osc crystal clock oscillators metal ceramic ausn tungsten (metalized) gold / nickel (surface) / (under) compliant (pb-free) lid base sealing terminal terminal plating rohs 327smo(b) 327smo(b) 327smo(b) (+3.3v 32.768 khz model) standard smd clock oscillators standard specifications package data package item item specifications 327smo(b) 32.768 khz  30 ppm to - 10 ppm at v dd =  3.3v at  25?c  30 ppm to - 100 ppm (v dd =  1.3v to  5.5v) - 40?c to  85?c  3.3v dc ? 10% (standard)  1.3v to  5.5v (option) v ih : 90%v dd min. v il : 10%v dd max. - 0.3v to  7.0v dc - 55?c to  125?c 1  a, typical (1.5  a max.) at v dd =  3.3v , no load 200 na max. (no load) 40% to 60% at 50%v dd level (cl = 15pf at  25?c) 200 ns max. (cl = 15pf at  25?c) v ol :  0.4v max. (cl = 15pf at  25?c) v oh : v dd - 0.4vmin. (cl = 15pf at  25?c) 15 pf max. (cmos) 100 ns max. 3 sec. max. (v dd =  3.3v at  25?c) 3 sec. max. (v dd =  3.3v at  25?c) ? 5 ppm max. at  25?c ? 3?c for first year  250?c ? 10?c for 10 seconds  170?c ? 10?c for 1 to 2 minutes (preheating) 32.768 khz oscillator ( t ) internal crystal oscillation to be halted (pin #1=v il ). part number output frequency frequency tolerance temperature stability ( - 20?c to  70?c) operating conditions operating temperature input voltage (v dd ) stand-by control voltage (pin#1) absolute max. ratings supply voltage storage temperature input current ( - 40?c to  85?c) stand - by current (  25?c) t output ( - 40?c to  85?c) symmetry rise and fall times (10%v dd to 90%v dd level) "0" level "1" level load disable delay time enable delay time startup time aging reflow condition 4.0 0.2 2.5 0.2 0.8 0.1 0.8 0.7 0.8 0.1 0.1 0.9 2.0 ab 0.9 #1 #2 #1 #2 #4 #3 #4 #3 ? the terminals (a & b) not to be connected. pin 1 connection "l" 2 gnd 3z "h" output z : high impedance 4v dd 327smo(b) 3.0 1.4 1.6 1.4 1.1 0.5 1.1 0.01  f ?  0.1  f soldering pattern tf t t 90% or 80% v dd 10% or 20% v dd ov dc symmetry=t/t  100(%) 50% v dd tr gnd v oh ("1"level) v ol ("0"level) v dd output waveform v dc power supply cl : including fixture and probe capacitance. v dd v dd cl t est point #2 #3 output tri-state gnd #1 #4 0.01  f ? 0.1  f e/d sw a test circuit a 4.4 2.9 12.0 5.5 4.0 1.5 0.3 1.2 180 1000pcs qty/reel b c d f j l m reel dia. 4.0 0.1 2.0 0.1 1.75 0.1 + 0.1 - 0  1.5 l b f d a c j m t ape specifications actual size


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