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fedl610q380full-01 issue date: mar 9, 2012 ML610Q380/ml610q383 ml610q384/ml610q385 8-bit microcontroller with voice output function i 1/29 general description equipped with a 8-bit cpu nx-u8/100, the ML610Q380/383/384/385 is a high-performance 8-bit cmos microcontroller that integrates a wide variety of peripherals such as 12-bit a/d converter, timer, pwm, synchronous serial port, uart, i c bus interface (master), battery level detect circuit, lcd driver, voice output function and speaker amplifier. the nx-u8/100 cpu is capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture. in addition, it has an on-chip debugging function, which allows software debugging/rewriting with the lsi mounted on the board. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system:16-bit instructions ? instruction set:transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on-chip debug function ? minimum instruction execution time approx 30.5 s (at 32.768khz system clock) approx 0.122 s (at 8.192mhz system clock) dv dd = 2.2 to 5.5v ? internal memory ? has 128-kbyte flash rom(64k 16-bit) built in. (1k byte of test domain that it cannot be used is included) ? has 2-kbyte ram (2048 8 bits) built in. ? has maximum of 16-mbit p2rom (only ml610q383/384/385) p2rom capacity: ml610q383 (4m bit), ml610q384 (8m bit), and ml610q385 (16m bit) ? interrupt controller ? 2 non-maskable interrupt sources (inte rnal source: 1, external source: 1) ? 24 maskable interrupt sources (intern al source: 20, external source: 4) ? time base counter ? low-speed time base counter 1 channel ? high-speed time base counter 1 channel ? watchdog timer ? generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) ? timers ? 8 bits 6ch (16-bit configuration available)
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 2/29 ? pwm ? resolution 16 bits 2 channel(igbt control) ? voice output function ? voice synthesis method: 4-bit adpcm2 / 8bit non-linear pcm / straight 8-bit pcm / straight 16-bit pcm ? sampling frequency: 6.4/8/10.7/12.8/16/21.3/25.6/32 khz ? d/a converter ? 12-bit d/a converter ? speaker amplifier output power ? 0.6w(at 5v) ? thermal detection circuit ? disconnection detection circuit ? synchronous serial port ? 2ch ( for ml610q383/384/385, ssio1 is used for p2rom access inside a chip.) ? master/slave selectable ? lsb first/msb first selectable ? 8-bit length/16-bit length selectable ? uart ? half-duplex ? txd/rxd 2 channels ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? i 2 c bus interface ? master function only ? fast mode (400kbit/s@4mhz), standard mode (100kbit/s@4mhz) ? successive approximation type a/d converter ? 10-bit a/d converter ? input: 8ch maximum ? conversion time: 12.75 s per channel ? general-purpose ports 45 maximum ? non-maskable interrupt input port 1ch ? input-only port 6ch ? output-only port 4ch (including secondary functions) ? input/output 18ch (including secondary functions) ? input/output 16ch (including lcd driver functions) ? lcd driver ? 96 dots max. (24 seg 4 com), 1/1 to 1/4 duty ? frame frequency selecable (approx. 64hz, 73hz, 85hz, 102hz, 32hz, 128hz, 171hz, and 256hz) ? lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable ? power supply voltage detect function ? judgment voltages: one of 4 levels ? judgment accuracy: 2% (typ.)
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 3/29 ? reset ? reset through the reset_n pin ? reset by the watchdog timer (wdt) overflow ? clock ? low-speed clock (this lsi can not guarantee the operation withoug low-speed clock) crystal oscillation (32.768 khz) or built-in rc oscillation (32.7khz) ? high-speed clock built-in oscillation (8.192mhz), crystal/ceramic oscillation (8mhz), external clock ? power management ? halt mode: instruction execution by cpu is suspended (peripheral circuits are in operating states). ? stop mode: stop of low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) ? clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) ? block control function: operation of an intact functional block circuit is powerd down. (register reset and clock stop) ? shipment ? 80-pin qfp (p-qfp80-1414-0.80-tk9-mc) ML610Q380-xxxga (blank product: ML610Q380-nnnga) ml610q383-xxxga (blank product: ml610q383-nnnga) ml610q384-xxxga (blank product: ml610q384-nnnga) ml610q385-xxxga (blank product: ml610q385-nnnga) xxx: rom code number ? guaranteed operating range ? operating temperature: ? 40 c to 70 c ? operating voltage: dv dd = p5v dd =2.2v to 5.5v, spv dd = 4.5v to 5.5v, v ref = 4.5v to 5.5v
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 4/29 block diagram block diagram of ML610Q380 figure 1-1 is a block diagram of the ML610Q380. symbols with an asterisk ?*? indicate that each of them is the secondary or tertiary function of the corresponding port. program memory flash 128kbyte ram 2048byte interrupt controller cpu (nx-u8/100) large model timing controller ea sp instruction decoder bus controller instruction register tbc int 4 int 6 8bit timer 6 gpio nmi p20 to p23 int 5 p40 to p43 data-bus test0 reset_n osc power v ddl reset & test alu epsw1-3 psw elr1-3 lr ecsr1-3 dsr/csr pc greg 0-15 v pp v dd v ss outclk* uart rxd0* 1 , rxd1* 1 txd0* 1 , txd1* 1 int 2 lsclk* p34 to p35 on-chip ice p00 to p03 ssio sck0* 1 , sck1* 1 sin0* 1 , sin1* 1 sout0* 1 , sout1* 1 int 2 wdt int 10bit-adc ain0 to ain3* 3 v ref v dd v ss osc0* voicecnt sg int 1 1 int aout i 2 c int 1 sda* 1 scl* 1 pwm int 2 pwm4* 1 pwm5* 1 lcd driver com0 to com3 seg8 to seg23* 2 lcd drive voltage v l1 , v l2 , v l3 xt0 xt1 speaker amp spp spm sg spv dd spv ss spin p44 to p47* 3 p50 to p53 pc0 to pc7* 2 pd0 to pd7* 2 ain4 to ain7* 3 bld pw45ev0* 1 p30 to p33* 3 test1_n osc1* seg0 to seg7 p10 to p11 * 1 secondary or tertiary function * 2 select i/o port or lcd driver * 3 select i/o port or a/d converter input pw45ev1* 1 p5v dd
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 5/29 block diagram of ml610q383/384/385 figure 1-2 is a block diagram of the ml610q383/384/385. symbols with an asterisk ?*? indicate that each of them is the secondary or tertiary function of the corresponding port. * 1 secondary or tertiary function * 2 select i/o port or lcd driver * 3 select i/o port or a/d converter input * 4 for p2rom program memory flash 128kbyte ram 2048byte interrupt controlle r timing controller ea sp instruction decode r bus controller instruction re g iste r tbc int 4 int 6 8bit timer 6 gpio nmi p20 to p23 int 5 data - bus test0 reset _ n osc power v ddl reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v pp dv dd v ss outclk* uart rxd0* 1 , rxd1* 1 txd0* 1 , txd1* 1 int 2 lsclk* p40 to p43 on-chip ice p00 to p03 ssio sck0* 1 , sck1* 4 sin0* 1 , sin1* 4 sout0*, sout1* 4 int 2 wdt int 10bit-adc ain0 to ain3 *3 v ref v dd v ss osc0 * voicecnt sg int 1 1 int aout i 2 c int 1 sda* 1 scl* 1 pwm int 2 pwm4 * 1 pwm5* 1 lcd driver com0 to com3 seg0 to seg7 lcd drive volta g e v l1 , v l2 , v l3 v ddr xt0 xt1 speaker amp spp spm sg spv dd spv ss spin pc0 to pc7 * 2 pd0 to pd7 * 2 ain4 to ain7 3 bld pw45ev0* 1 p30 to p33 *3 int 1 p1 0 to p11 p34 to p35 osc1 * test1 _ n p44 to p47 *3 seg8 to seg23 *2 pw45ev1* 1 gpio 16mbit p2rom * 1 p50(sin1) * 1 p51(sck1) * 1 p52(sout1) * 1 p53 pso psck psi pcsb pvpp cpu (nx-u8/100) large d
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 6/29 pin configuration (ml610q383/384/385) ML610Q380 qfp package product nc: no connection 12 1 2 3 4 5 6 7 8 9 11 54 55 56 57 58 59 60 30 29 28 27 10 14 13 16 15 18 17 20 19 p30/ain0 vref 75 p03/int3 74 p02/int2 73 p01/int1 72 p00/int0 71 p5vdd 70 (nc) 69 p53/txd1 68 p50/sin1 67 vss 66 p23/led3 65 p22/led2 64 p21/led1 63 p20/led0 62 spp 61 80 79 spm 78 77 76 pc3/seg11 pc2/seg10 pc1/seg9 pc0/seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com0 com1 com2 com3 vl3 vl2 vl1 p52/sout1 sg test1_n test0 nmi pd7/seg23 pd6/seg22 pd5/seg21 pd4/seg20 pd3/seg19 pd2/seg18 pd1/seg17 pd0/seg16 pc7/seg15 pc6/seg14 pc5/seg13 pc4/seg12 33 32 31 36 35 34 39 38 37 22 21 40 25 24 23 26 43 44 45 46 47 48 49 50 51 52 53 41 42 p45/ain5 p46/ain6 p47/ain7 p34/pwm4 p35/pwm5 p40/sda p41/scl p42/rxd0 p43/txd0 reset_n vss dvdd vddl xt0 xt1 vpp p10/osc0 p11/osc1 p51/sck1 p44/ain4 spvss spvdd spin aout p32/ain2 p31/ain1 p33/ain3
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 7/29 ml610q383/384/385 qfp package product 12 1 2 3 4 v l 6 7 8 9 11 54 55 56 57 58 59 60 30 29 28 27 10 14 13 16 15 18 17 20 19 p30/ain0 vref 75 p03/int3 74 p02/int2 73 p01/int1 72 p00/int0 71 vddr 70 pvpp 69 test03 68 test00 67 vss 66 p23/led3 65 p22/led2 64 p21/led1 63 p20/led0 62 spp 61 80 79 spm 78 77 76 pc3/seg11 pc2/seg10 pc1/seg9 pc0/seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com0 com1 com2 com3 vl3 vl2 vl1 test02 sg test1_n test0 nmi pd7/seg23 pd6/seg22 pd5/seg21 pd4/seg20 pd3/seg19 pd2/seg18 pd1/seg17 pd0/seg16 pc7/seg15 pc6/seg14 pc5/seg13 pc4/seg12 33 32 31 36 35 34 39 38 37 22 21 40 25 24 23 26 43 44 45 46 47 48 49 50 51 52 53 41 42 p45/ain5 p46/ain6 p47/ain7 p34/pwm4 p35/pwm5 p40/sda p41/scl p42/rxd0 p43/txd0 reset_n vss dvdd vddl xt0 xt1 vpp p10/osc0 p11/osc1 test01 p44/ain4 spvss spvdd spin a out p32/ain2 p31/ain1 p33/ain3
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 8/29 list of pins primary function secondary function tertiary function pin no. pin name i/o description pin name i/o description pin name i/o description 12,67 vss ? negative power supply pin ? ? ? ? ? ? 13 dv dd ? positive power supply pin ? ? ? ? ? ? 14 v ddl ? power supply for internal logic (internally generated) ? ? ? ? ? ? 60 spv ss ? negative power supply pin for built-in speaker amplifier ? ? ? ? ? ? 59 spv dd ? positive power supply pin for built-in speaker amplifier ? ? ? ? ? ? p5v dd *1 ? for p50 to p53 power supply pin ? ? ? ? ? ? 71 v ddr *2 ? for p2rom sioport power supply pin ? ? ? ? ? ? 70 pvpp *2 ? high voltage power supply pin of data to building p2rom ? ? ? ? ? ? 17 v pp ? power supply pin for flash rom ? ? ? ? ? ? 22 v l1 ? power supply pin for lcd bias ? ? ? ? ? ? 23 v l2 ? power supply pin for lcd bias ? ? ? ? ? ? 24 v l3 ? power supply pin for lcd bias ? ? ? ? ? ? 54 test0 i/o input/output pin for testing ? ? ? ? ? ? 55 test1_n i/o input/output pin for testing ? ? ? ? ? ? 11 reset_n i reset input pin ? ? ? ? ? ? 15 xt0 i low-speed clock oscillation pin ? ? ? ? ? ? 16 xt1 o low-speed clock oscillation pin ? ? ? ? ? ? 57 aout o line output ? ? ? ? ? ? 58 spin i analog input to the built-in speaker amplifier ? ? ? ? ? ? 56 sg o reference power supply pin of the built-in speaker amplifier ? ? ? ? ? ? 62 spp o positive output pin of the built-in speaker amplifier ? ? ? ? ? ? 61 spm o negative output pin of the built-in speaker amplifier ? ? ? ? ? ? 76 v ref i reference power supply pin of successive-approximation type adc ? ? ? ? ? ? 53 nmi i input port, non-maskable interrupt ? ? ? ? ? ? 72 p00/exi0/ pw45ev0 i input port / external interrupt / pw45ev0 input ? ? ? ? ? ? 73 p01/exi1 i input port / external interrupt ? ? ? ? ? ? 74 p02/exi2/ rxd0 i input port / external interrupt uart0 data input ? ? ? ? ? ? 75 p03/exi3/ rxd1 i input port / external interrupt / uart1 data input ? ? ? ? ? ? 18 p10 i input port osc0 i high-speed clock oscillation pin ? ? ? 19 p11 i input port osc1 o high-speed clock oscillation pin ? ? ? 63 p20/ led0 o output port / led drive lsclk o low-speed clock output ? ? ? 64 p21/ led1 o output port / led drive outclk o low-speed clock output ? ? ? 65 p22/ led2 o output port / led drive ? ? ? tm9out o timer9 output 66 p23/ led3 o output port / led drive ? ? ? tmbout o timerb output
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 9/29 primary function secondary function tertiary function pin no. pin name i/o description pin name i/o description pin name i/o description 77 p30/ pw45ev1 /ain0 i/o input/output port / pw45ev1 input / successive approximation type adc input ? ? ? ? ? ? 78 p31/ain1 i/o input/output port / successive approximation type adc input ? ? ? ? ? ? 79 p32/ain2 i/o input/output port / successive approximation type adc input ? ? ? ? ? ? 80 p33/ain3 i/o input/output port / successive approximation type adc input ? ? ? ? ? ? 5 p34 i/o input/output port ? ? ? pwm4 o pwm4 output 6 p35 i/o input/output port ? ? ? pwm5 o pwm5 output 7 p40 i/o input/output port sda i/o i 2 c data input/output sin0 i ssio0 data input 8 p41 i/o input/output port scl i/o i 2 c clock input/output sck0 i/o ssio0 synchronous clock input/output 9 p42 i/o input/output port rxd0 i uart0 data input sout0 o ssio0 data output 10 p43 i/o input/output port txd0 o uart0 data output pwm4 o pwm4 output 1 p44/ t0p4ck/ ain4 i input port / timer0 external clock input / pwm4 external clock input/ successive approximation type adc input ? ? ? sin0 i ssio0 data input 2 p45/ t1p5ck/ ain5 i input port / timer1 external clock input / pwm5 external clock input/ successive approximation type adc input ? ? ? sck0 i/o ssio0 synchronous clock input/output 3 p46/ t8ack/ ain6 i input port / timer8 external clock input / timera external clock input / successive approximation type adc input ? ? ? sout0 o ssio0 data output 4 p47/ t9bck/ ain7 i input port / timer9 external clock input / timerb external clock input / successive approximation type adc input ? ? ? pwm5 o pwm5 output p50 *1 68 testo0 *2 i/o input/output port ? ? ? sin1 i ssio1 data input p51 *1 20 testo1 *2 i/o input/output port ? ? ? sck1 i/o ssio1 synchronous clock input/output p52 *1 21 testo2 *2 i/o input/output port rxd1 i uart1 data input sout1 o ssio1 data output p53 *1 69 testo3 *2 i/o input/output port txd1 o uart1 data input ? ? ? 28 com0 o lcd common pin ? ? ? ? ? ? 27 com1 o lcd common pin ? ? ? ? ? ? 26 com2 o lcd common pin ? ? ? ? ? ? 25 com3 o lcd common pin ? ? ? ? ? ? 29 seg0 o lcd segment pin ? ? ? ? ? ? 30 seg1 o lcd segment pin ? ? ? ? ? ? 31 seg2 o lcd segment pin ? ? ? ? ? ? 32 seg3 o lcd segment pin ? ? ? ? ? ?
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 10/29 primary function secondary function tertiary function pin no. pin name i/o description pin name i/o description pin name i/o description 33 seg4 o lcd segment pin ? ? ? ? ? ? 34 seg5 o lcd segment pin ? ? ? ? ? ? 35 seg6 o lcd segment pin ? ? ? ? ? ? 36 seg7 o lcd segment pin ? ? ? ? ? ? 37 pc0 i/o input/output port seg8 o lcd segment pin ? ? ? 38 pc1 i/o input/output port seg9 o lcd segment pin ? ? ? 39 pc2 i/o input/output port seg10 o lcd segment pin ? ? ? 40 pc3 i/o input/output port seg11 o lcd segment pin ? ? ? 41 pc4 i/o input/output port seg12 o lcd segment pin ? ? ? 42 pc5 i/o input/output port seg13 o lcd segment pin ? ? ? 43 pc6 i/o input/output port seg14 o lcd segment pin ? ? ? 44 pc7 i/o input/output port seg15 o lcd segment pin ? ? ? 45 pd0 i/o input/output port seg16 o lcd segment pin ? ? ? 46 pd1 i/o input/output port seg17 o lcd segment pin ? ? ? 47 pd2 i/o input/output port seg18 o lcd segment pin ? ? ? 48 pd3 i/o input/output port seg19 o lcd segment pin ? ? ? 49 pd4 i/o input/output port seg20 o lcd segment pin ? ? ? 50 pd5 i/o input/output port seg21 o lcd segment pin ? ? ? 51 pd6 i/o input/output port seg22 o lcd segment pin ? ? ? 52 pd7 i/o input/output port seg23 o lcd segment pin ? ? ? *1 it applies to ML610Q380. *2 it applies to ml610q383/384/385.
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 11/29 supplementation: only ml610q383/384/385. ( ML610Q380 doesn't correspond.) p50 to p53 is connected with building p2rom by the inside of the chip into, and each function exists. (the external pin name becomes testo0 to testo3. please give the external terminal processing to me as an opening.) connected with p2rom content is shown as follows. the pins of built-in p2rom explanation pso serial-data output connected with p50/sin1 (tertiary functional) inside. psck serial-data output connected with p51/sck1 (tertiary functional) inside psi serial-data input connected with p52/sout1 (tertiary functional) inside pcsb chip select input connected with p53 (primary functional) inside
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 12/29 pin description pin name i/o description primary/ secondary logic power supply v ss ? negative power supply pin ? ? dv dd ? positive power supply pin ? ? v ddl ? positive power supply pin for internal logic (internally generated). connect capacitors (c l ) (see measuring circuit 1) between this pin and v ss . ? ? spv ss ? negative power supply pin for built-in speaker amplifier ? ? spv dd ? positive power supply pin for built-in speaker amplifier ? ? p5v dd ? port5 if power supply pin.(only ML610Q380) supply the power supply of the spi memory when you connect the spi memory with external.besides, supply the same level as dvdd. ? ? v ddr p2rom built in positive power supply(inner generation) pin. (only ml610q383/384/385)connect capacitors (c r ) (see measuring circuit 1) between this pin and v ss . ? ? pvpp ? high voltage power supply pin of the data write to building p2r om into. besides, fix at the vss level. ? ? v pp ? power supply pin for programming flash rom. ? ? v l1 ? power supply pins for lcd bias (external input) ? ? v l2 ? power supply pins for lcd bias (external input) ? ? v l3 ? power supply pins for lcd bias (external input) ? ? test test0 i/o input/output pin for testing. has a pull-down resistor built in. ? positive test1_n i/o input/output pin for testing. has a pull-up resistor built in. ? negative system reset_n i reset input pin. when this pin is set to a ? l ? level, the device is placed in system reset mode and the internal circuit is initialized. if after that this pin is set to a ? h ? level, program execution starts. this pin has a pull-up resistor built in. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal oscillator (see measuring circuit 1) is connected to this pin. capacitors c dl and c gl are connected across this pin and v ss as required. ? ? osc0 i secondary ? osc1 o external input pin for high-speed clock. this function is allocated to the secondary function of the p10 pin. secondary ? lsclk o low-speed clock output. this function is allocated to the secondary function of the p20 pin. secondary ? outclk o high-speed clock output. this function is allocated to the secondary function of the p21 pin. secondary ? general-purpose input port p00 to p03 i p10 to p11 i general-purpose input ports. provided with a secondary function for each port. cannot be used as ports if their secondary functions are used. primary positive general-output input port p20 to p23 o general-purpose output ports.provided with a secondary function for each port. cannot be used as ports if their secondary functions are used. primary positive
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 13/29 pin name i/o description primary/ secondary/ tertiary logic general-purpose input/output port p30 to p35 p40 to p47 p50 to p53 i/o general-purpose input/output ports.provided with a secondary function for each port. cannot be used as ports if their secondary functions are used. pc0 to pc7 pd0 to pd7 i/o general-purpose input/output ports.provided with a lcd segment for each port. cannot be used as ports if lcd segment are used. primary positive uart txd0 o uart0 data output pin. allocated to the secondary function of the p43 pin. secondary positive rxd0 i uart0 data input pin. allocated to the primary function of the p02 pin and the secondary function of the p42 pin. secondary positive txd1 o uart1 data output pin. allocated to the secondary function of the p53 pin. secondary positive rxd1 i uart1 data input pin. allocated to the primary function of the p03 pin and the secondary function of the p52 pin. secondary positive i 2 c bus interface sda i/o i 2 c data input/output pin. this pin is used as the secondary function of the p40 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive scl i/o i 2 c clock output pin. this pin is used as the secondary function of the p41 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive synchronous serial (ssio) sin0 i synchronous serial data input pin. allocated to the tertiary function of the p40 pin and p44 pin. tertiary positive sck0 i/o synchronous serial clock input/output pin. allocated to the tertiary function of the p41 pin and p45 pin. tertiary ? sout0 o synchronous serial data output pin. allocated to the tertiary function of the p42 pin and p46 pin. tertiary positive sin1 i synchronous serial data input pin. allocated to the tertiary function of the p50 pin . tertiary positive sck1 i/o synchronous serial clock input/output pin. allocated to the tertiary function of the p51 pin. tertiary ? sout1 o synchronous serial data output pin. allocated to the tertiary function of the p52 pin. tertiary positive pwm pwm4 o pwm4 output pin. allocated to the tertiary function of the p34 and p43 pins. tertiary positive pwm5 o pwm5 output pin. allocated to the tertiary function of the p35and p47 pins. tertiary positive t0p4ck i external clock input pin for timer 0 and pwm4. allocated to the primary function of the p44 pin. primary ? t1p5ck i external clock input pin for timer 1 and pwm5. allocated to the primary function of the p45 pin. primary ? pw45ev0 pw45ev1 i control start /stop pin for pwm4 and pwm5. allocated to the primary function of the p00 pin and p30 pin. primary ?
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 14/29 pin name i/o description primary/ secondary/ tertiary logic external interrupt nmi i external non-maskable interrupt input pin. the interrupt occurs on both the rising and falling edges. primary positive/ negative exi0?exi3 i external maskable interrupt input pins. it is possible, for each bit, to specify whether the interrupt is enabled and select the interrupt edge by software. allocated to the primary function of the p00?p03 pins. primary positive/ negative timer t0p4ck i external clock input pin for timer 0 and pwm4. allocated to the primary function of the p44 pin. primary ? t1p5ck i external clock input pin for timer 1 and pwm5. allocated to the primary function of the p45 pin. primary ? t8ack i external clock input pin for timer 8 and timer a. allocated to the primary function of the p46 pin. primary ? t9bck i external clock input pin for timer 9 and timer b. allocated to the primary function of the p47 pin. primary ? tm9out o timer9 overflow output pin. allocated to the secondary function of the p22 pin. tertiary positive tmbout o timerb overflow output pin. allocated to the secondary function of the p23 pin. tertiary positive led drive led0-led3 o pins for led driving. allocated to the primary function of the p20?p23 pins. primary positive/ negative voice output function aout o line output pin. the case of built-in speaker amplifier use, connect with the spin pin. ? ? spin i analog input pin of the internal speaker amplifier. ? ? sg o reference voltage output pin of the internal speaker amplifier. ? ? spp o positive output pin of the internal speaker amplifier. ? ? spm o negative output pin of the internal speaker amplifier. ? ? successive-approximation type a/d converter v ref i reference power supply pin for successive approximation type a/d converter. ? ? ain0?ain7 i analog inputs to ch0?ch7 of the successive-approximation type a/d converter. allocated to the secondary function of the p30 to p33 and p44 to p47 pins. lcd driver com0 to com3 o lcd common output pins. ? ? seg0 to seg7 o lcd segment output pins. ? ? seg8 to seg23 o lcd segment output pins. allocated to the secondary function of the pc0 to pc7 and pd0 to pd7 pins. ? ?
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 15/29 termination of unused pins how to terminate unused pins pin recommended pin termination v pp open reset_n open test0 open test1_n open v ref connect to dv dd spv dd connect to dv dd spv ss connect to dv ss p5v dd *1 connect to dv dd aout open spin open sg open spp open spm open p00 to p03 connect dv dd or v ss p10 to p11 connect dv dd or v ss p20 to p23 open p30 to p33 (ain0 to ain3) open p34 to p35 open p40 to p43 open p44 to p47 (ain4 to ain7) open p50 to p53 open com0 to com3 open seg0 to seg7 open pc0 to pc7 seg8 to15 open pd0 to pd7 seg16 to 23 open note: *1. only ML610Q380 is applied. for unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs and left open, the supply current may become excessively large. therefore, it is recommended to configure those pins as either inputs with a pull-down resistor/pull-up resistor or outputs.
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 16/29 electrical characteristics absolute maximum ratings (v ss = spv ss = 0v) parameter symbol condition rating unit power supply voltage 1 dv dd ta = 25 c ? 0.3 to +7.0 v power supply voltage 2 spv dd ta = 25 c ? 0.3 to +7.0 v power supply voltage 3 v pp ta = 25 c ? 0.3 to +9.5 v power supply voltage 4 v l1 ta = 25 c ? 0.3 to +2.33 v power supply voltage 5 v l2 ta = 25 c ? 0.3 to +4.66 v power supply voltage 6 v l3 ta = 25 c ? 0.3 to +7.0 v power supply voltage 7 p5v dd ta=25 -0.3 +7.0 v reference voltage v ref ta = 25 c ? 0.3 to dv dd +0.3 v analog input voltage v ai ta = 25 c ? 0.3 to dv dd +0.3 v input voltage v in ta = 25 c ? 0.3 to dv dd +0.3 v output voltage v out ta = 25 c ? 0.3 to dv dd +0.3 v output current 1 i out1 port3,4,5,c,d,com,seg, ta = 25 c ? 12 to +11 ma output current 2 i out2 port2,9 ta = 25 c ? 12 to +20 ma power dissipation pd ta = 25 c 1 w storage temperature t stg D ? 55 to +150 c recommended operating conditions (v ss = spv ss = 0v) parameter symbol condition range unit operating temperature t op D ? 40 to +70 c dv dd D 2.2 to 5.5 p5v dd D 2.2 to 5.5 operating voltage spv dd D 4.5 to 5.5 v operating frequency (cpu) f op D 30k to 8.4m hz low-speed crystal oscillation frequency f xtl D 32.768k hz capacitor externally connected to dv dd pin c v D 10 ?< 30% f capacitor externally connected to spv dd pin c sv D 1 ?< 30% f capacitor externally connected to v pp pin c 1 D 1 ?< 30% f capacitor externally connected to v ref pin c av D 1 ?< 30% f c dl 12 to 25 low-speed crystal oscillation external capacitor c gl use 32.768khz crystal oscillator dt-26s (daishinku corp.) 12 to 25 pf high-speed crystal/ceramic oscillation frequency f xth D 8m/8.192m hz c dh D 47 30% high-speed crystal oscillation external capacitor* c gh D 47 30% pf capacitor externally connected to v ddl pin c l D 10 30% f capacitor externally connected to v ddr pin c r D 1 30% f capacitor externally connected to v l1,2,3 pin c l1,2,3 D 0.22 ?< 30% f capacitor externally connected to aout pin ? spin pin c aosp D 0.022 30% f capacitor externally connected to sg pin c sg D 0.1 30% f * cgh and cdh are built into, external capacity is unnecessary for cstls8m00g56-a0 (made by murata mfg.).
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 17/29 flash memory operating conditions (v ss = spv ss = 0v) parameter symbol condition range unit operating temperature t op at write/erase 0 to +40 c dv dd at write/erase 2.7 to 5.5 v ddl at write/erase *1 2.5 to 2.75 operating voltage v pp at write/erase 1 7.7 to 8.3 v maximum rewrite count c epp D 80 times data retention period y dr D 10 years * 1 : at the writing of a flash rom, it is necessary to supply voltage to v ddl pin within the limits of the above-mentioned regulation. pulldown resistance is built in the v pp pin. dc characteristics (1 of 6) (dv dd = p5v dd =spv dd = 2.2 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit high-speed crystal oscillation start time t xth D D 2 20 ms low-speed crystal oscillation start time* 2 t xtl D D 0.6 2 s low-speed rc oscillator frequency f lcr D typ -5% 32.7k typ +5% hz pll oscillation frequency f pll lsclk=32.768khz 100 clock average typ -1% 8.192 typ +1% mhz reset pulse width p rst D 100 D D reset noise rejection pulse width p nrst D D D 0.4 s 1 * 1 : use 32.768khz crystal oscillator dt-26 (daishinku) with capacitance c gl /c dl 12pf. reset reset_n reset by reset_n pin p rst vil1 vil1
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 18/29 dc characteristics (2 of 6) (dv dd = p5v dd =spv dd = 4.5 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit line amplifier output voltage range v ad at 10k ? load for v ss spv dd 1/6 ? spv dd 5/6 v sg output voltage v sg D 0.95 spv dd /2 spv dd /2 1.05 spv dd /2 v sg output resistance r sg D 57 96 135 k spm, spp output load resistance r lsp D D 8 D speaker amplifier output power p spo1 spv dd = 5.0v, f = 1khz, rspo = 8 , thd 10% at spin input ? 0.6 ? w output offset voltage between spm and spp with no signal present v of spv dd =5.0v, spin ? spm gain = +0db with a load of 8 ? 50 ? +50 mv 1 dc characteristics (3 of 6) (dv dd = p5v dd =spv dd = 2.2 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) parameter symbol condition min. typ. max. unit meas uring circuit ld3 to 0 = 0h 2.35 ld3 to 0 = 3h 2.80 ld3 to 0 = 9h 3.70 bld threshold voltage v bld ta = 25 c ld3 to 0 = fh typ. -2% 4.60 typ. +2% v 1 dc characteristics (4 of 6) (dv dd = p5v dd =spv dd = 2.2 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) parameter symbol condition min. typ. max. unit meas uring circuit supply current 1 idd1 cpu: in stop state low-speed/high-speed oscillation: stopped dv dd =3.0v D 0.7 22 supply current 2 idd2 cpu: in halt state (ltbc,wbc: operating *2 ) high-speed oscillation: stopped dv dd =3.0v D 2.0 24 supply current 3 idd3 cpu: running at 32khz* 1 high-speed oscillation: stopped dv dd =3.0v D 13 42 a supply current 4 idd4 cpu: running at 8.192mhz crystal/ceramic oscillating mode* 2 dv dd = spv dd = 5.0v D 5 8 ma 1 * 1 : case when the cpu operating rate is 100% (with no halt state) * 2 : significant bits of blkcon0 to blkcon4 registers are all ?1?.
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 19/29 dc characteristics (5 of 6) (dv dd = p5v dd =spv dd = 2.2 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit voh1 ioh1 = ? 0.5ma dv dd ? 0.5 D D output voltage 1 (p20 to p23) (p30 to p35) (p40 to p47) (p50 to p53) (pc0 to pc7) (pd0 to pd7) vol1 iol1 = +0.5ma D D 0.5 output voltage 2 (p20?p23) vol2 when led drive mode is selected iol2 = +10ma dv dd 4.5v D D 0.5 output voltage 3 (p40?p41) vol3 when i 2 c mode is selected iol3 = +3ma D D 0.4 v 2 iooh voh = dv dd (in high-impedance state) D D 1 output leakage current (p20 to p23) (p30 to p35) (p40 to p47) (p50 to p53) (pc0 to pc7) (pd0 to pd7) iool vol = v ss (in high-impedance state) ? 1 D D a 3 vl3=3v vol=0.3v 15 40 D iol1 vl3=5v vol=0.5v 100 200 D vl3=3v voh=2.7v D -30 -15 output current 1 com0 to com3 ioh1 vl3=5v voh=4.5v D -90 -45 vl3=3v vol=0.3v 15 30 D iol2 vl3=5v vol=0.5v 70 150 D vl3=3v voh=2.7v D -13 -6 output current 2 seg0 to seg23 ioh2 vl3=5v voh=4.5v D -40 -20 a 3 iih1 vih1 = dv dd 0 D 1 input current 1 (reset_n) (test1_n) iil1 vil1 = v ss ? 1500 ? 300 ? 20 iih2 vih2 = dv dd (when pulled down) 2 30 250 iil2 vil2 = v ss (when pulled up) ? 250 ? 30 ? 2 iih2z vih2 = dv dd (in high-impedance state) D D 1 input current 2 (nmi) (p00 to p03) (p10 to p11) (p30 to p35) (p40 to p47) (p50 to p53) (pc0 to pc7) (pd0 to pd7) iil2z vil2 = v ss (in high-impedance state) -1 D D iih3 vih3 = dv dd 20 300 1500 input current 3 (test0) iil3 vil3 = v ss -1 D D a 4
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 20/29 dc characteristics (6 of 6) (dv dd = p5v dd =spv dd = 2.2 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit vih1 D 0.7 dv dd D dv dd input voltage 1 (reset_n) (test0) (test1_n) (nmi) (p00 to p03) (p10 to p11) (p30 to p35) (p40 to p43) (p50 to p53) (pc0 to pc7) (pd0 to pd7) vil1 D 0 D 0.3 dv dd v 5 input pin capacitance (reset_n) (test0) (test1_n) (nmi) (p00 to p03) (p10 to p11) (p30 to p35) (p40 to p43) (p50 to p53) (pc0 to pc7) (pd0 to pd7) cin f = 10khz v rms = 50mv ta = 25 c D D 10 pf D
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 21/29 measuring circuits measuring circuit 1 measuring circuit 2 1. only ML610Q380 is applied. 2. only ml610q383/384/385 is applied. input pins v vih vil output pins (*1) input logic circuit to determine the specified measuring conditions. (*2) measured at the specified output pins. ( *2 ) ( *1 ) dv dd v ref v ddl spv ss v l1 v l2 v l3 v ddr 2 v ss spv dd p5v dd 1 v l2 v l1 v l3 c l3 c l2 c l1 32.768khz crystal c gl c dl xt0 xt1 8mhz crystal c gh c dh osc0 osc1 a dv dd v ref v ddl c l c v spv ss v ddr 2 c r spv dd sg c sg v ss p5v dd 1 c v 10 f c l 10 f c r 10 f c sg 0.1 f c gl 12pf c dl 12pf c gh 47pf c dh 47pf c l1 ,c l2 ,c l3 0.22 f 32.768khz crystal oscillator (dmx-26s daishinku corp.) 8mhz crystal oscillator cstls8m00g56-a0 murata corp. it has built-in cgh, and cdh
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 22/29 measuring circuit 3 measuring circuit 4 measuring circuit 5 1. only ML610Q380 is applied. 2. only ml610q383/384/385 is applied. input pins vih vil output pins *1: input logic circuit to determine the specified measuring conditions. (*1) waveform monitoring dv dd v ref v ddl spv ss v ddr 2 spv dd v ss p5v dd 1 input pins a vih vil output pins *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) (*1) dv dd v ref v ddl spv ss p5v dd 1 v ss spv dd v ddr 2 input pins a output pins *3: measured at the specified input pins. (*3) dv dd v ref v ddl spv ss v ddr 2 spv dd v ss p5v dd 1
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 23/29 ac characteristics (external interrupt) (dv dd = p5v dd =spv dd = 2.2 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation 2.5 sysclk D 3.5 sysclk s t nul p00?p03 (rising-edge interrupt) p00?p03 (falling-edge interrupt) nmi, p00?p03 (both-edge interrupt) t nul t nul
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 24/29 ac characteristics (synch ronous serial port) (dv dd = p5v dd =spv dd = 2.2 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) parameter symbol condition min. typ. max. unit high-speed oscillation stopped 10 D D s sck input cycle (slave mode) t scyc during high-speed oscillation 500 D D ns sck output cycle (master mode) t scyc D D sck (*1) D sec high-speed oscillation stopped 4 D D s sck input pulse width (slave mode) t sw during high-speed oscillation 200 D D ns sck output pulse width (master mode) t sw D sck (*1) 0.4 sck (*1) 0.5 sck (*1) 0.6 sec sout output delay time (slave mode) t sd D D D 180 ns sout output delay time (master mode) t sd D D D 80 ns sin input setup time (slave mode) t ss D 50 D D ns sin input hold time t sh D 50 D D ns *1: clock period selected by s0ck3?0 of the serial port 0 mode register (sio0mod1) t sd sck0* sin0* sout0 *: indicates the secondary function of the corresponding port. t sd t ss t sh t sw t sw t scyc
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 25/29 ac characteristics (i 2 c bus interface: standard mode 100khz) (dv dd = p5v dd =spv dd = 2.2 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 100 khz scl hold time (start/restart condition) t hd:sta ? 4.0 ? ? s scl ?l? level time t low ? 4.7 ? ? s scl ?h? level time t high ? 4.0 ? ? s scl setup time (restart condition) t su:sta ? 4.7 ? ? s sda hold time t hd:dat ? 0 ? ? s sda setup time t su:dat ? 0.25 ? ? s sda setup time (stop condition) t su:sto ? 4.0 ? ? s bus-free time t buf ? 4.7 ? ? s ac characteristics (i2c bus interface: fast mode 400khz) (dv dd = p5v dd =spv dd = 2.2 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 400 khz scl hold time (start/restart condition) t hd:sta ? 0.6 ? ? s scl ?l? level time t low ? 1.3 ? ? s scl ?h? level time t high ? 0.6 ? ? s scl setup time (restart condition) t su:sta ? 0.6 ? ? s sda hold time t hd:dat ? 0 ? ? s sda setup time t su:dat ? 0.1 ? ? s sda setup time (stop condition) t su:sto ? 0.6 ? ? s bus-free time t buf ? 1.3 ? ? s p41/scl p40/sda start condition restart condition stop condition t buf t hd:sta t low t high t su:sta t hd:sta t su:dat t hd:dat t su:sto
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 26/29 electrical characteristics of successi ve approximation type a/d converter (dv dd = p5v dd =spv dd = 4.5 to 5.5v, v ss = spv ss =0v, ta= ? 40 to +70 c, unless otherwise specified) parameter symbol condition min. typ. max. unit resolution n D D D 10 bits integral non-linearity error idl 2.7v v ref 5.5v ? 4 D +4 differential non-linearity error dnl 2.7v v ref 5.5v ? 3 D +3 zero-scale error v off D ? 4 D +4 full-scale error fse D ? 4 D +4 lsb input impedance r i D D D 5k reference voltage v ref 4.5 D dv dd v conversion time t conv hsclk=3.0m to 8.4mhz D 102 D /ch : period of high-speed clock (hsclk) a dv dd v ref v ddl v ss analog input 10 f - r i 5k ain0 ain7 1 f 0.1 f + 10 f reference voltage v ddr 10 f
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 27/29 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact lapis semiconductor?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl610q380full-01 ML610Q380/ml610q383/ml610q384/ml610q385 28/29 revision history page document no. date previous edition current edition description fedl610q380full-01 mar 09, 2012 ? ? formal edition 1
fedl610q380full-01 ML610Q380/ml610q385 29/29 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failur e or malfunction of which may result in a direct threat to human life or create a risk of human injury (suc h as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011-2012 lapis semiconductor co., ltd.

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