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future technology devices international ltd (ftdi) unit 1, 2 seaward place, centurion business park, glasgow, g41 1hh, united kingdom tel.: +44 (0) 141 429 2777 fax: + 44 (0) 141 429 2758 e - mail (support): support1@ftdichip.c om web: http://www.vinculum.com neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or re produced in any material or electronic form without the prior written consent of the copyright holder. this product and its documentation are supplied on an as - is basis and no warranty as to their suitability for any particular purpose is either made or implied. future techn ology devices international ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. your statutory rights are not affected. this product or any variant of it is not intended for use in any medical appliance, device or system in which the fail ure of the product might reasonably be expected to result in personal injury. this document provides preliminary information that may be subject to change without notice. no freedom to use patents or other intellectual property rights is implied by the pub lication of this document. future technology devices international ltd, unit 1, 2 seaward place, centurion business park, glasgow, g41 1hh , united kingdom. scotland registered number: sc136640 copyright ? 2010 future technology devices international limited future technology devices international ltd. v2dip2 - 48 vnc2 - 48 development module datasheet document reference no.: ft_000237 version 1.01 issue date: 2010 - 0 5 - 2 5
` copyright ? 2010 future technology devices international limited 1 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 1 introduction v2dip2 - 48 module is designed to allow rapid development of designs using the vnc2 - 48q ic. the v2dip1 - 48 is supplied as a pcb designed to fit into a 40 pin 0.6 wide, 0. 1 pitch dip socket .the module provides access to the ua r t , parallel fifo, and spi interface pins o f the vnc2 - 48q device, via its io bus pins. two usb ports are accessed via type a usb connectors. figure 1 . 1 - v2dip2 48 the vnc2 is the second of f t di s v inculum family of embedded dual usb host controller devices. the vnc2 device provides usb host i nterfac ing capability for a variety of different usb device classes including support for boms (bulk only mass storage), printer, hid (human interface devices). for mass storage devices such as usb flash drives, vnc2 also transparently handles the f a t f ile structure . c ommunicat ion with non usb devices such as a low cost microcontroller is accomplished via either ua r t , spi or parallel fifo interfaces. the vnc2 provides a new cost effective solution for providing usb host capability into products that previously did not have the hardware resources available. the vnc2 supports the capability to enable customers to develop custom firmware using the vincul um ii development software tool suite. the development tools support compiler, linker and debugger tools complete within an integrated development environment (ide). the vinculum - ii vnc2 family of devices are available in pb - free (rohs compliant) 32 - l ead lqfp, 32 - l ead qfn, 48 - l ead lqfp, 48 - l ead qfn, 64 - lead lqfp and 64 - l ead qfn packages .
` copyright ? 2010 future technology devices international limited 2 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 table of contents 1 introduction ................................ ................................ ............................ 1 2 features ................................ ................................ ................................ . 3 3 pin out and signal description ................................ ............................ 4 3.1 module pin out ................................ ................................ ................................ .... 4 3.2 pin signal description ................................ ................................ ........................ 6 3.3 i/o configuration using the jumper pin header ................................ ............. 8 3.4 default interface i/o pin configuration ................................ .............................. 9 3.5 uart interface ................................ ................................ ................................ ... 10 3.5.1 signal description C uart interface ................................ ................................ .............. 10 3.6 serial peripheral interface (spi) ................................ ................................ ....... 11 3.6.1 signal description - spi slave ................................ ................................ ........................ 11 3.6.2 signal description - spi master ................................ ................................ ...................... 11 3.7 parallel fifo interface - asynchronous mode ................................ .................. 12 3.7.1 signal description - parallel fifo interface ................................ ................................ . 12 3.7.2 timing diagram C asynchronous fifo mode read and write cycle ..................... 13 3.8 parallel fifo interface - synchronous mode ................................ .................... 14 3.8.1 timing diagram C synchronous fifo mode read and write cycle ....................... 15 3.9 debugger interface ................................ ................................ ............................ 17 3.9.1 signal description - debugger interface ................................ ................................ ...... 17 4 firmware ................................ ................................ .............................. 18 4.1 firmware support ................................ ................................ .............................. 18 4.2 available firmware ................................ ................................ ............................ 18 4.3 firmware upgrades ................................ ................................ ........................... 18 5 mechanical dimensions ................................ ................................ ...... 19 6 schematic diagram ................................ ................................ ............. 20 7 contact information ................................ ................................ ............. 21 appendix a C references ................................ ................................ ............................ 22 appendix b C list of figures and tables ................................ ................................ .... 23 list of figures ................................ ................................ ................................ ............... 23 list of tables ................................ ................................ ................................ ................ 23 appendix c C revision history ................................ ................................ ................... 24
` copyright ? 2010 future technology devices international limited 3 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 2 features the v2dip2 - 48 incorporates the following features : uses ftdis vnc2 - 48q embedded usb host controller ic device two usb a type socket to interface with usb peripheral devices jumper selectable uart, parallel fifo or spi mcu interfaces uart, parallel fifo and spi interfaces can be programmed to a choice of available i/o pins single 5v supply input from dil connectors or 5v supplied via usb vbus slave interface or debugger module. auxiliary 3.3 v / 200 ma power output to external logic. all vnc2 signals available on 0. 6 wid e. 0.1 pitch dil male connectors. power and traffic indicator leds v2dip2 - 48 is a pb - free, rohs complaint development module. debugger interface pin available on dil pins or via 6 way male header which interfaces to separate debugger module. firmware upgrades via uart or debug ger interface pin header foc s oftware development suite of tools to create customised firmware includes a compiler , linker , debugger and assembler all wrapped up in an easy to use integrated design environment gui.
` copyright ? 2010 future technology devices international limited 4 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3 pin out and signal description 3.1 module pin out figure 3 . 1 - v2dip2 48 module pin out (top view)
` copyright ? 2010 future technology devices international limited 5 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 figure 3 . 2 - v2dip2 48 module pin out (bottom view)
` copyright ? 2010 future technology devices international limited 6 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3.2 pin signal description pin no. (vdip2) name (vdip2) pin name on pcb t ype description j1 - 1 (1) nc - - not connected j1 - 2 (2) 5v0 5v0 pwr input 5.0v module supply pin. this pin can be used to provide the 5.0v in put to the v2dip2 - 48 when the v2dip2 - 48 is not powered from the usb connector (vbus) or the debugger interface. also connected to dil connector pins j1 - 2, j1 - 3 and j1 - 9 and j3 - 6 . j1 - 3 (3) 5v0 5v0 pwr input 5.0v module supply pin. this pin can be used to provide the 5.0v in put to the v2dip2 - 48 when the v2dip2 - 48 is not powered from the usb connector (vbus) or the debugger interface. also connected to dil connector pins j1 - 2, j1 - 3 and j1 - 9 and j3 - 6 . j1 - 4 (4) iobus5 io5 output usb port 1 traffic activity indicator led. this pin is hard wired to a green led on board the pcb. it is also brought out onto this pin which allows for the possibility of brin g ing out an additional led traffic indicator out of the vdip2 board. for example, if the vdip2 usb connector is brought out onto an ins trument front panel, an activity led could be mounted along side it. j1 - 5 (5) iobus6 io6 output usb port 2 traffic activity indicator led. this pin is hard wired to a green led on board the pcb. it is also brought out onto this pin which allows for the possibility of bringing out an additional led traffic indicator out of the vdip2 board. for example, if the vdip2 usb connector is brought out onto an instrument front panel, an activity led could be mounted along side it. j1 - 6 (6) iobus7 io7 i/o 5v safe b idirectional data / control bus bit 7 j1 - 7 (7) iobus8 io8 i/o 5v safe b idirectional data / control bus bit 8 j1 - 8 (8) iobus9 io9 i/o 5v safe b idirectional data / control bus bit 9 j1 - 9 (9) 5v0 5v0 pwr 5.0v module supply pin. this pin can be used to provide the 5.0v in put to the v2dip2 - 48 when the v2dip2 - 48 is not powered from the usb connector (vbus) or the debugger interface. also connected to dil connector pins j1 - 2, j1 - 3 and j1 - 9 and j3 - 6 . j1 - 10 (10) iobus10 io10 i/o 5v safe b idirectional data / control bus bit 10 j1 - 1 1 (11) iobus11 io11 i/o 5v safe bidirectional data / control bus bit 11 j1 - 12 (12) gnd gnd pwr module ground supply pin j1 - 13 (13) gnd gnd pwr module ground supply pin j1 - 14 (14) iobus12 io12 i/o 5v safe bidirectional data / control bus bit 12 j1 - 15 (15) gnd gnd pwr module ground supply pin j1 - 16 (16) iobus13 io13 i/o 5v safe bidirectional data / control bus bit 13 j1 - 17 (17) iobus14 io14 i/o 5v safe bidirectional data / control bus bit 14 j1 - 18 (18) iobus15 io15 i/o 5v safe b idirectional data / control bus bit 15 table 3 . 1 - v2dip2 48 port selection jumper pins
` copyright ? 2010 future technology devices international limited 7 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 pin no. (vdip2 ) name pin name on pcb t ype description j1 - 19 (19) iobus16 io16 i/o 5v safe bidirectional data / control bus bit 16 j1 - 20 (20) iobus17 io17 i/o 5v safe bidirectional data / control bus bit 17 j2 - 1 ( 40 ) nc - - not connected j2 - 2 ( 39 ) 3v3 3v3 pwr output 3.3v output from v2dip2 - 48 on board 3.3v l.d.o. j2 - 3 ( 38 ) 3v3 3v3 pwr output 3.3v output from v2dip2 - 48 on board 3.3v l.d.o. j2 - 4 ( 37 ) iobus4 io 4 i/o 5v safe b idirectional data / control bus bit 4 j2 - 5 ( 36 ) iobus3 io 3 i/o 5v safe b idirectional data / control bus bit 3 j2 - 6 ( 35 ) iobus2 io 2 i/o 5v safe bidi rectional data / control bus bit 2 j2 - 7 ( 34 ) iobus1 io 1 i/o 5v safe b idirectional data / control bus bit 1 j2 - 8 ( 33 ) iobus0 io0 i/o 5v safe b idirectional data / control bus bit 0 j2 - 9 ( 32 ) 3v3 3v3 pwr output 3.3v output from v2dip2s on board 3.3v l.d.o. j2 - 1 0 ( 31 ) prog# pr g# input this pin is used in combination with the reset# pin and the ua r t interface to program firmware into the vnc2. j2 - 11 ( 30 ) reset# rst # input can be used by an external device to reset the vnc2. this pin can be used in combi nation with prog# and the ua r t interface to program firmware into the vnc2. j2 - 12 (29 ) iobus25 io25 i/o 5v safe bidirectional data / control bus bit 25 j2 - 13 (28 ) iobus24 io24 i/o 5v safe bidirectional data / control bus bit 24 j2 - 14 (27 ) iobus23 io23 i/o 5v safe bidirectional data / control bus bit 23 j2 - 15 (26 ) gnd gnd pwr module ground supply pin j2 - 16 (25 ) iobus22 io22 i/o 5v safe bidirectional data / control bus bit 22 j2 - 17 (24 ) iobus21 io21 i/o 5v safe bidirectional data / control bus bit 21 j2 - 18 (23 ) iobus20 io20 i/o 5v safe bidirectional data / control bus bit 20 j2 - 19 (22) iobus19 io19 i/o 5v safe bidirectional data / control bus bit 19 j2 - 20 (21) iobus18 io18 i/o 5v safe bidirectional data / control bus bit 18 table 3.1 - v2dip2 48 port selection jumper pins
` copyright ? 2010 future technology devices international limited 8 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3.3 i/o configuration using the jumper pin header t w o t hr e e w a y j u m p er pin h e ade r s are p r o vi d e d t o al l o w f o r sim p le c o nf i g u r a tio n o f t he i / o on d a t a and c o n tro l bus pins o f t he 48 pin qfn vinculum - ii . t his is d o ne b y a c o mbin a tio n o f pulling u p o r pulling d o w n t he 48 pin qfn vinculum - ii iobus25 (pin 4 6 ) and iobus26 (pin 4 7 ) . t he rel e v a n t po r tio n o f t he v2dip2 - 48 m o d ule s c hem a t ic is sh o w n in figure 3 . 3 figure 3 . 3 - v2dip2 48 on - board jumper pin configuration. iobus25 ( vnc2 - 48q pin 47) iobus26 ( vnc2 - 48q pin 46) i/o mode pull - up pull - up serial ua r t pull - up pull - down spi pull - down pull - up parallel fifo pull - down pull - down serial ua r t table 3 . 2 - v2dip2 48 port selection jumper pins note: this is only applicable when using vnc1l compatible firmware e.g. v2dap2. other wise the user can set the pins for their own use. i o b u s 2 5 i o b u s 2 6
` copyright ? 2010 future technology devices international limited 9 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3.4 default interface i/o pin configuration the vnc2 - 48q device is pre - programmed with default settings for the i/o pins ho wever they can be easily changed to suit a designers needs. the default interface i/o pin configuration of the vnc2 - 48q device are shown in table 3 . 3 pin no. name pin nam e on pcb t y pe data and control bus configuration options ua r t interface spi slave interface spi master interface parallel fifo interface debug g er interface j2 - 8 iobus0 io0 i/o na na na na d ebug. if j2 - 4 iobus4 io4 i/o na spi_s0_clk na na na j1 - 4 iobus5 io5 i/o na spi_s0_mosi na na na j1 - 5 iobus6 io6 i/o na spi_s0_miso na na na j1 - 6 iobus7 io7 i/o na spi_s0_ss# na na na j1 - 7 iobus8 io8 i/o na na spi_m_clk na na j1 - 8 iobus9 io9 i/o na na spi_m_mosi na na j1 - 10 iobus10 io10 i/o na na spi_m_miso na na j1 - 11 iobus11 io11 i/o na na spi_m_ss# na na j1 - 14 iobus12 io12 i/o uart_txd na na na na j1 - 16 iobus13 io13 i/o uart_rxd na na na na j1 - 17 iobus14 io14 i/o uart_rts# na na na na j1 - 18 iobus15 io15 i/o uart_cts# na na na na j1 - 19 iobus16 io16 i/o uart_dtr# na na na na j1 - 20 iobus17 io17 i/o uart_dsr# na na na na j2 - 20 iobus18 io18 i/o uart_dcd# na na na na j2 - 19 iobus19 io19 i/o uart_ri# na na na na j2 - 18 iobus20 io20 i/o uart_tx_active na na na na table 3 . 3 - default interface i/o pin configuration
` copyright ? 2010 future technology devices international limited 10 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3.5 uart interface when the data and control buses are configured in uart mode, the interface implements a standard asynchronous serial uart port with flow control. the uart can support b aud rates from 300 baud to 3 m baud. the uart interface is described more fully in a vincul um - ii datasheet please refer to: - ftdi website . 3.5.1 signal description C uart interface the uart signals can be programmed to a choice of i/o pin available . table 3 . 4 explains the available pins for each of the uart signals . available p ins name type description j2 - 8, j2 - 4, j1 - 7, j1 - 14 , j1 - 19, j2 - 18, j2 - 13 uart_txd output transmit asynchronous data output j2 - 7, j1 - 4, j1 - 8, j1 - 16, j1 - 20, j2 - 17 uart_rxd # input receive asynchronous data input j2 - 6, j1 - 5, j1 - 10 , j1 - 17 , j2 - 20, j2 - 16 uart_rts# output request to send control output j2 - 5, ji - 6, j1 - 11, j1 - 18, j2 - 19, j2 - 14 uart_cts# input clear to send control input j2 - 8, j2 - 4, j1 - 7, j1 - 14 , j1 - 19, j2 - 18, j2 - 13 uart_dtr# output data acknowledge (data terminal ready control) output j2 - 7, j1 - 4, j1 - 8, j1 - 16, j1 - 20, j2 - 17 uart_dsr# input data request (data set ready control) input j2 - 6, j1 - 5, j1 - 10, j1 - 17, j2 - 20, j2 - 16 uart_dcd# input data carrier detect control input j2 - 5, ji - 6, j1 - 11, j1 - 18, j2 - 19, j2 - 14 uart_ri# input ring indicator control input. uart_ri# low can be used to resume the pc usb host controller from suspend. j2 - 8, j2 - 4, j1 - 7, j1 - 14 , j1 - 19, j2 - 18, j2 - 13 uart_tx_active output enable transmit data for rs485 designs. uart_tx_active may be used to signal that a transmit operation is in progress.the uart_tx_active signal will be set high one bit - time before data is transmit ted and return low one bit time after the last bit of a data frame has been transmitted table 3 . 4 - data and control bus signal mode options C uart interface
` copyright ? 2010 future technology devices international limited 11 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3.6 serial peripheral interface (spi) the vnc2 - 4 8 q has one master module and two slave modules. the se m odules are described more fully in a vinculum - ii datasheet please refer to: - ftdi website . 3.6.1 signal description - spi slave the spi slave signals can be programmed to a choice of available i/o pin s. table 3 . 5 explains the available pins for each of the spi slave signals . available pins name type description j2 - 8, j2 - 4, j1 - 7, j1 - 14 , j1 - 19, j2 - 18, j2 - 13 spi_s0_clk spi_s1_clk input slave clock input j2 - 7, j1 - 4, j1 - 8, j1 - 16, j1 - 20, j2 - 17 spi_s0_mosi spi_s1_mosi input /output master out slave in synchronous data from master to slave j2 - 6, j1 - 5, j1 - 10, j1 - 17, j2 - 20, j2 - 16 spi_s0_miso spi_s1_miso output master in slave out synchronous data from slave to master j2 - 5, ji - 6, j1 - 11, j1 - 18, j2 - 19, j2 - 14 spi_s0_s s# spi_s1_s s# input slave chip select table 3 . 5 - data and control bus signal mode options C spi slave 3.6.2 signal description - spi master the spi master signals can be programmed to a choice of available i/ o pins table 3 . 6 shows the spi master signals and the available pins that they can be mapped. available pins name type description j2 - 8, j2 - 4, j1 - 7, j1 - 14 , j1 - 19, j2 - 18, j2 - 13 spi_m_clk output spi master clock input j2 - 7, j1 - 4, j1 - 8, j1 - 16, j1 - 20, j2 - 17 spi_m_mosi output master out slave in synchronous data from master to slave j2 - 6, j1 - 5, j1 - 10, j1 - 17, j2 - 20, j2 - 16 spi_m_miso input master in slave out synchronous data from slave to master j2 - 5, ji - 6, j1 - 11, j1 - 18, j2 - 19, j2 - 14 spi_m_cs_0# output active low slave select 0 from master to slave 0 j2 - 8, j2 - 4, j1 - 7, j1 - 14 , j1 - 19, j2 - 18, j2 - 13 spi_m_cs_1# output active low slave select 1 from master to slave 1 table 3 . 6 - data and control bus signal mode options C spi master
` copyright ? 2010 future technology devices international limited 12 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3.7 parallel fifo interface - asynchronous mode the parallel fifo asynchronous mode , functionally the same as the parallel fifo interface present in vdip2 has an eight bit parallel data bus, individual read and write strobes and two hardware flow control signals. 3.7.1 signal description - parallel fifo interface the parallel fifo interface signals can be programmed to a choice of available i/o pin s . table 3 . 7 shows the parallel fifo interface signals and the pins that they can be mapped. available pins name type description j2 - 8, j2 - 4, j1 - 7, j1 - 14 , j1 - 19, j2 - 18, j2 - 13 fifo_data[0] i/o fifo data bus bit 0 j2 - 7, j1 - 4, j1 - 8, j1 - 16, j1 - 20, j2 - 17 fifo_data[1] i/o fifo data bus bit 1 j2 - 6, j1 - 5, j1 - 10, j1 - 17, j2 - 20, j2 - 16 fifo_data[2] i/o fifo data bus bit 2 j2 - 5, ji - 6, j1 - 11, j1 - 18, j2 - 19, j2 - 14 fifo_data[3] i/o fifo data bus bit 3 j2 - 8, j2 - 4, j1 - 7, j1 - 14 , j1 - 19, j2 - 18, j2 - 13 fifo_data[4] i/o fifo data bus bit 4 j2 - 7, j1 - 4, j1 - 8, j1 - 16, j1 - 20, j2 - 17 fifo_data[5] i/o fifo data bus bit 5 j2 - 6, j1 - 5, j1 - 10, j1 - 17, j2 - 20, j2 - 16 fifo_data[6] i/o fifo data bus bit 6 j2 - 5, ji - 6, j1 - 11, j1 - 18, j2 - 19, j2 - 14 fifo_data[7] i/o fifo data bus bit 7 j2 - 8, j2 - 4, j1 - 7, j1 - 14 , j1 - 19, j2 - 18, j2 - 13 fifo_rxf# output when high, do not read data from the fifo. when low, there is data available in the fifo which can be read by strobing fifo_rd# low, then high. j2 - 7, j1 - 4, j1 - 8, j1 - 16, j1 - 20, j2 - 17 fifo_txe# output when high, do not write data into the fifo. when low, data can be written into the fifo by strobing fifo_wr# high, then low. j2 - 6, j1 - 5, j1 - 10, j1 - 17, j2 - 20, j2 - 16 fifo_rd# input enables the current fifo data byte on d0...d7 when low. fetches the next fifo data byte (if available) from the receive fifo buffer when fifo_rd# goes from high to low j2 - 5, ji - 6, j1 - 11, j1 - 18, j2 - 19, j2 - 14 fifo_wr# input writes the data byte on the d0...d7 pins into the transmit fifo buffer when fifo_wr# goes from high to low. table 3 . 7 - data and control bus s ignal mode options C parallel fifo interface
` copyright ? 2010 future technology devices international limited 13 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3.7.2 timing diagram C asynchronous fifo mode read and write cycle when in asynchronous fifo interface mode, the timing of a read and write operation on the fifo interface is shown in figure 3 . 4 and table 3 . 8 figure 3 . 4 C asynchronous fifo mode r ead and write cycle . t ime description min max unit t 1 rd # ina ctive to rxf# 1 14 ns t 2 rxf# ina ctive after rd# cycle 100 - ns t 3 rd # to data 1 14 ns t4 rd # active pulse width 30 - ns t5 rd# active after rxf# 0 - ns t6 wr# active to txe# inactive 1 14 ns t7 txe# inactive after wr# cycle 100 - ns t8 data to txe# active setup time 5 - ns t9 data hold time after wr# inactive 5 - ns t 1 0 wr# active pulse width 30 - ns t 1 1 wr# active after txe# 0 - ns table 3 . 8 - asynchronous fifo mode read cycle timing in asynchronous mode an external device can control data transfer driving fifo_wr# and fifo_rd# inputs. in contrast to synchronous mode, in asynchronous mode the 245 fifo module generates the output enable en# signal. en# signal is effectively the read sig nal rd#. current byte is available to be read when fifo_rd# goes low. when fifo_rd# goes high, fifo_rxf# output will also go high. it will only become low again when there is another byte to read. when fifo_wr# goes low fifo_txe# flag will always go hig h. fifo_txe# goes low again only when there is still space for data to be written in to the module.
` copyright ? 2010 future technology devices international limited 14 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3.8 parallel fifo interface - synchronous mode the parallel fifo synchronous mode has an eight bit data bus, indivi dual read and write strobes, two hardware flow control signals , an output enable and a clock out. the synchronous fifo mode uses the parallel fifo interface signals detailed in table 3 . 7 and an additional two signals detailed in table 3 . 9 . available pins name type description j2 - 8, j2 - 4, j1 - 7, j1 - 14 , j1 - 19, j2 - 18, j2 - 13 fifo_oe# output fifo output enable j2 - 7, j1 - 4, j1 - 8, j1 - 16, j1 - 20, j2 - 17 fifo_clkout output fifo output enable table 3 . 9 - data and control bus s ignal mode options C synchronous fifo mode
` copyright ? 2010 future technology devices international limited 15 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3.8.1 timing diagram C s ynchronous fifo mode read and write cycle when in synchronous fifo interface mode, the timing of a read and write operation on the fifo interface are shown in figure 3 . 5 and table 3 . 10 figure 3 . 5 - synchronous fifo mode read and write cycle t ime description min typical max uni t t1 clkout period - 20.83 - ns t2 clkout high period 9.38 10.42 11.46 ns t3 clkout low period 9.38 10.42 11.46 ns t4 clkout to rxf# 1 - 7.83 ns t5 clkout to read data valid 1 - 7.83 ns t6 oe# to read data valid 1 - 7.83 ns t7 clkout to oe# 1 - 7.83 ns t8 rd# setup time 12 - - ns t9 rd# hold time 0 - - ns t10 clkout to txe# 1 - - ns t11 write data setup time 12 - - ns t12 write data hold time 0 - - ns t13 wr # setup time 12 - - ns t14 wr # hold time 0 - - ns table 3 . 10 - synchronous fifo mode read and write cycle timing
` copyright ? 2010 future technology devices international limited 16 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 in synchronous mode data can be transmitted to and from the fifo module on each clock edge. an external device synchronises to the clkout output and it also has access to the output enable oe# input to control data flow. an external device should drive out put enable oe# low before pulling rd# line down. when bursts of data are to be read from the module rd# should be kept low. rxf# remains low when there is still data to be read. similarly when bursts of data are to be written to the module wr# should be ke pt low. txe# remains low when there is still space available for the data to be written
` copyright ? 2010 future technology devices international limited 17 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 3.9 debugger interface the purpose of the debugger interface is to provide access to the vnc2 silicon/firmware debugger. the debug interface can be accessed by connecting a debug module to the j3 connector. this debug module will give access to the debugger through a usb connection to a pc via the integrated development environme nt ( ide ). the ide is a graphical interface to the vnc2 software development tool - chain and gives the following debug capabilities through the debugger interface : flash erase, write and program. application debug - application code can have breakpoints, be single stepped and can be halted. detailed internal debug - memory and register read/write access. the debugger interface , and how to use it, is further described in the following applications note vinculum - ii debug interface description 3.9.1 signal description - debugger interface table 3 . 11 shows the signals and pins d escription for the debugger i nterface pin header j3 pin no. name name on pcb type description j3 - 1 io 0 dbg i/o debugger interface j3 - 2 - [key] - not connected. used to make sure that the debug module is connected correctly. j3 - 3 gnd gnd pwr module ground supply pin j3 - 4 reset# rst# input can be used by an external device to reset the vncl2. this pin is also used in combination with prog# an d the uart interface t o program firmware into the vnc 2. j3 - 5 prog# prg# input this pin is used in combination with the reset# pin an d the uart interface to program firmware into the vnc2 . j3 - 6 5v0 vcc pwr input 5.0v module supply pin. this pin can be used to provide the 5.0v in put to the v2dip2 - 48 when the v2dip2 - 48 is not powered from the usb connector (vbus) or the debugger interface. also connected to dil connector pins j1 - 2, j1 - 3 and j1 - 9 and j3 - 6 . table 3 . 11 - s ignal name and description C debugger interface
` copyright ? 2010 future technology devices international limited 18 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 4 firmware 4.1 firmware support the vnc2 on the v2dip2 - 48 can be programmed with the customers own firmware created using the vinculum ii firmware development tool chain or with various pre - compiled firmware profiles to allow a designer to easily change the functionality of the chip. please refer to: - ftdi website for full details on available pre - compiled firmware 4.2 available firmware v2dap firmware is currently available : usb host for single flash disk and general purpose usb peripherals. selectable uart, fifo or spi int erface command monitor. please refer to: - ftdi website for full details. 4.3 firmware upgrades r efer to the debugger interface section which can be used to update the firmware.
` copyright ? 2010 future technology devices international limited 19 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 5 mechanical dimensions figure 5 . 1 v2dip2 48 dimensions (top view) figure 5 . 2 v2dip2 48 dimensions (side view) tolerance is 0. 2 0 mm all dimensions are in mm 1 . 2 7 2 . 2 5 f t d i x x x x x x x x v n c 2 - 4 8 q 1 a y y w w 3 . 9 0 1 5 . 3 9 1 1 . 4 4 6 0 . 9 6 5 9 . 7 0 7 . 7 0 2 . 0 2 7 . 9 0 9 . 9 0 1 6 . 5 1 1 7 . 7 8 6 8 . 5 6 2 . 5 4 1 . 6 0 1 5 . 7 5 2 6 . 6 0 1 7 . 4 0 4 . 9 0
` copyright ? 2010 future technology devices international limited 20 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 6 schematic diagram figure 6 . 1 - schematic diagram
` copyright ? 2010 future technology devices international limited 21 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 7 contact information head office C glasgow, uk future technology devices international limited unit 1, 2 seaward place, centurion business park glasgow, g41 1hh united kingdom tel: +44 (0) 141 429 2777 fax: +44 (0) 141 429 2758 e - mail (sales) sales1@ftdichip.com e - mail (support) support1@ftdichip.com e - mail (general enquiries) admin1@ftdichip.com web site url http://www.ftdichip.com web shop url http://www.ftdichip.com branch office C taipei, taiwan future technology devices international limited (taiwan) 2f, no 516, sec. 1 neihu road taipei 114 taiwan, r.o.c. tel: +886 (0) 2 8791 3570 fax: +886 (0) 2 8791 3576 e - mail (sales) tw.sales1@ftdichip.com e - mail (support) tw.support1@ftdichip.com e - mail (general enquiries) tw.admin1@ftdichip.com web site url http://www.ftdichip.com branch office C hillsboro, oregon, usa future technology devices international limited (usa) 7235 nw evergreen parkway, suite 600 hillsboro, or 97123 - 5803 usa tel: +1 (503) 547 0988 fax: +1 (503) 547 0987 e - mail (sales) us.sales@ftdichip.com e - mail (support) us.admin@ftdichip.com web site url http://www.ftdichip.com branch office C shanghai, china future technology devices international limited (china) room 408, 317 xianxia road, changning district, shanghai, china tel: +86 (21) 62351596 fax: +86 (21) 62351595 e - mail (sales): cn.sales@ftd ichip.com e - mail (support): cn .support@ftdichip .com e - mail (general enquiries): cn. admin1@ftdichip.com web site url http://www.ftdichip.com distributor and sales representatives please visit the sales network page of the ftdi web site for the contact details of our distributor(s) and sales representative(s) in your country.
` copyright ? 2010 future technology devices international limited 22 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 appendix a C references application and technical notes vinculum - ii io cell description vinculum - ii debug interface description vinculum - ii io mux explained vinculum - ii pwm example migrating vinculum designs from vnc1l to vnc2 - 48l1a vinculum - ii errata technical note
` copyright ? 2010 future technology devices international limited 23 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 appendix b C list of figures and tables list of figures figure 1.1 - v2dip2 48 ................................ ................................ ................................ ................... 1 figure 3.1 - v2dip2 48 module pin out (top view) ................................ ................................ .......... 4 figure 3.3 - v2dip2 48 on - board jumper pin configuration. ................................ .............................. 8 figure 3.4 C asynchronous fifo mode read and write cycle. ................................ ........................... 13 figure 3.5 - synchronous fifo mode read and write cycle ................................ .............................. 15 figure 5.1 v2dip2 48 dimensions (top view) ................................ ................................ ................ 19 figure 5.2 v2dip2 48 dimensions (side view) ................................ ................................ ............... 19 figure 6.1 - schematic diagram ................................ ................................ ................................ ... 20 list of tables table 3.1 - v2dip2 48 port selection jumper pins ................................ ................................ ............. 6 table 3.2 - v2dip2 48 port selection jumper pins ................................ ................................ ............. 8 table 3.3 - default interface i/o pin configuration ................................ ................................ ........... 9 table 3.4 - data and control bus signal mode options C uart interface ................................ ........... 10 table 3.5 - data and control bus signal mode options C spi slave ................................ ................... 11 table 3.6 - data and control bus signal mode options C spi master ................................ ................. 11 table 3.7 - data and control bus signal mode options C parallel fifo interface ................................ . 12 table 3.8 - asynchronous fifo mode read cycle timing ................................ ................................ .. 13 table 3.9 - data and control bus signal mode options C synchronous fifo mode .............................. 14 table 3.10 - synchronous fifo mode read and write cycle timing ................................ ................... 15 table 3.11 - signal name and description C debug ger interface ................................ ....................... 17
` copyright ? 2010 future technology devices international limited 24 document reference no.: ft_000237 v2dip2 - 48 vnc2 - 48 de velopment module datasheet version 1.01 clearance n o.: ftdi# 152 appendix c C revision history version 1.0 first release 16 th april 20 10 version 1.0 1 added modules images and edited mechanical drawings 25 th may 20 10

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