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1 typical a pplica t ion fea t ures a pplica t ions descrip t ion boost/sepic/inverting dc/dc converter with 1a, 65v switch, soft-start and synchronization the lt ? 8580 is a pwm dc/dc converter containing an internal 1a, 65 v switch. the lt8580 can be configured as either a boost, sepic or inverting converter. the lt8580 has an adjustable oscillator, set by a resistor from the rt pin to ground. additionally, the lt8580 can be synchronized to an external clock. the switching frequency of the part may be free running or synchronized, and can be set between 200khz and 1.5mhz. the lt8580 also features innovative shdn pin circuitry that allows for slowly varying input signals and an adjust- able under voltage lockout function. additional features such as frequency foldback and soft-start are integrated. the lt8580 is available in tiny thermally enhanced 3mm 3mm 8- lead dfn and 8-lead msop packages. 1.5mhz, 5v to 12v boost converter n 1a, 65v power switch n adjustable switching frequency n single feedback resistor sets v out n synchronizable to external clock n high gain shdn pin accepts slowly varying input signals n wide input voltage range: 2.55v to 40v n low v cesat switch: 400mv at 0.75a (typical) n integrated soft-start function n easily configurable as a boost, sepic, or inverting converter n user configurable undervoltage lockout (uvlo) n pin compatible with lt3580 n tiny thermally enhanced 8-lead 3mm 3mm dfn and 8-lead msop packages n vfd bias supplies n tft -lcd bias supplies n gps receivers n dsl modems n local power supply efficiency and power loss l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners . protected by u.s. patents , including 7579816. load current (ma) 0 20 efficiency (%) power loss (mw) 40 50 60 100 100 8580 ta01b 30 50 150 200 70 80 90 0 180 300 480 240 60 120 360 420 efficiency power loss 4.7f v out 12v 200ma 15h 130k v in 5v v in sw 8580 ta01a lt8580 10k 6.04k 56.2k shdn gnd fbx vc sync ss rt 3.3nf 47pf 0.22f 2.2f lt 8580 8580f for more information www.linear.com/lt8580
2 a bsolu t e maxi m u m r a t ings v in voltage ................................................. C 0. 3 v to 40 v sw voltage ................................................ C 0. 4 v to 65 v rt voltage ................................................... C 0. 3 v to 5v ss voltage ................................................ C 0. 3 v to 2.5 v fbx voltage ................................................................. 5 v fbx current ............................................................ C1 ma vc voltage ................................................... C 0. 3 v to 2v (note 1) top view dd package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 9 gnd 4 3 2 1fbx vc v in sw sync ss rt shdn ja = 43c/w exposed pad ( pin 9) is gnd, must be soldered to pcb 1 2 3 4 fbx vc v in sw 8 7 6 5 sync ss rt shdn top view 9 gnd ms8e package 8-lead plastic msop ja = 35c/w to 40c/w exposed pad ( pin 9) is gnd, must be soldered to pcb p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt8580edd#pbf lt8580edd#trpbf lgkh 8-lead (3mm 3mm) plastic dfn C 40c to 125c lt8580idd#pbf lt8580idd#trpbf lgkh 8-lead (3mm 3mm) plastic dfn C 40c to 125c lt8580hdd#pbf lt8580hdd#trpbf lgkh 8-lead (3mm 3mm) plastic dfn C 40c to 150c lt8580ems8e#pbf lt8580ems8e#trpbf ltgkj 8-lead plastic msop C 40c to 125c lt8580ims8e#pbf lt8580ims8e#trpbf ltgkj 8-lead plastic msop C 40c to 125c lt8580hms8e#pbf lt8580hms8e#trpbf ltgkj 8-lead plastic msop C 40c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ shdn voltage ............................................ C 0. 3 v to 40 v sync voltage ............................................ C 0. 3 v to 5.5 v operating junction temperature range lt 8580 e ( n otes 2, 5) ......................... C 4 0 c to 125 c lt 858 0 i ( notes 2, 5) .......................... C 4 0 c to 125 c lt 8 580 h ( n otes 2, 5) ........................ C 40 c to 150 c storage te mperature range .................. C 6 5 c to 150 c lt 8580 8580f for more information www.linear.com/lt8580
3 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt8580e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt8580i is guaranteed over the full C40c to 125c operating junction temperature range. the lt8580h is guaranteed over the full C40c to 150c operating junction temperature range. operating lifetime is derated at junction temperatures greater than 125c. e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 5v, v shdn = v in unless otherwise noted. (note 2) parameter conditions min typ max units operating voltage range lt8580e, lt8580i lt8580h l l 2.55 2.9 40 40 v v positive feedback v oltage l 1.185 1.204 1.220 v negative feedback voltage l C3 3 12 mv positive fbx pin bias current v fbx = positive feedback voltage, current into pin l 81 83.3 85 a negative fbx pin bias current v fbx = negative feedback voltage, current out of pin l 81 83.3 86 a error amplifier transconductance 200 mhos error amplifier voltage gain 60 v/ v quiescent current v shdn = 2.5v, not switching 1.2 1.7 ma quiescent current in shutdown v shdn = 0v 0 1 a reference line regulation 2.5v v in 40v 0.01 0.05 %/ v switching frequency, f osc r t = 56.2k r t = 422k l l 1.23 165 1.5 200 1.77 235 mhz khz switching frequency in foldback compared to normal f osc 1/6 ratio switching frequency set range syncing or free running l 200 1500 khz sync high level for synchronization l 1.3 v sync low level for synchronization l 0.4 v sync clock pulse duty cycle v sync = 0v to 2v 35 65 % recommended minimum sync ratio f sync /f osc 3/4 minimum off-time 100 ns minimum on-time 350 ns switch current limit minimum duty cycle (note 3) maximum duty cycle (notes 3, 4), f osc = 1.5mhz maximum duty cycle (notes 3, 4), f osc = 200khz l l l 1.2 0.6 0.4 1.5 1 0.8 1.8 1.5 1.4 a a a switch v cesat i sw = 0.75a 400 mv switch leakage current v sw = 5v 0.01 1 a soft-start charging current v ss = 0.5v l 4 6 8 a shdn minimum input voltage high active mode, shdn rising active mode, shdn falling l l 1.23 1.21 1.31 1.27 1.4 1.33 v v shdn input voltage low shutdown mode l 0.3 v shdn pin bias current v shdn = 3v v shdn = 1.3v v shdn = 0v 9 44 12 0 56 15 0.1 a a a shdn hysteresis 40 mv note 3: current limit guaranteed by design and/ or correlation to static test. note 4: current limit measured at equivalent of listed switching frequency. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. lt 8580 8580f for more information www.linear.com/lt8580
4 typical p er f or m ance c harac t eris t ics switch current limit vs duty cycle switch saturation voltage commanded switch current vs ss switch current limit vs temperature positive and negative output voltage regulation positive and negative fbx current at output voltage regulation oscillator frequency t a = 25c, unless otherwise specified duty cycle (%) 10 0 switch current limit (a) 0.50 0.75 0.25 1.00 1.25 1.50 1.75 30 50 70 90 8580 g01 2.00 20 40 60 80 switch current (a) 0 saturation voltage (mv) 400 500 600 1.5 8580 g02 300 200 0 0.50.25 0.75 1 1.25 100 700 ss voltage (v) 0 0 switch current (a) 0.5 1.0 1.5 2.0 0.2 0.4 0.6 0.8 8580 g03 1 1.2 temperature (c) ?50 ?25 0 switch current limit (a) 0.5 1.0 1.5 2.0 0 5025 125 150 10075 8580 g04 temperature (c) ?50 ?25 1.170 positive fbx voltage (v) negative fbx voltage (mv) 1.200 1.220 0 50 75 8580 g05 1.175 1.180 1.185 1.190 1.195 1.215 1.210 1.205 ?20 15 30 ?10 ?15 ?5 0 5 10 25 20 25 100 150125 temperature (c) ?50 ?25 80 positive fbx current into pin (a) negative fbx current out of pin (a) 86 0 50 75 8580 g06 81 82 83 84 85 80 86 81 82 83 84 85 25 100 150125 temperature (c) ?50 ?25 frequency (mhz) 0.8 1.0 1.2 1.4 8580 g07 0.6 0.4 0 0 5025 75 100 125 150 0.2 1.8 1.6 r t = 56.2k r t = 422k lt 8580 8580f for more information www.linear.com/lt8580
5 typical p er f or m ance c harac t eris t ics shdn pin current shdn pin current active/lockout threshold t a = 25c, unless otherwise specified oscillator frequency during soft-start internal uvlo fbx voltage (v) 0 0 normalized oscillator frequency (f/f nom ) 1/4 1/2 1/3 1/6 1/5 1 0.2 0.4 inverting configurations noninverting configurations 0.6 0.8 8580 g08 1 1.2 temperature (c) ?50 ?25 2.1 v in voltage (v) 2.2 2.7 2.4 2.3 0 5025 75 8580 g09 2.5 2.6 125100 150 shdn voltage (v) 0 0 shdn pin current (a) 5 10 15 20 25 30 0.50.25 1 1.5 0.75 1.25 1.75 2 8580 g10 125c 25c ?40c shdn voltage (v) 0 shdn pin current (a) 200 250 300 350 400 15 25 8580 g11 150 100 5 10 20 30 35 40 50 0 125c 25c ?40c temperature (c) ?50 ?25 1.20 shdn voltage (v) 1.22 1.26 1.28 1.30 1.40 1.34 0 50 75 8580 g12 1.24 1.36 1.38 1.32 100 125 150 shdn rising shdn falling 25 lt 8580 8580f for more information www.linear.com/lt8580
6 p in func t ions fbx (pin 1): positive and negative feedback pin. for a noninverting or inverting converter, tie a resistor from the fbx pin to v out according to the following equations: r fbx = v out ? 1.204v ( ) 83.3a ; noninverting converter r fbx = v out + 3mv ( ) 83.3a ; inverting converter vc (pin 2): error amplifier output pin. tie external com- pensation network to this pin. v in (pin 3): input supply pin. must be locally bypassed. sw (pin 4): switch pin. this is the collector of the internal npn power switch. minimize the metal trace area connec - ted to this pin to minimize emi. shdn ( pin 5): shutdown pin. in conjunction with the uvlo ( undervoltage lockout) circuit, this pin is used to enable/ disable the chip and restart the soft- start sequence. drive below 1.21v to disable the chip. drive above 1.40v to activate the chip and restart the soft-start sequence. do not float this pin. rt (pin 6): timing resistor pin. adjusts the switching frequency. place a resistor from this pin to ground to set the frequency to a fixed free running level. do not float this pin. ss (pin 7): soft-start pin. place a soft-start capacitor here. upon start-up, the ss pin will be charged by a (nominally) 280k resistor to about 2.1v. sync (pin 8): to synchronize the switching frequency to an outside clock, simply drive this pin with a clock. the high voltage level of the clock needs to exceed 1.3 v, and the low level should be less 0.4 v. drive this pin to less than 0.4 v to revert to the internal free-running clock. see the applications information section for more information. gnd ( exposed pad pin 9): ground. exposed pad must be soldered directly to local ground plane. lt 8580 8580f for more information www.linear.com/lt8580
7 b lock diagra m ? + ? + ? + ? + + ? 7 5 3 1.204v reference adjustable oscillator frequency foldback slope compensation comparator discharge detect ss vc 280k q2 sr2 r s 14.5k 14.5k q sr1 a3 a4 a1 a2 sync n rt shdn fbx 1.3v vc c1 sw 0.02 gnd r t r fbx driver l1 d1 i limit v in v out c ss c c c in r c v in soft- start sync block uvlo r s q 6 2 1 8580 bd 8 4 q1 9 50k lt 8580 8580f for more information www.linear.com/lt8580
8 o pera t ion figure 1. sepic topology allows for the input to span the output voltage. coupled or uncoupled inductors can be used. follow noted phasing if coupled figure 2. dual inductor inverting topology results in low output ripple. coupled or uncoupled inductors can be used. follow noted phasing if coupled d1 shutdown l2 c3 l1 r1 v in > v out or v in = v out or v in < v out v out v in sw 8580 f01 lt8580 r t r c c2 shdn gnd fbx vc sync ss rt c c c ss c1 + + ? ? d1 shutdown c3 l1 r1 v in v out v in sw 8580 f02 lt8580 c2 shdn gnd fbx vc sync ss rt c ss c1 l2 + + ? ? r t r c c c the lt8580 uses a constant- frequency, current mode con - trol scheme to provide excellent line and load regulation. refer to the block diagram for the following description of the parts operation. at the start of each oscillator cycle, the sr latch ( sr1) is set, which turns on the power switch, q1. the switch current flows through the internal current sense resistor, generating a voltage proportional to the switch current. this voltage ( amplified by a 4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the pwm comparator a 3. when this voltage exceeds the level at the negative input of a 3, the sr latch is reset, turning off the power switch. the level at the negative input of a 3 (vc pin) is set by the error amplifier a 1 ( or a2) and is simply an amplified version of the difference between the feedback voltage ( fbx pin) and the reference voltage (1.204v or 3mv, depending on the configuration). in this manner, the error amplifier sets the correct peak current level to keep the output in regulation. the lt8580 has an fbx pin architecture that can be used for either noninverting or inverting configurations. when configured as a noninverting converter, the fbx pin is pulled up to the internal bias voltage of 1.204 v by the r fbx resistor connected from v out to fbx. amplifier a2 becomes inactive and amplifier a1 performs the invert- ing amplification from fbx to vc. when the lt8580 is in an inverting configuration, the fbx pin is pulled down to 3mv by the r fbx resistor connected from v out to fbx. amplifier a1 becomes inactive and amplifier a2 performs the noninverting amplification from fbx to vc. sepic topology as shown in figure 1, the lt8580 can be configured as a sepic ( single-ended primary inductance converter). this topology allows for the input to be higher, equal, or lower than the desired output voltage. output disconnect is inherently built into the sepic topology, meaning no dc path exists between the input and output. this is useful for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. inverting topology the lt8580 can also work in a dual inductor inverting topology, as shown in figure 2. the parts unique feedback pin allows for the inverting topology to be built by simply changing the connection of external components . this solution results in very low output voltage ripple due to the inductor l2 in series with the output. abrupt changes in output capacitor current are eliminated because the output inductor delivers current to the output during both the off-time and the on-time of the lt8580 switch. lt 8580 8580f for more information www.linear.com/lt8580
9 start-up operation several functions are provided to enable a very clean start-up for the lt8580. ? first, the shdn pin voltage is monitored by an internal voltage reference to give a precise turn-on voltage level. an external resistor ( or resistor divider) can be connected from the input power supply to the shdn pin to provide a user-programmable undervoltage lockout function. ? second, the soft-start circuitry provides for a gradual ramp-up of the switch current. when the part is brought out of shutdown, the external ss capacitor is first discharged ( providing protection against shdn pin glitches and slow ramping), then an integrated 280k resistor pulls the ss pin up to ~2.1 v. by connecting an external capacitor to the ss pin, the voltage ramp rate on the pin can be set. typical values for the soft-start capacitor range from 100nf to 1f. ? finally, the frequency foldback circuit reduces the switch - ing frequency when the fbx pin is in a nominal range of 300 mv to 920 mv. this feature reduces the minimum duty cycle that the part can achieve thus allowing better control of the switch current during start-up. when the fbx voltage is pulled outside of this range, the switching frequency returns to normal. current limit and thermal shutdown operation the lt8580 has a current limit circuit not shown in the block diagram. the switch current is constantly monitored and not allowed to exceed the maximum switch current at a given duty cycle ( see the electrical characteristics table). if the switch current reaches this value, the sr latch (sr1) is reset regardless of the state of the comparator (a1/ a2). also, not shown in the block diagram is the thermal shutdown circuit. if the temperature of the part exceeds approximately 165 c, the sr2 latch is set regardless of the state of the amplifier ( a1/a2). when the part temperature falls below approximately 160 c, a full soft-start cycle will then be initiated. the current limit and thermal shutdown circuits protect the power switch as well as the external components connected to the lt8580. o pera t ion lt 8580 8580f for more information www.linear.com/lt8580
10 a pplica t ions i n f or m a t ion inductor selection general guidelines : the high frequency operation of the lt8580 allows for the use of small surface mount inductors. for high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. to improve efficiency, choose inductors with more volume for a given inductance. the inductor should have low dcr ( copper wire resistance) to reduce i 2 r losses, and must be able to handle the peak inductor current without saturating. note that in some applications, the current handling requirements of the inductor can be lower, such as in the sepic topology, where each inductor only carries a fraction of the total switch current. multilayer or chip inductors usually do not have enough core area to sup- port peak inductor currents in the 1 a to 2 a range. to minimize radiated noise, use a toroidal or shielded induc- tor. note that the inductance of shielded types will drop more as current increases, and will saturate more easily. see table 1 for a list of inductor manufacturers. thorough lab evaluation is recommended to verify that the following guidelines properly suit the final application. table 1. inductor manufacturers coilcraft xal5050, msd7342, mss7341 and lps4018 series www.coilcraft.com coiltronics dr, drq, ld and cd series www. coiltronics. com sumida cdrh8d58/ld, cdrh64b, and cdrh70d430mn series www.sumida.com wrth we-pd, we-dd, we-tpc, we-lhmi and we-lqs series www.we-online.com minimum inductance : although there can be a trade-off with efficiency, it is often desirable to minimize board space by choosing smaller inductors. when choosing an inductor, there are two conditions that limit the mini- mum inductance : (1) providing adequate load current, and (2) avoiding subharmonic oscillation. choose an inductance that is high enough to meet both of these requirements. adequate load current : small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be setting output voltage the output voltage is set by connecting a resistor (r fbx ) from v out to the fbx pin. r fbx is determined from the following equation: r fbx = |v out ? v fbx | 83.3a where v fbx is 1.204 v ( typical) for noninverting topologies (i.e., boost and sepic regulators) and 3mv ( typical) for inverting topologies (see the electrical characteristics). power switch duty cycle in order to maintain loop stability and deliver adequate current to the load, the power npn (q1 in the block dia - gram) cannot remain on for 100% of each clock cycle. the maximum allowable duty cycle is given by: dc max = (t p ? min off time) t p ? 100% where t p is the clock period and min off time ( found in the electrical characteristics) is typically 100ns. the application should be designed so that the operating duty cycle does not exceed dc max . duty cycle equations for several common topologies are given below, where v d is the diode forward voltage drop and v cesat is typically 400mv at 0.75a. for the boost topology: dc ? v out ? v in + v d v out + v d ? v cesat for the sepic or dual inductor inverting topology (see figure 1 and figure 2): dc ? v d + |v out | v in + |v out | + v d ? v cesat the lt8580 can be used in configurations where the duty cycle is higher than dc max , but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. lt 8580 8580f for more information www.linear.com/lt8580
11 a pplica t ions i n f or m a t ion provided to a load (i out ). in order to provide adequate load current, l should be at least: l boost > dc ? v in 2(f) i lim ? |v out | ? i out v in ? h ? ? ? ? ? ? for boost, topologies, or: l dual > dc ? v in 2(f) i lim ? v out ? i out v in ? h ? i out ? ? ? ? ? ? for the sepic and inverting topologies. where: l boost = l1 for boost topologies (see figure 15) l dual = l1 = l2 for coupled dual inductor topologies (see figure 16 and figure 17) l dual = l1||l2 for uncoupled dual inductor topologies (see figure 16 and figure 17) dc = switch duty cycle (see previous section) i lim = switch current limit, typically about 1.2 a at 50% duty cycle ( see the typical performance characteristics section). h = power conversion efficiency ( typically 85% for boost and 83% for dual inductor topologies at high currents). f = switching frequency i out = maximum load current negative values of l indicate that the output load current i out exceeds the switch current limit capability of the lt8580. avoiding subharmonic oscillations : the lt8580 s internal slope compensation circuit can prevent subharmonic oscil - lations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. in applications that operate with duty cycles greater than 50%, the inductance must be at least: ? l min > v in 1.25 ? (dc ? 300ns ? f) ? f ? 2 ? dc ? 1 1 ? dc l min = l1 for boost topologies (see figure 15) l min = l1 = l2 for coupled dual inductor topologies (see figure 16 and figure 17) l min = l1 || l2 for uncoupled dual inductor topologies (see figure 16 and figure 17) maximum inductance : excessive inductance can reduce current ripple to levels that are difficult for the current com - parator ( a3 in the block diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. the maximum inductance can be calculated by: l max = v in ? v cesat i min-ripple ? dc f where l min = l1 for boost topologies (see figure 15) l min = l1 = l2 for coupled dual inductor topologies (see figure 16 and figure 17) l min = l1 || l2 for uncoupled dual inductor topologies (see figure 16 and figure 17) i min(ripple) = typically 80ma current rating : finally, the inductor(s) must have a rating greater than its peak operating current to prevent inductor saturation resulting in efficiency loss. in steady state, the peak input inductor current ( continuous conduction mode only) is given by: i l1-peak = |v out ? i out | v in ? h + v in ? dc 2 ? l1? f for the boost, uncoupled inductor sepic and uncoupled inductor inverting topologies. lt 8580 8580f for more information www.linear.com/lt8580
12 a pplica t ions i n f or m a t ion for uncoupled dual inductor topologies, the peak output inductor current is given by: i l2-peak = i out + v out ? 1 ? dc ( ) 2 ? l2 ? f for the coupled inductor topologies: i l2-peak = i out 1 + v out h ? v in ? ? ? ? ? ? + v in ? dc 2 ? l ? f note: inductor current can be higher during load transients. it can also be higher during start- up if inadequate soft- start capacitance is used. capacitor selection low esr ( equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage . multilayer ceramic capacitors are an excellent choice, as they have an extremely low esr and are available in very small packages. x5r or x7r dielectrics are preferred, as these materials retain their capacitance over wider voltage and temperature ranges. a 0.47 f to 10 f output capacitor is sufficient for most applications. always use a capacitor with a sufficient voltage rating. many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. solid tantalum or os-con capacitors can be used, but they will occupy more board area than a ceramic and will have a higher esr with greater output ripple. ceramic capacitors also make a good choice for the input decoupling capacitor, which should be placed as closely as possible to the v in pin of the lt8580 as well as to the inductor connected to the input of the power path. if it is not possible to optimally place a single input capacitor, then use one at the v in pin of the chip (c vin ) and one at the input of the power path (c pwr ). see equations in table 4, table 5 and table 6 for sizing information. a 1f to 2.2 f input capacitor is sufficient for most applications. table 2 shows a list of several ceramic capacitor manu- facturers. consult the manufacturers for detailed informa- tion on their entire selection of ceramic parts. table 2. ceramic capacitor manufacturers kemet www.kemet.com murata www.murata.com taiyo yuden www.t-yuden.com tdk www.tdk.com compensationadjustment to compensate the feedback loop of the lt8580, a series resistor- capacitor network in parallel with a single capacitor should be connected from the vc pin to gnd. for most applications, the series capacitor should be in the range of 470 pf to 2.2 nf with 1 nf being a good starting value. the parallel capacitor should range in value from 10 pf to 100pf with 47 pf a good starting value. the compensation resistor, r c , is usually in the range of 5 k to 50 k. a good technique to compensate a new application is to use a 100k? potentiometer in place of series resistor r c . with the series capacitor and parallel capacitor at 1 nf and 47pf respectively, adjust the potentiometer while observing the transient response and the optimum value for r c can be found. figure 3 (3 a to 3 c) illustrates this process for the circuit of figure 4 with a load current stepped be - tween 60 ma and 160 ma. figure 3 a shows the transient response with r c equal to 2 k. the phase margin is poor, as evidenced by the excessive ringing in the output voltage and inductor current. in figure 3 b, the value of r c is increased to 3 k, which results in a more damped response. figure 3 c shows the results when r c is increased further to 6 k. the transient response is nicely damped and the compensation procedure is complete. compensationtheory like all other current mode switching regulators, the lt8580 needs to be compensated for stable and efficient operation. tw o feedback loops are used in the lt8580 a fast current loop which does not require compensation, and a slower voltage loop which does. standard bode plot analysis can be used to understand and adjust the voltage feedback loop. lt 8580 8580f for more information www.linear.com/lt8580
13 a pplica t ions i n f or m a t ion (3a) transient response shows excessive ringing figure 3. transient response (3b) transient response is better (3c) transient response is well damped figure 4. 1.5mhz, 5v to 12v boost converter v out 500mv/div ac-coupled i l1 200ma/div i step 100ma/div 100s/div 8580 f03a v out 500mv/div ac-coupled i l1 200ma/div i step 100ma/div 100s/div 8580 f03b v out 500mv/div ac-coupled i l1 200ma/div i step 100ma/div 100s/div 8580 f03c c out 4.7f v out 12v 200ma l1 15h d1 r fbx 130k v in 5v v in sw 8580 f04 lt8580 10k r c 6.04k r t 56.2k shdn gnd fbx vc sync ss rt c c 3.3nf c f 47pf c ss 0.22f c in 2.2f lt 8580 8580f for more information www.linear.com/lt8580
14 a pplica t ions i n f or m a t ion as with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical . figure 5 shows the key equivalent elements of a boost con - verter. because of the fast current control loop, the power stage of the ic, inductor and diode have been replaced by a combination of the equivalent transconductance ampli - fier g mp and the current controlled current source which converts i vin to ( h v in /v out ) ? i vin . g mp acts as a current source where the peak input current, i vin , is proportional to the vc voltage. h is the efficiency of the switching regulator, and is typically about 85%. note that the maximum output currents of g mp and g ma are finite. the limits for g mp are in the electrical characteristics section ( switch current limit), and g ma is nominally limited to about +15a and C17a. figure 5. boost converter equivalent model ? + ? + g ma r c r o r2 r2 c c : compensation capacitor c out : output capacitor c pl : phase lead capacitor c f : high frequency filter capacitor g ma : transconductance amplifier inside ic g mp : power stage transconductance amplifier r c : compensation resistor r l : output resistance defined as v out divided by i load(max) r o : output resistance of g ma r1, r2: feedback resistor divider network r esr : output capacitor esr : converter efficiency (~85% at higher currents) 8580 f05 r1 fbx c out c pl r l r esr v out i vin v c c c c f g mp 1.204v reference ? v in v out ? i vin from figure 5, the dc gain, poles and zeros can be cal- culated as follows: output pole: p1= 2 2 ? ? r l ? c out error amp pole: p2 = 1 2 ? ? r o + r c [ ] ? c c error amp zero: z1= 1 2 ? ? r c ? c c dc gain: (breaking loop at fbx pin) a dc = a ol (0) = ?v c ?v fbx ? ?i vin ?v c ? ?v out ?i vin ? ?v fbx ?v out = g ma ? r 0 ( ) ? g mp ? h ? v in v out ? r l 2 ? ? ? ? ? ? ? 0.5r2 r1+ 0.5r2 esr zero: z2 = 1 2 ? ? r esr ? c out rhp zero: z3 = v in 2 ? r l 4 ? ? v out 2 ? l high frequency pole: p3 > f s 3 phase lead zero: z4 = 1 2 ? ? r1 ? c pl phase lead pole: p4 = 1 2 ? ? r1 ? r2 2 r1+ r2 2 ? c pl error amp filter pole: p5 = 1 2 ? ? r c ? r o r c + r o ? c f , c f < c c 10 the current mode zero ( z3) is a right-half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. lt 8580 8580f for more information www.linear.com/lt8580
15 a pplica t ions i n f or m a t ion using the circuit in figure 4 as an example, table 3 shows the parameters used to generate the bode plot shown in figure 6. in figure 6, the phase is C125 when the gain reaches 0db giving a phase margin of 55. the crossover frequency is 20khz, which is more than three times lower than the fre - quency of the rhp zero to achieve adequate phase margin. diode selection schottky diodes, with their low forward-voltage drops and fast switching speeds, are recommended for use with the lt8580. for applications where v r ( see tables 4, 5 and 6) < 40 v, the diodes, inc. sbr1v40lp is a good choice. where v r > 40 v, the diodes inc. dfls1100 works well. these diodes are rated to handle an average forward current of 1a. oscillator the operating frequency of the lt8580 can be set by the internal free-running oscillator. when the sync pin is driven low (< 0.4 v), the frequency of operation is set by a resistor from r t to ground. an internally trimmed timing capacitor resides inside the ic. the oscillator frequency is calculated using the following formula: f osc = 85.5 (r t + 1) where f osc is in mhz and r t is in k?. conversely, r t (in k?) can be calculated from the desired frequency (in mhz) using: r t = 85.5 f osc ? 1 clock synchronization the operating frequency of the lt8580 can be synchro- nized to an external clock source. to synchronize to the external source, simply provide a digital clock signal into the sync pin. the lt8580 will operate at the sync clock frequency. the lt8580 will revert to the internal free- running oscillator clock after sync is driven low for a few free-running clock periods. figure 6. bode plot for example boost converter frequency (hz) 10 60 gain (db) phase (deg) 80 100 120 100 1k 10k 100k 1m 8580 f06 40 20 0 ?20 140 ?180 ?135 ?90 ?45 ?225 ?270 ?315 ?360 0 55 at 20khz phase gain table 3. bode plot parameters parameter value units comment r l 40 w application specific c out 4.7 f application specific r esr 10 mw application specific r o 305 kw not adjustable c c 3300 pf adjustable c f 47 pf optional/adjustable c pl 0 pf optional/adjustable r c 6.04 kw adjustable r1 130 kw adjustable r2 14.6 kw not adjustable v out 12 v application specific v in 5 v application specific g ma 230 mho not adjustable g mp 7 mho not adjustable l 15 h application specific f s 1.5 mhz adjustable lt 8580 8580f for more information www.linear.com/lt8580
16 a pplica t ions i n f or m a t ion driving sync high for an extended period of time effec- tively stops the operating clock and prevents latch sr1 from becoming set ( see the block diagram). as a result, the switching operation of the lt8580 will stop. the duty cycle of the sync signal must be between 35% and 65% for proper operation. also, the frequency of the sync signal must meet the following two criteria: (1) sync may not toggle outside the frequency range of 200khz to 1.5 mhz unless it is stopped low to enable the free-running oscillator. (2) the sync frequency can always be higher than the free-running oscillator frequency, f osc , but should not be less than 25% below f osc . operating frequency selection there are several considerations in selecting the operat - ing frequency of the converter. the first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. for example, in products incorporating rf communications, the 455 khz if frequency is sensitive to any noise, therefore switching above 600 khz is desired. some communications have sensitivity to 1.1 mhz, and in that case, a 1.5 mhz switching converter frequency may be employed. the second consideration is the physical size of the converter. as the operating frequency goes up , the inductor and filter capacitors go down in value and size . the trade-off is efficiency, since the switching losses due to npn base charge ( see thermal calculations), schottky diode charge, and other capacitive loss terms increase proportionally with frequency. soft-start the lt8580 contains a soft- start circuit to limit peak switch currents during start-up. high start-up current is inherent in switching regulators in general since the feedback loop is saturated due to v out being far from its final value. the regulator tries to charge the output capacitor as quickly as possible, which results in large peak currents. the start-up current can be limited by connecting an external capacitor (typically 100nf to 1f) to the ss pin. this capacitor is slowly charged to ~2.1 v by an internal 280k resistor once the part is activated. ss pin voltages below ~1.1 v reduce the internal current limit. thus, the gradual ramping of the ss voltage also gradually increases the current limit as the capacitor charges. this, in turn, allows the output capacitor to charge gradually toward its final value while limiting the start-up current. in the event of a commanded shutdown or lockout (shdn pin), internal undervoltage lockout ( uvlo) or a thermal lockout, the soft- start capacitor is automatically discharged to ~200 mv before charging resumes, thus assuring that the soft-start occurs after every reactivation of the chip. shutdown the shdn pin is used to enable or disable the chip. for most applications, shdn can be driven by a digital logic source. voltages above 1.4 v enable normal active op - eration. v oltages below 300 mv will shutdown the chip, resulting in extremely low quiescent current. while the shdn voltage transitions through the lockout voltage range (0.3 v to 1.21 v) the power switch is disabled and the sr2 latch is set ( see the block diagram). this causes the soft- start capacitor to begin discharging, which continues until the capacitor is discharged and active op - eration is enabled. although the power switch is disabled, shdn voltages in the lockout range do not necessarily reduce quiescent current until the shdn voltage is near or below the shutdown threshold. also note that shdn can be driven above v in or v out as long as the shdn voltage is limited to less than 40v. figure 7. chip states vs shdn voltage (hysteresis and tolerance) shutdown (low quiescent current) active (normal operation) lockout (power switch off, ss capacitor discharged) 1.21v 0.0v 1.40v 0.3v 8580 f07 shdn (v) lt 8580 8580f for more information www.linear.com/lt8580
17 a pplica t ions i n f or m a t ion configurable undervoltage lockout figure 8 shows how to configure an undervoltage lock- out ( uvlo) for the lt8580. typically, uvlo is used in situations where the input supply is current-limited, has a relatively high source resistance, or ramps up/down slowly. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current-limit or latch low under low source voltage conditions. uvlo prevents the regulator from operating at source voltages where these problems might occur. the shutdown pin comparator has voltage hysteresis with typical thresholds of 1.31 v ( rising) and 1.27 v ( falling ). re - sistor r uvlo2 is optional. r uvlo2 can be included to reduce the overall uvlo voltage variation caused by variations in shdn pin current ( see the electrical characteristics). a good choice for r uvlo2 is 10k 1%. after choosing a value for r uvlo2 , r uvlo1 can be determined from either of the following: r uvlo1 = v in + ? 1.31v 1.31v r uvlo2 ? ? ? ? ? ? + 12a or r uvlo1 = v in ? ? 1.27v 1.27v r uvlo2 ? ? ? ? ? ? + 12a where v in + and v in C are the v in voltages when rising or falling, respectively. figure 8. configurable uvlo for example, to disable the lt8580 for v in voltages below 3.5v using the single resistor configuration, choose: r uvlo1 = 3.5v ? 1.27v 1.27v ? ? ? ? ? ? + 12a = 187k to activate the lt8580 for v in voltages greater than 4.5v using the double resistor configuration, choose r uvlo2 = 10k and: r uvlo1 = 4.5v ? 1.31v 1.31v 10k ? ? ? ? ? ? + 12a = 22.1k internal undervoltage lockout the lt8580 monitors the v in supply voltage in case v in drops below a minimum operating level ( typically about 2.35v). when v in is detected low, the power switch is deactivated, and while sufficient v in voltage persists, the soft-start capacitor is discharged. after v in is detected high, the power switch will be reactivated and the soft- start capacitor will begin charging. thermal considerations for the lt8580 to deliver its full output power, it is impera - tive that a good thermal path be provided to dissipate the heat generated within the package. this is accomplished by taking advantage of the thermal pad on the underside of the ic. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into a copper plane with as much area as possible. r uvlo2 (optional) 1.3v r uvlo1 8580 f08 v in v in active/ lockout gnd 12a at 1.3v ? + shdn lt 8580 8580f for more information www.linear.com/lt8580
18 a pplica t ions i n f or m a t ion thermal lockout if the die temperature reaches approximately 165 c, the part will go into thermal lockout, the power switch will be turned off and the soft-start capacitor will be discharged . the part will be enabled again when the die temperature has dropped by ~5c (nominal). thermal calculations power dissipation in the lt8580 chip comes from four primary sources: switch i 2 r loss, npn base drive ( ac), npn base drive ( dc), and additional input current. the following formulas can be used to approximate the power losses. these formulas assume continuous mode opera - tion, so they should not be used for calculating efficiency in discontinuous mode or at light load currents. average input current: i in = v out ? i out v in ? h switch i 2 r loss: p sw = (dc)(i in ) 2 (r sw ) base drive loss (ac): p bac = 20ns(i in )(v out )(f) base drive loss (dc): p bdc = (v in )(i in )(dc) 40 input power loss: p inp = 6ma (v in ) where: r sw = switch resistance (typically 530m? at 0.75a) dc = duty cycle ( see the power switch duty cycle sec- tion for formulas) h = power conversion efficiency (typically 85% at high currents) example: boost configuration, v in = 5 v, v out = 12 v, i out = 0.2a, f = 1.25mhz, v d = 0.5v: i in = 0.56a dc = 62.0% p sw = 105mw p bac = 169mw p bdc = 44mw p inp = 30mw total lt8580 power dissipation (p tot ) = 348mw thermal resistance for the lt8580 is influenced by the pres - ence of internal, topside or backside planes. to calculate die temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: t j = t a + ja ? p tot where t j = junction temperature, t a = ambient temperature, and ja is the thermal resistance from the silicon junction to the ambient air. the published ja value is 43 c/w for the 3mm 3mm dfn package and 35 c/w to 40 c/w for the msop ex- posed pad package. in practice, lower ja values can be obtained if the board layout uses ground as a heat sink. for instance, thermal resistances of 34.7 c/w for the dfn package and 22.5 c/w for the msop package were obtained on a board designed with large ground planes. v in ramp rate while initially powering a switching converter application, the v in ramp rate should be limited . high v in ramp rates can cause excessive inrush currents in the passive components of the converter. this can lead to current and/or voltage overstress and may damage the passive components or the chip. ramp rates less than 500mv/s, depending on component parameters, will generally prevent these issues. also, be careful to avoid hot - plugging. hot - plugging occurs when an active voltage supply is instantly connected or switched to the input of the converter. hot - plugging results in very fast input ramp rates and is not recommended. finally, for more information, refer to linear application note an88, which discusses voltage overstress that can occur when an inductive source impedance is hot-plugged to an input pin bypassed by ceramic capacitors. lt 8580 8580f for more information www.linear.com/lt8580
19 a pplica t ions i n f or m a t ion the board reduces die temperature and increases the power capability of the lt8580. provide as much copper area as possible around this pad. adding multiple feedthroughs around the pad to the ground plane will also help. figure 10 and figure 11 show the recommended component place - ment for the boost and sepic configurations, respectively . layout hints for inverting topology figure 12 shows recommended component placement for the dual inductor inverting topology. input bypass capaci - tor, c 1, should be placed close to the lt8580, as shown. the load should connect directly to the output capacitor, c2, for best load regulation. the local ground may be tied into the system ground plane at the c3 ground terminal. the cut ground copper at d1s cathode is essential to obtain low noise. this important layout issue arises due to the chopped nature of the currents flowing in q1 and d1. if they are both tied directly to the ground plane before being combined, switching noise will be introduced into the ground plane. it is almost impossible to get rid of this noise, once present in the ground plane. the solution is to tie d1s cathode to the ground pin of the lt8580 before the combined currents are dumped in the ground plane as drawn in figure 2, figure 13 and figure 14. this single layout technique can virtually eliminate high frequency spike noise, so often present on switching regulator outputs. d ifferences from lt3580 lt8580 is very similar to lt3580. however, lt8580 does deviate from lt3580 in a few areas: ? 65v, 1a switch ? 40v v in and shdn absolute maximum rating ? fb renamed to fbx ? 5v fbx absolute maximum rating figure 9. high speed chopped switching path for boost topology layout hints as with all high frequency switchers, when considering layout, care must be taken to achieve optimal electrical, thermal and noise performance. one will not get adver - tised per formance with a careless layout. for maximum efficiency, switch rise and fall times are typically in the 10ns to 20 ns range. to prevent noise, both radiated and conducted, the high speed switching current path, shown in figure 9, must be kept as short as possible. this is imple - mented in the suggested layout of a boost configuration in figure 10. shortening this path will also reduce the parasitic trace inductance. at switch-off, this parasitic inductance produces a flyback spike across the lt8580 switch. when operating at higher currents and output voltages, with poor layout, this spike can generate voltages across the lt8580 that may exceed its absolute maximum rating. a ground plane should also be used under the switcher circuitry to prevent interplane coupling and overall noise. the vc and fbx components should be kept as far away as practical from the switch node. the ground for these components should be separated from the switch cur - rent path . failure to do so can result in poor stability or subharmonic oscillation. board layout also has a significant effect on thermal re - sistance. the exposed package ground pad is the copper plate that runs under the lt8580 die. this is a good thermal path for heat out of the package. soldering the pad onto 8580 f09 v out l1 sw gnd lt8580 d1 c2 c1 v in high frequency switching path load lt 8580 8580f for more information www.linear.com/lt8580
20 figure 10. suggested component placement for boost topology (both dfn and msop packages. not to scale). pin 9 (exposed pad) must be soldered directly to the local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance figure 11. suggested component placement for sepic topology (both dfn and msop packages. not to scale). pin 9 (exposed pad) must be soldered directly to the local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance figure 12. suggested component placement for inverting topology (both dfn and msop packages. not to scale). note cut in ground copper at diodes cathode. pin 9 (exposed pad) must be soldered directly to local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance a pplica t ions i n f or m a t ion 8580 f11 v out v in 5 6 7 8 9 4 3 2 1 sw l1 l2 d1 c3 c2 c1 shdn sync gnd vias to ground plane required to improve thermal performance 8580 f12 v out v in 5 6 7 8 9 4 3 2 1 sw c1 c2 d1 c3 l1 l2 shdn sync gnd vias to ground plane required to improve thermal performance 8580 f10 v out v in c2 l1 c1 d1 5 6 7 8 9 4 3 2 1 sw shdn sync gnd vias to ground plane required to improve thermal performance lt 8580 8580f for more information www.linear.com/lt8580
21 a pplica t ions i n f or m a t ion figure 13. switch-on phase of an inverting converter. l1 and l2 have positive di/dt figure 14. switch-off phase of an inverting converter. l1 and l2 currents have negative di/dt + + l1 l2 c2 ?(v in + ?v out ?) sw swx d1 q1 8580 f13 c1 c3 r load ?v out v in v cesat + + l1 l2 c2 v in + ?v out ?+ v d sw swx d1 q1 c1 c3 r load ?v out v in v d 8580 f14 lt 8580 8580f for more information www.linear.com/lt8580
22 figure 15. boost converter: the component values and voltages given are typical values for a 1.5mhz, 5v to 12v boost a pplica t ions i n f or m a t ion c out 4.7f v out 12v 200ma l1 15h d1 r fbx 130k v in 5v v in sw 8580 f15 lt8580 10k r c 6.04k r t 56.2k shdn gnd fbx vc sync ss rt c c 3.3nf c f 47pf c ss 0.22f c in 2.2f b oost c onverter c omponent s election the lt8580 can be configured as a boost converter as in figure 15. this topology allows for positive output voltages that are higher than the input voltage. a single feedback resistor sets the output voltage. for output voltages higher than 60 v, see the charge pump aided regulators section. table 4 is a step-by-step set of equations to calculate com - ponent values for the lt8580 when operating as a boost converter. input parameters are input and output voltage, and switching frequency (v in , v out and f osc respectively). refer to the applications information section for further information on the design equations presented in table 4. variable definitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum average output current i ripple = inductor ripple current table 4. boost design equations parameters/equations step 1: inputs pick v in , v out , and f osc to calculate equations below step 2: dc dc max = v out C v in(min) + 0.5 v v out + 0.5 vC 0.4 v dc min = v out C v in(max) + 0.5 v v out + 0.5 vC 0.4 v step 3: l1 l typ = (v in(min) C 0.4v) ? dc max f osc ? 0.3a (1) l min = (v in(min) C 0.4v) ? (2 ? dc max C 1) 1.25 ? (dc max ? 300ns ? f osc ) ? (1C dc max ) (2) l max1 = (v in(min) C 0.4v) ? dc max f osc ? 0.08a (3) l max2 = (v in(max) C 0.4v) ? dc min f osc ? 0.08a (4) ? solve equations 1 to 4 for a range of l values ? the minimum of the l value range is the higher of l typ and l min ? the maximum of the l value range is the lower of l max1 and l max2 . step 4: i ripple i ripple(min) = (v in(min) C 0.4v) ? dc max f osc ? l 1 i ripple(max) = (v in(max) C 0.4v) ? dc min f osc ? l 1 step 5: i out i out(min) = 1a ? i ripple(min) 2 ? ? ? ? ? ? ? (1 ? dc max ) i out(max) = 1a ? i ripple(max) 2 ? ? ? ? ? ? ? (1 ? dc min ) step 6: d1 v r > v out ; i avg > i out step 7: c out c out i out ? dc max f osc ? 0.005 ? v out step 8: c in c in c vin + c pwr 1a ? dc max 40 ? f osc ? 0.005 ? v in(min) + i ripple(max) 8 ? f osc ? 0.005 ? v in(max) ? refer to the capacitor selection section for definition of c vin and c pwr step 9: r fbx r fbx = v out ? 1.204v 83.3a step 10: r t r t = 85.5 f osc C1; f osc in mhz and r t in k? note 1: this table uses 1a for the peak switch current. refer to the electrical characteristics table and typical performance characteristics plots for the peak switch current at an operating duty cycle. note 2: the final values for c out and c in may deviate from the previous equations in order to obtain desired load transient performance. lt 8580 8580f for more information www.linear.com/lt8580
23 figure 16. sepic converter: the component values and voltages given are typical values for a 1mhz, 9v to 16v input to 12v output sepic converter a pplica t ions i n f or m a t ion c out 4.7f v out 12v 240ma l1 22h d1 c1 1f r fbx 130k v in 9v to 16v v in sw 8580 f16 lt8580 487k r c 16.2k r t 84.5k shdn gnd fbx vc sync ss rt c c 1nf c f 22pf c ss 0.22f c in 4.7f l2 22h ? ? sepic c onverter c omponent s election (c oupled or u n c oupled i nductors ) the lt8580 can also be configured as a sepic, as shown in figure 16. this topology allows for positive output volt- ages that are lower, equal or higher than the input volt- age. output disconnect is inherently built into the sepic topology, meaning no dc path exists between the input and output due to capacitor c1. table 5 is a step- by- step set of equations to calculate com - ponent values for the lt8580 when operating as a sepic converter. input parameters are input and output voltage, and switching frequency ( v in , v out and f osc , respectively). refer to the applications information section for further information on the design equations presented in table 5. variable definitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum average output current i ripple = inductor ripple current table 5. sepic design equations parameters/equations step 1: inputs pick v in , v out and f osc to calculate equations below step 2: dc dc max = v out + 0.5 v v in(min) + v out + 0.5 vC 0.4v dc min = v out + 0.5 v v in(max) + v out + 0.5 vC 0.4v step 3: l l typ = (v in(min) C 0.4v) ? dc max f osc ? 0.3a (1) l min = (v in(min) C 0.4v) ? (2 ? dc max C 1) 1.25 ? (dc max ? 300ns ? f osc ) ? f osc ? (1C dc max ) (2) l max = (v in(min) C 0.4v) ? dc max f osc ? 0.08a (3) ? solve equations 1, 2 and 3 for a range of l values ? the minimum of the l value range is the higher of l typ and l min ? the maximum of the l value range is l max ? l = l1 = l2 for coupled inductors ? l = l1|| l2 for uncoupled inductors step 4: i ripple i ripple(min) = (v in(min) C 0.4v) ? dc max f osc ? l i ripple(max) = (v in(max) C 0.4v) ? dc min f osc ? l step 5: i out i out(min) = 1a ? i ripple(min) 2 ? ? ? ? ? ? ? 1 ? dc max ( ) i out(max) = 1a ? i ripple(max) 2 ? ? ? ? ? ? ? 1 ? dc min ( ) step 6: d1 v r > v in + v out ; i avg > i out step 7: c1 c1 1f; v rating v in step 8: c out c out i out(min) ? dc max f osc ? 0.005 ? v out step 9: c in c in c vin + c pwr 1a ? dc max 40 ? f osc ? 0.005 ? v in(min) + i ripple(max) 8 ? f osc ? 0.005 ? v in(max) ? refer to the capacitor selection section for definition of c vin and c pwr step 10: r fbx r fbx = v out ? 1.204v 83.3a step 11: r t r t = 85.5 f osc C1; f osc in mhz and r t in k? note 1: this table uses 1a for the peak switch current. refer to the electrical characteristics table and typical performance characteristics plots for the peak switch current at an operating duty cycle. note 2: the final values for c out , c in and c1 may deviate from the previous equations in order to obtain desired load transient performance. lt 8580 8580f for more information www.linear.com/lt8580
24 a pplica t ions i n f or m a t ion figure 17. dual inductor inverting converter: the component values and voltages given are typical values for a 750khz wide input (5v to 40v) to C15v inverting topology using coupled inductors c out 4.7f v out ?15v 90ma (v in = 5v) 210ma (v in = 12v) 420ma (v in = 40v) l1 22h l2 22h c1 1f d1 r fbx 182k v in 5v to 40v v in sw 8580 f17 lt8580 10k r c 13.7k r t 113k shdn gnd fbx vc sync ss rt c c 10nf c f 47pf c ss 0.22f c in 4.7f ? ? d ual i nductor i nver ting c onver ter c omponent s election (c oupled or u n c oupled i nductors ) due to its unique fbx pin, the lt8580 can work in a dual inductor inverting configuration as in figure 17. chang- ing the connections of l2 and the schottky diode in the sepic topology results in generating negative output voltages. this solution results in very low output voltage ripple due to inductor l2 being in series with the output. output disconnect is inherently built into this topology due to the capacitor c1. table 6 is a step-by-step set of equations to calculate component values for the lt8580 when operating as a dual inductor inverting converter. input parameters are input and output voltage, and switching frequency (v in , v out and f osc respectively). refer to the applications information section for further information on the design equations presented in table 6. variable definitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum average output current i ripple = inductor ripple current table 6. dual inductor inverting design equations parameters/equations step 1: inputs pick v in , v out and f osc to calculate equations below step 2: dc dc max = v out + 0.5 v v in(min) + v out + 0.5 vC 0.4 v dc min = v out + 0.5 v v in(max) + v out + 0.5 vC 0.4 v step 3: l l typ = (v in(min) C 0.4v) ? dc max f osc ? 0.3a (1) l min = (v in(min) C 0.4v) ? (2 ? dc max C 1) 1.25 ? (dc max ? 300ns ? f osc ) ? f osc ? (1C dc max ) (2) l max = (v in(min) C 0.4v) ? dc max f osc ? 0.08a (3) ? solve equations 1, 2 and 3 for a range of l values ? the minimum of the l value range is the higher of l typ and l min ? the maximum of the l value range is l max ? l = l1 = l2 for coupled inductors ? l = l1|| l2 for uncoupled inductors step 4: i ripple i ripple(min) = (v in(min) C 0.4v) ? dc max f osc ? l i ripple(max) = (v in(max) C 0.4v) ? dc min f osc ? l step 5: i out i out(min) = 1a ? i ripple(min) 2 ? ? ? ? ? ? ? 1 ? dc max ( ) i out(max) = 1a ? i ripple(max) 2 ? ? ? ? ? ? ? 1 ? dc min ( ) step 6: d1 v r > v in + |v out |; i avg > i out step 7: c1 c1 1f; v rating v in(max) + |v out | step 8: c out c out i ripple(max) 8 ? f osc (0.005 ? v out ) step 9: c in c in c vin + c pwr 1a ? dc max 40 ? f osc ? 0.005 ? v in(min) + i ripple(max) 8 ? f osc ? 0.005 ? v in(max) ? refer to the capacitor selection section for definition of c vin and c pwr step 10: r fbx r fbx = v out + 3mv 83.3a step 11: r t r t = 85.5 f osc C1; f osc in mhz and r t in k? note 1: this table uses 1a for the peak switch current. refer to the electrical characteristics table and typical performance characteristics plots for the peak switch current at an operating duty cycle. note 2: the final values for c out , c in and c1 may deviate from the previous equations in order to obtain desired load transient performance. lt 8580 8580f for more information www.linear.com/lt8580
25 typical a pplica t ions 1.5mhz, 5v to 12v output boost converter 50ma to 150ma to 50ma output load step efficiency and power loss c out 4.7f v out 12v 200ma l1 15h d1 130k v in 5v v in sw 8580 ta02a lt8580 10k 6.04k 56.2k shdn gnd fbx vc sync ss rt 3.3nf 47pf 0.22f l1: wrth 15h we-lqs 74404054150 d1: diodes inc. sbr1u40lp c in : 2.2f, 35v, 0805, x7r c out : 4.7f, 16v, 0805, x7r c in 2.2f load current (ma) 0 20 efficiency (%) power loss (mw) 40 50 60 100 100 8580 ta02b 30 50 150 200 70 80 90 0 180 300 480 240 60 120 380 420 efficiency power loss v out 500mv/div ac-coupled i step 100ma/div i l1 500ma/div 100s/div 8580 ta02c lt 8580 8580f for more information www.linear.com/lt8580
26 750khz, C15v output inverting converter accepts 5v to 40v input t ypical a pplica t ions efficiency and power loss (v in = 12v) 60ma to 160ma to 60ma output load step (v in = 12v) c out 4.7f v out ?15v 90ma (v in = 5v) 210ma (v in = 12v) 420ma (v in = 40v) l1 22h l2 22h c1 1f d1 182k v in 5v to 40v v in sw 8580 ta03a lt8580 10k 13.7k 113k shdn gnd fbx vc sync ss rt 10nf 47pf 0.22f c in 4.7f ? ? l1, l2: coilcraft 22h msd7342-223 d1: central semi cmmsh1-60 c in : 4.7f, 50v, 1206, x5r c out : 4.7f, 25v, 1206, x7r c1: 1f, 100v, 0805, x7s load current (ma) 0 10 efficiency (%) power loss (mw) 30 40 50 100 90 8580 ta03b 20 50 150 200 60 70 80 0 240 400 640 320 80 160 480 560 efficiency power loss v out 200mv/div ac-coupled i step 100ma/div i l1 + i l2 200ma/div 200s/div 8580 ta03c lt 8580 8580f for more information www.linear.com/lt8580
27 t ypical a pplica t ions 1.2mhz inverting converter generates C48v output from 12v input switching waveforms efficiency and power loss start-up waveforms c out 2.2f v out ?48v 70ma l1 150h l2 330h c1 1f d1 576k v in 12v v in sw 8580 ta04a lt8580 619k 20.5k 69.8k shdn gnd fbx vc sync ss rt 4.7nf 47pf 0.33f c in 1f c2 2.2f l1: cooper 150h dr74-151 l2: cooper 330h dr74-331 d1: diodes, inc. dfls1100 c in : 1f, 50v, 0805, x7r c out : 2.2f, 100v, 1206, x7r c1: 1f, 100v, 0805, x7s c2: 2.2f, 100v, 1206, x7s 49.9 load current (ma) 0 20 efficiency (%) power loss (mw) 30 40 50 50 90 8580 ta04b 40 60 2010 30 70 60 70 80 200 560 800 1040 680 320 440 920 efficiency power loss v out 20mv/div ac-coupled v sw 20v/div i l1 + i l2 200ma/div 200s/div 8580 ta04c v out 10v/div v sw 20v/div i l1 + i l2 200ma/div 200s/div 8580 ta04d lt 8580 8580f for more information www.linear.com/lt8580
28 t ypical a pplica t ions start-up waveforms vfd (vacuum fluorescent display) power supply switches at 1mhz danger high voltage! operation by high voltage trained personnel only efficiency and power loss (v in = 12v with load on v out3 ) c1 1 f v out1 60v 60ma* v out3 180v 20ma* v out2 120v 30ma* l1 68h c2 1f d1 698k v in 9v to 16v v in sw 8580 ta05a lt8580 487k 22.1k 84.5k shdn gnd fbx vc sync ss rt 4.7nf 330pf 0.47f c in 1f c4 1f c3 1f c5 1f d3 d2 l1: wrth 68h we-lqs 74404084680 d1-d5: diodes, inc. dfls1100 c in : 1f, 100v, 1206, x7r c1-c5: 1f, 100v, 1206, x7s *max total output power 3.5w 22 d4 22 d5 output power (w) 0 20 efficiency (%) power loss (mw) 30 40 50 2.5 90 8580 ta05b 2 3 10.5 1.5 3.5 60 70 80 400 640 800 960 720 480 560 880 efficiency power loss v out3 50v/div v out2 50v/div v out1 50v/div i l1 200ma/div 2ms/div 8580 ta05c lt 8580 8580f for more information www.linear.com/lt8580
29 550khz sepic converter generates 24v from 15v to 30v input transient response with 100ma to 225ma to 100ma output load step (v in = 24v) t ypical a pplica t ions efficiency and power loss (v in = 24v) load current (ma) 0 10 efficiency (%) power loss (mw) 30 20 40 50 200 90 8580 ta06b 150 250 50 100 300 60 70 80 200 800 1100 1400 950 500 350 650 1250 efficiency power loss v out 500mv/div ac-coupled i step 100ma/div i l1 + i l2 500ma/div 100s/div 8580 ta06c c out 4.7f v out 24v 195ma (v in = 15v) 300ma (v in = 24v) l1 47h l2 47h c1 1f d1 274k v in 15v to 30v v in sw 8580 ta06a lt8580 1m 12.7k 154k shdn gnd fbx vc sync ss rt 3.3nf 22pf 0.1f c in 2.2f ? ? l1, l2: coilcraft 47h msd7342-473 d1: diodes inc. dfls1100 c in : 2.2f, 35v, 0805, x7r c out : 4.7f, 35v, 1206, x7r c1: 1f, 100v, 0805, x7s lt 8580 8580f for more information www.linear.com/lt8580
30 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50 bsc 0.70 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. lt 8580 8580f for more information www.linear.com/lt8580
31 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms8e) 0213 rev k 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 8 1 bottom view of exposed pad option 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 1.68 (.066) 1.88 (.074) 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.889 0.127 (.035 .005) recommended solder pad layout 0.65 (.0256) bsc 0.42 0.038 (.0165 .0015) typ 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref ms8e package 8-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1662 rev k) lt 8580 8580f for more information www.linear.com/lt8580
32 ? linear technology corporation 2014 lt 0714 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt8580 r ela t e d p ar t s typical a pplica t ion part number description comments lt1310 2a (i sw ), 40v, 1.2mhz high efficiency step-up dc/dc converter v in : 2.3v to 16v, v out(max) = 40v, i q = 3ma, i sd < 1a, thinsot? package lt1613 550ma (i sw ), 1.4mhz high efficiency step-up dc/dc converter v in : 0.9v to 10v, v out(max) = 34v, i q = 3ma, i sd < 1a, thinsot package lt 1618 1.5a (i sw ), 1.25mhz high efficiency step-up dc/dc converter v in : 1.6v to 18v, v out(max) = 35v, i q = 1.8ma, i sd < 1a, ms10 package lt 1930 /lt1930a 1a (i sw ), 1.2mhz/2.2mhz high efficiency step-up dc/dc converter v in : 2.6v to 16v, v out(max) = 34v, i q = 4.2ma/5.5ma, i sd < 1a, thinsot package lt 1935 2a (i sw ), 40v, 1.2mhz high efficiency step-up dc/dc converter v in : 2.3v to 16v, v out(max) = 40v, i q = 3ma, i sd < 1a, thinsot package lt 1944 /lt1944-1 dual output 350ma (i sw ), constant off-time, high efficiency step-up dc/dc converter v in : 1.2v to 15v, v out(max) = 34v, i q = 20a, i sd < 1a, ms10 package lt 1946 /lt1946a 1.5a (i sw ), 1.2mhz/2.7mhz high efficiency step-up dc/dc converter v in : 2.6v to 16v, v out(max) = 34v, i q = 3.2ma, i sd < 1a, ms8e package lt 3467 1.1a (i sw ), 1.3mhz high efficiency step-up dc/dc converter v in : 2.6v to 16v, v out(max) = 40v, i q = 1.2ma, i sd < 1a, thinsot, 2mm 3mm dfn packages lt 3477 42v, 3a, 3.5mhz boost, buck-boost, buck led driver v in : 2.5v to 25v, v out(max) = 40v, analog/ pwm , i sd < 1a, qfn, tssop-20e packages lt 3479 3a full-featured dc/dc converter with soft-start and inrush current protection v in : 2.5v to 24v, v out(max) = 40v, analog/ pwm , i sd < 1a, dfn, tssop packages lt 3580 2a (i sw ), 42v, 2.5mhz, high efficiency step-up dc/dc converter v in : 2.5v to 32v, v out(max) = 42v, i q = 1ma, i sd = <1a, 3mm 3mm dfn-14, msop-16e lt 3581 3.3a (i sw ), 42v, 2.5mhz, high efficiency step-up dc/dc converter v in : 2.5v to 22v, v out(max) = 42v, i q = 1.9ma, i sd = <1a, 4mm 3mm dfn-14, msop-16e lt 3579 6a (i sw ), 42v, 2.5mhz, high efficiency, step-up dc/dc converter v in : 2.5v to 16v, v out(max) = 42v, i q = 1.9ma, i sd = <1a, 4mm 5mm dfn-20, tssop-20 lt 8582 dual channel, 3a (i sw ), 42v, 2.5mhz, high efficiency step-up dc/dc converter v in : 2.5v to 22v, v out(max) = 42v, i q = 2.1ma, i sd = <1a, 4mm 7mm dfn-24 efficiency and power loss (v in = 12v) 12v battery stabilizer survives 40v transients c out 4.7f v out 12v 240ma l1 22h l2 22h c1 1f d1 130k v in 9v to 16v up to 40v transient v in sw 8580 ta07a lt8580 487k 16.2k 84.5k shdn gnd fbx vc sync ss rt 1nf 22pf 0.22f c in 4.7f ? ? l1, l2: wrth 22h we-dd 744877220 d1: diodes inc. dfls1100 c in : 4.7f, 50v, 1206, x7r c out : 4.7f, 25v, 1206, x7r c1: 1f, 100v, 0805, x7s load current (ma) 0 10 efficiency (%) power loss (mw) 30 20 40 50 160 90 8580 ta07b 120 200 40 80 240 60 70 80 0 400 600 800 500 200 100 300 700 efficiency power loss lt 8580 8580f for more information www.linear.com/lt8580

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