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1. product profile 1.1 general description the blm7g1822s-20pb(g) is a dual section, 2-stage power mmic using nxp?s state of the art gen7 ldmos technology. this multiband device is perfectly suited as general purpose driver or small cell final in the frequency range from 1805 mhz to 2170 mhz. available in gull wing or straight lead outline. 1.2 features and benefits ? designed for broadband operation (frequency 1805 mhz to 2170 mhz) ? high section-to-section isolatio n enabling multip le combinations ? integrated temperature compensated bias ? biasing of individual stages is externally accessible ? integrated esd protection ? excellent thermal stability ? high power gain ? on-chip matching for ease of use ? compliant to directive 2002/ 95/ec, regarding restricti on of hazardous substances (rohs) 1.3 applications ? rf power mmic for multi-carrier and mu lti-standard gsm, w-cdma and lte base stations in the 1805 mhz to 2170 mhz frequ ency range. possible circuit topologies are the following as also depicted in section 8.1 : ? dual section or single ended ? doherty ? quadrature combined ? push-pull blm7g1822s-20pb; blm7g1822s-20pbg ldmos 2-stage power mmic rev. 3 ? 1 july 2015 product data sheet table 1. performance typical rf performance at t case = 25 ? c; i dq1 = 27 ma; i dq2 = 76 ma. test signal: 3gpp test model 1; 64 dpch; par = 9.9 db at 0.01% probability on ccdf; per section unless otherwise specified in a class-ab production circuit. test signal f v ds p l(av) g p ? d acpr 5m (mhz) (v) (w) (db) (%) (dbc) single carrier w-cdma 2167.5 28 2 32.3 23 ? 41
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 2 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 2. pinning information 2.1 pinning 2.2 pin description transparent top view the exposed backside of the package is the ground terminal of the device. fig 1. pin configuration ddd 9 '6$ 9 '6% 9 *6$ 9 *6% 9 *6$ 5)b287b$9 '6$ 5)b287b%9 '6% 9 *6% 5)b,1b$ 5)b,1b% qf qf qf qf qf qf slqlqgh[ table 2. pin description symbol pin description v ds(a1) 1 drain-source voltage of driver stage a1 v gs(a2) 2 gate-source voltage of final stage a2 v gs(a1) 3 gate-source voltage of driver stage a1 rf_in_a 4 rf input section a n.c. 5 not connected n.c. 6 not connected n.c. 7 not connected n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected rf_in_b 11 rf input section b v gs(b1) 12 gate-source voltage of driver stage b1 v gs(b2) 13 gate-source voltage of final stage b2 v ds(b1) 14 drain-source voltage of driver stage b1
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 3 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 3. ordering information 4. block diagram 5. limiting values [1] continuous use at maximum temperature will affect the reliability. for details refer to the online mtf calculator. rf_out_b/v ds(b2) 15 rf output section b / drain-source voltage of final stage b2 rf_out_a/v ds(a2) 16 rf output section a / drain-source voltage of final stage a2 gnd flange rf ground table 2. pin description ?continued symbol pin description table 3. ordering information type number package name description version blm7g1822s-20pb hsop16f plastic, heatsink smal l outline package; 16 leads(flat) sot1211-2 blm7g1822s-20pbg hsop16 plastic, heatsink small outline package; 16 leads sot1212-2 fig 2. block diagram ddd 9 '6$ 9 '6% 9 *6$ 5)b287b$9 '6$ 5)b287b%9 '6% 9 *6% 5)b,1b$ 5)b,1b% 7(03(5$785( &203(16$7('%,$6 9 *6% 9 *6$ 7(03(5$785( &203(16$7('%,$6 table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ds drain-source voltage - 65 v v gs gate-source voltage ? 0.5 +13 v t stg storage temperature ? 65 +150 ?c t j junction temperature [1] -225 ?c t case case temperature - 150 ?c
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 4 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 6. thermal characteristics [1] when operated with a cw signal. 7. characteristics [1] in production circuit with 1105 ? gate feed resistor. [2] in production circuit with 765 ? gate feed resistor. table 5. thermal characteristics measured for total device. symbol parameter conditions value unit r th(j-c) thermal resistance from junction to case final stage; t case =90 ? c; p l = 3.56 w [1] 1.9 k/w driver stage; t case =90 ? c; p l = 3.56 w [1] 6.2 k/w table 6. dc characteristics t case = 25 ? c; per section unless otherwise specified. symbol parameter conditions min typ max unit final stage v (br)dss drain-source breakdown voltage v gs =0v; i d = 150.8 ? a65--v v gsq gate-source quiescent voltage v ds =28 v; i d = 76 ma 1.5 2 2.5 v v ds =28 v; i d = 76 ma [1] 1.7 2.65 3.6 v ? i dq / ? t quiescent drain current variation with temperature ? 40 ?c ? t case ? +85 ?c [1] - ? 1- % i dss drain leakage current v gs =0v; v ds =28v --1.4 ? a i dsx drain cut-off current v gs = 5.55 v; v ds = 10 v - 2.8 - a i gss gate leakage current v gs =1.0v; v ds = 0 v - - 140 na driver stage v (br)dss drain-source breakdown voltage v gs =0v; i d = 30.16 ? a65--v v gsq gate-source quiescent voltage v ds =28 v; i d = 27 ma 1.6 2.1 2.6 v v ds =28 v; i d = 27 ma [2] 1.9 2.85 3.8 v ? i dq / ? t quiescent drain current variation with temperature ? 40 ?c ? t case ? +85 ?c [2] - ? 1- % i dss drain leakage current v gs =0v; v ds =28v --1.4 ? a i dsx drain cut-off current v gs = 5.55 v; v ds = 10 v - 0.55 - a i gss gate leakage current v gs =1.0v; v ds = 0 v - - 140 na
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 5 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic [1] 3gpp test model 1; 64 dpch; par = 9.9 db at 0.01% probability on ccdf. [2] f = 2170 mhz. 8. application information [1] measured on dual section evaluation board i dq1 = 40 ma (both sections); i dq2 = 150 ma (both sections). table 7. rf characteristics typical rf performance at t case = 25 ? c; v ds = 28 v; i dq1 = 27 ma; i dq2 = 76 ma; p l(av) = 2 w. per section unless otherwise specified, measured in a nxp wideband f = 1807.5 mhz to 2167.5 mhz straight lead production circuit. symbol parameter conditions min typ max unit test signal: single carrier w-cdma [1] g p power gain f = 1807.5 mhz - 34 - db f = 2167.5 mhz 30.8 32.3 33.8 db ? d drain efficiency f = 1807.5 mhz - 22 - % f = 2167.5 mhz 20 23 - % rl in input return loss f = 2167.5 mhz - ? 19 ? 10 db acpr 5m adjacent channel power ratio (5 mhz) f = 1807.5 mhz - ? 41 - dbc f = 2167.5 mhz - ? 41 ? 37 dbc par o output peak-to-average ratio f = 1807.5 mhz - 8.4 - db f = 2167.5 mhz 7.2 8.4 - db ? i dq / ? t quiescent drain current variation with temperature t = ? 40 ? c to +85 ? c final stage i dq ; gate feed resistor = 1105 ? - ? 1- % driver stage i dq ; gate feed resistor = 765 ? - ? 1- % test signal: cw [2] ?? s21 phase response difference between sections ? 10 - +10 deg ?? s 21 ? 2 insertion power gain difference between sections ? 0.5 - +0.5 db table 8. typical performance test signal: 1-tone cw; rf performance at t case = 25 ? c; v ds = 28 v; i dq1 = 45 ma (both sections); i dq2 = 140 ma (both sections) unless otherwise specif ied, measured in a nxp f = 2110 mhz to 2170 mhz straight lead class ab application circuit (see figure 3 for the component layout and figure 4 for the electrical schematic). symbol parameter conditions min typ max unit p l(1db) output power at 1 db gain compression f = 2140 mhz - 43.5 - w p l(3db) output power at 3 db gain compression f = 2140 mhz - 44.1 - w ? d drain efficiency at p l(1db) ; f = 2140 mhz - 47.6 - % g p power gain p l(av) = 1.585 w; f = 2140 mhz - 31.5 - db b video video bandwidth 2-tone cw; p l(av) = 1.585 w; f = 2140 mhz -170- mhz g flat gain flatness over a frequency range of 60 mhz; p l(av) =1.585w -0.4- db ? g/ ? t gain variation with temperature f = 2140 mhz - 0.03 - db/ ?c ?s 12 ? 2 isolation between sections a and b; p l(av) = 1.585 w; f = 2140 mhz [1] -28.5- db k rollett stability factor t = ? 40 ? c; f = 0.1 ghz to 3 ghz - >1 -
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 6 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic printed-circuit board (pcb): rogers 4350; thickness = 0.508 mm. fig 3. component layout ddd g% g% /0 /0 9 ** $ 9 ** % ? ? s) s) s) ?s) s) ?
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 7 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic fig 4. electrical schematic 5)b287b$9 '6$ 5)b287b%9 '6% 9 '6$ 6hfwlrq$ %/0*63% 6hfwlrq% %/0*63% 9 *6$ 9 *6$ 5)b,1b$ qf qf qf qf qf qf 5)b,1b% 9 *6% 9 *6% 9 '6% ddd n ;&36 ;&36 5)lq ) 9 ) 9 s) $7 & ) ) 9 ) 9 s) $7 & ) s) $7&) s) $7&) s) $7&) s) $7&) 'ulyhu fodpshg 5)vhqvh)(7 'ulyhu 5)srzhu)(7 9 '6 9 9 '6 9 9 '6 9 ) 9 /0 qp n n n n ) 9 ) 9 ) 9 '$&gulyh a9 a9 )lqdo fodpshg 5)vhqvh)(7 'ulyhu fodpshg 5)vhqvh)(7 )lqdo fodpshg 5)vhqvh)(7 )lqdo 5)srzhu)(7 'ulyhu 5)srzhu)(7 )lqdo 5)srzhu)(7 4xdg $%rxw ) 9 /0 qp n n n n ) 9 ) 9 ) 9 '$&gulyh a9 a9 9 '6 9 9 '6 9
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 8 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 8.1 possible circuit topologies fig 5. dual section or single ended fig 6. doherty fig 7. quadrature combined ddd ,q $ ,q g%-? g%-? ,q% 2xw$ 2xw 2xw% ddd g%-? g%-? &rpelqhu 2xw 6solwwhu ,q ddd g%-? g%-? 2xw g%&rxsohu g%&rxsohu ,q
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 9 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 8.2 ruggedness in class-ab operation the blm7g1822s-20pb and blm7g1822s-20pbg are capable of withstanding a load mismatch corresponding to vswr = 10 : 1 through all phases under the following conditions: v ds =32v; i dq1 = 20 ma (per section); i dq2 = 75 ma (per section); p i = 16 dbm (cw and corresponding to p l(3db) under z s = 50 ? load); f = 2140 mhz. 8.3 impedance information fig 8. push-pull ddd g%-? g%-? &rpelqhu 2xw 6solwwhu ,q table 9. typical impedance at 3 db compression point measured load-pull data per sect ion; test signal: pulsed cw; t case = 25 ? c; v ds = 28 v; i dq1 =20ma; i dq2 =65ma; t p =100 ? s; ? =10%; z s =50 ? . typical values unless otherwise specified. tuned for maximum output power tuned for maximum efficiency f z l g p(max) p l ? add am-pm conversion z l g p(max) p l ? add am-pm conversion (mhz) (? ) (db) (w) (%) (deg) (? ) (db) (w) (%) (deg) blm7g1822s-20pb 1700 15.3 ? j14.5 33.2 42.7 50.6 8.3 28.5 ? j20.2 34.6 41.6 56.5 9.2 1800 16.3 ? j11.7 32.9 42.7 50.8 6.3 31.3 ? j8.60 34.1 41.6 57.1 7.0 1900 16.1 ? j9.70 32.1 42.8 50.8 6.1 26.5 ? j0.01 33.3 41.7 57.3 6.9 2000 15.5 ? j8.10 31.5 42.8 50.1 6.1 21.0 + j2.20 32.6 42.0 56.4 7.3 2100 14.4 ? j6.90 31.5 42.9 50.0 6.9 15.6 + j2.00 32.9 42.1 55.8 8.6 2200 13.7 ? j6.60 31.7 42.7 49.8 8.5 12.3 + j1.20 33.0 41.6 54.3 9.6 2300 12.8 ? j6.80 31.4 42.5 49.1 10.6 10.0 + j0.10 32.5 41.3 53.6 10.3 blm7g1822s-20pbg 1700 15.8 ? j16.1 33.5 42.5 52.9 9.2 28.9 ? j21.8 35.1 41.6 57.9 11.1 1800 16.5 ? j13.8 32.9 42.5 51.2 7.7 30.6 ? j11.6 34.2 41.6 56.8 8.4 1900 16.7 ? j12.4 32.2 42.5 50.2 7.2 27.9 ? j4.64 33.5 41.7 55.9 7.8 2000 16.3 ? j9.74 31.7 42.5 51.2 7.3 20.4 + j0.45 32.7 41.7 55.6 9.0 2100 15.6 ? j8.61 31.5 42.6 52.0 9.5 15.9 + j0.68 32.6 41.7 56.5 11.8 2200 14.6 ? j8.87 31.3 42.5 49.7 10.3 12.7 ? j0.44 32.4 41.6 53.8 12.1 2300 13.4 ? j9.32 30.5 42.4 48.2 12.8 10.7 ? j1.98 31.7 41.6 53.7 13.2
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 10 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 8.4 graphs t case = 25 ? c; v ds =28v; i dq1 =22ma; i dq2 =70ma; p l = 1.585 w. per section. (1) magnitude of g p (2) magnitude of rl in t case = 25 ? c; v ds =28v; i dq1 =22ma; i dq2 =70ma; p l = 1.585 w. per section. (1) magnitude of g p (2) magnitude of rl in fig 9. wideband power gain and input return loss as function of frequency; typical values fig 10. in-band power gain and input return loss as function of frequency; typical values t case = 25 ? c; v ds =28v; i dq1 =22ma; i dq2 =70ma. per section. (1) f = 2110 mhz (2) f = 2140 mhz (3) f = 2170 mhz normalized at p l = 22 dbm; t case =25 ? c; v ds =28v; i dq1 =22ma; i dq2 = 70 ma. per section. (1) f = 2110 mhz (2) f = 2140 mhz (3) f = 2170 mhz fig 11. power gain and drain efficiency as function of output power; typical values fig 12. normalized phase response as a function of output power; typical values ddd i0+] * s * s g% g% g% 5/ 5/ lq lq 5/ lq g% g% g% ddd i0+] * s * s g% g% g% 5/ 5/ lq lq 5/ lq g% g% g% ddd 3 / g%p * s * s g% g% g% ' ' * s * s ' ' ddd 3 / g%p 3 3 v v 3 3 vqrup vqrup 3 v 3 vqrup ghj ghj ghj
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 11 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic t case = 25 ? c; v ds =28v; i dq1 =22ma; i dq2 = 70 ma; f = 2140 mhz; 2-tone cw; p l(av) = 0.25 w. per section. (1) imd low (2) imd high fig 13. intermodulation distortion as a function of tone spacing; typical values t case = 25 ? c; v ds =28v; i dq1 =22ma; i dq2 =70ma; f = 2140 mhz; 1-carrier w-cdma; test model 1; par = 7.2 db at 0.01 % probability on ccdf. per section. t case = 25 ? c; v ds =28v; i dq1 =20ma; i dq2 =75ma. per section. measured on evaluation board. fig 14. adjacent channel power ratio and drain efficiency as function of output power; typical values fig 15. isolation as a function of frequency; typical values ddd wrqhvsdflqj0+] ,0' ,0' ,0' g%f g%f g%f ,0' ,0' ,0' ,0' ,0' ,0' ,0' ,0' ,0' ddd 3 / g%p $&35 $&35 $&35 g%f g%f g%f ' ' $&35 $&35 0 0 $&35 0 $&35 $&35 0 0 $&35 0 ' ' ddd i0+] _v _v _ _v _ g% g% g%
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 12 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 9. package outline fig 16. package outline sot1211-2 (hsop16f) 5hihuhqfhv 2xwolqh yhuvlrq (xurshdq surmhfwlrq ,vvxhgdwh ,(& -('(& -(,7$ 627 vrwbsr 8qlw pp pd[ qrp plq $ +623)sodvwlfkhdwvlqnvpdoorxwolqhsdfndjhohdgviodw 627 $ $ e e f' ' ) ' ' ( ( ( ( h hh h h h h \ + ( 4 yz vfdoh ghwdlo; h ' ' h p p ' % \ % z ( ( slq lqgh[ e [ % z e[ $ $ 4 $ $ ( f + ( ' ( y$ ; 'lphqvlrqvppduhwkhruljlqdoglphqvlrqv h [ h [ h [ [ h [ h [0(7$/ 3527586,2166285&( )[ 1rwh 3dfndjherg\glphqvlrqv3'dqg3(grqrwlqfoxghprogdqgph wdosurwuxvlrqv$oorzdeohsurwuxvlrqlvppshuvlgh /hdgzlgwkglphqvlrqv3edqg3 e grqrwlqfoxghgdpedusurwuxvlrqv$oorzdeohgdpedusurwuxvlrqlvpplqwrwdoshuohdg
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 13 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic fig 17. package outline sot1212-2 (hsop16) ' 5hihuhqfhv 2xwolqh yhuvlrq (xurshdq surmhfwlrq ,vvxhgdwh ,(& -('(& -(,7$ 627 vrwbsr +623sodvwlfkhdwvlqnvpdoorxwolqhsdfndjhohdgv 627 ghwdlo; h ' ( f + ( ( ( [0(7$/ 3527586,2166285&( ' ' \ % + $ y$ ; z% e [ z% e [ $ 4 $ $ $ $ slqlqgh[ h h [ h [ [ / s h ( h [ h [ ? 8qlw pp pd[ qrp plq $ 'lphqvlrqvppduhwkhruljlqdoglphqvlrqv 1rwh 3dfndjherg\glphqvlrqv3'

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blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 14 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 10. handling information 11. abbreviations caution this device is sensitive to electrostatic di scharge (esd). observe precautions for handling electrostatic sensitive devices. such precautions are described in the ansi/esd s20.20 , iec/st 61340-5 , jesd625-a or equivalent standards. table 10. abbreviations acronym description am amplitude modulation 3gpp 3rd generation partnership project ccdf complementary cumulative distribution function cw continuous wave dpch dedicated physical channel esd electrostatic discharge gen7 seventh generation gsm global system for mobile communications ldmos laterally diffused metal oxide semiconductor lte long term evolution mmic monolithic microwave integrated circuit mtf median time to failure par peak-to-average ratio pm phase modulation vswr voltage standing-wave ratio w-cdma wideband code division multiple access
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 15 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 12. revision history table 11. revision history document id release date data sheet status change notice supersedes blm7g1822s-20pb_s-20pbg v.3 20150701 product data sheet - blm7g1822s-20pb_ s-20pbg v.2 modifications: ? table 1 on page 1 : the table has been updated ? section 1.3 on page 1 : first paragraph has been updated ? table 2 on page 2 : the table has been updated ? table 3 on page 3 : the package version of the blm7g1822s-20pb has been changed to sot1211-2 ? table 3 on page 3 : the package version of the blm7g1822s-20pbg has been changed to sot1212-2 ? table 6 on page 4 : the table has been updated ? table 7 on page 5 : the table has been updated ? table 8 on page 5 : the general conditions have been updated ? figure 3 on page 6 : the title of the figure has been changed ? section 8.2 on page 9 : the section has been updated ? table 9 on page 9 : the table has been updated ? figure 16 on page 12 : the figure now shows the sot1211-2 package outline ? figure 17 on page 13 : the figure now shows the sot1212-2 package outline blm7g1822s-20pb_s-20pbg v.2 20140626 objective data sheet - blm7g1822s-20pb_ s-20pbg v.1 blm7g1822s-20pb_s-20pbg v.1 20131219 objective data sheet - -
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 16 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 13. legal information 13.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 13.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 13.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 3 ? 1 july 2015 17 of 18 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 13.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 14. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic ? nxp semiconductors n.v. 2015. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 1 july 2015 document identifier: blm7g1822s-20pb_s-20pbg please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 15. contents 1 product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 general description . . . . . . . . . . . . . . . . . . . . . 1 1.2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 pinning information . . . . . . . . . . . . . . . . . . . . . . 2 2.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 thermal characteristics . . . . . . . . . . . . . . . . . . 4 7 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 application information. . . . . . . . . . . . . . . . . . . 5 8.1 possible circuit topologies . . . . . . . . . . . . . . . . 8 8.2 ruggedness in class-ab operation . . . . . . . . . 9 8.3 impedance information . . . . . . . . . . . . . . . . . . . 9 8.4 graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9 package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 10 handling information. . . . . . . . . . . . . . . . . . . . 14 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 13 legal information. . . . . . . . . . . . . . . . . . . . . . . 16 13.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 13.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 14 contact information. . . . . . . . . . . . . . . . . . . . . 17 15 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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