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18-bit, 2.5 lsb inl, 800 ksps sar adc ad7674 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2009 analog devices, inc. all rights reserved. features 18-bit resolution with no missing codes no pipeline delay (sar architecture) differential input range: v ref (v ref up to 5 v) throughput: 800 ksps (warp mode) 666 ksps (normal mode) 570 ksps (impulse mode) inl: 2.5 lsb max (9.5 ppm of full scale) dynamic range : 103 db typ (v ref = 5 v) s/(n+d): 100 db typ @ 2 khz (v ref = 5 v) parallel (18-,16-, or 8-bit bus) and serial 5 v/3 v interface spi?/qspi?/microwire?/dsp compatible on-board reference buffer single 5 v supply operation power dissipation: 98 mw typ @ 800 ksps 78 mw typ@ 500 ksps (impulse mode) 160 w @ 1 ksps (impulse mode) 48-lead lqfp or 48-lead lfcsp package pin-to-pin compatible upgrade of ad7676/ad7678/ad7679 applications ct scanners high dynamic data acquisition geophone and hydrophone sensors - replacement (low power, multichannel) instrumentation spectrum analysis medical instruments general description the ad7674 is an 18-bit, 800 ksps, charge redistribution sar, fully differential analog-to-digital converter that operates on a single 5 v power supply. the part contains a high speed 18-bit sampling adc, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports. the part is available in 48-lead lqfp or 48-lead lfcsp packages with operation specified from C40c to +85c. functional block diagram switched cap dac 18 control logic and calibration circuitry clock ad7674 d[17:0] busy rd cs mode0 ognd ovdd dgnd dvdd avdd agnd ref refgnd in+ in? pd reset serial port parallel interface cnvst pdbuf refbufin warp impulse mode1 03083?0?001 figure 1. functional block diagram table 1. pulsar tm selection type/ksps 100C250 500C570 800C 1000 pseudo- differential ad7651 ad7660/ad7661 ad7650/ad7652 ad7664/ad7666 ad7653 ad7667 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 18-bit ad7678 ad7679 ad7674 multichannel/ simultaneous ad7654 ad7655 product highlights 1. high resolution, fast throughput. the ad7674 is an 800 ksps, charge redistribution, 18-bit sar adc (no latency). 2. excellent accuracy. the ad7674 has a maximum integral nonlinearity of 2.5 lsb with no missing 18-bit codes. 3. serial or parallel interface. versatile parallel (18-, 16- or 8-bit bus) or 3-wire serial interface arrangement compatible with both 3 v and 5 v logic.
ad7674 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 table of contents .............................................................................. 2 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 definitions of specifications ......................................................... 11 typical performance characteristics ........................................... 12 circuit information ........................................................................ 16 converter operation .................................................................. 16 typical connection diagram ................................................... 18 power dissipation versus throughput .................................... 20 conversion control ................................................................... 20 digital interface .......................................................................... 20 parallel interface ......................................................................... 21 serial interface ............................................................................ 21 master serial interface ............................................................... 21 slave serial interface .................................................................. 22 microprocessor interfacing ....................................................... 24 application hints ........................................................................... 25 layout .......................................................................................... 25 evaluating the ad7674s performance .................................... 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 6/09rev. 0 to rev. a changes to zero error, t min to t max parameter ........................... 3 changes to gain error, t min to t max parameter ........................... 3 changes to endnote 3 ...................................................................... 4 changes to pin configuration section .......................................... 8 changes to evaluating the ad7679s performance section ...... 25 changes to ordering guide .......................................................... 26 7/03revision 0: initial version
ad7674 rev. a | page 3 of 28 specifications table 2. C40c to +85c, v ref = 4.096 v, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted. parameter conditions min typ max unit resolution 18 bits analog input voltage range v in+ C v inC Cv ref +v ref v operating input voltage v in+ , v inC to agnd C0.1 avdd v analog input cmrr f in = 100 khz 65 db input current 800 ksps throughput 100 a input impedance 1 throughput speed complete cycle in warp mode 1.25 s throughput rate in warp mode 1 800 ksps time between conversions in warp mode 1 ms complete cycle in normal mode 1.5 s throughput rate in normal mode 0 666 ksps complete cycle in impulse mode 1.75 s throughput rate in impulse mode 0 570 ksps dc accuracy integral linearity error C2.5 +2.5 lsb 2 differential linearity error C1 +1.75 lsb no missing codes 18 bits transition noise v ref = 5 v 0.7 lsb zero error, t min to t max in warp mode C25 +25 lsb zero error, t min to t max in normal or impulse mode C85 +85 lsb zero error temperature drift all modes 0.5 ppm/c gain error, t min to t max 3 in warp mode C0.034 +0.034 % of fsr gain error, t min to t max 3 in normal or impulse mode C0.048 +0.048 % of fsr gain error temperature drift all modes 1.6 ppm/c power supply sensitivity avdd = 5 v 5% 4 lsb ac accuracy signal-to-noise f in = 2 khz, v ref = 5 v 101 db 4 v ref = 4.096 v 97.5 99 db f in = 10 khz, v ref = 4.096 v 98 db f in = 100 khz, v ref = 4.096 v 97 db dynamic range v in+ = v inC = v ref /2 = 2.5 v 103 db spurious-free dynamic range f in = 2 khz 120 db f in = 10 khz 118 db f in = 100 khz 105 db total harmonic distortion f in = 2 khz C115 db f in = 10 khz C113 db f in = 100 khz C98 db signal-to-(noise + distortion) f in = 2 khz, v ref = 4.096 v 98 db f in = 2 khz, C60 db input 40 db C3 db input bandwidth 26 mhz sampling dynamics aperture delay 2 ns aperture jitter 5 ps rms transient response full-scale step 250 ns overvoltage recovery 250 ns
ad7674 rev. a | page 4 of 28 parameter conditions min typ max unit reference external reference voltage range ref 3 4.096 avdd + 0.1 v ref voltage with reference buffer refbufin = 2.5 v 4.05 4.096 4.15 v reference buffer input voltage range refbufin 1.8 2.5 2.6 v refbufin input current C1 +1 a ref current drain 800 ksps throughput 330 a digital inputs logic levels v il C0.3 +0.8 v v ih +2.0 dvdd + 0.3 v i il C1 +1 a i ih C1 +1 a digital outputs data format 5 pipeline delay 6 v ol i sink = 1.6 ma 0.4 v v oh i source = C500 a ovdd C 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 dvdd + 0.3 7 v operating current 8 800 ksps throughput avdd 16 ma dvdd 9 6.5 ma ovdd 9 50 a power dissipation 9 pdbuf high @ 500 ksps 10 78 90 mw pdbuf high @ 1 ksps 10 160 w pdbuf high @ 800 ksps 8 114 126 mw pdbuf low @ 800 ksps 8 126 138 mw temperature range 11 specified performance t min to t max C40 +85 c 1 see analog inputs section. 2 lsb means least significant bit. with th e 4.096 v input range, 1 lsb is 31.25 v. 3 see definitions of specifications section. the nominal gain error is no t centered at zero and is ?0 .029% of fsr. this specific ation is the deviation from this nominal value. these specifications do not include the error contribution from the external reference, but do include the error contrib ution from the reference buffer if used. 4 all specifications in db are referred to a full-scale input, fs. tested with an input signal at 0.5 db below full scale unless otherwise specified. 5 data format parallel or serial 18-bit. 6 conversion results are available imme diately after completed conversion. 7 the max should be the minimu m of 5.25 v and dvdd + 0.3 v. 8 in warp mode. 9 tested in parallel reading mode. 10 in impulse mode. 11 contact factory for extended temperature range.
ad7674 rev. a | page 5 of 28 timing specifications table 3. C40c to +85c, avdd = dvdd = 5 v, ov dd = 2.7 v to 5.25 v, unless otherwise noted. parameter symbol min typ max unit refer to figure 34 and figure 35 convert pulsewidth t 1 10 ns time between conversions (warp mode/normal mode/impulse mode) 1 t 2 1.25/1.5/1.75 s cnvst low to busy high delay t 3 35 ns busy high all modes except master serial read after convert (warp mode/normal mode/impulse mode) t 4 1/1.25/1.5 s aperture delay t 5 2 ns end of conversion to busy low delay t 6 10 ns conversion time (warp mode/normal mode/impulse mode) t 7 1/1.25/1.5 s acquisition time t 8 250 ns reset pulsewidth t 9 10 ns refer to figure 36, figure 37, and figure 38 (parallel interface modes) cnvst low to data valid delay (warp mode/normal mode/impulse mode) t 10 1/1.25/1.5 s data valid to busy low delay t 11 20 ns bus access request to data valid t 12 45 ns bus relinquish time t 13 5 15 ns refer to figure 40 and figure 41 (master serial interface modes) 2 cs low to sync valid delay t 14 10 ns cs low to internal sclk valid delay t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay (warp mode/normal mode/impulse mode) t 17 25/275/525 ns sync asserted to sclk first edge delay 3 t 18 3 ns internal sclk period 3 t 19 25 40 ns internal sclk high 3 t 20 12 ns internal sclk low 3 t 21 7 ns sdout valid setup time 3 t 22 4 ns sdout valid hold time 3 t 23 2 ns sclk last edge to sync delay 3 t 24 3 cs high to sync hi-z t 25 10 ns cs high to internal sclk hi-z t 26 10 ns cs high to sdout hi-z t 27 10 ns busy high in master serial read after convert 3 t 28 table 4 cnvst low to sync asserted delay (warp mode/normal mode/impulse mode) t 29 1/1.25/1.5 s sync deasserted to busy low delay t 30 25 ns refer to figure 42 and figure 43 (slave serial interface modes) external sclk setup time t 31 5 ns external sclk active edge to sdout delay t 32 3 18 ns sdin setup time t 33 5 ns sdin hold time t 34 5 ns external sclk period t 35 25 ns external sclk high t 36 10 ns external sclk low t 37 10 ns 1 in warp mode only, the maximu m time between conversions is 1 ms; otherw ise, there is no re quired maximum time. 2 in serial interface modes, the sync, sclk, an d sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 3 in serial master read during convert mode. see table 4 for serial master read after convert mode.
ad7674 rev. a | page 6 of 28 table 4. serial clock timings in master read after convert divsclk[1] symbol 0 0 1 1 unit divsclk[0] 0 1 0 1 sync to sclk first edge delay minimum t 18 3 17 17 17 ns internal sclk period minimum t 19 25 60 120 240 ns internal sclk period maximum t 19 40 80 160 320 ns internal sclk high minimum t 20 12 22 50 100 ns internal sclk low minimum t 21 7 21 49 99 ns sdout valid setup time minimum t 22 4 18 18 18 ns sdout valid hold time minimum t 23 2 4 30 89 ns sclk last edge to sync delay minimum t 24 3 60 140 300 ns busy high width maximum (warp) t 28 1.75 2.5 4 7 s busy high width maximum (normal) t 28 2 2.75 4.25 7.25 s busy high width maximum (impulse) t 28 2.25 3 4.5 7.5 s
ad7674 rev. a | page 7 of 28 absolute maximum ratings table 5. ad7674 absolute maximum ratings 1 parameter rating analog inputs in+ 2 , inC 2 , ref, refbufin, refgnd to agnd agnd C 0.3 v to avdd + 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages avdd, dvdd, ovdd C0.3 v to +7 v avdd to dvdd, avdd to ovdd 7 v dvdd to ovdd C0.3 v to +7 v digital inputs C0.3 v to dvdd + 0.3 v internal power dissipation 3 700 mw internal power dissipation 4 2.5 w junction temperature 150c storage temperature range C65c to +150c lead temperature range (soldering 10 sec) 300c 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute max imum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: ja = 91c/w, jc = 30c/w. 4 specification is for device in free air: 48-lead lfcsp: ja = 26c/w. to output pin c l 60pf 1 500 a i oh 1.6ma i ol 1.4v in serial interface modes,the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise,the load is 60pf maximum. note 1 03083?0?002 figure 2. load circuit for digital interface timing, sdout, sync, sclk outputs, c l = 10 pf 0.8v 2v 2v 0.8v t delay 2v 0.8v t delay 03083?0?003 figure 3. voltage reference levels for timing esd caution
ad7674 rev. a | page 8 of 28 pin configuration and fu nction descriptions 13 14 15 16 17 18 19 20 21 22 23 24 d6/ext/int d7/invsync d8/invsclk d9/rdc/sdin ognd ovdd dvdd dgnd d10/sdout d11/sclk d12/sync d13/rderror 48 47 46 45 44 43 42 41 40 39 38 37 pdbuf avdd refbufin nc agnd in+ nc nc nc in? refgnd ref 1 2 3 4 5 6 7 8 9 10 11 12 agnd avdd mode0 mode1 d0/ob/2c warp impulse d1/a0 d2/a1 d3 d4/divsclk[0] d5/divsclk[1] notes 1. nc = no connect. 2 . the exposed pad is internally connected to agnd. this connection is not required to meet the electrical performances however, for increased reliability of the solder joints, it is recommended that the pad be soldered to the analog ground of the system. cnvst pd reset cs rd dgnd busy d17 d16 d15 d14 35 agnd 36 34 33 32 31 30 29 28 27 26 25 ad7674 top view (not to scale) pin 1 indicator 03083-004 figure 4. 48-lead lqfp and 48-lead lfcsp (st-48 and cp-48) table 6. pin function descriptions pin no. mnemonic type 1 description 1, 44 agnd p analog power ground pin. 2, 47 avdd p input analog power pins. nominally 5 v. 3 mode0 di data output interface mode selection. 4 mode1 di data output interface mode selection: interface mode # mode1 mode0 description 0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 byte interface 3 1 1 serial interface 5 d0/ob/2c di/o when mode = 0 (18-bit interface mode), this pin is bit 0 of the parallel port data output bus and the data coding is straight binary. in all other modes, this pin allows choice of straight binary/binary twos complement. when ob/2c is high, the digital output is straight binary; when low, the msb is inverted, resulting in a twos complement output from its internal shift register. 6 warp di conversion mode selection. when this input is hi gh and the impulse pin is low, warp selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. when lo w, full accuracy is maintained independent of the minimum conversion rate. 7 impulse di conversion mode selection. when this input is high and the warp pin is low, impulse selects a reduced power mode. in this mode, the power dissipation is approximately proportional to the sampling rate. when warp and impulse pins are low, the normal mode is selected. 8 d1/a0 di/o when mode = 0 (18-bit interface mode), this pin is bi t 1 of the parallel port data output bus. in all other modes, this input pin controls the form in wh ich data is output, as shown in table 7.
ad7674 rev. a | page 9 of 28 pin no. mnemonic type 1 description 9 d2/a1 di/o when mode = 0 or 1 (18-bit or 16-bit interface mode), this pin is bit 2 of the parallel port data output bus. in all other modes, this input pin controls the fo rm in which data is outp ut, as shown in table 7. 10 d3 do in all modes except mode = 3, this output is used as bit 3 of the paralle l port data output bus. this pin is always an output, regardless of the interface mode. 11, 12 d[4:5]or divsclk[0:1] di/o in all modes except mode = 3, these pins ar e bit 4 and bit 5 of the parallel port data output bus. when mode = 3 (serial mode), when ext/int is low and rdc/sdin is low (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. in other serial modes, these pins are not used. 13 d6 or ext/int di/o in all modes except mode = 3, this output is used as bit 6 of the parallel port data output bus. when mode = 3 (serial mode), this in put, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data cl ock. with ext/int tied low, the internal clock is selected on the sclk output. with ext/int set to a logic high, output data is synchronized to an external clock signal connected to the sclk input. 14 d7 or invsync di/o in all modes except mode = 3, this output is used as bit 7 of the parallel port data output bus. when mode = 3 (serial mode), this inp ut, part of the serial port, is used to select the active state of the sync signal. when low, sync is active high. when high, sync is active low. 15 d8 or invsclk di/o in all modes except mode = 3, this output is used as bit 8 of the parallel port data output bus. when mode = 3 (serial mode), this inp ut, part of the serial port, is used to invert the sclk signal. it is active in both master and slave mode. 16 d9 or rdc/sdin di/o in all modes except mode = 3, this output is used as bit 9 of the parallel port data output bus. when mode = 3 (serial mode), this inp ut, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of ext/int . when ext/ int is high, rdc/sdin could be used as a data input to da isy-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 18 sclk periods after the initiation of the read sequence. when ext/int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the data is o utput on sdout during conversion. wh en rdc/sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground. 18 ovdd p output interface digital power. nominally at the same supply as the host interface (5 v or 3 v). should not exceed dvdd by more than 0.3 v. 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground. 21 d10 or sdout do in all modes except mode = 3, this output is used as bit 10 of the parallel port data output bus. when mode = 3 (serial mode), this output, part of the serial port, is used as a se rial data output synchronized to sclk. conversion results are stor ed in an on-chip register. the ad7674 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/2c . in serial mode when ext/int is low, sdout is valid on both edges of sclk. in serial mode when ext/int is high and invsclk is low, sdout is updated on the sclk rising edge and is valid on the next falling edge; if invsclk is high, sdout is updated on the sclk falling edge and is valid on the next rising edge. 22 d11 or sclk di/o in all modes except mode = 3, this output is used as bit 11 of the parallel port data output bus. when mode = 3 (serial mode), this pin, part of the se rial port, is used as a serial data clock input or output, dependent upon the logic state of the ext/int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. 23 d12 or sync do in all modes except mode = 3, this output is used as bit 12 of the parallel port data output bus. when mode = 3 (serial mode), this output, part of the serial port, is used as a digital output frame synchronization for use with th e internal data clock (ext/int = logic low). when a read sequence is initiated and invsync is low, sync is driven high and remains high while the sdout output is valid. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. 24 d13 or rderror do in all modes except mode = 3, this output is used as bit 13 of the parallel port data output bus. in mode = 3 (serial mode) and when ext/ int is high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started and not complete when the following conversion is complete, the curren t data is lost and rd error is pulsed high. 25C28 d[14:17] do bit 14 to bit 17 of the parallel port data output bus. these pins are always outputs regardless of the interface mode.
ad7674 rev. a | page 10 of 28 pin no. mnemonic type 1 description 29 busy do busy output. transitions high when a conversion is started. remains high until the conversion is complete and the data is latched into the on-chip shif t register. the falling edge of busy could be used as a data ready clock signal. 30 dgnd p must be tied to digital ground. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock. 33 reset di reset input. when set to a logic high, reset the ad7674. current conversion, if any, is aborted. if not used, this pin could be tied to dgnd. 34 pd di power-down input. when set to a logic high, power consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst di start conversion. a falling edge on cnvst puts the internal sample/hold into the hold state and initiates a conversion. in impulse mode (impulse high, warp low), if cnvst is held low when the acquisition phase (t 8 ) is complete, the internal sample/hold is put in to hold and a conversion is immediately started. 36 agnd p must be tied to analog ground. 37 ref ai reference input voltage and internal reference buffer output. apply an external reference on ref if the internal reference buffer is not used. should be deco upled effectively with or wi thout the internal buffer. 38 refgnd ai reference input analog ground. 39 inC ai differential negative analog input. 40C42, 45 nc no connect. 43 in+ ai differential positive analog input. 46 refbufin ai reference buffer input voltage. the internal reference buffer has a fixed gain. it outputs 4.096 v typically when 2.5 v is applied on this pin. 48 pdbuf di allows choice of buffering reference. when low, buffer is selected. when high, buffer is switched off. 49 (epad) exposed pad the exposed pad is internally connected to agnd. this connection is not required to meet the electrical performances however, for increased reliability of th e solder joints, it is recommended that the pad be soldered to the analog ground of the system. 1 ai = analog input; di = digital input; di/o = bi directional digital; do = dig ital output; p = power. table 7. data bus interface definitions mode mode1 mode0 d0/ob/ 2c d1/a0 d2/a1 d[3] d[4:9] d[10:11] d[12:15] d[16:17] description 0 0 0 r[0] r[1] r[2] r[ 3] r[4:9] r[10:11] r[12:15] r[16:17] 18-bit parallel 1 0 1 ob/2c a0:0 r[2] r[3] r[4:9] r[10:11] r[12:15] r[16:17] 16-bit high word 1 0 1 ob/2c a0:1 r[0] r[1] all zeros 16-bit low word 2 1 0 ob/2c a0:0 a1:0 all hi-z r[10:11] r[12:15] r[16:17] 8-bit high byte 2 1 0 ob/2c a0:0 a1:1 all hi-z r[2:3] r[4:7] r[8:9] 8-bit mid byte 2 1 0 ob/2c a0:1 a1:0 all hi-z r[0:1] all zeros 8-bit low byte 2 1 0 ob/2c a0:1 a1:1 all hi-z all zeros r[0:1] 8-bit low byte 3 1 1 ob/2c all hi-z serial interface serial interface r[0:17] is the 18-bit adc value stored in its output register.
ad7674 rev. a | page 11 of 28 definitions of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. gain error the first transition (from 00000 to 00001) should occur for an analog voltage ? lsb above the nominal negative full scale (C4.095991 v for the 4.096 v range). the last transition (from 11110 to 11111) should occur for an analog voltage 1? lsb below the nominal full scale (4.095977 v for the 4.096 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. zero error the zero error is the difference between the ideal midscale input voltage (0 v) from the actual voltage producing the midscale output code. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input, and is expressed in bits. it is related to s/(n+d) by the following formula: enob = ( s /[ n + d ] db C 1.76)/6.02 total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response transient response is the time required for the ad7674 to achieve its rated accuracy after a full-scale step function is applied to its input.
ad7674 rev. a | page 12 of 28 typical performance characteristics code 2.5 0 65536 131072 196608 262144 inl-lsb (18-bit) 1.5 1.0 0 ?1.5 0.5 ?0.5 03083-0-005 ?1.0 2.0 figure 5. integral nonlinearity vs. code code in hex 70000 2004c 0 counts 60000 40000 20000 0 30000 10000 50000 2004d 0 2004e 87 2004f 5073 20050 59121 20051 20052 20053 47 20054 0 20055 0 v ref = 5v 7165 58556 03083-0-006 figure 6. histogram of 131,072 conversions of a dc input at the code transition positive inl (lsb) 120 0 number of units 100 60 20 0 40 80 0.5 1.0 1.5 2.0 03083-0-007 2.5 figure 7. typical positive inl distribution (424 units) code 2.0 0 65536 131072 196608 26214 4 dnl-lsb (18-bit) 1.5 1.0 0 ?1.0 0.5 ?0.5 03083-0-008 figure 8. differential nonlinearity vs. code code in hex 90000 2004d 0 counts 60000 40000 20000 0 30000 10000 50000 1 2004e 2004f 20050 20051 20052 20053 627 20054 8 20055 0 v ref = 5v 25964 70000 80000 26939 28939 03083-0-009 793 figure 9. histogram of 131,072 conversions of a dc input at the code center negative inl (lsb) 100 ?2.5 number of units 80 60 20 0 50 70 ?2.0 ?1.5 1.0 ?0.5 03083-0-010 90 40 30 10 0 figure 10. typical negative inl distribution (424 units)
ad7674 rev. a | page 13 of 28 positive dnl (lsb) 120 0 number of units 100 60 20 0 40 80 0.5 1.0 1.5 03083-0-011 2.0 figure 11. typical positive dnl distribution (424 units) frequency (khz) 0 0 50 100 400 amplitude (db of full scale) ?40 ?60 ?100 ?180 ?80 ?120 03083-0-012 ?140 ?20 ?160 150 200 250 300 350 f s = 800ksps f in = 10khz v ref = 4.096v snr = 98.4db thd = 119.1db sfdr = 120.4db sinad = 98.4db figure 12. fft (10 khz tone) frequency (khz) 0 0 50 100 400 amplitude (db of full scale) ?40 ?60 ?100 ?180 ?80 ?120 03083-0-013 ?140 ?20 ?160 150 200 250 300 350 f s = 800ksps f in = 100khz v ref = 4.096v snr = 98.8db thd = 104.3db sfdr = 104.9db sinad = 97.8db figure 13. fft (100 khz tone) negative dnl (lsb) 250 ?2.0 number of units 200 150 50 0 ?1.5 ?1.0 ?0.5 03083-0-014 100 0 figure 14. typicalnegative dnl distribution (424 units) frequency (khz) 102 1 snr and s/[n+d] (db) 99 90 78 75 84 96 10 100 1000 03083-0-015 93 81 87 enob s/(n+d) snr 16.0 16.5 15.0 15.5 14.0 14.5 13.5 enob (bits) figure 15. snr, s/(n+d), and enob vs. frequency frequency (khz) ?60 1 thd, harmonics (db) ?70 ?100 ?130 ?120 ?80 10 100 1000 03083-0-016 ?90 ?110 thd third harmonic sfdr 140 60 20 40 0 sfdr (db) 120 80 100 second harmonic figure 16. thd, sfdr, and harmonics vs. frequency
ad7674 rev. a | page 14 of 28 input level (db) ?60 snr referred to full scale (db) 101 98 95 96 100 03083-0-017 99 97 snr ?50 0 ?10 ?20 ?30 ?40 105 102 104 103 v ref = 4.096v s/(n+d) figure 17. snr and s/(n+d) vs. input level ?55 snr, s/[n+d] (db) 98 96 03083-0-018 99 97 ?35 125 85 65 5 ?15 100 snr enob 14.5 15.0 15.5 16.5 16.0 s/(n+d) 25 45 105 temperature ( c) v ref = 4.096v figure 18. snr, s/(n+d), and enob vs. temperature temperature ( c) ?55 thd, harmonics (db) ?120 ?140 03083-0-019 ?110 ?130 ?35 125 85 65 5 ?15 ?100 25 45 105 third harmonic second harmonic thd figure 19. thd and harmonics vs. temperature sampling rate (sps) 100000 operating currents ( a) 0.001 1m 10000 1000 100 10 1 0.1 0.01 100k 10k 1k 100 1 avdd, warp/normal avdd, impulse 10 dvdd, warp/normal dvdd, impulse ovdd, all modes pdbuf high 03083-0-020 figure 20. operating current vs. sampling rate temperature ( c) 800 ?55 power-down operating currents (na) 700 500 300 0 400 100 600 125 dvdd ?35?155 25456585105 avdd ovdd 03083-0-021 figure 21. power-down operating currents vs. temperature temperature ( c) ?55 zero error,positive and negative full scale (lsb) ?15 ?25 03083-0-022 ?20 ?35 125 85 65 5 ?15 25 25 45 105 ?5 5 ?10 0 10 15 20 positive full scale negative full scale zero error figure 22. zero error, positive and negative full scale vs. temperature
ad7674 rev. a | page 15 of 28 avdd (v) 4.50 20 ?30 03083-0-023 5.50 5.25 4.75 30 5.00 10 10 20 zero error,positive and negative full scale (lsb) positive full scale negative full scale zero error 0 figure 23. zero error, positive and negative full scale vs. supply c l (pf) 0 t 12 delay (ns) 10 0 03083-0-024 200 150 50 50 100 30 20 40 ovdd = 2.7v @ 85c ovdd = 5v @ 85c ovdd = 5v @ 25c ovdd = 2.7v @ 25c figure 24. typical delay vs. load capacitance c l
ad7674 rev. a | page 16 of 28 circuit information in+ ref refgnd in? msb 4c 2c c c lsb sw+ switches control 262,144c 131,072c msb 4c 2c c c lsb sw? busy output code cnvst control logic comp 262,144c 131,072c 03083?0?025 figure 25. adc simplified schematic the ad7674 is a very fast, low power, single-supply, precise 18-bit analog-to-digital converter (adc) using successive approximation architecture. the ad7674s linearity and dynamic range are similar to or better than many - adcs. with the advantages of its successive architecture, which ease multiplexing and reduce power with throughput, it can be advantageous in applications that normally use - adcs. the ad7674 features different modes to optimize performance according to the applications. in warp mode, the ad7674 is capable of converting 800,000 samples per second (800 ksps). the ad7674 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. the ad7674 can be operated from a single 5 v supply and can be interfaced to either 5 v or 3 v digital logic. it is housed in a 48-lead lqfp, or a tiny 48-lead lfcsp package that offers space savings and allows for flexible configurations as either a serial or parallel interface. the ad7674 is a pin-to-pin compatible upgrade of the ad7676, ad7678, and ad7679. converter operation the ad7674 is a successive approximation adc based on a charge redistribution dac. figure 25 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 18 binary weighted capacitors that are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to agnd via sw+ and swC. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and inC inputs. when the acquisition phase is complete and the cnvst input goes low, a conversion phase is initiated. when the conversion phase begins, sw+ and swC are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the refgnd input. therefore, the differential voltage between the in+ and inC inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between refgnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4, ... v ref /262144). the control logic toggles these switches, starting with the msb first, to bring the comparator back into a balanced condition. after completing this process, the control logic generates the adc output code and brings the busy output low. modes of operation the ad7674 features three modes of operation: warp, normal, and impulse. each mode is more suited for specific applications. warp mode allows conversion rates up to 800 ksps. however, in this mode and this mode only, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. if the time between two consecutive conversions is longer than 1 ms (e.g., after power-up), the first conversion result should be ignored. this mode makes the ad7674 ideal for applications where a fast sample rate is required. normal mode is the fastest mode (666 ksps) without any limitation on the time between conversions. this mode makes the ad7674 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. impulse mode, the lowest power dissipation mode, allows power saving between conversions. the maximum throughput in this mode is 570 ksps. when operating at 1 ksps, for example, it typically consumes only 136 w. this feature makes the ad7674 ideal for battery-powered applications.
ad7674 rev. a | page 17 of 28 transfer functions except in 18-bit interface mode, the ad7674 offers straight binary and twos complement output coding when using ob/ 2c . see figure 26 and table 8 for the ideal transfer characteristic. 000...000 000...001 000...010 111...101 111...110 111...111 analog input +fs ? 1.5 lsb +fs ? 1 lsb ?fs + 1 lsb ?fs ?fs + 0.5 lsb adc code (straight binary) 03083-0-026 figure 26. adc ideal transfer function table 8. output codes and ideal input voltages description analog input v ref = 4.096 v straight binary (hex) twos complement (hex) fsr C 1 lsb 4.095962 v 3ffff 1 1ffff 1 fsr C 2 lsb 4.095924 v 3fffe 1fffe midscale + 1 lsb 31.25 v 20001 00001 midscale 0 v 20000 00000 midscale C 1 lsb C31.25 v 1ffff 3ffff Cfsr + 1 lsb C4.095962 v 00001 20001 Cfsr C4.096 v 00000 2 20000 2 1 this is also the code fo r overrange analog input (v in+ C v inC above v ref C v refgnd ). 2 this is also the code fo r underrange analog input (v in+ C v inC below Cv ref + v refgnd ). avd d agnd dgnd dvdd ovdd ognd cnvst busy sdout sclk rd cs reset pd 2.5v ref note 1 refbufin 20 d clock ad7674 c/ p/dsp serial port digital supply (3.3v or 5v) analog supply (5v) dvdd ob/2c note 6 pdbuf dvdd 50k 100nf 1m in+ analog input+ c c 2.7nf u1 note 3 note 4 50 ad8021 ? + 15 note 2 note 5 adr421 10 f 100nf + 10 f 100nf + 100nf + 10 f in? analog input? c c 2.7nf u2 note 3 note 4 50 ad8021 ? + 15 50 100nf notes 1. see voltage reference input section. 2. optional circuitry for hardware gain calibration. 3. the ad8021 is recommended . see driver amplifier choice section. 4. see analog inputs section. 5. option, see power supply section. 6. optional low jitter cnvst, see conversion control section. 47 f mode1 mode0 note 1 c ref ref refgnd 03083-0-027 figure 27. typical connection diagram (internal reference buffer, serial interface)
ad7674 rev. a | page 18 of 28 typical connection diagram figure 27 shows a typical connection diagram for the ad7674. different circuitry shown on this diagram is optional and is discussed later in this data sheet. analog inputs figure 28 shows a simplified analog input section of the ad7674. the diodes shown in figure 28 provide esd protection for the inputs. care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs. this will cause these diodes to become forward biased and start conducting current. these diodes can handle a forward-biased current of 120 ma max. this condition could eventually occur when the input buffers u1 or u2 supplies are different from avdd. in such a case, an input buffer with a short-circuit current limitation can be used to protect the part. in+ in? agnd av d d r+ = 102 c s c s r? = 102 03083-0-028 figure 28. simplified analog input this analog input structure is a true differential structure. by using these differential inputs, signals common to both inputs are rejected as shown in figure 29, which represents typical cmrr over frequency. frequecy (khz) 66 cmrr (db) 64 50 100 1000 10000 110 62 60 58 56 54 52 03083-0-029 figure 29. analog input cmrr vs. frequency during the acquisition phase for ac signals, the ad7674 behaves like a 1-pole rc filter consisting of the equivalent resistance r+, rC, and c s . the resistors r+ and rC are typically 102 and are lumped components made up of a serial resistor and the on resistance of the switches. c s is typically 60 pf and mainly consists of the adc sampling capacitor. this 1-pole filter with a C3 db cutoff frequency of 26 mhz typ reduces any undesirable aliasing effect and limits the noise coming from the inputs. because the input impedance of the ad7674 is very high, the part can be driven directly by a low impedance source without gain error. this allows the user to put an external 1-pole rc filter between the amplifier output and the adc analog inputs, as shown in figure 27, to improve the noise filtering done by the ad7674 analog input circuit. however, the source impedance has to be kept low because it affects the ac performance, especially the total harmonic distortion (thd). the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of source impedance and the maximum input frequency, as shown in figure 30. input resistance ( ) ?95 thd (db) ?120 45 75 105 15 ?100 ?105 ?110 ?115 20khz 10khz 2khz 03083-0-030 figure 30. thd vs. analog input frequency and source resistance driver amplifier choice although the ad7674 is easy to drive, the driver amplifier needs to meet the following requirements: ? the driver amplifier and the ad7674 analog input circuit have to be able to settle for a full-scale step of the capacitor array at an 18-bit level (0.0004%). in the amplifiers data sheet, settling at 0.1% or 0.01% is more commonly specified. this could differ significantly from the settling time at an 18-bit level and, therefore, should be verified prior to driver selection. the tiny op amp ad8021, which combines ultralow noise and high gain-bandwidth, meets this settling time requirement. ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the ad7674. the noise coming from the driver is filtered by the ad7674 analog input circuit 1-pole low-pass filter made by r+, rC, and c s . the snr degradation due to the amplifier is
ad7674 rev. a | page 19 of 28 ? ? ? ? ? ? ? ? ? ? ? ? ? ? = + 2 ) ( 625 25 log 20 n 3db C loss ne f snr where: f C 3db is the C3 db input bandwidth in mhz of the ad7674 (26 mhz) or the cutoff frequency of the input filter, if used. n is the noise factor of the amplifiers (1 if in buffer configuration). e n is the equivalent input noise voltage of each op amp in nv/ hz. for instance, for a driver with an equivalent input noise of 2 nv/ hz (e.g., ad8021) configured as a buffer, thus with a noise gain of +1, the snr degrades by only 0.34 db with the filter in figure 27, and by 1.8 db without it. ? the driver needs to have a thd performance suitable to that of the ad7674. the ad8021 meets these requirements and is usually appropriate for almost all applications. the ad8021 needs a 10 pf external compensation capacitor, which should have good linearity as an npo ceramic or mica type. the ad8022 could be used if a dual version is needed and gain of 1 is present. the ad829 is an alternative in applications where high frequency (above 100 khz) performance is not required. in gain of 1 applications, it requires an 82 pf compensation capacitor. the ad8610 is another option when low bias current is needed in low frequency applications. single-to-differential driver for applications using unipolar analog signals, a single-ended- to-differential driver will allow for a differential input into the part. the schematic is shown in figure 31. when provided an input signal of 0 to v ref , this configuration will produce a differential v ref with midscale at v ref /2. if the application can tolerate more noise, the ad8138 differential driver can be used. u2 8.25k 2.5v ad8021 590 ad7674 in+ in? ref u1 analog input (unipolar 0v to 4.096v) 10pf ad8021 590 10pf 10 f 100nf 1.82k 2.7nf 15 2.7nf 15 refbufin 03083-0-031 figure 31. single-ended-to-di fferential driver circuit (internal reference buffer used) voltage reference the ad7674 allows the use of an external voltage reference either with or without the internal reference buffer. using the internal reference buffer is recommended when sharing a common reference voltage between multiple adcs is desired. however, the advantages of using the external reference voltage directly are: ? the snr and dynamic range improvement (about 1.7 db) resulting from the use of a reference voltage very close to the supply (5 v) instead of a typical 4.096 v reference when the internal buffer is used ? the power saving when the internal reference buffer is powered down (pdbuf high) to use the internal reference buffer, pdbuf should be low. a 2.5 v reference voltage applied on the refbufin input will result in a 4.096 v reference on the ref pin. in both cases, the voltage reference input ref has a dynamic input impedance and therefore requires an efficient decoupling between ref and refgnd inputs, the decoupling consists of a low esr 47 f tantalum capacitor connected to the ref and refgnd inputs with minimum parasitic inductance. care should also be taken with the reference temperature coefficient of the voltage reference, which directly affects the full-scale accuracy if this parameter matters. for instance, a 4 ppm/c temperature coefficient of the reference changes the full scale by 1 lsb/c. power supply the ad7674 uses three sets of power supply pins: an analog 5 v supply (avdd), a digital 5 v core supply (dvdd), and a digital output interface supply (ovdd). the ovdd supply defines the output logic level and allows direct interface with any logic working between 2.7 v and dvdd + 0.3 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply, as shown in figure 27. the ad7674 is independent of power supply sequencing once ovdd does not exceed dvdd by more than 0.3 v, and is therefore free from supply voltage induced latch-up. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 32.
ad7674 rev. a | page 20 of 28 frequecy (khz) 70 psrr (db) 65 40 100 1000 10000 110 60 55 50 45 03083-0-032 figure 32. psrr vs. frequency power dissipation versus throughput in impulse mode, the ad7674 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows for a significant power savings when the conversion rate is reduced, as shown in figure 33. this feature makes the ad7674 ideal for very low power battery applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (dvdd and dgnd), and ovdd should not exceed dvdd by more than 0.3 v. sampling rate (sps) 1000000 power dissapation ( w) 1m 100000 10000 1000 100 10 1 0.1 100k 10k 1k 100 1 warp/normal 10 pdbuf high 03083-0-033 impulse figure 33. power dissipa tion vs. sample rate conversion control figure 34 shows the detailed timing diagrams of the conversion process. the ad7674 is controlled by the cnvst signal, which initiates conversion. once initiated, it cannot be restarted or aborted, even by pd, until the conversion is complete. the cnvst signal operates independently of cs and rd signals. cnvst t 1 t 2 mode acquire convert acquire convert t 7 t 8 busy t 4 t 3 t 5 t 6 03083-0-034 figure 34. basic conversion timing although cnvst is a digital signal, it should be designed with special care with fast, clean edges and levels with minimum overshoot and undershoot or ringing. for applications where snr is critical, the cnvst signal should have very low jitter. this may be achieved by using a dedicated oscillator for cnvst generation, or to clock it with a high frequency low jitter clock, as shown in figure 27. in impulse mode, conversions can be initiated automatically. if cnvst is held low when busy goes low, the ad7674 controls the acquisition phase and automatically initiates a new conversion. by keeping cnvst low, the ad7674 keeps the conversion process running by itself. note that the analog input has to be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the ad7674 could sometimes run slightly faster than the guaranteed limits of 570 ksps in impulse mode. this feature does not exist in warp or normal modes. digital interface the ad7674 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the ad7674 digital interface also accommodates both 3 v and 5 v logic by simply connecting the ad7674s ovdd supply pin to the host system interface digital supply. finally, by using the ob/ 2c input pin in any mode but 18-bit interface mode, both twos complement and straight binary coding can be used. the two signals, cs and rd , control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7674 in multicircuit applications, and is held low in a single ad7674 design. rd is generally used to enable the conversion result on the data bus.
ad7674 rev. a | page 21 of 28 t 9 reset data bus busy cnvst t 8 03083-0-035 figure 35. reset timing cnvst busy data bus cs = rd = 0 previous conversion data new data t 1 t 10 t 4 t 3 t 11 03083-0-036 figure 36. master parallel data timing for reading (continuous read) parallel interface the ad7674 is configured to use the parallel interface with an 18-bit, a 16-bit, or an 8-bit bus width, according to table 7. the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in figure 37 and figure 38, respectively. when the data is read during the conversi on, however, it is recommended that it is read only during the first half of the conversion phase. this avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. refer to table 7 for a detailed description of the different options available. data bus t 12 t 13 busy cs rd current conversion 03083-0-037 figure 37. slave parallel data timing for reading (read after convert) cs = 0 cnvst, rd t 1 previous conversion data bus t 12 t 13 busy t 4 t 3 03083-0-038 figure 38. slave parallel data timing for reading (read during convert) cs rd a0, a1 pins d[15:8] pins d[7:0] hi-z hi-z high byte low byte low byte high byte hi-z hi-z t 12 t 12 t 13 03083-0-039 figure 39. 8-bit and 16-bit parallel interface serial interface the ad7674 is configured to use the serial interface when mode0 and mode1 are held high. the ad7674 outputs 18 bits of data, msb first, on the sdout pin. this data is synchronized with the 18 clock pulses provided on the sclk pin. the output data is valid on both the rising and falling edge of the data clock. master serial interface internal clock the ad7674 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. the ad7674 also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. depending on the rdc/sdin input, the data can be read after each conversion or during the following conversion. figure 40 and figure 41 show the detailed timing diagrams of these two modes. usually, because the ad7674 is used with a fast throughput, the master read during conversion mode is the most recommended serial mode. in read during conversion mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions.
ad7674 rev. a | page 22 of 28 in read after conversion mode, it should be noted that unlike in other modes, the busy signal returns low after the 18 data bits are pulsed out and not at the end of the conversion phase, which results in a longer busy width. to accommodate slow digital hosts, the serial clock can be slowed down by using divsclk. t 3 busy cs, rd cnvst sync sclk sdout 123 161718 d17 d16 d2 d1 d0 x ext/int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 14 t 20 t 15 t 16 t 22 t 23 t 29 t 28 t 18 t 19 t 21 t 30 t 25 t 24 t 26 t 27 03083-0-040 figure 40. master serial data timing for reading (read after convert) rdc/sdin = 1 invsclk = invsync = 0 d17 d16 d2 d1 d0 x 123 161718 busy sync sclk s dout cs, rd cnvst t 3 t 1 t 17 t 14 t 15 t 19 t 20 t 21 t 16 t 22 t 23 t 24 t 27 t 26 t 25 t 18 ext/int = 0 03083-0-046 figure 41. master serial data timing for reading (read previous conversion during convert) slave serial interface external clock the ad7674 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. the external serial clock is gated by cs . when cs and rd are both low, the data can be read after each conversion or during the following conversion. the external clock can be either a continuous or a discontinuous clock. a discontinuous clock can be either normally high or normally low when inactive. figure 42 and figure 43 show the detailed timing diagrams of these methods. while the ad7674 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or
ad7674 rev. a | page 23 of 28 degradation of the conversion result could occur. this is particularly important during the second half of the conversion phase because the ad7674 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that only toggles when busy is low or, more importantly, that it does not transition during the latter half of busy high. external discontinuous clock data read after conversion though maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. figure 42 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the result of this conver sion can be read while both cs and rd are low. data is shifted out msb first with 18 clock pulses, and is valid on the rising and falling edge of the clock. among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. also, data can be read at speeds up to 40 mhz, accommodating both slow digital host interface and the fastest serial reading. finally, in this mode only, the ad7674 provides a daisy-chain feature using the rdc/sdin input pin to cascade multiple converters together. this feature is useful for reducing component count and wiring connections when desired (for instance, in isolated multiconverter applications). an example of the concatenation of two devices is shown in figure 44. simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the edge of sclk opposite the one used to shift out data on sdout. thus, the msb of the upstream converter follows the lsb of the downstream converter on the next sclk cycle. sclk sdout d17 d16 d1 d0 d15 x17 x16 x15 x1 x0 y17 y16 busy sdin invsclk = 0 x17 x16 x 123 1617181920 ext/int = 1 rd = 0 t 35 t 36 t 37 t 31 t 32 t 34 t 16 t 33 cs 03083-0-042 figure 42. slave serial data timing for reading (read after convert)
ad7674 rev. a | page 24 of 28 sdout sclk d1 d0 x d17 d16 d15 12 3 161718 busy invsclk = 0 ext/int = 1 rd = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 3 cs cnvst 03083-0-043 figure 43. slave serial data timing for reading (read previous conversion during convert) busy busy ad7674 #2 (upstream) ad7674 #1 (downstream) rdc/sdin sdout cnvst cs sclk rdc/sdin sdout cnvst cs sclk data out sclk in cs in cnvst in busy out 03083-0-044 figure 44. two ad7674s in a daisy-chain configuration external clock data read during conversion figure 43 shows the detailed timing diagrams of this method. during a conversion, while both cs and rd are low, the result of the previous conversion can be read. the data is shifted out msb first with 18 clock pulses, and is valid on both the rising and falling edge of the clock. the 18 bits have to be read before the current conversion is complete. if that is not done, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy- chain feature in this mode, and the rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock is recommended to ensure that all bits are read during the first half of the conversion phase. it is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. microprocessor interfacing the ad7674 is ideally suited for traditional dc measurement applications supporting a microprocessor, and for ac signal processing applications interfacing to a digital signal processor. the ad7674 is designed to interface either with a parallel 8-bit or 16-bit wide interface, or with a general-purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7674 to prevent digital noise from coupling into the adc. the following section illustrates the use of the ad7674 with an spi equipped dsp, the adsp-219x. spi interface (adsp-219x) figure 45 shows an interface diagram between the ad7674 and the spi equipped adsp-219x. to accommodate the slower speed of the dsp, the ad7674 acts as a slave device, and data must be read after conversion. this mode also allows the daisy- chain feature. the convert command could be initiated in response to an internal timer interrupt. the 18-bit output data are read with 3-byte spi access. the reading process could be initiated in response to the end-of-conversion signal (busy going low) using an interrupt line of the dsp. the serial interface (spi) on the adsp-219x is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1, and spi interrupt enable (timod) = 00, by writing to the spi control register (spicltx). it should be noted that to meet all timing requirements, the spi clock should be limited to 17 mbps, which allows it to read an adc result in about 1.1 s. when a higher sampling rate is desired, use of one of the parallel interface modes is recommended. ad7674 1 adsp-219x 1 pfx misox sckx pfx or tfsx sdout sclk cnvst cs rd invsclk 1 additional pins omitted for clarity. spixsel (pfx) busy dvdd mode0/mode1 ext/int 03083-045 figure 45. interfacing the ad7674 to an spi interface
ad7674 rev. a | page 25 of 28 application hints layout the ad7674 has very good immunity to noise on the power supplies. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7674 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this calls for the use of ground planes, which can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the ad7674, or at least as close to the ad7674 as possible. if the ad7674 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close to the ad7674 as possible. the user should avoid running digital lines under the device, as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7674 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of feedthrough through the board. the power supply lines to the ad7674 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supplys impedance presented to the ad7674 and to reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed close to and ideally right up against each power supply pin (avdd, dvdd, and ovdd) and their corresponding ground pins. additionally, low esr 10 f capacitors should be located near the adc to further reduce low frequency ripple. the dvdd supply of the ad7674 can be a separate supply or can come from the analog supply, avdd, or the digital interface supply, ovdd. when the system digital supply is noisy or when fast switching digital signals are present, and if no separate supply is available, the user should connect the dvdd digital supply to the analog supply avdd through an rc filter, (see figure 27), and connect the system supply to the interface digital supply ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. the ad7674 has four different ground pins: refgnd, agnd, dgnd, and ognd. refgnd senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. agnd is the ground to which most internal adc analog signals are referenced. this ground must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the configuration. ognd is connected to the digital system ground. the layout of the decoupling of the reference voltage is important. the decoupling capacitor should be close to the adc and should be connected with short and large traces to minimize parasitic inductances. evaluating the ad7674s performance an evaluation board for the ad7674 allows a quick means to measure both dc (histograms and time domain) and ac (time and frequency domain) performances of the converter. the eval-ad7674cbz is an evaluation board package that includes a fully assembled and tested evaluation board, documentation, and software. the accompanying software requires the use of a capture board which must be ordered seperately from the evaluation board (see the ordering guide for information). the evaluation board can also be used in a stand alone configuration and does not use the software when in this mode. refer to the eval-ad76xxedz and eval- ad76xxcbz documents available from www.analog.com for evaluation board details. two types of data capture boards can be used with the eval- ad7674cbz: ? usb based (eval-ced1z recommended) ? parallel port based (eval-control brd3z not recommended as many newer pcs do not include parallel ports any longer) the recommended board layout for the ad7674 is outlined in the evaluation board data sheet.
ad7674 rev. a | page 26 of 28 outline dimensions top view (pins down ) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc s q seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.10 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 10 6 2 0.15 0.05 compliant to jedec standards ms-026bbc figure 46. 48-lead low profile quad flat package (lqfp) (st-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 080108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 47. 48-lead lead frame chip scale package [lfcsp_vq] 7 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model temperature range packag e description package option ad7674astz 1 ?40c to +85c 48-lead low profile quad flat package [lqfp] st-48 ad7674astzl ?40c to +85c 48-lead low pr ofile quad flat package [lqfp] st-48 ad7674acpz ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48 ad7674acpzrl ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48 eval-ad7674cbz 2 evaluation board eval-ced1z 3 usb data capture board eval-control brd2z 3 parallel port capture board, 32k ram eval-control brd3z 3 parallel port capture board, 128k ram 1 z = rohs compliant part. 2 this board can be used as a standalone ev aluation board or in conjunction with a ca pture board for evaluati on/demonstration pur poses. 3 these capture boards allow the pc to control and communicate with all analog devices evaluation boards ending in ed for eval-c ed1z and cb for eval-control brdxz (x = 2, 3)
ad7674 rev. a | page 27 of 28 notes
ad7674 rev. a | page 28 of 28 notes ?2003C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03083-0-6/09(a)

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