may 2013 ?2013 fairchild semiconductor corporation FDMC86570L rev. c www.fairchildsemi.com 1 FDMC86570L n-channel shie lded gate powertrench ? mosfet FDMC86570L n-channel shielded gate powertrench ? mosfet 60 v, 56 a, 4.3 m features ? shielded gate mosfet technology ? max r ds(on) = 4.3 m at v gs = 10 v, i d = 18 a ? max r ds(on) = 6.5 m at v gs = 4.5 v, i d = 15 a ? high performance technology for extremely low r ds(on) ? termination is lead-free ? rohs compliant general description this n-channel mosfet is produced using fairchild semiconductor?s advanced powertrench ? process that incorporates shielded gate technology. this process has been optimized for the on-state resistance and yet maintain superior switching performance. application ? dc-dc conversion power 33 bottom top pin 1 pin 1 g d s s s d d d s s s g d d d d power 33 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol paramete r ratings units v ds drain to source voltage 60 v v gs gate to source voltage 20 v i d drain current -continuous t c = 25 c 56 a -continuous t a = 25 c (note 1a) 18 -pulsed (note 4) 200 e as single pulse avalanche energy (note 3) 253 mj p d power dissipation t c = 25 c 54 w power dissipation t a = 25 c (note 1a) 2.3 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case (note 1) 2.3 c/w r ja thermal resistance, junction to ambient (note 1a) 53 device marking device package reel size tape width quantity FDMC86570L FDMC86570L power33 13 ?? 12 mm 3000 units
FDMC86570L n-channel shie lded gate powertrench ? mosfet www.fairchildsemi.com 2 ?2013 fairchild semiconductor corporation FDMC86570L rev. c electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 60 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 30 mv/c i dss zero gate voltage drain current v ds = 48 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 1.0 1.8 3.0 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -7 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 18 a 3.1 4.3 m v gs = 4.5 v, i d = 15 a 4.7 6.5 v gs = 10 v, i d = 18 a, t j = 125 c 5.0 6.9 g fs forward transconductance v dd = 5 v, i d = 18 a 75 s c iss input capacitance v ds = 30 v, v gs = 0 v, f = 1 mhz 4790 6705 pf c oss output capacitance 821 1150 pf c rss reverse transfer capacitance 19 30 pf r g gate resistance 0.1 0.9 2.7 t d(on) turn-on delay time v dd = 30 v, i d = 18 a, v gs = 10 v, r gen = 6 19 34 ns t r rise time 6.2 12 ns t d(off) turn-off delay time 38 61 ns t f fall time 3.9 10 ns q g(tot) total gate charge v gs = 0 v to 10 v v dd = 30 v, i d = 18 a 63 88 nc q g(tot) total gate charge v gs = 0 v to 4.5 v 29 41 nc q gs gate to source charge 14 nc q gd gate to drain ?miller? charge 6.3 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 18 a (note 2) 0.8 1.3 v v gs = 0 v, i s = 1.9 a (note 2) 0.7 1.2 v t rr reverse recovery time i f = 18 a, di/dt = 100 a/ s 43 69 ns q rr reverse recovery charge 26 42 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. e as of 253 mj is based on starting t j = 25 c, l = 3 mh, i as = 13 a, v dd = 60 v, v gs = 10 v. 100% test at l = 0.1 mh, i as = 43 a. 4. pulsed id limited by junction temperature, td<=100 s, please refer to soa curve for more details. g df ds sf ss 53 c/w when mounted on a 1 in 2 pad of 2 oz copper g df ds sf ss 125 c/w when mounted on a minimum pad of 2 oz copper a. b.
FDMC86570L n-channel shie lded gate powertrench ? mosfet www.fairchildsemi.com 3 ?2013 fairchild semiconductor corporation FDMC86570L rev. c typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 40 80 120 160 200 v gs = 3.5 v v gs = 5 v v gs = 4.5 v v gs = 6 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 4 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on-region characteristics figure 2. 0 40 80 120 160 200 0 1 2 3 4 5 v gs = 6 v v gs = 4 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4.5 v v gs = 5 v v gs = 3.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 i d = 18 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 0 4 8 12 16 20 t j = 125 o c i d = 18 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 12345 0 40 80 120 160 200 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 200 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMC86570L n-channel shie lded gate powertrench ? mosfet www.fairchildsemi.com 4 ?2013 fairchild semiconductor corporation FDMC86570L rev. c figure 7. 0 1428425670 0 2 4 6 8 10 i d = 18 a v dd = 40 v v dd = 30 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 20 v gate charge characteristics figure 8. 0.1 1 10 60 1 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 100 400 1 10 50 t j = 125 o c t j = 25 o c t j = 100 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 20 40 60 80 100 v gs = 4.5 v limited by package r t jc = 2.3 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature figure 11. 0.01 0.1 1 10 100 300 0.001 0.01 0.1 1 10 100 300 10 s curve bent to measured data 100 p s 10 ms dc 1 s 100 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c fo rwa rd bi as sa fe operating area f i g u r e 1 2 . s i n g l e p u l s e m a x i m u m po wer dissipation 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.1 1 10 100 1000 10000 single pulse r t ja = 125 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) typical characteristics t j = 25 c unless otherwise noted
FDMC86570L n-channel shie lded gate powertrench ? mosfet www.fairchildsemi.com 5 ?2013 fairchild semiconductor corporation FDMC86570L rev. c figure 13. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 100 0.0001 0.001 0.01 0.1 1 2 single pulse r t ja = 125 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25 c unless otherwise noted
FDMC86570L n-channel shie lded gate powertrench ? mosfet www.fairchildsemi.com 6 ?2013 fairchild semiconductor corporation FDMC86570L rev. c dimensional outlin e and pad layout
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