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datasheet 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 9ZXL0651 idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 1 9ZXL0651 rev c 040115 general description the 9ZXL0651 is a low-power 6-output differential buffer that meets all the performance requirements of the intel db1200z specification. it consumes 50% less power than standard hcsl devices and has internal terminations to allow direct connection to 85 ohm transmission lines. the 9ZXL0651 is backwards compatible to pcie gen1 and gen2 and qpi 6.4gt/s specifications. a fixed, internal feedback path maintains low drift for critical qpi applications. recommended application 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi output features ? 6 - 0.7v low-power hcsl (lp-hcsl) output pairs w/integrated terminations features/benefits ? low-power-hcsl outputs w/zo = 85 ? ; save power and board space - no termination resistors required. ideal for blade servers. ? space-saving 40-pin vfqfpn package ? fixed feedback path for 0ps input-to-output delay ? 6 oe# pins; hardware control of each output ? pll or bypass mode; pll can dejitter incoming clock ? selectable pll bandwidth; minimizes jitter peaking in downstream pll's ? spread spectrum compatible; tracks spreading input clock for low emi key specifications ? cycle-to-cycle jitter <50ps ? output-to-output skew <65 ps ? input-to-output delay variation <50ps ? pcie gen3 phase jitter <1.0ps rms ? qpi 9.6gt/s 12ui phase jitter <0.2ps rms block diagram logic dif(5:0) hibw_bypm_lobw# smbdat smbclk ckpwrgd/pd# z-pll (ss compatible) dfb_out_nc dif_in dif_in# oe(5:0)#
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 2 9ZXL0651 rev c 040115 pin configuration power management table pll operating mode power connections pll operating mode readback table tri-level input thresholds 9ZXL0651 smbus address nc vdd voe5# dif_5# dif_5 vdd dif_4# dif_4 voe4# vdd 40 39 38 37 36 35 34 33 32 31 vdda 130 nc ^vhibw_bypm_lobw# 229 vdd ckpwrgd_pd# 328 voe3# gnd 427 dif_3# vddr 526 dif_3 dif_in 625 vdd dif_in# 724 dif_2# smbdat 823 dif_2 smbclk 922 voe2# dfb_out_nc# 10 21 vdd 11 12 13 14 15 16 17 18 19 20 dfb_out_nc vdd voe0# dif_0 dif_0# vdd dif_1 dif_1# voe1# vdd pin 1 9ZXL0651 epad is gnd 40-vfqfpn ^ pref ix indicates internal pull-up resistor v prefix indicates internal pull-dow n resistor ^v prefix indicates interal pull-up/dow n resistor (biased to vdd/2) 5mm x 5mm 0.4mm pin pitch ckpwrgd_pd# dif_in/ dif_in# smbus en bit dif(5:0)/ dif(5:0)# pll state if not in bypass mode 0 x x low/low off 0 low/low on 1 running on running 1 hibw_bypm_lobw# mode low pll lo bw mid bypass high pll hi bw note: pll is off in bypass mode vdd gnd 141analog pll 5 4 analog input 12,16,20,24,27 ,31,32,36,40 41 dif clocks pin number descri p tion hibw_bypm_lobw# byte0, bit 7 byte 0, bit 6 low (low bw) 0 0 mid (bypass) 0 1 high (high bw) 1 1 level voltage low <0.8v mid 1.2 2.2v 1101100 + read/write bit
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 3 9ZXL0651 rev c 040115 pin descriptions pin # pin name pin type description 1 vdda pwr 3.3v power for the pll core. 2 ^vhibw_bypm_lobw# latche d in trilevel input to select high bw, bypass or low bw mode. see pll operatin g mode table for details. 3 ckpwrgd_pd# trays 3.3v input notifies device to sample latched inputs and start up on first high assertion, or exit power down mode on subsequent assertions. low enters power down mode. 4 gnd gnd ground pin. 5 vddr pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analo g power rail and filtered appropriately. 6 dif_in in 0.7 v differential true input 7 dif_in# in 0.7 v differential complementary input 8 smbdat i/o data pin of smbus circuitry, 5v tolerant 9 smbclk in clock pin of smbus circuitry, 5v tolerant 10 dfb_out_nc# out complementary half of differential feedback output, provides feedback signal to the pll for synchronization with input clock to eliminate phase error. this pin should not be connected on the circuit board, the feedback is internal to the package. 11 dfb_out_nc out true half of differential feedback output, provides feedback signal to the pll for synchronization with the input clock to eliminate phase error. this pin should not be connected on the circuit board, the feedback is internal to the packa g e. 12 vdd pwr power supply, nominal 3.3v 13 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 14 dif_0 out 0.7v differential true clock output 15 dif_0# out 0.7v differential complementary clock output 16 vdd pwr power supply, nominal 3.3v 17 dif_1 out 0.7v differential true clock output 18 dif_1# out 0.7v differential complementary clock output 19 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 20 vdd pwr power supply, nominal 3.3v 21 vdd pwr power supply, nominal 3.3v 22 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 23 dif_2 out 0.7v differential true clock output 24 dif_2# out 0.7v differential complementary clock output 25 vdd pwr power supply, nominal 3.3v 26 dif_3 out 0.7v differential true clock output 27 dif_3# out 0.7v differential complementary clock output 28 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 29 vdd pwr power supply, nominal 3.3v 30 nc n/a no connection. 31 vdd pwr power supply, nominal 3.3v 32 voe4# in active low input for enabling dif pair 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 33 dif_4 out 0.7v differential true clock output 34 dif_4# out 0.7v differential complementary clock output 35 vdd pwr power supply, nominal 3.3v 36 dif_5 out 0.7v differential true clock output 37 dif_5# out 0.7v differential complementary clock output 38 voe5# in active low input for enabling dif pair 5. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 39 vdd pwr power supply, nominal 3.3v 40 nc n/a no connection. 41 epad gnd ground pad.
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 4 9ZXL0651 rev c 040115 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9ZXL0651. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical pa rameters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters parameter symbol conditions min typ max units notes 3.3v core supply voltage vdd, vdda, vddr vdd for core logic and pll 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor g uaranteed. t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (sin g le-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (sin g le-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value (single-ended measurement) 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.35 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 50 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured throu g h +/-75mv window centered around differential zero
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 5 9ZXL0651 rev c 040115 electrical characteristics?in put/supply/common parameters t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial range 0 35 70 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ib yp v dd = 3.3 v, bypass mode 1 150 mhz 2 f i p ll v dd = 3.3 v, 100mhz pll mode 90 100.00 110 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c i ndi f_i n dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.53 1 ms 1,2 input ss modulation frequency f modi n allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 4 8 12 cycles 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 10 ns 1,2 trise t r rise time of control inputs 10 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swin g . 5 the differential input clock must be running for the smbus to be active input current 3 time from deassertion until out p uts are >200 mv 4 dif in in p ut capacitance input frequency
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 6 9ZXL0651 rev c 040115 electrical characteristics?dif 0.7v low power hcsl outputs electrical characterist ics?current consumption t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes slew rate trf scope avera g in g on 1 2.9 4 v/ns 1, 2, 3 slew rate matchin g ? % 1, 2, 4 voltage high vhigh 660 754 850 1 voltage low vlow -150 62 150 1 max volta g e vmax 827 1150 1 min voltage vmin -300 10 1 vswing vswing scope averaging off 300 1395 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 300 453 550 mv 1, 5 crossing voltage (var) ? -vcross scope averaging off 14 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting ? -vcross to be smaller than vcross absolute. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by desi g n and characterization, not 100% tested in production. c l = 2pf, zo = 85 ? 4 6ma1 i ddvddapll 100mhz, vdda rail, pll mode 14 20 ma 1 i ddvddabyp 100mhz, vdda rail, bypass mode 3 5ma1 i ddvdd 100mhz, vdd rail 41 50 ma 1 i ddvddrpd power down, vddr rail 3.5 5ma1 i ddvddapd power down, vdda rail 1.6 3ma1 i ddvddpd power down, vdd rail 0.3 2ma1 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 c l = 2pf, zo = 85 ?
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 7 9ZXL0651 rev c 040115 electrical characteristics?skew and differential jitter parameters t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes clk_in, dif[x:0] t spo_pll in-to-out skew in pll mode @ 100mhz nominal value @35c, 3.3v -100 53 100 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp in-to-out skew in bypass mode @ 100mhz nominal value @ 35c, 3.3v 2.5 3.4 4.5 ns 1,2,3,5,8 clk_in, dif[x:0] t dspo_pll in-to-out skew varation in pll mode across volta g e and temperature -50 0 50 ps 1,2,3,5,8 clk_in, dif[x:0] t dspo_byp in-to-out skew varation in bypass mode across volta g e and temperature -250 0 250 ps 1,2,3,5,8 clk_in, dif[x:0] t dte random differential tracking error beween two 9zx devices in hi bw mode 35 ps (rms) 1,2,3,5,8 clk_in, dif[x:0] t dsste random differential spread spectrum tracking error beween two 9zx devices in hi bw mode 15 75 ps 1,2,3,5,8 dif{x:0] t skew_all output-to-output skew across all outputs (common to bypass and pll mode) 39 65 ps 1,2,3,8 pll jitter peaking j p eak-hibw lobw#_bypass_hibw = 1 2.5 db 7,8 pll jitter peaking j p eak-lobw lobw#_bypass_hibw = 0 2 db 7,8 pll bandwidth pll hi bw lobw#_bypass_hibw = 1 4 mhz 8,9 pll bandwidth pll lobw lobw#_bypass_hibw = 0 1.4 mhz 8,9 duty cycle t d c measured differentially, pll mode 45 50.1 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -1.7 |2| % 1,10 pll mode 14 50 ps 1,11 additive jitter in bypass mode 0 25 ps 1,11 notes for preceding table: 6. t is the period of the input clock 7 measured as maximum pass band g ain. at frequencies within the loop bw, hi g hest point of ma g nification is called pll jitter peakin g . 8. guaranteed by design and characterization, not 100% tested in production. 9 measured at 3 db down or half power point. 10 duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in by pass mode. 11 measured from differential waveform 1 c l = 2pf, zo = 85 ? differential trace impedance. input to output skew is measured at the first output edge following the corresponding input. 2 measured from differential cross- p oint to differential cross- p oint. this p arameter can be tuned with external feedback p ath , if p resent. jitter, cycle to cycle t jcyc-cyc 3 all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 4 this parameter is deterministic for a given device 5 measured with scope averaging on to find mean value.
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 8 9ZXL0651 rev c 040115 electrical characteristi cs?phase jitter parameters t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max industry limit units notes t jp hpcieg1 pcie gen 1 43 46 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.4 1.5 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.4 2.7 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, 2-5mhz, cdr = 10mhz) 0.56 0.61 1 ps (rms) 1,2,4 qpi & smi ( pll bw of 17.04mhz 100/133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.27 0.51 1 ps (rms) 1,5 qpi & smi ( pll bw of 7.8mhz 100/133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.22 0.49 0.5 ps (rms) 1,5 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.16 0.28 0.3 ps (rms) 1,5 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.11 0.17 0.2 ps (rms) 1,5 t jphpcieg1 pcie gen 1 1 5 n/a ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.0 0.0 n/a ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.0 0.0 n/a ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, 2-5mhz, cdr = 10mhz) 0.0 0.0 n/a ps (rms) 1,2,4,6 qpi & smi ( pll bw of 17.04mhz 100/133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.25 0.3 n/a ps (rms) 1,5,6 qpi & smi ( pll bw of 7.8mhz 100/133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.10 0.15 n/a ps (rms) 1,5,6 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.0 0.0 n/a ps (rms) 1,5,6 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.0 0.0 n/a ps (rms) 1,5,6 1 applies to all outputs. 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter)^2 = (total jittter)^2 - (i nput jitter)^2 4 subject to final ratification by pci sig. 5 calculated from intel-supplied clock jitter tool 2 see http://www.pcisig.com for complete specs t jphpcieg2 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. t jphqpi_smi phase jitter, pll mode t jphqpi_smi additive phase jitter, bypass mode t jphpcieg2
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 9 9ZXL0651 rev c 040115 clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled test loads 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max dif 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3 ssc off measurement wi ndow units notes center freq. mhz 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max dif 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3 notes: 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, 100 mhz pll mode or bypass mode notes 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck420bq/ck410b+ accuracy requirements (+/-100ppm). the 9ZXL0651 itself does not contribute to ppm error. measurement wi ndow units ssc on center freq. mhz 85ohm differential zo low-power hcsl output buffer w/internal termination rs rs 2pf 2pf 10 inches differential output terminations dif zo ( ? )rs ( ? ) 100 7 85 0 note: no resistors are required for connection to 85ohm transmission lines.
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 10 9ZXL0651 rev c 040115 general smbus serial interf ace information for 9ZXL0651 how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 11 9ZXL0651 rev c 040115 smbustable: pll mode, and frequency select register pin # name control function t yp e 0 1 default bit 7 pll mode 1 pll o p eratin g mode rd back 1 r latch bit 6 pll mode 0 pll o p eratin g mode rd back 0 r latch bit 5 0 bit 4 0 bit 3 pll_sw_en enable s/w control of pll bw r w hw latch smbus control 0 bit 2 pll mode 1 pll o p eratin g mode 1 r w 1 bit 1 pll mode 0 pll o p eratin g mode 1 r w 1 bit 0 1 smbustable: output control register pin # name control function t yp e 0 1 default bit 7 1 bit 6 dif_3_en output control - '0' overrides oe# pin rw 1 bit 5 dif_2_en output control - '0' overrides oe# pin r w 1 bit 4 1 bit 3 1 bit 2 dif_1_en output control - '0' overrides oe# pin r w 1 bit 1 dif_0_en output control - '0' overrides oe# pin r w 1 bit 0 1 smbustable: output control register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 1 bit 2 dif_5_en output control - '0' overrides oe# pin r w 1 bit 1 dif_4_en output control - '0' overrides oe# pin r w 1 bit 0 1 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved low/low enable low/low enable reserved reserved reserved reserved reserved low/low enable reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved b y te 3 b y te 4 reserved reserved reserved b y te 0 2 2 36/37 26/27 23/24 b y te 1 17/18 14/15 b y te 2 see pll operating mode readback table see pll operating mode readback table note: setting bit 3 to '1' allows the user to overide the latch value from pin 5 via use of bits 2 and 1. use the values from the pl l operating mode readback table. note that bits 7 and 6 will keep the value originally latched on pin 5. a warm reset of the system will h ave to accomplished if the user changes these bits. 33/34 reserved reserved reserved reserved reserved reserved reserved reserved reserved
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 12 9ZXL0651 rev c 040115 smbustable: vendor & revision id register pin # name control function t yp e 0 1 default bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id pin # name control function t yp e 0 1 default bit 7 r1 bit 6 r1 bit 5 r1 bit 4 r1 bit 3 r1 bit 2 r0 bit 1 r1 bit 0 r1 smbustable: byte count register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 r w 0 bit 3 bc3 r w 1 bit 2 bc2 r w 0 bit 1 bc1 r w 0 bit 0 bc0 r w 0 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved writing to this register configures how many bytes will be read back. default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. reserved device id 0 fb hex reserved - reserved device id 2 device id 1 device id 4 revision id a rev = 0000 - b y te 6 - - - - b y te 7 - - - - - device id 3 vendor id - device id 6 - - - - reserved b y te 5 reserved reserved - - - b y te 8 - - reserved device id 7 ( msb ) reserved device id 5 reserved
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 13 9ZXL0651 rev c 040115 marking diagram notes: 1. ?l? denotes rohs compliant package. 2. ?lot? denotes the lot number. 3. ?coo?: country of origin. 4. yyww is the last two digits of the year and week that the part was assembled. ics xl0651al yyww coo lot
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 14 9ZXL0651 rev c 040115 package outline and package dimensions (ndg40) package dimensions are kept current with jedec publication no. 95
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 15 9ZXL0651 rev c 040115 ordering information "lf" suffix to the part number denotes pb-free configuration, rohs compliant. ?a? is the device revision designator (will not correlate with th e datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number shipping package package temperature 9ZXL0651aklf trays 40-pin vfqfpn 0 to +70c 9ZXL0651aklft tape and reel 40-pin vfqfpn 0 to +70c
9ZXL0651 6-output low-power hcsl buffe r for pcie gen1-2-3 and qpi idt? 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi 16 9ZXL0651 rev c 040115 revision history rev. issue date issuer description page # a 10/31/2013 rdw updated electrical tables with characterization data and moved to final. various b 11/25/2014 rdw 1. updates to byte 6, bits 7:4; default should be ?1?. 2. updated device id in byte 6 from ?8b? to ?fb?. 12 c 3/30/2015 rdw 1. corrected test loads to remove references to iref and rp. these are not present on parts that have lp-hcsl outputs. 9
? 2015 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp pcclockhelp@idt.com innovate with idt and accelerate your future netw orks. contact: www.idt.com 9ZXL0651 6-output low-power hcsl buffer for pcie gen1-2-3 and qpi synthesizers

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